F3856

F3851 FAIRCHILD | Alldatasheet

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A a F3851/F3856 FAIRCHILD ew Program Storage Unit A Schlumberger Company Microprocessor Product Description © 1024/2048 Bytes of Program Storage ; ¢ intemal Memory Addressing Logie The Fairchild F9851 and F3856 are the principal program © 16 Bidirectional, individually Controlled 10 storage devices for the F8 microcomputer system. The Lines, Organized as Two &-Bit Ports F3851 provides 1024 bytes of ROM; the F3856 provides 2048 © Programmable Timer (F3856)— Preset, Start, Stop, bytes. The program storage unit (PSU) is customized with and Read-Back Ability; Four Selectable Timer programs and permanent data tabies, which are specified Count Rates, and Pulse Width Measurement as ROM masks. © Full Interrupt Level — Daisy-Chain Expandable, Independent Interrupt Address Vectors The PSU devices have two &-bit, bidirectional I/O ports, for Timer and External Interrupt interrupt logic, a programmable timer, and a pulse width ‘© 2MHz Operation measurement circult. They also contain memory addressing TTL and LSTTL Compatible logic with data counters and program counters. The inter- ‘© Low Power Dissipation, Typically Less Than 275 mW rupt logic responds to requests from an external device and = @ +5 Vand +12 V Power Supplies internally from the timer. The pulse width measurement cir- cuit (F3856) is a combination of these two capabil ities. The PSU devices are manufactured using N-channel, iso- planar MOS technology; therefore, power dissipation is very low, typically less than 275 mW. a Connection Diagram Signal Functions wag so []oe, 70 Ao By Tom le 39 [J oe. HO Ay 28, vo] afqvom ire oe voo C4 wbx i a, oe, bata Brint Qs wee 70 ay Des — — TB Ag 086 mort Cs as fyiom ‘o on el Da write (7 a4 [7] oe, PORTS: 76 fy BOR 1 8, ds Dom ie nomca-<— rR Cs afm pad eee owe, Pm C10 alien <>|i70 8, ROMC2}-<— 7 CONTROL mie won foe nome, adn afes me rome, srmowe ne” L] 12 alien tend exit omc. [13 26] om INT REQ) STROBE |STROBE/NC* PRI iN, INTERRUPT notwcs [4 aoe, haan Veo PRIoUT owes [15 ahies vowen { ied " rome: sprex ie Ve maT } ete owes (17 xbox vss C18 allion TomO 22[ Joe, Tou Lj2 21 [7] 08 NC for F3851 ony ee 331

a F3851 a Device Organization System Clock Timing The PSU is more than a read-only memory unit: every mem- All timing within the F3851/F3856 PSU is controlled by the ory device within the F8 system contains its own memory 4nd WRITE signals, which are generated from the F3850 addressing logic along with associated address registers. CPU. Refer to the F3850 data sheet for a description of Refer to figure 1 for a simplified block diagram of the PSU. these clock signals, The WRITE clock refreshes and up- A single &-bit data bus provides all necessary communica- dates PSU address registers, which are dynamic. The ¢ tion between a PSU (or any other memory device) and an clock drives sequencing logic to precharge the ROM matrix; F3850 CPU. it also drives the programmable timer. The PSU has an elementary arithmetic unit that can incre- VO Ports ment and add 16-bit data units; for memory addressing logic, these two operations are sufficient. The PSU is func- The unit contains four preassigned I/O port addresses: the tionally illustrated in figure 2. These devices also contain a two lowest are assigned to I/O ports A and B and are used control unit that decodes the five read-only memory contro! to transfer data to and from external devices. The other two (ROMC) lines, generated by the CPU, as though they were a /O addresses are assigned to the programmable timer and Sbit instruction code. Similar to the CPU, the PSU gener- the interrupt control register and are treated as 1/O ports. ates internal signals to control data flow and arithmetic Associated with the I/O ports is an I/O port address select Jogic within itself. One contro! output, data bus drive register (ASR). This is a 6-bit register for the F3851 and a (DBDR), is generated to coincide with data being output S-bit register for the F3856. The contents are a mask option, by the PSU. which must be specified at the time the PSU is created. The ports are addressed as follows: XXXXXX00 W/O port A XXXXXX01 VO port B X000XX10 Interrupt control register XXXXXX11 Programmabie timer ea Figure 1 PSU Simplified Block Diagram Ves Yoo GND 3 waire eo 3:32

For example, if the six binary digits are 000010, the four I/O. ROM Addressing port addresses are H'08, H'09, H'0A,, and H'0B. ‘The F3851 8K PSU has 1024 bytes of read-only memory; the ‘When a logic 1 is output to 1/0 port A or B, it places a0 V F3856 16K PSU has 2048 bytes. This ROM array may con- level on the output pin. This same inverted logic applies to tain object program code and/or tables of nonvarying data. input. Every PSU is implemented using a custom mask that specl- fies the state of every ROM bit and certain address mask The F3851 1/0 ports, timer, and interrupt control register are options that are external to the ROM array. Not initialized during the power-on reset cycle. The F3856 W/O ports and interrupt control register are initialized during both the power-on or external reset cycle; the timer register is not initialized during power-on or external reset cycles. Figure 2 PSU Functional Diagram I TT I FT | \\ | J» ts | =) | prrouT—t 6 | werenyer | PRT Ee | + ares s | UPPER BYTE ; cane | | Lowen BYTE MutTPLexen Aponese [— nomes —F= wr | wurvoaie |= nome, — % = rows: SE is | TcneMenTen veren ove teen [towne | lero =, oe : sso oz i (é stow > oe SR H srt es Es Ve] [estates |] Lara | eT | i ij + Eee =e 8 oma worms Lee ES | 5 COUNTER DCo - & = % = } | . +, <a e | vorore faz Ips Ete 8 | a" L 2 ee A 333

— ee F3851 ‘The ROM addressing logic consists of 16-it registers: pro- If the high-order bits of the address coincide exactly with gram counter PCo, stack register PC, and data counter DCo. the page select mask, an enable signal is generated, caus- Data counter DC; is provided on the F3856 as an additional ing the PSU logic to respond to a memory access request. If buffer for DCp. the high-order bits of the address do not coincide exactly with the page select, no enabling signal is generated and A6bit page select register and 10-bit address select regis- the PSU does not respond to memory access requests. ‘ter provide decode logic for the F3851. The F3856 uses a S-bit page select register and an 11-bit address select ‘The page select register identifies the memory addressing register. space of the individual PSU device. Each of the 32 (or 64) page select options allowed by the Sit (or 6-bit) page Program Counter, Data Counter, and Stack Registers select register identifies a single address space consisting Program counter PCo always addresses the memory loca- ‘of 2048 (or 1024) continguous memory addresses. tion out of which the next program instruction byte is read. If the instruction requires data (Le. an operand) to be Incrementer Adder Logic accessed, data counter DCy must address memory for this, There are only two arithmetic operations that memory purpose; PCy cannot be used to address data, since it is devices need to perform on the contents of memory address saving the address of the next instruction code. By using registers: the exchange DC instruction in the F3856 program, the two data counter contents of DCp and DC; can be exchanged. 1. Increment by 1 the 16bit value stored in address PCy or DOo. The provision of two address registers, PCy and DC, is a convenience to the F3850 CPU and is not a necessary part 2. Add an &bit value, treated as a signed binary number of the memory addressing logic sequence within a PSU. {subject to twos complement arithmetic) to the 16-bit Address decoding is identical, whether originating in PCy or value stored in an address register. If the 6-bit value is Dp. being treated as a signed binary number, the high-order bit of the &-bit value is the sign bit; the sign bit must be The PCp, PC;, and DCp are loaded from two consecutive propagated through the missing high-order eight bits. single-byte inputs on the data bus; PC; and DCp are trans- mitted as two single-byte outputs on the data bus. The con- ‘The PSU control unit implements the incrementer adder tents of DCp and DC, of F3856 can be exchanged in one logic through control signals internal to PSU device logic. instruction. Addressing Consistency in Multiple Stack register PC, is a buffer for program counter PCo; the Memory Devices contents of PC; are never used directly to address memory. ‘When an ROMC state specifies a memory access, only one ‘When an interrupt is acknowledged, the contents of PCy are memory device responds to the memory access operation saved in PC. itself. However, every memory device responds to ROMC states that call for modifying the contents of a program Page Select and Address Select Registers counter or data counter register. Providing every memory Ail memory addresses are 16 bits wide, whether originating device that is connected to the &-bit data bus of an F3850 in the program counter or in the data counter. Address. CPU is also connected to the ROMC control lines of the decode logic within the PSU separates the 16-bit address same CPU, address contentions cannot arise. Every memory into two portions: the low order addresses the ROM storage device simultaneously receives the same ROMC state sig- bytes; the high order addresses the page. nals from the CPU; every memory device responds to ROMC states by identically modifying the contents of memory oe address registers, if such modifications are specified. High-Order Low-Order Therefore, every PC register on every memory device Byte Address Page Address always contains identical information; the same is true for F3851 1024 Byte Select 64 Page Options Cp and PC; registers. _______6Bits___10Bits__ Only one memory device (the one whose address space F 3856 2048 Byte Select 32 Page Options includes the specified memory address) actually responds SS Bits ts to any memory access request. To avoid addressing con- flicts, it is only necessary to ensure that the following conditions exist: al 334

ne] F3851 ee SSSSSsSSSSSSSSSSSSSSSSSSseses Signal Descriptions The PSU input and output signals are described in table 1. Table 1 PSU Signal Descriptions Mnemonic [Pinto | Name |Description Clock ry 8 Clock The two clock input signals that originate at the WRITE 7 F3850 CPU. 3 | MO Ports TO Ag-10 Ay 19, 24, 25, VO Ports A Bidirectional ports through which the PIO 30, 31, 36, ‘communicates with logic external to the 37,2 microprocessor system.

10 Bo-i10 By 20, 23, 26, VO Ports B

29, 31, 35, 38,1 Control ROMCy-ROMC, 17, 16, 15, Read-Only Input signals that originate at the F3850 CPU 14,13 Memory Controt__| control internal functions of the PSU. Data Bus DB)-DB, 21, 22, 27, Data Bus Bidirectional 3-state lines that link the PSU to all 28, 33, 34, other devices within the microprocessor system. 99, 40 DEDR 1" Data Bus Drive A low output, open-drain signal that indicates the data bus currently contains data flowing from the PSU. Strobe STROBE This output signal provides a positive pulse whent/O port Ais being read by an input instruc- tion or is being updated by an output instruction (F3856). Internat ExT fl External Interrupt | A high-to4ow transition on this input signal is interpreted as an interrupt request from an external device. iNT REQ Interrupt Request | This output signal is the INT REQ input to the F860 CPU Kt must be output low 1 interupt the CPU, which occurs only if PRI IN is low and PSU interrupt control logic is requesting an interrupt. PRI iN Priority In Unless thie Input signal is low, the PSU does not set the INT signal low in response to an interrupt. PRI OUT Priority Out This output signal becomes the PRI iN signal to the next device inthe interrupt priory datsy chain; it is output high unless the PRI IN signal is entering the PSU low and the PSU is not requesting an interrupt Power Voo 4 Power Supply +5V +5% Vea 3 Power Supply +12 V 45% Ves 18 Ground ‘System ground —0 V; Vpp and Veg are referenced to Ves. NNN e EE 3:35

data bus. This timing applies whenever a PSU is the data worst case, in time for the setup required by any F3850 CPU source. The PSU places data on the data bus, even in the destination (refer to the F3850 CPU data sheet). Table 2 Data Bus Contents as a Function of the ROMC State ROMC State lf F3850 CPU Is the Source i

00 Instruction PCy

01 Offset for branch PCy

02 Operand DC

03 Operand PCy

05 Byte to be stored

06 Upper byte, DCo

07 Upper byte, PC;

08 =00 for PCy

09 Lower byte, DCy

0B Lower byte, PC; oc Byte for PCo, lower PCy op OE Byte for DCp, lower PC OF Lower byte of interrupt vector if it is source of the interrupt "1 Byte for DCo, upper PCo

12 Byte for PCp, lower

3 Upper byte of interrupt vector if it is source of

14 Byte for PCo, upper

15 Byte for PC;, upper

16 Byte for DCo, upper

7 Byte for PCo, lower

18 Byte for PC;, lower

19 Byte for DCo, lower

1A Byte for selected 1/0 port 1B Byte from 1/0 register, it selected 1c (Note 1) 1E Lower byte, PCy 1F Upper byte, PCo Only drives the data bus within the segment of address space that belongs to the PSU. **An entry In this column specities the register from which a memory address was obtained. ‘Note + During INS or OUTS instruction for port 0 or 1: 1/0 byte During INS or OUTS instruction for port 4-F: 1/0 address During all other instructions, F850 does not drive. Henne nnn el 337

‘The data bus drive signal (OBDA) is low, while data output Each I/O port pin Is a wire-AND structure between an inter- by the PSU is stable on the data bus. Thus, a DBDR low nal latch and an external signal, if any. The latch is always signal indicates that the data bus currently contains data loaded directly from the accumulator. Each 1/0 pin is set flowing from a PSU. For systems with more than one PSU, high or low under program control. if a 1 (high) is presented the DEOA ‘outputs can be wire-ORed and the result used as at the latch, gate (b) tums on and gate (a) turns off, so that a bus data flow direction indicator. The DBDA signal Pis at Veg (low). If a 0 (low) is presented at the latch, gate (a) remains low until timing delay tds into the instruction cycle turns on and gate (b) tums off, so that P is at Voo (high). following the one in which DBDR was set low. ‘When data is output through an I/O port, the pin Is connect Data Input to the PSU ed directly to a standard TTL gate input. Data is input to the ‘When the PSU receives data off the data bus, in the worst pin from a TTL output. In normal operation, high or low case, the data must be added to a 16-bit number within the levels at P drive the external TTL device input transistor PSU adder/incrementer. This worst case corresponds to (d). If a low level is set at P, transistor (d) conducts current data coming from the accumulator of the CPU for an ADC through the path J, |, P, and FET (b). This is transferred as instruction or from a memory device for a BR instruction. alow level to the rest of the circuits in the TTL device and For this worst case, arriving data must allow sufficient time results in a high or low level at the output of the device, for 16bit adder logic (time delay td, in figure 3 identifies this depending on its characteristics. If the level at P is set high, worst-case timing). transistor (d) cuts off and a high level is transferred by (d). When data is input to the I/O pin, a high or low signal at the PSU Input/Output Interfacing pin transfers a logic 1 or 0 to the accumulator. The VO ports with addresses XXXXXXOO and XXXXXX01 (XXXXXX is the Git I/O port address select) are used to ‘Since the I/O pin and the TTL device output at 0 are wire- transmit data between the PSU and external devices. The IN ANDed, it is possible for the state of one to affect the trans- and INS instructions cause data at the I/O ports to be trans- fer of data out from the I/O pin or in from the TTL device mitted to the CPU; the OUT and OUTS instructions cause ‘output. For example, if the latch in the I/O port is set so that data in the CPU accumulator to be loaded into an 1/0 port. the pin is clamped low by (b), the level at 0 cannot pull P Each I/O pin has an output latch that holds the pin DC data. high. Conversely, if P is clamped to a low level by (c), setting the latch for a high level has no effect. Input and output operations using the two PSU I/O ports execute in three instruction cycles. During the first cycle, Open-Drain Configuration (Figure 5)— When the 1/0 port is the port address is transmitted to the data bus. During the configured as shown in figure 5, the drain connection of second cycle, data is elther sent from the accumulator to FET (a) is open, i.e., not connected to Vpp through a pull-up the 1/0 latch or enabled from the I/O pin to the accumulator, transistor. This option is most useful in applications where depending on whether the instruction is an output or an several signals (possibly several {/O port lines) are to be Input. At the falling edge of the WRITE signal (marking the wire-ORed together. A common external pull-up, R., is used end of the second cycle and beginning of the third cycle), to establish the logic 1 levels. Another advantage of this the data is strobed into either the latch (OUTS) or the option is that the output (point Y) can be tied through a pull- accumulator (INS), respectively. The third cycle is then used up resistor to a voltage higher than Vpp (clear up to Veg) for by the CPU for its next instruction fetch. interfacing to external circuits requiring a higher logic 1 level than Vp provides. MO Port Options Data bus timing associated with the execution of I/O {f a high level is present at point X (coming from the port instructions does not differ from data bus timing associated latch), FET (a) will conduct and pull point Y to a low level by with any other data transfer to or from the PSU. However, current flow through R. This low level at Y causes transis- timing at the I/O port itself depends on which port option is tor (b) to turn on and present a low level to the input TTL being used. Figures 4, 5, and 6 illustrate the three port circuit. options; figure 7 illustrates timing for the three cases. If a low level Is present at X, FET (a) turns off and point Y is Standard Pull-Up Configuration (Figure 4)— All /O port bits pulled toward Vop by R,. This causes transistor (b) to turn should be set for a high level, before data input, to prevent off and present a high level to the internal TTL circuits. incoming logic Os from being masked by logic 1s preset at the port from previous outputs. In some instances, the abil- When data is input, a high level at the base of transistor (c) ity to mask bits of a port to logic 1 is useful. (Note that logic causes (c) to conduct and pull point Y low, with current flow 1 becomes a 0 V electrical level at the VO pin; logic 0 cor- through T., This transfers a high level to the internal I/O port responds to a high electrical level.) logic through inverting action by the hysteresis circult. If a Henne eee ee 3:38

ee) F3851 SSS Figure 4 Standard Pull-Up Configuration Sialeiaienenaneneneneneneneneneta Pye ttt ttt Voo ' | oureur io ! | Srnose Dae, | lhe, 0) 1 i] a waren fe 3 | ves || Bott vevsTenesis RCUT \\ i --- i} I+ \\ {rm pevice oureur ----- ee LQOPEN-COLLECTOR) Figure § Open-Drain Configuration vopoRT Ve oe rsh] \\ 1 to nvsrenesis, --- ccncurT 1 Vr inpur x—$—E | Le \\ a = I ie 1 1 --- 1 \\ ! l=

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a Figure 6 Driver Pull-Up Configuration tow level is present at the base of (c), conduction stops and vo pont Yoo | Yoo as a low level to internal 1/O port logic through the hystere- 1 sis circuit. On LED lon Driver Pull-Up Configuration (Figure 6)— Figure 6 shows the @ VO port driver pull-up option used to drive an LED indicator. fl This application is typical of a front-panel address or data x ey display, where a row of LED indicators shows the logic 1 state at each pin of an I/O port. | Ahigh level at X turns FET (b) on and (a) off, providing a See ee ee eee path for current through resistor R from the base of transis: tor (c). This stops (c) from conducting and the LED does not light. If a low level is present at X, (b) turns off and (a) turns SS 3.39

‘on, providing a path for current from Vpp through (a) to R. During input instrucions, the trailing edge of the STROBE This current through R turns on (c), which causes the LED to signal is used to indicate to the external device that the conduct and be lighted. current data on the 1/O port is read and new data can be The three options for I/O port output configurations describ- fone the. see eT ee neta. ‘ed above are provided to aid the designer in optimizing advonce the shift real in . jignal is used to (minimizing) the system hardware for a particular applica- . tlon. The choice in configuration is specified as a mask During output instruction, the trailing edge of this STROBE ‘option by the designer. signal indicates that the new data on the I/O port latches is being changed. The output on the latches becomes true after typically 500 ns of the trailing edge of this signal. Ty Figure 7 PSU I/O Port Timing Refer to the “Timing Characteristics” section for all signal characteristics. o : (stanpano PutcuP) a cr) STABLE (oPeW ORAIN) tav STABLE ts —>} (oniven putcuP) x 20¥ STABLE _ a F3856 1/0 Strobe F3851 Programmable Timer ‘An additional output strobe signal is provided on the F3856 to indicate the execution of an input or output instruction ‘The F3851 PSU has an 8bit shitt register, addressable as for the low address I/O port on the PSU circuit. (This is port 110 port XXXXXX11, that can be used as a programmable 4 of the PSU circuit with the 4-7 address.) A pulse of the timer (KXXXXX is the 6bit I/O port address select, a PSU duration of the WRITE clock on the STROBE pin is provided mask option). Figure 9 illustrates the shift register logic and at the end of the second cycle of the 1/0 instruction for this the exclusive-OR feedback path. . Figure 8 the timing relationship of this output por reapect ate execution boing performed. ia Based'on the logic illustrated in figure 9, binary values in the range 0 through 254, when loaded into the timer, are Although this pulse appears for both input and output converted into “timer counts.” As shown in table 3, ‘‘timer instructions for this port, two different signals for input only contents” is the actual binary value loaded into a timer, and are derived from the external gating of the STROBE and “timer counts” is the corresponding number of time inter- ROMC) signals, as shown below. vals the timer takes to time out. Data cannot be read out of the programmable timer I/O port. STROBE nome OUTPUT ONLY As described in the Guide to Programming the F8 Micro- computer, an assembly-language program specifies timer counts, and the assembler converts timer counts into the inpur ONLY binary value that must be loaded into the programmable timer. This is the value given under “Contents” in table 3, To al 3-40

Table 3 F3851 Timer Counts ne 8E 244 FO 179 75 "4 55 49 10 243 EO 178 EB 113 AA 8 38 242 ct 7 06 12 54 47 76 241 82 176 AD 1 AB 46 ED 240, 04 475. 5A 110 50. 5 DA 239) 06 174 5 109 ‘A0 44 Ba 238 12 173 6A 108 41 43 68 237 24 172 05 107 83 42 1 236 a 1 AB 108 06 at Aa 235 90 170 56. 105 oD 40 a7 24 2 169 AC 704 1A 39 8F 233 42 168 58 103 35 38 1F 232 Ey 167 81 102 6B 7 3F 231 ” 166 62 301 o7 36 Te 230 14 165. cA 100 AF. 35 FC 229 28 164 88 EJ SE u Fo 28 51 163 cl 98 8D 3 F3 227 A2 162 22 97 7B 32 6 226 45 161 4 96 F6 3 co 225 8B 160 89 95, EC 30 9B 224 7 159 13 34 D8. 29 36 223 2E 158 26 % 80 2B 6D 22 5D 157 4c 92 60 2 0B 221 BB 156 98 Ea co 26 86 220 7? 156 30 0 80 25 6c 219 EF 154 61 89 00 24 09 218 DE 153 ca 88 01 2B B2 217 Bc 182 84 87 03 2 64 216 79 151 03 86 or 2 8 215 F2 150 40 85 oF 20 1 214 4 149 20 oF 1E 19 23 213 co 148 40 8 30 18 46 212 9 147 at 82 7A 7 8D 2n1 Psa 146 02 81 Fa 16 1B 210 4E 145 05 80 EB 5 a7 208 9c 144 0B 79 Do 14 6F 208 38 143 16 78 Al 13 OF 207 70 142 2c 7 43 2 BE 206 Et 141 59 76 a7 1 7D 205 3 140 83 75 4 40 FA 204 86 139 66 74 1c 9 FS 203 oc 198 cc 73 39 8 EA 202 18 197 99 72 72 7 D4 201 3t 136 32 n ES 6 Ag 200 63 135. 65 70 cB 5 52 199 ce 134 cA 6 97 4 Aa 198 ac 133 Ea 68 2F 3 49 197 19 132 2B 67 5F 2 92 16 33 131 57 6 BF 1 25 195 67. 130 AE 65 TF 0 4a 194 CE 129 5C 64 FE 254 94 193 9D 128 Bo 63 29 192 3A 127 73 62 53 191 74 126 €7 61 AS 190 Eo 125 cr 60 SNe en 343

In these I/O port contents definitions, X represents “don't The flip-flop is not cleared by a loading of ICR. While count- care” binary digits. ing, the timer jumps from all-zero value to all-one value and, depending on prescaler values, provides an interrupt period F3856 Timer and interrupt Control Registers. of every 512, 2048, 8192, or 32768 ¢ clocks. The F3856 logic responds to an interrupt request that can If the timer is In the run mode and the ICR is set for a originate internally from the timer logic or from input by an prescaler value of 2 at the time a value of 2 or 1 is loaded external device, or from the pulse width measurement cir- into the TR, the next transition from a one-count to a zero- cuits. Interrupt functions present in the F3856 include the count is not detected. ability to program the active transition of the external inter- rupt, the ability to have both the timer and the external F856 Interrupt Control Register Configuration interrupts active at the same time, and the ability to mea- The ICR is a 7-bit register used to define various modes of sure pulse width of an external signal. interrupt, the value of the prescaler, and external pulse width measurement. This register is loaded by output in- The timer is an 8-bit binary count-down register that is used structions; no provision is made to read the contents of this in conjunction with interrupt logic to generate real-time register. The ICR, along with the I/O ports on the F3856, is intervals, to measure elapsed time between two events, or reset to zero during the reset sequence. to measure a pulse width appearing on the EXT INT signal. The timer is selected to run in one of four values provided ‘The configuration of this register is shown in figure 11 by the prescaler and can be made to start counting or stop counting under program control. Also, the timer contents a can be read back under program control. Figure 11 F3856 ICR Configuration A zero-detect circuit in the timer detects transitions from a ese aaa ‘one-count to a zero-count and provides a signal to the inter- rupt circuits, If all other conditions are satisfied, interrupt CITTITITL I circuits, after receiving this signal, request an interrupt service from the CPU. | T* Tica nrennuer connotes PRESCALER CONTROL BITS. ‘An external interrupt can be selected under program control eootontcan to detect the falling or rising edge of the signal. The active EXTERNAL PULSE WIDTH MODE edge is determined by the contents in a bit in the interrupt control register. as Both interrupts can be enabled at the same time. When Local Interrupt Control (Bits 0-1)— These modes define both interrupts are enabled, they are serviced on a first- the interrupt state of the timer and external interrupts come, first-served basis. For example, if the timer interrupt (see table 4). arrives later than the unserviced external interrupt, the external interrupt is serviced first, and the timer interrupt Table 4 F3856 Timer and Extemal Interrupt Modes remains stored until it is serviced or cleared. If both interrupts arrive at the same cycle, the timer interrupt is Bit4 [ Bito | Function handled first. 0 0 No Interrupt ‘The internal timer register (TR) and interrupt control register ° 4 Enable External interrupt Only (ICR) are associated with the two high address ports. The 1 0 Enable Both External and Timer TR, depending on various functions, is in one of two modes: Interrupts stationary or run. In the stationary mode, the contents of the 1 1 Enable Timer Interrupt Only TR remain unaffected. In the run mode, the TR is a binary Feioek time esoncing on Gocroments every 2, prescaler Prescaler Control (Bits 2~3)—These bits define one of the bits on the ICR. A circuit detects the one-count-tozero-count four different prescalers for the timer (refer to table 6). transition of the register and stores it in a flip-flop for interrupt purposes. This flip-flop is cleared any time a new value is loaded into TR. ES 344

Table 5 3856 Timer Prescaler Modes 2. Load TR with an initial value. Timer Timer 3, As soon as the pulse arrives, the timer starts counting Resolution Period ‘and provides the timer interrupts at zero crossing. Bit 3 at2MHz | at2MHz 4, At the end of the pulse, the timer stops counting and 1 2 1s 256 us provides an external interrupt, indicating the end of the 1 8 4us 1.024 ms pulse. The timer contents can now be read under pro- Q 82 16 us 4.095 ms gram control for calculating the pulse width. tC) 128 64 us 16.384 ms In this procedure, both interrupts are enabled. It is possible Start-Stop Timer (Bit 4)—This bit controls the TR. When at to disable one or both interrupts. if the external interrupt is 0, the TR is in the run mode; when at 1, the TR Is in the sta- Not enabled, the timer stops at the end of the pulse. How- tlonary mode. ‘ever, some means of indication are necessary to detect the ‘end of the pulse to the main program. If the timer interrupt Edge Detect Control (Bit 5)—This bit defines the active is not enabled, the timer zero crossing Is not detected. If the ‘edge of the EXT INT input signal as the source during pulse duration is always short, such that the timer is ‘external interrupts. When this bit is at 0, the falling edge is stopped before reaching zero, it Is not necessary to enable active; when it is at 1, the rising edge is active. the timer interrupt. External Pulse Width Mode (Bit 6)— When this bit Is at 0, no When the timer is loaded with a zero count, the timer inter- ‘special function is performed and the interrupts and timer rupt does not occur immediately, although the timer is a circuits are controlled by bits 0 through 5 of the ICR. How- zero-count. The timer interrupt occurs only after the one+to- ever, when this bit is at 1, the special function of pulse zero transition during the countdown. Hence, when the width measurement is performed. timer Is loaded with a zero count, the timer interrupt occurs after 256 timer counts. Pulse Width Measurement The following procedure is used to measure pulse width for This feature of being able to load a zero count in the timer the F356 PSU (refer to figure 12). without getting interrupted allows the programmer to have complete control over the timer count and is also useful 1. Before the pulse arrives, set the ICR as follows: during the pulse width measurement mode. During reset procedures, the ICR is loaded with zero, which 8. Set the external pulse width mode bit t0 1. disables the loca! ntrupt controls and etabishes the trailing edge of the input signal as the active edge b Sat.the edge detect bit to 1 for a negative pulse or for the external interrupt. The active edge of the external to 0 for a positive pulse. signal can be changed by bit 5 of the ICR. However, when this bit is changed, and the level appearing on the external ©. Sat the start/stop bit to 1 (stop mode). signals is of the same level as the one obtained after the new active edge, an external interrupt is generated. For 4. Set the preecaler bits to the value of preecsler example, when changing the active edge of the external sig- ested. nal from ‘trailing edge to rising edge under program control, \\ level, an interrupt @. Set the interrupt bits to turn on both interrupts. io roreoa Signal is already at a high level, an interrup a Figure 12 F3856 Pulse Width Measurement scrur EXTERNAL ae TIMER STARTS TIMER INTERRUPT INTERRUPT EDGE DETECT BIT =1 li i] xT int ! i} i H H SS nmen stors eae erect erro H H ‘EXTINT ' 1 ST 345

rupt flip-flop is set at this time only if the external interrupt 3. The current instruction fetch is not protected. mode is enabled within the local control logic. Event F—The CPU generates the interrupt acknowledge Event D—The INT REQ line is pulled low by the PSU, sequence of ROMC states. passing the request for servicing on to the CPU. The follow- ing conditions must be present for this to occur: Event G—At this point, the CPU begins fetching the first instruction of the interrupt service routine. In the PSU inter- 1. The PRI IN pin must be low. rupt logic, the service request flip-flop and the appropriate interrupt request flip-flop have been cleared. 2. The proper enable state must exist in the local con- trol logic for the type of interrupt {timer or external). Event H—The CPU begins executing the first instruction of the interrupt service routine. 3. The system Is not already into Event F because of servicing some other interrupt. Interrupt Address Vector During the interrupt acknowledge, the interrupting PSU pro- Event E—The CPU now begins its response to the INT vides a 16-bit interrupt address vector (refer to figure 17). REG line by transmitting the unique ROMC state H’10. The CPU causes this vector to be loaded into PCp so that program execution can branch to the routine that handles This occurs only when the following conditions are this particular interrupt. Fifteen bits of the interrupt vector satisfied: are specified as a mask option. Bit 7 cannot be masked; it is set by the interrupt control logic to 0 if the timer interrupt 4. The CPU is executing the last cycle of an instruction is enabled or to 1 if the external interrupt is enabled. (beginning an instruction fetch). 2. The ICB is enabled (ICB = 0). ee Figure 15 Timer Interrupt Sequence events a . c > rg 6 " Ware CLOOK (us) us) l us) LU Ss) wy © w 4S) syne FF TIMER INT FF J —+-—— rs | ‘TNT REG (ro cpu) (US) —e LONG oR sHoRT CYCLE (y — toncycie (9 —> short cvcte el 3-48

—_— F3851 Interrupt Signal Timing Timing for signals associated with the PSU interrupt logic is shown in figure 18. All signal characteristics are given in the timing characteristics section of this data sheet. Note: Timing measurements are made at valid logic level to valid logic level of the signals referenced unless otherwise noted. Figure 18 PSU Interrupt Timing aw iNTREG x eee an ron a ‘exTIRT —_— ee 3-50

The timing characteristics of the PSU devices are described in table 6. The ac characteristics are Vsg=0V, Vpp= +5.0V £5%, Vag = +12 V#5%, Ta =0°C to +70°C, unless other- wise specified. Table 6 PSU Signal Timing Characteristics 3 | Symbol] Parameter Min. Typ, [| Max. __|_Units [Test Conditions Pe | Period 05 10 “s PW, |} Pulse Width 180 4-180 ns | t,,ty=50ns typ. td, td, |# to Write + Delay 250 ns | C.=100pF td, | WRITE to DB Input Delay 2P6+1.0 “s Pw, | WRITE Pulse Width P$-100 Py ns | t,,ty=50ns typ. PWe | WRITE Period; Short 4Pe PW, | WRITE Period; Long ns tds | WRITE to ROMC Delay 550 ns td; | WRITE to DB Output Delay | 2P§+100-td, | 2P}+200 | 2P}+850-td, ns | O=100pF WRITE to DBDR ~ Delay tds | WRITE to DBDR + Delay 200 ns | Open drain tr, | WRITE to INT REQ - Delay 430 ns | OC, =100pF” tg _ |WRITE to INT REQ + Delay 430 ns | C)=100pF® tpr; | PRI IN to INT REQ ~ Delay 200 ns | CO. =100 pF tpd;, | PRI IN to PRI OUT Delay 800 ns | C.=50pF pda __ tpdg, | WRITE to PRI OUT Delay 600 ns C.=50 pF tpdy tsp _ | WRITE to Output Stable 1.0 s C, =50 pF, standard pull-up? tog __ | WRITE to Output Stable 25 “s ©, =50 pF, Ri = 125 kQ, open drain® tap | WRITE to Output Stable 200 400 ns | C.=80 pF, driver pull-up tay |/O Set-up Time 13 4s th VO Hold Time ) ns tec | EXT INT Set-up Time 400 ns tsB; | WRITE to STROBE + Delay SP} +300 ns | C.=50pF t,B2 _| WRITE to STROBE — Delay 6P} +410 ns | C.=50pF Notes — 1. Assume priority in was enabled (FR iN =0) In the previous F8 cycle, before the interrupt is detected In the PSU. 2. The PSU has an interrupt pending before priority in is enabled.

3 Assume pin tod to INT RE Input ofthe F860 CPU

1. Input and output capacitance is 3 to 5 pF, typical, on all pins except Vop, Vac. and Vss- a DC Characteristics The de characteristics of the PSU devices are provided in tables 7 and 8. Supply Currents Ves =0 V, Vop = +5 V +5%, Vag = +12 V 5%, Ta =0°C, +70°C ‘Symbol Parameter Min. Typ. ‘Max. __—Units__‘Test Conditions loo Vpo Current 28 60 mA f=2MHz, outputs unloaded lea Vee Current 10 30 mA __f=2MHz, outputs unloaded SS 361

——— Table 7 F385 PSU DC Characteristics Symbol [Parameter | Signal Min. | Max. | Units | Tost Conditions: Vin Input High Voltage Data Bus (DBp -DB7) 29 | Voo v Viv Input Low Voltage Ves 08 v Vou | Output High Voltage 39 | Voo V | lon= -100 pA Vo. | Output Low Voltage Ves 04 V | lp =1.6mA hia Input High Current 1.0 vA | Vin =Vpo, 3state mode lou Input Low Current -1.0 vA_| _Vin=Vsg, 3-state mode Vin Input High Voltage Clock Lines (¢, WRITE) 40 | Voo Vv Vit Input Low Voltage Vss 08 v in Leakage Current 3.0 vA_| Vin=Vop Vin Input High Voltage Priority In and Control 35 Vpo v Vit Input Low Voltage Lines (PRI IN, ROMCo - Ves 08 v \\ Leakage Current ROMC,) 3.0 vA_|_Vin =Voo Von Output High Voltage Priority out (PRI OUT) 39 Voo v lon = —100 pA Vo.___| Output Low Voltage Ves 04 V_| to, =100 pA Von | Output High Voltage Interrupt Request V_ | Open-drain output Vo. | Output Low Voltage (INT REQ) Ves Vo} lo =tmA { Leakage Current uA_| Vin =Vpo Vox | Output High Voltage Data Bus Drive (DBDA) External pull-up Vo. | Output Low Voltage Ves V | t=2ma \\ Leakage Current vA_|_Vin=Voo Vin Input High Voltage External Interrupt 35 v Vit Input Low Voltage (EXT INT) 08 Vv Vic Input Clamp Voltage 15 Vo] y= 185 yA ha Input High Current 10 uA | Vin=Voo Ie Input Low Current -225 uA | Vin =2V \\ Input Low Current -150__ |~500 uA_| Vin=Ves Vou | Output High Voltage 1/0 Port Option A 39° | Voo Vi] tow = —30 pA Vou | Output High Voltage (Standard Pull-up) 29 Voo Ve | ton = ~150 yA Vo. | Output Low Voltage Ves, 04 V | to =1.6 mA Vin Input High Voltage 29° | Vo V__| Internal pull-up to Voo® Vit Input Low Voltage Vss, 08 v i Leakage Current 10 uA | Vin=Voo ir Input Low Current -16 mA | Viv=0.4 Vox | Output High Voltage 1/0 Port Option B External pull-up Vo. | Output Low Voltage (Open Drain) Vss 04 Vi | ty =2ma Vin Input High Voltage 299 | Voo vile Vie Input Low Voltage Ves 08 v ir Leakage Current 20 wA_| Vn=+12V Von | Output High Voltage W/O Port Option C 375 | Voo Vv | low=—1mA Vo. __| Output Low Voltage (Driver Pull-up) Vss. 04 V__ | top =1.6 mA Notes 4. Pullup resistor to Vop on CPU. 2. Positive current is defined as conventional current flowing into the pin referenced. Hysteresis input circuit provides additional 0.3 V noise immunity while internal/external pull-up provides TTL compatibility, 44. Measured while 1/0 port Is outputting a high level. 5. Guaranteed but not tested. ———— 362

eee) F3851/F3856 Table 8 F3856 PSU DC Characteristics Symbol | Parameter [Signal | Min. | Max. [| Units | Test Conditions Vin Input High Voltage Data Bus (DBp -DB7) 29 Voo Vv Vi Input Low Voltage Vss 08 v Vox | Output High Voltage 39 | Vpoo V | lon = —100 pA Vo. _| Output Low Voltage Vss 04 Vv | lp =1.6mA tin Input High Current 3.0 yA Vin = Vop, 3-state mode loi Input Low Current -30 A_| Viv=Ves, 3state mode 3 Vin Input High Voltage. Clock Lines (¢, WRITE) 40 Voo v Viv input Low Voltage Vss 08 v \\ Leakage Current 3.0 pA Vin = Vop Vin Input High Voltage Priority In and Control 35 Vo Vv Vie Input Low Voltage Lines (PRI IN, ROMCo - Vss. 08 v i Leakage Current ROMC,) 3.0 A Vin =Vop Vox Output High Voltage Priority out (PRI OUT) 39 Voo Vo | ton= —100uA Vou Output Low Voltage Vss 04 v lo. = 100 vA Von Output High Voltage Interrupt Request V_— | Open-drain output” Vor Output Low Voltage (INT REQ) Ves Vo] lo, =1.0mA I Leakage Current wA__| Vin =Vpp Vou Output High Voltage Data Bus Drive (OBDR) External pull-up Vo. | Output Low Voltage Vss Vv | to. =20mA i Leakage Current uA Vin = Vop Vox Input High Voltage 39 Voo Vv low = 21.0 mA. Vou __| Output Low Voltage Vss 04 v_| lo. = 20mA Vin Input High Voltage External Interrupt 29 Voo V_— | hy = 130 pA (internal pull-up) Vic Input Low Voltage (XT INT) Ves 08 v \\ Input Low Current -16 mA Vin =0.4 V Vou Output High Voltage VO Port Option A 39 Yoo VT ton = -30nA® Vou Output High Voltage (Standard Pull-up) 29 Voo v Jou = —150 pA Vo. —_| Output Low Voltage Vss 04 Vv | lop =1.6mA Vin Input High Voltage 29 Vop Vv Internal pull-up to Vop® Vie Input Low Voltage Vss 08 Vv Mn Input Low Current -16 mA Vin = 0.4 Vi Vou Output High Voltage VO Port Option B External pull-up Vou Output Low Voltage (Open Drain) Vss 04 Vv lop =2 mA? Via Input High Voltage 29 | Voo v Vie Input Low Voltage Vss 08 v Vox Output High Voltage 1/0 Port Option C 4.0 Vo Vv lon = —1.0 mA Vo. | Output Low Voltage (Driver Pull-up) Vss 04 Vv | to =2.0mA Notes 1. Pullup resistor to Vop on CPU. 2. Positive curent is defined as conventional curent flowing into the pin referenced. 3. Hysteresis input circuit provides additional 0.3 V noise Immunity while interallexternal pullup provides TTL compatibility, 4. Measured while 110 por is outputing a high level 5. Guaranteed but not tested el 3-53

ene] F3851/F3856 Mask Options Thermal Resistance Values The ROM array may contain object program code, tables of Plastic —_ nonvarying data, or both. Every PSU is implemented using a @q Wunction to Ambient) = 60°C/W (Still Air) custom mask that specifies the state of every ROM bit, as Qc Wunction to Case) = 42°C/W well as certain address mask options that are external to Cami the ROM array. 3k opti ified: Cora array. The following mask options are spec @a (Junction to Ambient) = 48°C/W (Still Air) 1. The 1024 or 2048 bytes of ROM storage. This reflects 4c Wunction toCase) — =33°CW programs and permanent data table stored in the PSU memory. Recommended Operating Ranges 2, The Sit or 6-bit page select. This defines the PSU The recommended operating ranges of the PIO devices are address space. shown below. four PSU I/O port addresses. Voo ‘Supply Voltage +475V 45V +5.25V 4. The 16-bit interrupt address vector, excluding bit 7. Vea ‘Supply Voltage +114V 0 412V0 +126V V. Ground ov 5. The 1/0 port output option. The choices are the standard “ss_Sroune. pull-up (option A), the open-drain (option B), and the driver pulkup (option C). Ordering Information PSU Mask Option Formats oo Temperature The format for mask options must be submitted to Fairchild Part Number Package Range* Microprocessor Division before device manufacture. The F8510C Ceramic c data to be stored in permanent memory may be submitted F3851DM Ceramic. M in the form of an EPROM or HP2644/HP2645 cartridge F3851PC Plastic Cc (Formulator format only). Other options must be specified F3856DC Ceramic C on the Fairchild ROM Code Entry Form, available from a FO856DM Ceramic Mw Fairchild representative. F3856PC Plastic Cc *C = Commercial Temperature Range 0° to +70°C Absolute Maximum Ratings = Limitea Temperature Range - 40°C to + 85°C 4 = Military Temperature Range ~ 55°C to + 125°C These are stress ratings only, and functional operation at these ratings, or under any conditions above those indi- cated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Supply Voltage Veg -03V, +15V Supply Voltage Voo -0.3V, +7V MO Port Open Drain Option -03V, +15V External Interrupt Input (F3851) = 600 wA, +225 yA Other 1/0 Port Options -03V, +7V All inputs and Outputs ~03V, +7V Storage Temperature ~55°C, +150°C Operating Temperature 0°C, +70°C SS 364