F3850

Fairchild Semiconductor

The Fairchild F3850 is the Central Processing Unit (CPU) for

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| F3850 FAIRCHILD eee eee | ‘A Schlumberger Company Central Processing Unit (CPU) Microprocessor Product

Description

The Fairchild F3850 is the Central Processing Unit (CPU) for ‘© 8-Bit Arithmetic and Logic Unit, Supporting Both Binary and ‘the F8 8-Bit Microprocessor family. The F3850 contains more Decimal Arithmetic ‘than 70 instructions in its instruction set and operates on 8-bit © Interrupt Control Logic units of information. © Power-on Reset Logic ® Clock Generation Logic Within the CPU Chip, With Crystal © N-channel Isoplanar MOS Technology and External Ciock Generation © 2s Cycle Time ‘© More Than 70 Instructions © 64-Byte Scratchpad on the CPU Chip. © +5 V and +12 V Power Supplies ‘© Two Bidirectional, 8-Bit I/O Ports, with Output Latches © Low Power Dissipation (Typically Less Than 330 mW) a ‘Signal Functions ‘Connection Diagram = |o iNTREQ | <— | F upr eo «oj mz <—— | ware ice} —» | Wines write (2 fF) xz cuoce | 4 barux nomc,| > Yoo (]3 [my —+ |x rome, Veo (]4 a Denes — | conrnoe > |xnz Romc, | —_» | LINES Wats w]e owes] —» oes e os om <+|e str ule onal lie exrnes| <— reser Wats ch + | 082 (9 a2 [TJ oes <> |i 08 a CJ 10 Po on rd |i oe, cn Py ord + | es cf bs, C2 29) O86 vo | <> | "x 08s para oo 2 2 [ie Peer ion pus we ONES | <> | 7a oe. oe mou Pa +e 08s a] 15 28)», + lion be ote 2s) <>] ioe be, OMG [5] 17 26) ves ee Ward rome, [18 2 [C] inTRes | ion ves | —— nome, [18 2pm |i; vec | powen owe, aif rome, pare Veo} <— Trop view) ee Le al

i F3850 ce Device Organization The contents of the instruction register are decoded by control unit logic, which generates signals to enable specific sequences The logical organization and pins for the F3850 CPU are of logic operations within the CPU chip. In response to the con- illustrated in Figure 1. tents of the instruction register, the contro! unit also generates five signals, ROMCg through ROMC,, that control operations Arithmetic and Logic Unit throughout the microprocessor system. ‘The arithmetic and logic unit (ALU) provides all data manipulating logic for the F3850. It contains logic that operates on a single 8-bit Accumulator ‘source data word or combines two 8-bit words of source data to ‘The accumulator is a general-purpose 8-bit data register, generate a single 8-bit result. Additional information is reported in which is the most common data source and results destination status flags, where appropriate. for the ALU. Operations performed on two units of source data include addition, ‘Scratchpad and ISAR compare, and the Boolean operations (AND, OR, Exclusive-OR). The scratchpad provides 64 8-bit registers that may be used ‘The two sources are input to the ALU through the left and right as general-purpose RAM memory (see Figure 2). multiplexer buses; the result is placed on the result bus. oo Operations performed ona single 8-bit unit of source data include Figure 2. F8 Programming Model complement, increment, decrement, shift right, shift left, and clear. errno. The source is input to the ALU through either the left or right multi- s Ld bad 2 ul s plexer bus; the result is placed on the result bus. LILLITITI san The CPU contains registers for storing various types of data. HI Lo The instruction register holds an 8-bit code, which defines the normeenenres { sicpemenres ano operations to be performed by the CPU. OR DECREMENTED DECREMENTED phe ili Figure 1 F3850 CPU Logical Organization : eas rn wrenauer | POWER ciock wee | CB | Bas Voo Yoo Vas ! t t a woe nobes ca TR tz Hn Tw i

—_—— F3850 The indirect scratchpad address register (ISAR) is a 6-bit register Le., the ISAR is assumed to hold the address of the scratchpad used to address the 64 scratchpad registers. byte that is to be referenced. ‘The first 16 scratchpad bytes can be identified either by instruc- The ISAR may be visualized as holding two octal digits, HI and LO, tions without using the ISAR or referenced through the ISAR. as illustrated in Figure 3. This division of the ISAR is important, ‘The remaining scratchpad bytes are referenced through the ISAR; since a number of instructions increment or decrement the con- Figure 3 ISAR Register 3 | 1 secamuron 9 nen a Reto} i); a a ge (——_}: |): cs come vst sen se

eo BTN. ‘Overflow (O Bit)—When the results of an ALU operation are being interpreted as a signed binary number, since the high-order [é | le]? ] Le Ts] STATUS REGISTER (W) bit (bit 7) represents the sign of the number, some method must be provided for indicating a carry out of the highest numeric bit t_ (bit 6). This is done using the O bit. After arithmetic operations, ‘sIGN the O bit is set to the Exclusive-OR of a carry out of bits 6 and 7. canny ‘The simplification of signed binary arithmetic is described in the F8 and F3870 Guide to Programming; examples are presented below 3 | ZERO ovenrvow 76543210 — BitNumber Accumulator contents: 10110011 wTeARUPT MASTER Valueadded: 01110001 ENABLE Sum: 11100100 Sign (S Bit}—When the results of an ALU operation are being There is a carry out of bit 6 and a carry out of bit 7, so the O bit is interpreted as a signed binary number, the high-order bit (bit 7) reset to.0 (1 1=0). The C bitis set to 1. represents the sign of the number. At the conclusion of instruc tions that may modify the accumulator bit 7, the S bit is set to 76543210 — BitNumber the complement of the accumulator bit 7. Accumulatorcontents: 01100111 Value added: 00100100 os Sum: 10001011 Table 1 Summary of Status Bits There is a carry out of bit 6, but no carry out of bit 7; the O bit is set to1 (1®0=1). The C bits reset to 0. OVERFLOW = CARRY;+CARRYe ZERO = ALU; ALU, ALU; ALU, ALU; ALU, ALU; ALU Interrupts (ICB Bit)}—External logic can alter program execution CARRY = = CARRY, sequence within the CPU by interrupting ongoing operations. SIGN = ALU, However, interrupts are allowed only when the ICB is set to 1; interrupts are disallowed when the ICB is reset to 0. Control Unit Carry (C Bit)—The C bit may be visualized as an extension of an The control unit decodes the contents of the instruction register 8-bit data unit; ie., the ninth of a 9-bit data unit. When two bytes and generates two sets of control signals. These signals are are added, and the sum is greater than 255, then the carry out of transparent to the user. the high-order bit appears in the C bit; e.g. Five control signals (ROMCo through ROMC,) are output by © 76543210 — Bit Number the control unit to identify operations that other chips of the F8 Accumulator contents: 01100101 family must perform. These signals are described in the "ROMC Valueadded: 01110110 Signals” section. Sum: 047011011 'n Logle terruy There is no carry, so C is reset to 0. : This oye handles the interrupt requests. For a complete lator contents: c 6 ate a ~ Bit Number description refer to the “Interrupt” discussion within the Valueadded: 11010001 Instruction Execution” section Sum: 101101110 Power on Detect There is a carry, so Cis set to 1. When the External Reset (EXT RES) signal is pulled low and then returned high, or when power is turned on, the power on detect Zero (Z bit)—The Z bit is set whenever an arithmetic or logical logic sets the PC registers to 0, causing a program originating at ‘operation generates a zero result. The Z bit is reset to 0 when an memory location Oto be executed, Also, the interrupt control arithmetic or logical operation could have generated a zero result status bits set low, inhibiting interrupt acknowledgement. The but did not. system is locked in an idle state while EXT RES is held low. Leanne ant

a Signal Descriptions ‘The F3850 input and output signals are described in Table 2. a Table 2 F3850 Signal Descriptions a toon ‘Clock ¢ 1 Clock These output signals drive all other devices in the F8 family. WRITE 2 write XTX 39 Crystal Clock The XTLX output signal is used when generating the system clock in the crystal mode (with the XTLY and XTLZ signals). XTLY 38 External Clock ‘The XTLY input signal is used with the XTLX signal when generating the system clock in the crystal mode, and is also used for operating in the external clock mode. xTLZ 40 Crystal Clock This input signal must be grounded for crystal clock or external clock. VO Port WorOa 16, 11, 10, 5, 36, 31, 30, 25 VO Port Zero ‘These bidirectional signals are ports through which the CPU communicates with logic external to the microprocessor system. WO 14, 13,8, 7,94, 33, 28,27 | VO PortOne Interrupt ie 22 Interrupt Control _| The ICB output signal indicates whether or not the CPU is Bit currently ignoring the INT REQ line. if the ICB signal is low, the CPU responds to interrupt requests; if the ICB signal is high, the CPU ignores interrupt requests. WWTREQ. 23 Interrupt Request | This input line is used to signal the CPU that an interrupt is being requested. The F3851 PSU, F3861 and F3871 PIOs, and F3853 SMI devices contain logic to initiate interrupt requests by pulling the INT REQ signal low. The CPU acknowledges interrupt requests by outputting the appropriate ROMC signals. Control ROMCo- v2 Control The ROMC output signals control logic operations for other ROMC, devices in the F8 family. These signals assume a state early in ‘each machine cycle and hold that state for the duration of the cycle. Refer to the “instruction Execution” section for further discussion and a summary table of the ROMC interpretation by CPU logic. SS 312

a F3850 has a unique address space, i.e., a unique block of memory As referenced in the “ROMC Signal Functions” section, each addresses within which it responds to memory access ROMC state is identified by individual signal line states (1 for ‘commands. high, 0 for low), and by a two-digit hexadecimal code. The hexadecimal code is used to identify ROMC states throughout For example, an F3851 PSU may have an address space of this data sheet. Also given in the “ROMC Signal Functions” section H'0000' through H'03FF"; an F3852 DMI may have an address is the instruction cycle length (short or long) implied by each code, ‘space of H'0400' through H‘07FF’. Ifa microcomputer system has plus the way in which codes must be interpreted by the other these two memory devices and no others, then the F3851 PSU F8 devices. will respond to memory access commands when the PCO or DCO registers (whichever are identified as the address source) contain Instruction Execution Sequence a value between H’0000’ and H‘03FF’; the F3852 DM! will Every instruction execution sequence ends with an instruction respond to addresses in the range H'0400' through H’'07FF’.No code being fetched from memory to identify the next instruction device will respond to addresses beyond H’'07FF’, even though cycle. The instruction code is loaded into the CPU instruction ‘such addresses may exist in PCO and/or DCO. register, out of which it is decoded by the CPU control unit logic. An instruction fetch is executed during the last instruction cycle Each device compares its address space with the contents of PCO of the previous instruction, as illustrated in Figure 9. and DCO, whichever is identified as the address source, and only responds to a memory access command if the contents of PCO or ‘There is a group of F8 instructions that cause operations to occur DCO is within the device's address space. entirely within the F3850 CPU. These instructions do not use the data bus, therefore can execute in one cycle. Since one-cycle in- It all memory address registers (PCO, PC1, DCO, and DC1) are to ‘structions do not use the data bus, no ROMC state needs to be contain the same information, then ROMC states that require any generated for the one-cycie instruction being executed; therefore, of these registers’ contents to be modified must be acted upon by a illustrated in Figure 9, ROMC state 0 is specified, causing the all devices containing any of these four registers. If devices are instruction fetch of the next instruction. not to compete when an ROMC state specifies that a memory access must be performed, then only a device whose address Multi-cycle instructions must end with a cycle that does not use ‘space includes the identified memory address must respond to ‘the data bus; ROMC state 0 is specified at the beginning of this the ROMC state. last instruction cycle, causing the next instruction to be fetched. As illustrated in Figure 8, the five ROMC signals that define the Following an instruction fetch, CPU logic decodes the fetched ROMC state are output early in the instruction cycle and are main- instruction code and executes the specified instruction. There tained stable for the duration of the instruction cycle; i.e., onlyone are Five types of instruction cycles that can follow. ROMC state can be specified per instruction cycle. Therefore, devices can only be called upon to perform one instruction execu- 1. Operations may all be internal to the CPU. This will be the last tion related operation per one instruction cycle. or the only cycle for an instruction, and will specify ROMC state 0, as illustrated in Figure 9. Figure 8 ROMC Timing Signals Output by F3850 CPU on ee | tT _.| le Sf \\ ee D*N "FN fowl Tone erer a ee 3-15

Data may be transferred between the F3850 CPU and Refer to the “Instruction Cycle Execution and Timing” section for memory devices. See the “Referencing Memory” section. alist of the instruction cycles and their associated ROMC state. 3. Data may be transferred from one memory device to all memory devices. The CPU is not the transmitter or the Referencing Memory receiver of data in this transfer. See the “Memory-to-Memory Memory may be referenced during an instruction cycle either to Data Transfers” section. transfer the data from the CPU to a memory word or to transfer 4, Data may be transferred to or from an I/O port, as described data from a memory word to the CPU. A memory reference in the “Input/Output interfacing” section. ‘occurs as shown in Figure 10. 5. An interrupt may be acknowledged, as described in the “Interrupts” section. If datais being output by the CPU, then the delay before data out- put is stable will be tdb, when data comes from the accumulator; Every F8 instruction is executed as one, or a sequence of, the instruction cycle will be long. The delay before data output is standard instruction cycles. Timing for the standard instruction stable will be tdb when data comes from the scratchpad; the cycles is illustrated in Figures 9, 10, 11 and 12 instruction cycle in this case will also be long. Figure 10 Memory Reference Timing rw, wm/A NY CUNY | 1 | | bt | DATABUS (1) | x | | I tp (GH PEDANCE) 1 T i i I oaTaeus(n 1 X! 1 —— ] i | I patasus I x ] + | ks ——\\+} paTasus x DATASTABLE I bk — “1 DaTABUS x DATASTABLE | (1) Timing for CPU outputing data onto the data bus. (2) There are four possible cases when inputting data tothe CPU, via the data bus lines which depend on the data path and the destination nthe CPU, as follows: (Delay tai the delay whon data is coming from the accumulator. ‘db Destination — IR (instruction Fetch) Delay tab, is the delay when datas coming from the scratchpad (or trom a ‘db: Destination — Accumulator (with ALU operation — AM) memory device). ‘dbs: Destination — Scratchpad (LA KP etc) {bg Destination — Accumulator (no ALU operation — LM) Delay tab isthe delay for the CPU to stop driving the data bus Ineach case a stable data hold time of 50s from the WRITE reference point ‘isroquired Sl 347

If data is being input to the CPU, then the delay before incoming 1/O port pin is a “wire-AND" structure between an internal latch data must be stable depends on the destination of the data, as and an external signal, if any. The latch is always loaded directly illustrated in Figure 10. from the accumulator. The type of data transfer is identified by the ROMC state that is Each F8 I/O pin can be set high or low under program control. ‘output at the beginning of the instruction cycle. Ita (high) is presented at the latch, then gate (b) turns on and gate (a) turns off, so that P is at Vs (low). If a 0 (low) is presented The instruction fetch may also be viewed as a memory reference at the latch, then gate (a) turns on and gate (b) turns off, so that P ‘operation where the destination is the instruction register. Timing is at Vpo (high). for this case is illustrated in Figure 9. When outputting data through an I/O port, the pin can be ‘Memory-to-Memory Data Transfers connected directly to a TTL gate input (“TTL Device Input” In response to appropriate ROMC states, data can be trans- in Figure 13). Data is input to the pin from a “TTL Device ferred from one memory device to all memory devices during Output" in Figure 13. ‘one instruction cycle. For example, data can be transferred from a memory byte within (or controlled by) one memory In normal operation, high or low levels at P drive the external device, to one byte of an address register (PCO or DCO) within TTL device input transistor (d). If a low level is set at P, transistor all memory devices. (d) conducts current through the path J, 1, P, and FET(b). This is transferred as a low level to the rest of the circuits in the TTL Three ROMC states (C, E, and 11) specify operations of this type, device and results in a high or low level at the output of the and Figure 10 illustrates timing for the data transfer. device, depending on its characteristics. If the level at P is set In Figure 10, tdb. is the delay until data from memory ora high, transistor (d) does not conduct current, and a high level is memory address register is stable on the data bus. transferred by (d). Input/Output Interfacing When data is input to the I/O pin, high or low levels at 0 drive the Programmed I/O in the F8 microcomputer system is influenced hysteresis circuit in the port and result in logic ones or zeros being by the design of the |/O port pins. As illustrated in Figure 13, each transferred to the accumulator. Figure 13 F8 I/O Port Bit —---— ee 7 ‘oo Yoo 1 | o | | ° | | Co | n oe ’ 1 oureur Loi Srnose | Tr bevice weUT waren » | Vss | | a ] | oo I | vvsTEREsis CRCUIT | | 4 Live Tr peviee oureur Wooresnzeron, SSS 3.19

Nm] F3850 ‘Since the I/O pin and the TTL device output at 0 are wire-ANDed, nothing happens until the next interruptable instruction comes to itis possible for the state of one to affect the transfer of data out the end of execution. In the case of the EXT RES signal, from the /O pin or in from the TTL device output. For example, if ‘execution of the interrupt routine begins in the machine cycle the latch in the I/O port is set so that the pin is clamped low by immediately following that in which the signal goes low, pro- (b), then the level at 0 cannot pull P high. Conversely, if P is vided that the setup time specified in Figure 12 has been met. The clamped to a low level by (c), setting the latch for a high level EXT RES signal response logic ignores the ICB signal. has no effect. In response to the INT REQ signal being low, when the CPU. All /O port bits should be set for a high level, before data input, to acknowledges the interrupt, it forces the ICB signal high and prevent incoming logic zeros from being “masked” by logic ones initiates instruction cycles with ROMC states 1C, OF, 13, and 00, in present at the port from previous outputs. In some instances, the that order. This causes program execution to branch to the inter- ability to mask bits of a port to logic 1 is useful. (Note that logic 1 rupting device's address vector. becomes a 0 V electrical level at the I/O pin; logic 0 corresponds toa high electrical level.) In response to the EXT RES signal being low, when the CPU acknowledges the interrupt, it forces the ICB signal high, then ‘The F8 CPU can execute two types of programmed 1/0 initiates instruction cycles with ROMC states 1C, 08, and 00, in operation: that order. This causes program execution to branch to memory location 0. 1) VO via the two CPU ports (0 and 1) 2) V/O via ports on the other devices The ICB signal is pulled low by the E1 instruction and is returned high by the D1 instruction. Input/Output operations that use the two CPU I/O ports execute in two instruction cycles. During the first cycle, the fetched Instruction Set Summary instruction is decoded; the data bus is unused. In this cycle data is either sent from the accumulator to the 1/O latch or enabled ‘The F3850 CPU instruction set is summarized in Table 3. This sec- from the I/O pin to the accumulator, depending on whether the tion does not attempt to give complete directions for programming instruction is an output or an input. At the falling edge of the the F8 microcomputer system; it explains signals and timing WRITE signal (marking the end of the first cycle and beginning of associated with the execution of every instruction. Refer to F8 the second cycle), the data is strobed into either the latch (OUTS) and F3870 Guide to Programming for programming details. or the accumulator (INS), respectively. The second cycle is then The columns used in Table 3 are described below. used by the CPU for its next instruction fetch. Figure 11 illustrates VO timing. Op Code—The Op Code is the instruction mnemonic that appears in the mnemonic field of an assembly language Note that for the data input (INS) the setup and hold times instruction and identifies the instruction. specified are with respect to the WRITE pulse occurring at the end of the first cycle in the two-cycle instruction. For output data ‘Operand (s)—If the instruction contains any information in the (OUTS) the delay is specified with respect to the falling edge operand field of the assembly language source code, the infor- of the WRITE signal marking the beginning of the second cycle in mation is shown in this column. Arrows identify the portion of the two-cycle instruction. object code that represents the operand field. Any portion of ‘object code that does not represent the operand field must Input/Output instructions that address /O ports with an I/O port represent the mnemonic field. Table 4 explains symbology used address greater than H'OF’ occupy two bytes; the first byte in the operand field. specifies an IN or OUT instruction, while the second byte provides the /O port address. Required timing at I/O port pins is Object Code—This is the hexadecimal representation of the given in the section of this data sheet that describes the device instruction's object code. The first byte of object code, or in containing the addressed I/O port. some cases'the first hexadecimal digit of object code, represents the Op Code. The operand is represented by the second and third Interrupts bytes of object code, if present, or in some cases by the second There are three CPU signals with interrupt processing; timing hexadecimal digit ofthe first object code byte. Refer to Table 4 for for all signals is illustrated in Figure 12. symbology used in the object code field. An interrupt sequence is initiated by pulling either the INT REQ ‘Cycle—This column identifies each instruction cycle for every signal or the EXT RES signal low. In the case of the INT REQ. instruction. Every cycle is listed on a separate horizontal line and signal nothing happens unless the ICB signal is low. Also, is identified by the letter S for a short (four clock period) cycle or SNe ene el 3-20

Table 3. Instruction Cycle Execution and Timing (Continued)

a ‘Table 3 Instruction Cycle Execution and Timing (Continued) op Object ROMC ust e 68+e o | 3s -|-|-]- ISARL ~ Oe" us a Ta o | 3s -|-|-|- A~ H0e" BT ail ad 1c 0 -J-|J-|- Test e a W register i 3 ° -|-|-|- Res = 0s0 PCO = (PCO) + 2 o | 3s 1c 0 —~|-J-|j- 1 2 -j-|-]- Teste AW register - -|-|-|- Res ¥ 0 so PCO = (PCO) o | 3s +H +t AM 88 2 4 -|-|]-J- vo | vo | 0 | 10 A~ (A) + ((0CO)) Binary, o | 3s DCO ~ (DC) +1 AMD 89 2 4 -|-|-|- vo | v0 | 0 | 10 ‘A~ (A) + ((0C0)) Decimal, DCO ~ (DCO) +1 o | 3s -|-|-|- NM 8A 2 4 o | w]o]w A~ (A) a ((0CO); o | 3s -|-|-|- DCO — (DCO) +1 OM 8B 2 4 oO vo 0 vo A= (A) a ((DCO)): o | 3s -|-j-j- DCO - (DCO) +1 XM ac 2 4 o | w}o | wo A= (A) & ((DCO)); cM 80 2 4 vw | v0 | | wo Set status flags on basis, ADC 8 A 1 -|-|-|- DC ~ (DC) + (A) i) 3s - _ _ _ BR7 ij 8F 3 ) _ _ - _ PCO — (PCO) + 2 ii o | 3s -|-|-]- because (ISARL) = 7 1 2 - - - _ PCO — (PCO) + Hii +1 o | 3s -|-|-|- because (ISARL) # 7 BF til st 1c 0 -|-|-|- Test t 4 W. register ii 1 2 -|-|-|- Res = 0so PCO = (PCO) 1c ° ~-{-|[-|- Test ta W. register 3 0 -|-jJ-|- Res # 0s0 PCO = (PCO) + 2 o | 3s -|-|-|- INS Oort A0,At 1c 0 o| wi] o| w A= (VO PortOor1) o | 3s -|-|-|- INS 4 AA 1c 0 o| wi o}| w DB — Port address (4 thru 15) thru thru 1B 6 -|-|-|-

8 AF o | 3s -|-|-j|- A~ (Port4thru 15)

outs | dort Bo, 81 1c 0 —-|-|-|- VO PortOor1 — (A) o | 3s -|-|-|- outs | 4 B4 1c 0 -|-|-|- DB ~ Port address (4 thru 15) thru they 1A 1 -|-jJ-|-

6 BF o | 3s -{-|-|- Port (4 thru 15) (A)

Table 3 Instruction Cycle Execution and Timing (Continued) op Object [___Status Fiags 2 |onmmtn| | oe [RE rane [oe | e [S| ee | AS r Cr s 0 3s |vo | 10} 1} 10 A~ (A) + (1) Binary ASD. r Or Ss 1c ty vw | vw} w |” A=— (A) + (1) Decimal s 0 ss |— |-|]-]- xs r Er s 0 3s [0 |] 0 | w A-(A) OI 3 | NS r Fr s 0 3s o |wi}o!w A-Av() INTRPT xx L 1c o }/—-;-]-]- IDLE L oF 2};-}]-]-j- PCOL ~ Int. address (lower byte); PC1 — PCO L 13 2 -{-J-|J- y PCOU - Int. address (upper byte) L 8 1}/-]-J-]- y PCO —0,PC1— PCO Table 4 Instruction Execution and Timing Symbology Symbol Interpretation ‘Symbol Interpretation A The accumulator ISAR, The 6-bit scratchpad address register ) The complement of accumulator contents ISARL The low order three bits of ISAR. a Asingle hexadecimal digit being interpreted as ISARU The high order three bits of ISAR data J Scratchpad byte 9 aa ‘Two hexadecimal digits being interpreted as a ii ‘Two hexadecimal digits being interpreted as the single byte of data or as the high order byte of 16 low order byte of a 16-bit address bits of data kK Scratchpad bytes 12 and 13 bb ‘Two hexadecimal digits being interpreted as the KL Scratchpad byte 13 low order byte of 16 bits of data ku Scratchpad byte 12 Binary Binary arithmetic specified ° The overflow status flag c The carry status flag Pp Asingle hexadecimal digit being interpreted as an 0B F8 system data bus VO port address (0-15) DCO —The primary data counter register PP ‘Two hexadecimal digits being interpreted as an 1/0 DCOL The loworder byte of the primary data counter port address (0-255) register PCO —_—_The program counter register DCOU The high order byte of the primary data counter PCOL The low order byte of the program counter register register PCOU The high order byte of the program counter DC1 —_The secondary data counter register register Decimal Decimal arithmetic specitied PC1 —_—_Thestack register e Asingle octal digit being interpreted as data PCIL The low order byte of the stack register H Scratchpad bytes 10.and 11 PCIU —_Thehigh order byte of the stack register it ‘Two hexadecimal digits being interpreted as the Q Scratchpad bytes 14 and 15 high order byte of a 16-bit address or as a simple aL Scratchpad byte 15 byte address displacement Qu Scratchpad byte 14 SO eel 3.25

a Table 4 Instruction Execution and Timing Symbology (Continued) se SS Symbol Interpretation Symbol Interpretation i Sym r ‘Single hexadecimal digit interpreted as scratchpad Zz The zero status flag address: A The logical OR of 8-bit quantities on each side of 4 = 0 through B for locations 0 through B in this symbol is specified scratchpad v ‘The logical AND of 8-bit quantities on each side of r= C for ISAR as address source with no change this symbol is specified after access ® ‘The logical Exclusive-OR of 8-bit quantities on 1 = D for ISAR as address source with each side of this symbol is specified ISARL = ISARL + 1 afteraccess - The value to the right of this symbol is to be loaded 1 = E for ISARas address source with into the location specified on the left of this symbol ISARL = ISARL-1 after access 0 The contents of the location within the brackets is r= Fisnotallowed specified s The sign status flag 0) The contents of the memory word addressed by t Asingle hexadecimal digit identifying a status the contents of the location within the double condition that is tested by a Branch on brackets is specified Condition instruction + The binary address of 8-bit quantities on each side w The status register of this symbol is specified ee Oe ee ROMC Signal Functions Table 5 describes the ROMC signals and their functions. ‘Table ROMC Signal Functions ROMC

43210 Function

9.0000] 00 | S.L | instruction Fetch. The device whose address space includes the contents of the PCO register must place on the data bus the op code addressed by PCO; then all devices increment the contents of PCO. 00001] 1 L__ | The device whose address space includes the contents of the PCO register must place on the data bus the contents of the memory location addressed by PCO; then all devices add the 8-bit value on the data bus, asa signed binary number, to PCO. 0.0010] 02 | L__ | Thedevice whose DCO addresses a memory word within the address space of that device must place on the data bus the contents of the memory location addressed by DCO; then all devices increment DCO. 0.0011] 03 | LS | Similarto 00, except that itis used for Immediate Operand fetches (using PCO) instead of instruction fetches. 00100] 04 | S$ _ | Copythe contents of PC1 into PCO. 00101| 05 L__ | Store the data bus contents into the memory location pointed to by DCO; increment DCO. 00110] 06 | L_ | Placethe high order byte of DCO on the data bus. 00111| 07 | L_ | Placethe high order byte of PC1 on the data bus. 01000] 08 L__| Alldevices copy the contents of PCO into PC1. The CPU outputs zero on the data bus in this ROMC state. Load the data bus into both halves of PCO, thus clearing the register. 01001] 09 L__ | The device whose address space includes the contents of the DCO register must place the low order byte of DCO onto the data bus. 01010] 0a | L_ | Alldevices add the 8-bit value on the data bus, treated as a signed binary number, to the data counter. 010111 0B | L_ | Thedevice whose address space includes the value in PC1 must place the low order byte of PC! on the data bus. EE 3-26

Table 5 ROMC Signal Functions (Continued) ROMC. Cycle

43210 Length Function

01100] oc | L_ | Thedevice whose address space includes the contents of the PCO register must place the contents of the memory word addressed by PCO onto the data bus; then all devices move the value that has just been placed on the data bus into the low order byte of PCO. 01101] 0D | S$ | Alldevices store in PC1 the current contents of PCO, incremented by 1; PCO is unaltered. 01110] 0€ | L_ | Thedevice whose address space includes the contents of PCO must place the contents of the word addressed by PCO onto the data bus. The value on the data bus is then moved to the low order byte of DCO by all devices. 01111] OF | L_ | Theinterrupting device with highest priority must place the low order byte of the interrupt vector on the data bus. All devices must copy the contents of PCO into PC1. All devices must move the contents of the data bus into the low order byte of PCO. 10000] 10 L_| Inhibit any modification to the interrupt priority logic. 10001] 11 L__| Thedevice whose memory space includes the contents of PCO must place the contents of the addressed memory word on the data bus. All devices must then move the contents of the data bus to the upper byte of DCO. 10010] 12 L__ | Alldevices copy the contents of PCO into PC1. All devices then move the contents of the data bus into the low order byte of PCO. 100114] 13 L_ | The interrupting device with highest priority must move the high order half of the interrupt vector onto the data bus. All devices must move the contents of the data bus into the high order byte of PCO. The interrupting device resets its interrupt circuitry (so that it is no longer requesting CPU servicing and can respond to another interrupt) 10100] 14 L__ | Alldevices move the contents of the data bus into the high order byte of PCO. 101014] 15 L_ | Alldevices move the contents of the data bus into the high order byte of PC1. 10110] 16 L_ | Alldevices move the contents of the data bus into the high order byte of DCO. 10111] 17 L_ | Alldevices move the contents of the data bus into the low order byte of PCO. 11000/ 18 L_ | Alldevices move the contents of the data bus into the low order byte of PC1. 11001] 19 L_ | Alldevices move the contents of the data bus into the low order byte of DCO. 11010] 1A] L | During the prior cycle, an 1/0 port timer or interrupt control register was addressed; the device containing the addressed port must move the current contents of the data bus into the addressed port. 11011] 18 | L | During the prior cycle, the data bus specitied the address of an I/O port. The device containing the addressed 1/O port must place the contents of the I/O port on the data bus. (Note that the contents of timer and interrupt control registers cannot be read back onto the data bus.) 11100] 1¢ | Lors} None. 111014] 1D} S | Devices with DCO and DC1 registers must switch registers. Devices without a DC1 register perform no operation. 11110) 1€ L The device whose address space includes the contents of PCO must place the low order byte of PCO onto the data bus. 11111) 1F L The device whose address space includes the contents of PCO must place the high order byte of PCO onto the data bus. Ne ee 3-27

a F3850 ce Timing Characteristics ‘The timing characteristics of the F3850 are described in Table 6. Vop = +5 V 5%, Vag = +12 V 5%, Vgg= OV, Ta = O°C to +70°C [sansa ssn Table6 F3850 CPU Signal Timing Characteristics Seat | Ghanies [mmm [Mee [vate | TniConatone Extended Temp. Range ns Extended Temp. Range a Extended Temp. Range 400 ns Extended Temp. Range 400 Pag | wareremasor | fw fit | pu | wrens ng | few | it wf esate fw | i | wo ratin fs | | it «| a ww | tease | wo ff it | ‘external timing generation, and possible external RAM timing, The remaining 3. ININT REO is being supplied asynchronously, it can be pulled down at any ‘parameters are typically those that are only relevant between FB devices, and time except during a fetch cycle that has been preceded by a non-privileged ‘not normally of concern to the user. outer Inthat case INT REQ must go down according to the requirements a 3-28

a Supply Currents Absolute Maximum Ratings ee Test Veo 03 V, HBV ‘Symbol Parameter Min Typ Max Unit Conditions Vpo -03 V,47V HE, XTLX, XTLY, and XTLZ -0.3 V,+15V lop Voo Current 4575 ~~ mA_—_ Outputs All other inputs 03 V,+7V Unloaded Storage temperature ~85°C, +150°C rr Operating temperature 0° C, +70°C loc Veg Current 12 30. mA _— Outputs Unloaded ‘These are stress ratings only, and functional operation at these ——_ ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum ——_ rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may Recommended Operating Ranges cause permanent damage to the device, The recommended operating ranges of the F3850 are shown below, ee oe __ ‘Supply Voltage (Vpp) ‘Supply Voltage (Vac) _PartNumber Min, Typ Max Min Typ Mx Msg F3850 +4.75V +5V +5.25V +114V +12V +126V ov rE ‘Ordering Information oo Order Code Package ‘Temperature Range F3850DC Ceramic 0°C to+70°C F3850DM Ceramic 55°C to +125°C F3850PC Plastic OPC to +70°C _Fsesopc Paste Cr 3:30

Product Information

F3850 specifications and overview.

Summary

Central Processing Unit (CPU)

Description

The Fairchild F3850 is the Central Processing Unit (CPU) for

Source title F3850 Datasheet(PDF) - Fairchild Semiconductor

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