Microcontroller

F369GA

fujitsu semiconductor

32-BIT RISC MICROCONTROLLER

Manufacturer: fujitsu semiconductor

Document: 206 Pages / 2Mb

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MB91F369GA FUJITSU | Alldatasheet

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32-bit RISC Microcontroller CMOS FR50 Family MB91360G Series MB91FV360GA/F362GA/F369GA I DESCRIPTION The Fujitsu MB91360G series is a standard microcontroller containing a wide range of I/O peripherals and bus control functions. The MB91360G series features a 32-bit RISC CPU (FR50 series) core and is suitable for embedded control applications requiring high-performance and high-speed CPU processing. The MB91360G series also contains up to 4 Kbytes instruction cache memory and other internal memories to improve the execution speed of the CPU. I FEATURES

Execution time : down to 15.6 ns (64 MHz)
FR50 series CPU : RISC architecture The CPU has a general-purpose register architecture with improved numeric implementation whereby a wide range of delayed branch instructions reduces losses in execution time due to pipeline breaks. Bit manipulation instructions and memory access instructions have been enhanced resulting in improved code efficiency and execution speed for control implementation.
A five-stage pipeline structure provides high-speed processing (one instruction per cycle)
32-bit linear address space : 4 Gbytes
Fixed 16-bit instruction size (basic instructions)
High-speed multiplication/step division
High-speed interrupt processing (6 cycles)
General-purpose registers : 16 × 32 bits (Continued) I PACKAGE 401-pin Ceramics PGA 208-pin plastic QFP 160-pin plastic QFP (PGA-401C-A02) (FPT-208P-M04) (FPT-160P-M15)

(Continued)

External bus interface unit with a wide range of functions Divides the external memory space into a maximum of eight areas. Chip select signal setting, data bus width selection (8, 16, 32-bit) , and area size can be specified for each area.
Address bus up to 32 bit wide
Programmable auto-wait function
Internal instruction cache The MB91360G series contains up to 4-Kbyte instruction cache to improve the execution speed of external programs.
Two-way set associative caching
DMAC Direct memory access (DMA) can be used to perform various types of data transfer without going via the CPU. This improves system performance.
Eight channels (including up to 3 external channels)
Three transfer modes supported : single/block, burst, continuous transfer
Power consumption control mechanisms The MB91360G series contains a number of functions for controlling the operating clock to reduce power consumption.
Software control : Sleep and stop/real time clock functions
Hardware control : Hardware standby function
Gear (divider) function : The CPU and peripheral clock frequencies can be set independently.
Contains a range of peripheral functions
UART, U-timer
Real Time Clock (with optional subclock operation and subclock calibration module)
Stepper Motor Control
Sound Generator
Serial IO (SIO) , SIO-Prescaler
Power Down Reset
Alarm Comparator
IO-Timer
I2C Interface
10 Bit D/A Converter
CAN Interface
10-bit A/D converter
16-bit reload timer
16-bit PWM timer
Watchdog timer
Bit search module
Interrupt controller
External interrupt inputs
I/O port function
Interrupt levels “16 maskable interrupt levels”
Other
Power supply voltage
5 V power supply used, the internal regulator creates internal supply of 3.3 V
Package : MB91FV360GA uses a PGA401 package, MB91F362GA is delivered in a QFP208 package, and MB91F369GA in QFP160 package.

4 KB / 4 KB

/ 4 KB - / 4 KB D-bus RAM 16 KB 12 KB 16 KB F-bus RAM 16 KB 4 KB 16 KB Flash/ROM

512 KB on F-bus

Ext. Interrupt 8 ch 8 ch 8 ch Non maskable Interrupt Real Time Clock 32 kHz subclock option for RTC yes no no subclock calibration yes no no LED port 8 bit 8 bit Power down Reset Bit search Module Watchdog timer Ext. Address Bus 32 bit 21 bit up to 24 bit Ext. Data Bus 32 bit 32 bit 32 bit Ext. DMA 3 ch 1 ch 1 ch Max operating frequency

64 MHz

••• MB91FV360GA (BOTTOM VIEW) (PGA-401C-A02) 120 119 121 122 123 124 125 126 127 128 129 130 131 175 174 176 177 178 179 180 181 182 183 184 185 186 187 231 230 232 233 234 235 236 237 238 239 240 241 242 243 244 284 173 285 286 287 288 289 290 291 292 293 294 295 296 297 188 229 118 334 335 336 337 338 339 340 341 342 343 344 345 346 245 132 172 117 228 333 171 282 379 116 227 332 170 281 378 115 226 331 169 280 377 114 225 330 168 279 376 113 224 329 167 278 375 112 223 328 166 277 374 111 222 327 165 276 373 110 221 326 164 275 372 109 220 325 163 274 371 108 219 324 162 273 370 107 218 323 161 272 369 368 367 366 365 364 363 362 361 360 359 358 320 319 318 317 316 315 314 313 312 311 310 257 144 201 268 267 266 265 264 263 262 261 260 259 258 212 211 210 209 208 207 206 205 204 203 202 155 154 153 152 151 150 149 148 147 146 145 101 100 309 200 106 217 322 321 160 271 270 269 216 215 214 213 159 158 157 156 105 104 103 102 283 380 381 382 383 384 385 386 387 388 389 390 391 298 189 347 246 133 392 299 190 348 247 134 393 300 191 349 248 135 394 301 192 350 249 136 395 302 193 351 250 137 396 303 194 352 251 138 397 304 195 353 252 139 398 305 196 354 253 140 399 306 197 355 254 141 400 307 198 356 255 142 401 308 199 357 256 143 INDEX

••• MB91F362GA (TOP VIEW) (FPT-208P-M04) 156 157 UART PQ [5:0] PP [5:0] PO [7:0] PN [5:0] PM [3:0] P9 [7:0] P8 [7:0] P7 [4:6] P6 [4:0] P5 [7:0] P4 [7:0] P3 [7:0] P2 [7:0] P1 [7:0] P0 [7:0] PS [7:0] PR [7:0] PL [7:0] PK [7:0] PJ [7:0] PI [6:0] PH [7:0] PB [2:0] PG [7:0] CAN PPG SIO I2C XTAL + PLL OCU ICU LED DAC ADC DMA ADC 208 INDEX SMC 105 104 SIN2 SOT1 SIN1 SOT0 SIN0 RX2 TX2 RX1 TX1 RX0 TX0 VSS VDD OCPA7 OCPA6 OCPA5 OCPA4 OCPA3 OCPA2 OCPA1 OCPA0 SCK3 SOT3 SIN3 SCK4 SIN4 SOT4 SCL SDA SGA SGO VCI CPO VSS X1A X0A VDD SELCLK MONCLK INITX HSTX MD2 MD1 MD0 VSS OUT3 OUT2 OUT1 OUT0 IN3 D24 D25 D26 D27 D28 D29 D30 D31 A10 A11 A12 A13 A14 A15 VDD VSS A16 A17 A18 A19 A20 CS4X CS5X CS6X RDY BGRNTX BRQ RDX WR0X WR1X WR2X WR3X AS ALE CLK AH/BOOT CS0X CS1X CS2X CS3X VDD VSS IN2 IN1 IN0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 VSS VDD LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 LTESTX CPUTESTX TESTX ATGX VDD VSS ALARM DA1 DA0 AVSS AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVRH AVCC DEOP0 DACK0 DREQ0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 SOT2 VSS VCC3C VDD HVSS PWM1P0 PWM1M0 PWM2P0 PWM2M0 HVDD PWM1P1 PWM1M1 PWM2P1 PWM2M1 HVSS PWM1P2 PWM1M2 PWM2P2 PWM2M2 HVDD PWM1P3 PWM1M3 PWM2P3 PWM2M3 HVSS VDD D10 D11 D12 D13 D14 VDD VSS D15 D16 D17 D18 D19 D20 D21 D22 D23 Ext. Interrupt Ext. Bus Data Ext. Bus Address Chip Select Ext. Bus Control Chip Select Mode Sound Gen.

••• MB91F369GA (TOP VIEW) (FPT-160P-M15) P0 [3:0] PQ [1:0] PP [3:0] PB [2:0] P8 [7:0] P7 [6:4] PN [5:0] PK [7:0] PG [1:0] PH [7:0] Ext.Bus Control Osci. CAN SIO Mode ADC Ext. Bus Data VSS VDD35 RDY WR0X WR1X WR2X WR3X VSS VDD35 VSS MONCLK VDD VSS VDD OCPA3 OCPA2 OCPA1 OCPA0 VSS VDD SOT0 SIN0 RX1 TX1 RX0 TX0 VSS VCC3C VDDI VDDI VDDI VDDI VSS SCK3 SOT3 SIN3 SCK4 SIN4 D10 D11 D12 D13 D14 D15 VDD35 VSS D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 VDD35 VSS 120 117 119 116 118 115 112 113 114 111 104 106 101 100 102 103 105 107 108 109 110 A10 A11 VDD35 CLK VSS A12 A13 A14 A15 A16 A17 A18 A19 A20 VDD35 VSS CS4X CS5X CS6X RDX BGRNTX BRQ AS ALE AH CS0X CS1X CS2X CS3X DREQ0 DACX0 DEOP VSS VDD35 121 125 130 129 128 123 127 126 124 122 142 141 140 139 137 138 136 135 133 134 132 131 150 149 151 152 148 147 146 145 144 143 159 158 157 154 155 156 153 160 SOT4 SCL SDA SGA SGO INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 VSS VDD LTESTX CPUTESTX TESTX INITX HSTX MD2 MD1 MD0 ATGX VDD VSS ALARM AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS AVCC AVRH PPG UART I C Sound Gen. Ext.Interrupt Ext. Bus Address DMA Chip Select Chip Select Ext. Bus Control PM [3:0] P13

MB91FV360GA I/O Pins and Their Functions (Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function D18 I/O Q Ext. Bus Data Bit 18 D11 I/O Q Ext. Bus Data Bit 11 I/O Q Ext. Bus Data Bit 2 not connected HVSS HVDD5B PWM2M1 I/O PR7 M SMC 1 PWM1M1 I/O PR5 K SMC 1 PWM1P0 I/O PR0 K SMC 0 VDD5R VDD5P SCK4 I/O PN2 A SIO Clock VDD5J EXRAM I P Trace Control TWRX O X Trace Control TAD9 O X Trace Address TAD5 O X Trace Address TAD3 O X Trace Address TDT68 I/O W Trace Data TDT63 I/O W Trace Data TDT57 I/O W Trace Data TDT49 I/O W Trace Data TDT23 I/O W Trace Data TDT16 I/O W Trace Data TDT7 I/O W Trace Data TDT2 I/O W Trace Data ICD0 I/O N ICE Data ICLK I/O L ICE Clock H

4 MHz Oscillator Pin

I U Initial Pin MD1 I T Mode Pin 1 IN3 I/O PL3 A ICU Input 3 INT3 I/O PK3 A Ext. Interrupt 3

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function AN3 I/O PH3 B ADC Input 3 DACK2 I/O PB6 A DMA Acknowledge 2 AN13 I/O PG5 B ADC Input 13 AN8 I/O PG0 B ADC Input 8 ALE I/O P91 A Ext. Bus Control WR1X I/O P85 S Ext. Bus Control RDX I/O P83 S Ext. Bus Control CS7X I/O A Chip Select 7 (CANs) A26 I/O Q Ext. Bus Address Bit 26 A20 I/O Q Ext. Bus Address Bit 20 A12 I/O Q Ext. Bus Address Bit 12 D21 I/O Q Ext. Bus Data Bit 21 D16 I/O Q Ext. Bus Data Bit 16 D13 I/O Q Ext. Bus Data Bit 13 I/O Q Ext. Bus Data Bit 7 I/O Q Ext. Bus Data Bit 3 VSS PWM2P2 I/O PS2 K SMC 2 PWM2P1 I/O PR6 K SMC 1 PWM1P1 I/O PR4 K SMC 1 not connected SIN1 I/O PQ2 A UART 1 Input TX3 I/O PP6 Q CAN 3 TX SOT3 I/O PN4 A SIO Output SOT4 I/O PN0 A SIO Output not connected not connected SGO I/O PM0 A Sound Generator SGO TOEX O X Trace Control TAD8 O X Trace Address TAD2 O X Trace Address TDT67 I/O W Trace Data TDT60 I/O W Trace Data

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function TDT54 I/O W Trace Data TDT48 I/O W Trace Data TDT26 I/O W Trace Data TDT21 I/O W Trace Data TDT18 I/O W Trace Data TDT12 I/O W Trace Data TDT8 I/O W Trace Data TDT3 I/O W Trace Data ICS2 O G ICE Status VDD5F RSTX I E Reset Pin OUT2 I/O PL6 A OCU Output 2 IN0 I/O PL0 A ICU Input 0 INT2 I/O PK2 A Ext. Interrupt 2 AN6 I/O PH6 B ADC Input 6 AN1 I/O PH1 B ADC Input 1 AVCC Analog VCC DEOP0 I/O PB2 A DMA EOP 0 AN14 I/O PG6 B ADC Input 14 AN9 I/O PG1 B ADC Input 9 AS I/O P90 A Ext. Bus Control BRQ I/O P82 A Ext. Bus Control CS6X I/O P76 A Chip Select 6 A23 I/O Q Ext. Bus Address Bit 23 A17 I/O Q Ext. Bus Address Bit 17 A11 I/O Q Ext. Bus Address Bit 11 D27 I/O Q Ext. Bus Data Bit 27 D22 I/O Q Ext. Bus Data Bit 22 D17 I/O Q Ext. Bus Data Bit 17 I/O Q Ext. Bus Data Bit 16 VDD5S PWM1M3 I/O PS5 K SMC 3 PWM2M3 I/O PS7 M SMC 3 100 HVDD5A

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 101 PWM2P0 I/O PR2 K SMC0 102 VCC3/C C Bypass Capacitor Pin 103 SOT1 I/O PQ3 A UART 1 Output 104 SIN0 I/O PQ0 A UART 0 Input 105 TX1 I/O PP2 Q CAN 1 TX 106 OCPA2 I/O PO2 A PPG Output 107 SCK3 I/O PN5 A SIO Clock 108 SIN4 I/O PN1 A SIO Input 109 SCL I/O PM3 Y I2C SCL 110 TCLK I/O W Trace Control 111 TAD12 O X Trace Address 112 TAD15 O X Trace Address 113 TAD1 O X Trace Address 114 TDT65 I/O W Trace Data 115 TDT59 I/O W Trace Data 116 TDT55 I/O W Trace Data 117 TDT51 I/O W Trace Data 118 TDT42 I/O W Trace Data 119 TDT32 I/O W Trace Data 120 TDT27 I/O W Trace Data 121 TDT22 I/O W Trace Data 122 TDT11 I/O W Trace Data 123 TDT4 I/O W Trace Data 124 ICD3 I/O N ICE Data 125 TDT1 I/O W Trace Data 126 SELCLK I F Clock Selection 127 NMIX I E Non maskable Interrupt 128 OUT1 I/O PL5 A OCU Output 1 129 IN1 I/O PL1 A ICU Input 1 130 INT5 I/O PK5 A Ext. Interrupt 5 131 LED4 I/O PJ4 J LED Port 4 132 ALARM I D Alarm Comparator Input 133 AN7 I/O PH7 B ADC Input 7 134 AN2 I/O PH2 B ADC Input 2

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 135 DACK0 I/O PB1 A DMA acknowledge 0 136 AN10 I/O PG2 B ADC Input 10 137 CS0X I/O P94 A Chip select 0 138 CS3X I/O P97 A Chip select 3 139 BGRNTX I/O P81 A Ext. Bus Control 140 CS4X I/O P74 A Chip select 4 141 A22 I/O Q Ext. Bus Address Bit 22 142 A18 I/O Q Ext. Bus Address Bit 18 143 A14 I/O Q Ext. Bus Address Bit 14 144 I/O Q Ext. Bus Address Bit 5 145 INDEX 146 D30 I/O Q Ext. Bus Data Bit 30 147 D26 I/O Q Ext. Bus Data Bit 26 148 D19 I/O Q Ext. Bus Data Bit 19 149 D10 I/O Q Ext. Bus Data Bit 10 150 I/O Q Ext. Bus Data Bit 9 151 I/O Q Ext. Bus Data Bit 5 152 PWM2M2 I/O PS3 M SMC 2 153 PWM1P3 I/O PS4 K SMC 3 154 PWM2M0 I/O PR3 M SMC 0 155 VSS 156 SOT2 I/O PQ5 A UART 2 Output 157 SOT0 I/O PQ1 A UART 0 Output 158 VDD5O 159 OCPA7 I/O PO7 A PPG Output 160 OCPA5 I/O PO5 A PPG Output 161 OCPA1 I/O PO1 A PPG Output 162 VDD5K 163 X1A O I 32 kHz Oscillator Pin 164 X0A I I 32 kHz Oscillator Pin 165 SDA I/O PM2 Y I2C SDA 166 TAD10 O X Trace Address 167 TAD11 O X Trace Address 168 TDT66 I/O W Trace Data

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 169 TDT61 I/O W Trace Data 170 TDT58 I/O W Trace Data 171 TDT52 I/O W Trace Data 172 TDT45 I/O W Trace Data 173 TDT39 I/O W Trace Data 174 TDT35 I/O W Trace Data 175 TDT31 I/O W Trace Data 176 TDT24 I/O W Trace Data 177 TDT15 I/O W Trace Data 178 TDT14 I/O W Trace Data 179 TDT10 I/O W Trace Data 180 ICD1 I/O N ICE Data 181 ICD2 I/O N ICE Data 182 HSTX I E Hardware Standby 183 OUT3 I/O PL7 A OCU Output 3 184 OUT0 I/O PL4 A OCU Output 0 185 INT6 I/O PK6 A Ext. Interrupt 6 186 LED7 I/O PJ7 J LED Port 7 187 LED1 I/O PJ1 J LED Port 1 188 CPUTESTX I E Test Input 189 DA1 O C DAC Output 190 AN4 I/O PH4 B ADC Input 4 191 DEOP1 I/O PB5 A DMA EOP 1 192 DACK1 I/O PB4 A DMA Acknowledge 1 193 DREQ0 I/O PB0 A DMA Request 0 194 CLK I/O P92 A Ext. Bus Clock 195 AH/BOOT I/O P93 A Ext. Bus Control/Boot Signal 196 CS5X I/O P75 A Chip Select 5 197 A24 I/O Q Ext. Bus Address Bit 24 198 A21 I/O Q Ext. Bus Address Bit 21 199 A15 I/O Q Ext. Bus Address Bit 15 200 I/O Q Ext. Bus Address Bit 8 201 I/O Q Ext. Bus Address Bit 2 202 I/O Q Ext. Bus Address Bit 0

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 203 D29 I/O Q Ext. Bus Address Bit 29 204 D25 I/O Q Ext. Bus Address Bit 25 205 D20 I/O Q Ext. Bus Address Bit 20 206 D15 I/O Q Ext. Bus Address Bit 15 207 I/O Q Ext. Bus Address Bit 4 208 HVDD5C 209 PWM1M2 I/O PS1 K SMC2 210 PWM1P2 I/O PS0 K SMC2 211 PWM1M0 I/O PR1 K SMC0 212 SIN2 I/O PQ4 A UART 2 Input 213 RX3 I/O PP7 Q CAN 3 RX 214 VSS 215 RX0 I/O PP1 Q CAN 0 RX 216 VDD5N 217 OCPA4 I/O PO4 A PPG Output 218 OCPA0 I/O PO0 A PPG Output 219 SIN3 I/O PN3 A SIO Input 220 VSS 221 SGA I/O PM1 A Sound Generator SGA 222 TAD13 O X Trace Address 223 TAD7 O X Trace Address 224 TAD6 O X Trace Address 225 TDT64 I/O W Trace Data 226 TDT56 I/O W Trace Data 227 TDT50 I/O W Trace Data 228 TDT44 I/O W Trace Data 229 TDT41 I/O W Trace Data 230 TDT37 I/O W Trace Data 231 TDT34 I/O W Trace Data 232 TDT30 I/O W Trace Data 233 TDT25 I/O W Trace Data 234 TDT20 I/O W Trace Data 235 TDT9 I/O W Trace Data 236 BREAK I O ICE Break

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 237 ICS1 O G ICE Status 238 ICS0 O G ICE Status 239 MD2 I T Mode Pin 2 240 IN2 I/O PL2 A ICU Input 2 241 INT4 I/O PK4 A Ext. Interrupt 4 242 LED6 I/O PJ6 J LED Port 6 243 LED3 I/O PJ3 J LED Port 3 244 not connected 245 TESTX I E Test Input 246 DA0 O C DAC Output 247 AN5 I/O PH5 B ADC Input 5 248 AN0 I/O PH0 B ADC Input 0 249 AN15 I/O PG7 B ADC Input 15 250 CS1X I/O P95 A Chip select 1 251 WR3X I/O P87 S Ext. Bus Control 252 WR2X I/O P86 S Ext. Bus Control 253 DREQ2 I/O P73 A DMA Request 2 254 A19 I/O Q Ext. Bus Address Bit 19 255 A13 I/O Q Ext. Bus Address Bit 13 256 I/O Q Ext. Bus Address Bit 7 257 I/O Q Ext. Bus Address Bit 4 258 D31 I/O Q Ext. Bus Data Bit 31 259 D28 I/O Q Ext. Bus Data Bit 28 260 D23 I/O Q Ext. Bus Data Bit 23 261 D14 I/O Q Ext. Bus Data Bit 14 262 I/O Q Ext. Bus Data Bit 8 263 I/O Q Ext. Bus Data Bit 1 264 I/O Q Ext. Bus Data Bit 0 265 not connected 266 HVSS 267 not connected 268 VSS 269 RX2 I/O PP5 Q CAN 2 RX 270 RX1 I/O PP3 Q CAN 1 RX

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 271 VSS 272 OCPA3 I/O PO3 A PPG Output 273 VSS 274 not connected 275 VDD5I 276 TADSCX O X Trace Control 277 TCE1X O X Trace Control 278 TAD4 O X Trace Address 279 TAD0 O X Trace Address 280 TDT62 I/O W Trace Data 281 TDT53 I/O W Trace Data 282 TDT47 I/O W Trace Data 283 TDT43 I/O W Trace Data 284 TDT36 I/O W Trace Data 285 TDT33 I/O W Trace Data 286 TDT28 I/O W Trace Data 287 TDT19 I/O W Trace Data 288 TDT13 I/O W Trace Data 289 TDT6 I/O W Trace Data 290 TDT5 I/O W Trace Data 291 H O G Clock Output for test purposes 293 MD0 I T Mode Pin 0 294 INT7 I/O PK7 A Ext. Interrupt 7 295 INT1 I/O PK1 A Ext. Interrupt 1 296 LED5 I/O PJ5 J LED Port 5 297 LTESTX I E Test Input 298 ATGX I/O PI3 A Analog Reference Low 299 AVRL R Analog Reference High 300 AVRH R DMA Request 1 301 DREQ1 I/O PB3 A ADC Input 12 302 AN12 I/O PG4 B ADC Input 11 303 AN11 I/O PG3 B Ext. Bus Control 304 WR0X I/O P84 S Ext. Bus Control

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 305 RDY I/O S Ext. Bus Control 306 A25 I/O Q Ext. Bus Address Bit 25 307 A16 I/O Q Ext. Bus Address Bit 16 308 A10 I/O Q Ext. Bus Address Bit 10 309 I/O Q Ext. Bus Address Bit 6 310 I/O Q Ext. Bus Address Bit 1 311 not connected 312 D24 I/O Q Ext. Bus Data Bit 24 313 D12 I/O Q Ext. Bus Data Bit 12 314 not connected 315 PWM2P3 I/O PS6 K SMC 3 316 HVSS 317 HVSS 318 not connected 319 VDD5Q 320 TX2 I/O PP4 Q CAN 2 TX 321 TX0 I/O PP0 Q CAN 0 TX 322 OCPA6 I/O PO6 A PPG Output 323 VDD5M 324 VDD5L 325 not connected 326 VDD5H 327 TAD14 O X Trace Address 328 VSS3 329 VSS3 330 not connected 331 VDD3C 332 TDT46 I/O W Trace Data 333 TDT40 I/O W Trace Data 334 TDT38 I/O W Trace Data 335 VDD3B 336 TDT29 I/O W Trace Data 337 TDT17 I/O W Trace Data 338 VDD3A

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 339 TDT0 I/O W Trace Data 340 VSS 341 VSS 342 not connected 343 VDD5E 344 INT0 I/O PK0 A Ext. Interrupt 0 345 LED2 I/O PJ2 J LED Port 2 346 LED0 I/O PJ0 J LED Port 0 347 VDD5D 348 AVSS Analog VSS 349 DEOP2 I/O PB7 A DMA EOP 2 350 VDD5C 351 CS2X I/O P96 A Chip select 2 352 VSS 353 VSS 354 VDD5B 355 not connected 356 I/O Q Ext. Bus Address Bit 9 357 I/O Q Ext. Bus Address Bit 3 358 VSS 359 VSS 360 VDD5T 361 VSS 362 VSS 363 VSS 364 not connected 365 HVSS 366 VSS 367 VSS 368 not connected 369 VSS 370 VSS 371 not connected 372 VSS

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 373 VSS 374 VSS 375 VDD3D 376 VSS3 377 VSS3 378 VSS3 379 not connected 380 VSS3 381 VSS3 382 not connected 383 VSS3 384 VSS3 385 VSS3 386 VDD5G 387 VSS 388 VSS 389 VSS 390 not connected 391 VSS 392 VSS 393 not connected 394 VSS 395 VSS 396 VSS 397 not connected 398 VSS 399 VSS 400 VSS 401 VDD5A

MB91FV362GA I/O Pins and Their Functions (Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function D24 I/O Q Ext. Bus Data Bit 24 D25 I/O Q Ext. Bus Data Bit 25 D26 I/O Q Ext. Bus Data Bit 26 D27 I/O Q Ext. Bus Data Bit 27 D28 I/O Q Ext. Bus Data Bit 28 D29 I/O Q Ext. Bus Data Bit 29 D30 I/O Q Ext. Bus Data Bit 30 D31 I/O Q Ext. Bus Data Bit 31 I/O Q Ext. Bus Address Bit 0 I/O Q Ext. Bus Address Bit 1 I/O Q Ext. Bus Address Bit 2 I/O Q Ext. Bus Address Bit 3 I/O Q Ext. Bus Address Bit 4 I/O Q Ext. Bus Address Bit 5 I/O Q Ext. Bus Address Bit 6 I/O Q Ext. Bus Address Bit 7 I/O Q Ext. Bus Address Bit 8 I/O Q Ext. Bus Address Bit 9 A10 I/O Q Ext. Bus Address Bit 10 A11 I/O Q Ext. Bus Address Bit 11 A12 I/O Q Ext. Bus Address Bit 12 A13 I/O Q Ext. Bus Address Bit 13 A14 I/O Q Ext. Bus Address Bit 14 A15 I/O Q Ext. Bus Address Bit 15 VDD35 Separated Ext. Bus VDD, 3.3 V or 5.0 V VSS A16 I/O Q Ext. Bus Address Bit 16 A17 I/O Q Ext. Bus Address Bit 17 A18 I/O Q Ext. Bus Address Bit 18 A19 I/O Q Ext. Bus Address Bit 19 A20 I/O Q Ext. Bus Address Bit 20 CS4X I/O P74 A Chip select 4 CS5X I/O P75 A Chip select 5

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function CS6X I/O P76 A Chip select 6 RDY I/O S Ext. Bus Control BGRNT I/O P81 A Ext. Bus Control BRQ I/O P82 A Ext. Bus Control RDX I/O S Ext. Bus Control WR0X I/O S Ext. Bus Control WR1X I/O S Ext. Bus Control WR2X I/O S Ext. Bus Control WR3X I/O S Ext. Bus Control AS I/O P90 A Ext. Bus Control ALE I/O P91 A Ext. Bus Control CLK I/O A Ext. Bus Clock AH I/O P93 A Ext. Bus Control Signal CS0X I/O P94 A Chip select 0 CS1X I/O P95 A Chip select 1 CS2X I/O P96 A Chip select 2 CS3X I/O P97 A Chip select 3 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V VSS AN8 I/O PG0 B ADC Input 8 AN9 I/O PG1 B ADC Input 9 AN10 I/O PG2 B ADC Input 10 AN11 I/O PG3 B ADC Input 11 AN12 I/O PG4 B ADC Input 12 AN13 I/O PG5 B ADC Input 13 AN14 I/O PG6 B ADC Input 14 AN15 I/O PG7 B ADC Input 15 DREQ0 I/O PB0 A DMR Request 0 DACK0 I/O PB1 A DMA Acknowledge 0 DEOP0 I/O PB2 A DMA EOP 0 AVCC Analog VCC AVRH R Analog Reference High AN0 I/O PH0 B ADC Input 0

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function AN1 I/O PH1 B ADC Input 1 AN2 I/O PH2 B ADC Input 2 AN3 I/O PH3 B ADC Input 3 AN4 I/O PH4 B ADC Input 4 AN5 I/O PH5 B ADC Input 5 AN6 I/O PH6 B ADC Input 6 AN7 I/O PH7 B ADC Input 7 AVSS, AVRL Analog VSS, Analog Reference Low DA0 O C DAC Output DA1 O C DAC Output ALARM I D Alarm Comparator Input VSS VDD ATGX I/O PI3 A ADC Trigger Input TESTX I E Test Input (should be connected to VDD) CPUTESTX I E Test Input (should be connected to VDD) LTESTX I E Test Input (should be connected to VDD) LED0 I/O PJ0 J LED Port 0 LED1 I/O PJ1 J LED Port 1 LED2 I/O PJ2 J LED Port 2 LED3 I/O PJ3 J LED Port 3 LED4 I/O PJ4 J LED Port 4 LED5 I/O PJ5 J LED Port 5 LED6 I/O PJ6 J LED Port 6 LED7 I/O PJ7 J LED Port 7 VDD VSS INT0 I/O PK0 A Ext. Interrupt 0 INT1 I/O PK1 A Ext. Interrupt 1 INT2 I/O PK2 A Ext. Interrupt 2 INT3 I/O PK3 A Ext. Interrupt 3 INT4 I/O PK4 A Ext. Interrupt 4 INT5 I/O PK5 A Ext. Interrupt 5 100 INT6 I/O PK6 A Ext. Interrupt 6

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 101 INT7 I/O PK7 A Ext. Interrupt 7 102 IN0 I/O PL0 A ICU Input 0 103 IN1 I/O PL1 A ICU Input 1 104 IN2 I/O PL2 A ICU Input 2 105 IN3 I/O PL3 A ICU Input 3 106 OUT0 I/O PL4 A OCU Output 0 107 OUT1 I/O PL5 A OCU Output 1 108 OUT2 I/O PL6 A OCU Output 2 109 OUT3 I/O PL7 A OCU Output 3 110 VSS 111 MD0 I T Mode Pin 0 112 MD1 I T Mode Pin 1 113 MD2 I T Mode Pin 2 114 HSTX I E Hardware Standby 115 INITX I U Initial Pin 116 MONCLK O G System Clock Output for evaluation purposes 117 SELCLK I F Clock Selection, must be connected to VDD 118 VDD 119 H H I I reserved-must be connected to VSS 122 X1A O I reserved-should be left open 123 VSS 124 CPO C reserved-should be left open 125 VCI D reserved-must be connected to VSS 126 SGO I/O PM0 A Sound Generator SGO 127 SGA I/O PM1 A Sound Generator SGA 128 SDA I/O PM2 Y I2C SDA 129 SCL I/O PM3 Y I2C SCL 130 SOT4 I/O PN0 A SIO Output 131 SIN4 I/O PN1 A SIO Input 132 SCK4 I/O PN2 A SIO Clock 133 SIN3 I/O PN3 A SIO Input 134 SOT3 I/O PN4 A SIO Output

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 135 SCK3 I/O PN5 A SIO Clock 136 OCPA 0 I/O PO0 A PPG Output 137 OCPA 1 I/O PO1 A PPG Output 138 OCPA 2 I/O PO2 A PPG Output 139 OCPA 3 I/O PO3 A PPG Output 140 OCPA 4 I/O PO4 A PPG Output 141 OCPA 5 I/O PO5 A PPG Output 142 OCPA 6 I/O PO6 A PPG Output 143 OCPA 7 I/O PO7 A PPG Output 144 VDD 145 VSS 146 TX0 I/O PP0 Q CAN 0 TX 147 RX0 I/O PP1 Q CAN 0 RX 148 TX1 I/O PP2 Q CAN 1 TX 149 RX1 I/O PP3 Q CAN 1 RX 150 TX2 I/O PP4 Q CAN 2 TX 151 RX2 I/O PP5 Q CAN 2 RX 152 SIN0 I/O PQ0 A UART 0 Input 153 SOT0 I/O PQ1 A UART 0 Output 154 SIN1 I/O PQ2 A UART 1 Input 155 SOT1 I/O PQ3 A UART 1 Output 156 SIN2 I/O PQ4 A UART 2 Input 157 SOT2 I/O PQ5 A UART 2 Output 158 VSS 159 VCC3/C C Bypass Capacitor Pin 160 VDD 161 HVSS 162 PWM1P0 I/O PR0 K SMC 0 163 PWM1M0 I/O PR1 K SMC 0 164 PWM2P0 I/O PR2 K SMC 0 165 PWM2M0 I/O PR3 M SMC 0 166 HVDD 167 PWM1P1 I/O PR4 K SMC 1 168 PWM1M1 I/O PR5 K SMC 1

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 169 PWM2P1 I/O PR6 K SMC 1 170 PWM2M1 I/O PR7 M SMC 1 171 HVSS 172 PWM1P2 I/O PS0 K SMC 2 173 PWM1M2 I/O PS1 K SMC 2 174 PWM2P2 I/O PS2 K SMC 2 175 PWM2M2 I/O PS3 M SMC 2 176 HVDD 177 PWM1P3 I/O PS4 K SMC 3 178 PWM1M3 I/O PS5 K SMC 3 179 PWM2P3 I/O PS6 K SMC 3 180 PWM2M3 I/O PS7 M SMC 3 181 HVSS 182 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V 183 I/O Q Ext. Bus Data Bit 0 184 I/O Q Ext. Bus Data Bit 1 185 I/O Q Ext. Bus Data Bit 2 186 I/O Q Ext. Bus Data Bit 3 187 I/O Q Ext. Bus Data Bit 4 188 I/O Q Ext. Bus Data Bit 5 189 I/O Q Ext. Bus Data Bit 6 190 I/O Q Ext. Bus Data Bit 7 191 I/O Q Ext. Bus Data Bit 8 192 I/O Q Ext. Bus Data Bit 9 193 D10 I/O Q Ext. Bus Data Bit 10 194 D11 I/O Q Ext. Bus Data Bit 11 195 D12 I/O Q Ext. Bus Data Bit 12 196 D13 I/O Q Ext. Bus Data Bit 13 197 D14 I/O Q Ext. Bus Data Bit 14 198 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V 199 VSS 200 D15 I/O Q Ext. Bus Data Bit 15 201 D16 I/O Q Ext. Bus Data Bit 16 202 D17 I/O Q Ext. Bus Data Bit 17

(Continued) Note : If pins VDD35 (25, 51, 182, 198) are connected to 3.3 V then the external bus interface (pins 1-52, 182-208) can be operated at 3.3 V levels. Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 203 D18 I/O Q Ext. Bus Data Bit 18 204 D19 I/O Q Ext. Bus Data Bit 19 205 D20 I/O Q Ext. Bus Data Bit 20 206 D21 I/O Q Ext. Bus Data Bit 21 207 D22 I/O Q Ext. Bus Data Bit 22 208 D23 I/O Q Ext. Bus Data Bit 23

MB91F369GA I/O Pins and Their Functions (Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function I/O Q Ext. Bus Address Bit 4 I/O Q Ext. Bus Address Bit 5 I/O Q Ext. Bus Address Bit 6 I/O Q Ext. Bus Address Bit 7 I/O Q Ext. Bus Address Bit 8 I/O Q Ext. Bus Address Bit 9 A10 I/O Q Ext. Bus Address Bit 10 A11 I/O Q Ext. Bus Address Bit 11 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V CLK I/O A Ext. Bus Clock VSS A12 I/O Q Ext. Bus Address Bit 12 A13 I/O Q Ext. Bus Address Bit 13 A14 I/O Q Ext. Bus Address Bit 14 A15 I/O Q Ext. Bus Address Bit 15 A16 I/O Q Ext. Bus Address Bit 16 A17 I/O Q Ext. Bus Address Bit 17 A18 I/O Q Ext. Bus Address Bit 18 A19 I/O Q Ext. Bus Address Bit 19 A20 I/O Q Ext. Bus Address Bit 20 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V VSS CS4X I/O P74 A Chip Select 4 CS5X I/O P75 A Chip Select 5 CS6X I/O P76 A Chip Select 6 RDX I/O S Ext. Bus Control BGRNTX I/O P81 A Ext. Bus Control BRQ I/O P82 A Ext. Bus Control AS I/O P90 A Ext. Bus Control ALE I/O P91 A Ext. Bus Control AH I/O P93 A Ext. Bus Control Signal CS0X I/O P94 A Chip select 0 CS1X I/O P95 A Chip select 1

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function CS2X I/O P96 A Chip select 2 CS3X I/O P97 A Chip select 3 DREQ0 I/O PB0 A DMA Request 0 DACK0 I/O PB1 A DMA Acknowledge 0 DEOP0 I/O PB2 A DMA EOP 0 VSS VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V AVRH R Analog Reference High AVCC Analog VCC AVSS, AVRL Analog VSS, Analog Reference Low AN0 I/O PH0 B ADC Input 0 AN1 I/O PH1 B ADC Input 1 AN2 I/O PH2 B ADC Input 2 AN3 I/O PH3 B ADC Input 3 AN4 I/O PH4 B ADC Input 4 AN5 I/O PH5 B ADC Input 5 AN6 I/O PH6 B ADC Input 6 AN7 I/O PH7 B ADC Input 7 AN8 I/O PG0 B ADC Input 8 AN9 I/O PG1 B ADC Input 9 ALARM I D Alarm Comparator Input VSS VDD ATGX I/O P13 A ADC Trigger Input MD0 I T Mode Pin 0 MD1 I T Mode Pin 1 MD2 I T Mode Pin 2 HSTX I E Hardware Standby INITX I U Initual Pin TESTX I E Test Input (should be connected to VDD) CPUTESTX I E Test Input (should be connected to VDD) LTESTX I E Test Input (should be connected to VDD) VDD

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function VSS INT0 I/O PK0 A Ext. Interrupt 0 INT1 I/O PK1 A Ext. Interrupt 1 INT2 I/O PK2 A Ext. Interrupt 2 INT3 I/O PK3 A Ext. Interrupt 3 INT4 I/O PK4 A Ext. Interrupt 4 INT5 I/O PK5 A Ext. Interrupt 5 INT6 I/O PK6 A Ext. Interrupt 6 INT7 I/O PK7 A Ext. Interrupt 7 SGO I/O PM0 A Sound Generator SGO SGA I/O PM1 A Sound Generator SGA SDA I/O PM2 Y I2C SDA SCL I/O PM3 Y I2C SCL SOT4 I/O PN0 A SIO Output SIN4 I/O PN1 A SIO Input SCK4 I/O PN2 A SIO Clock SIN3 I/O PN3 A SIO Input SOT3 I/O PN4 A SIO Output SCK3 I/O PN5 A SIO Clock VSS VDDI Supply voltage for internal regulator VDDI Supply voltage for internal regulator VDDI Supply voltage for internal regulator VDDI Supply voltage for internal regulator VCC3C Capacitor pin for internal regulator VSS TX0 I/O PP0 Q CAN 0 TX RX0 I/O PP1 Q CAN 0 RX TX1 I/O PP2 Q CAN 1 TX RX1 I/O PP3 Q CAN 1 RX SIN0 I/O PQ0 A UART 0 Input SOT0 I/O PQ1 A UART 0 Output VDD 100 VSS

(Continued) Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 101 OCPA0 I/O PO0 A PPG Output 102 OCPA1 I/O PO1 A PPG Output 103 OCPA2 I/O PO2 A PPG Output 104 OCPA3 I/O PO3 A PPG Output 105 VDDX 106 H H O System Clock Output 111 VSS 112 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V 113 VSS 114 WR3X I/O S Ext. Bus Control 115 WR2X I/O S Ext. Bus Control 116 WR1X I/O S Ext. Bus Control 117 WR0X I/O S Ext. Bus Control 118 RDY I/O S Ext. Bus Control 119 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V 120 VSS 121 I/O Q Ext. Bus Data Bit 0 122 I/O Q Ext. Bus Data Bit 1 123 I/O Q Ext. Bus Data Bit 2 124 I/O Q Ext. Bus Data Bit 3 125 I/O Q Ext. Bus Data Bit 4 126 I/O Q Ext. Bus Data Bit 5 127 I/O Q Ext. Bus Data Bit 6 128 I/O Q Ext. Bus Data Bit 7 129 I/O Q Ext. Bus Data Bit 8 130 I/O Q Ext. Bus Data Bit 9 131 D10 I/O Q Ext. Bus Data Bit 10 132 D11 I/O Q Ext. Bus Data Bit 11 133 D12 I/O Q Ext. Bus Data Bit 12 134 D13 I/O Q Ext. Bus Data Bit 13

(Continued) Note : If pins VDD35 (9, 21, 40, 112, 119, 137, 155) are connected to a 3.3 V supply the external bus interface (pins 1-40, 112-160) can be operated at 3.3 V levels. Pin No. Pin Name I/O General Purpose IO Port Circuit Type Function 135 D14 I/O Q Ext. Bus Data Bit 14 136 D15 I/O Q Ext. Bus Data Bit 15 137 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V 138 VSS 139 D16 I/O Q Ext. Bus Data Bit 16 140 D17 I/O Q Ext. Bus Data Bit 17 141 D18 I/O Q Ext. Bus Data Bit 18 142 D19 I/O Q Ext. Bus Data Bit 19 143 D20 I/O Q Ext. Bus Data Bit 20 144 D21 I/O Q Ext. Bus Data Bit 21 145 D22 I/O Q Ext. Bus Data Bit 22 146 D23 I/O Q Ext. Bus Data Bit 23 147 D24 I/O Q Ext. Bus Data Bit 24 148 D25 I/O Q Ext. Bus Data Bit 25 149 D26 I/O Q Ext. Bus Data Bit 26 150 D27 I/O Q Ext. Bus Data Bit 27 151 D28 I/O Q Ext. Bus Data Bit 28 152 D29 I/O Q Ext. Bus Data Bit 29 153 D30 I/O Q Ext. Bus Data Bit 30 154 D31 I/O Q Ext. Bus Data Bit 31 155 VDD35 separated Ext. Bus VDD, 3.3 or 5.0 V 156 VSS 157 I/O Q Ext. Bus Address Bit 0 158 I/O Q Ext. Bus Address Bit 1 159 I/O Q Ext. Bus Address Bit 2 160 I/O Q Ext. Bus Address Bit 3

(Continued) Type Circuit type Remarks A

I/O, CMOS Automotive Schmitt-Trigger Input, STOP control, IOH = 4 mA, IOL = 4 mA B
I/O, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control, IOH = 4 mA, IOL = 4 mA C
Analog output D
Analog Input P N R Stop control Digital input Digital output Digital output VSS P N R R Stop control Digital input Analog input Digital output Digital output VSS P N Analog output VSS VCC P N R Analog input VSS VCC

(Continued) Type Circuit type Remarks E

CMOS Schmitt-Trigger Input, Pullup Resistor: 50 kΩ F
CMOS Schmitt-Trigger Input G
Tristate Output, IOH = 4 mA, IOL = 4 mA H
4 MHz Oscillator Pin P N R Digital input P VSS VSS VCC VCC P N R Digital input VSS VCC P N Digital output Digital output VSS VCC Stop control Clock input

(Continued) Type Circuit type Remarks I

32 kHz Oscillator Pin J
I/O, CMOS Automotive Schmitt-Trigger Input, STOP control (LED) , IOH = 14 mA, IOL = 24 mA K
I/O, CMOS Automotive Schmitt-Trigger Input, STOP control (SMC) , IOH = 30 mA, IOL = 30 mA
Typ slew rate of 40 ns L
I/O, CMOS Input: 5 V or 3 V input, IOH = 4 mA, IOL = 4 mA Stop control Clock input X1A X0A P N R Stop control Digital input Digital output Digital output VSS P N R Stop control Digital input Digital output Digital output VSS P N R Digital input Digital output Digital output VSS VCC

(Continued) Type Circuit type Remarks M

I/O, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control (SMC) , IOH = 30 mA, IOL = 30 mA
Typ slew rate of 40 ns N
I/O, CMOS Input, Pulldown Resistor: 50 kΩ,

5 V or 3 V input,

IOH = 4 mA, IOL = 4 mA O

CMOS Input, Pulldown Resistor: 50 kΩ,

5 V or 3 V input

CMOS Input: 3 V input P N R R Stop control Digital input Analog input Digital output Digital output VSS P N R Digital input Digital output Digital output N VSS VCC P N R Digital input N VSS VSS VCC VCC P N R Digital input VSS VCC

(Continued) Type Circuit type Remarks Q/Q1

Q : I/O CMOS Input, STOP control, IOH = 4 mA, IOL = 4 mA
Q1 : I/O CMOS Input, STOP control, IOH = 8 mA, IOL = 8 mA S
I/O, CMOS Schmitt-Trigger Input, STOP control, Pullup Resistor : 10 kΩ, IOH = 4 mA, IOL = 4 mA T
CMOS Input
can withstand high VID for flash programming U
CMOS Schmitt-Trigger Input, Pullup Resistor: 50 kΩ,

3 V and 5 V input to the core

P N R Stop control Digital input Digital output Digital output VSS P N R P VSS VCC Digital output Digital output Digital input Stop control R Control signal MD Input P N R Digital input P VSS VSS VCC VCC

(Continued) Note : Symbols used in circuit types (Common to all circuit diagrams) P : P channel transistor N : N channel transistor R : Diffusion resistor Type Circuit type Remarks V

I/O, CMOS Schmitt-Trigger Input, STOP control, Pullup Resistor: 50 kΩ,, IOH = 4 mA, IOL = 4 mA W
I/O, CMOS Input: 3 V input X
Tristate Output, 3 V Y
I/O CMOS Input, STOP control, IOH = 3 mA, IOL = 3 mA, in I2C mode operating as open drain outputs P N R P VSS VCC Digital output Digital output Digital input Stop control P N R Digital input Digital output Digital output VSS 3 V P N Digital output Digital output VSS 3 V P N R Stop control Digital input Digital output Digital output VSS

Description

A I/O, IOH = 4 mA / IOL = 4 mA, CMOS Automotive Schmitt-Trigger Input, STOP control B I/O, IOH = 4 mA / IOL = 4 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control C Analog Output D Analog Input E CMOS Schmitt-Trigger Input, Pull-up Resistor: 50 kΩ, F CMOS Schmitt-Trigger Input G Tristate Output, IOH = 4 mA / IOL = 4 mA H I 32 kHz Oscillator pin J I/O, IOH = 14 mA / IOL = 24 mA, CMOS Automotive Schmitt-Trigger Input, STOP control (LED) K I/O, IOH = 30 mA / IOL = 30 mA, CMOS Automotive Schmitt-Trigger Input, STOP control, slew rate improved for EMC (SMC) L I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input: 5 V or 3 V input M I/O, IOH = 30 mA / IOL = 30 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control, slew rate improved for EMC (SMC) N I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input : 5 V or 3 V input, Pulldown Resistor: 50 kΩ O CMOS Input : 5 V or 3 V input, Pulldown Resistor: 50 kΩ P CMOS Input: 3 V input Q I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, STOP control I/O, IOH = 8 mA / IOL = 8 mA, CMOS Input, STOP control R AVRL / AVRH Input S I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, STOP control, Pull-up Resistor: 10 kΩ, T CMOS Input, can withstand VID for flash programming U CMOS Schmitt-Trigger Input, Pull-up Resistor: 50 kΩ, 3.3 V and 5 V inputs to core W I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input: 3 V input X Tristate Output, IOH = 4 mA / IOL = 4 mA, 3 V Y I/O, IOH = 3 mA / IOL = 3 mA (I2C) , CMOS Input, STOP control

Latch-up may occur in a CMOS IC if a voltage greater than VDD or less than VSS is applied to an input or output pin or if the voltage applied between VDD and VSS exceeds the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. Connecting unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be tied to VDD or VSS through resistors. In this case those resistors should be more than 2 KOhm. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. The resistor of more than 2 KOhm is used to limit currents through the protection diodes. In case of voltages at the not used pin of 0.3 V or more below VSS or 0.3 V or more above VDD currents which could cause latch-up will flow through those diodes. External reset input When inputting an “L” level to the INITX pin, hold this low level at the INITX pin long enough so that after release of the low level at INITX and the passing of the built in waiting time stable oscillation of the oscillation circuit is achieved. INITX must be pulled low for at least 8 cycles of the 4 MHz oscillation clock. Power supply pins All VDD pins should be connected to the same potential (exception can be the external bus interface on F362GA and F369GA) . The analogue supply voltage (AVCC) must not be turned on before the digital supply voltage. If the external bus interface is supplied with 3.3 V this voltage also must not be turned on before the 5 V digital voltage has been switched on. If the supply voltage to the external bus interface is switched off (it may not be tristate but should be pulled low) it must be made sure that all related signals do not have a voltage higher than this pulled down supply. When multiple VDD and VSS pins are provided, be sure to connect all VDD and VSS pins to the power supply or ground externally. Although pins at the same potential are connected together in the internal device design so as to prevent malfunctions such as latch-up, connecting all VDD and VSS pins appropriately minimizes unwanted radiation, prevents malfunction of strobe signals due to increases in the ground level, and keeps the overall output current rating. Also, take care to connect VDD and VSS to current source in the lowest possible impedance. Connection of a ceramic bypass capacitor of approximately 0.1 µF between VDD and VSS close to the device is recommended. The MB91360G series contains a regulator. To use the device with the 5-V power supply, supply 5-V power to the VCC pins and be sure to connect a bypass capacitor of 10 µF parallel to 10 nF to the VCC3C pin for the regulator. 5 V 5 V 10 µF 10 nF VCC3C VCC AVCC AVRH AVSS VSS GND [Use with 5-V power supply]

Crystal oscillator circuit Noise in the vicinity of the X0 and X1 pins can be a cause of device malfunction. Design the circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. A printed circuit board design that surrounds the X0 and X1 pins with ground provides for stable operation and is strongly recommended. Mode pins Connect the mode pins (MD0 to MD2) directly to VDD or VSS. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VDD or VSS and to provide a low-impedance connection. Turning the power supply on Immediately after power on always execute INIT at the INITX pin (start with a low level at the INITX pin) . Hold this low level at the INITX pin long enough so that after release of the low level at INITX and the passing of the built in waiting time stable oscillation of the oscillation circuit is achieved. INITX must be pulled low for at least 8 cycles of the 4 MHz oscillation clock. The analogue supply voltage (AVCC) must not be turned on before the digital supply voltage. If the external bus interface is supplied with 3.3 V this voltage also must not be turned on before the 5 V digital voltage has been switched on. A state in turning power on As long as the minimum operating voltage has not been reached during power-on the output pin levels are not guaranteed.

Prog. Pulse Generator External Bus

00 : 0000 00 : 03FF 00 : 07FF 00 : 1000 00 : 1024 01 : 1000 01 : 1FFF 03 : C000 03 : FFFF 04 : 0000 04 : 3FFF 05 : 0000 05 : 07FF 08 : 0000 0F : 4000 0F : FFFF 10 : 0000 128 K 128 K 128 K 64 K 16 K 16 K 32 K CAN Fixed Reset Vector Bootsector Flash Memory on F-bus Boot ROM F-bus RAM D-bus RAM I-RAM DMA IO Area Direct Direct (short) addressing 0..0FF : Byte access 0..1FF : Halfword access (16 bit) 0..3FF : Word access (32 bit) 03 : D000 - 03 : FFFF on F362GA 04 : 0000 - 04 : 0FFF on F362GA 10 : 07FF Addresses for CAN depend on set- tings for the chip select areas CS7. The addresses given here are valid for the CS7 settings done in the Boot ROM.

Each of the dedicated registers is used for a particular purpose. The dedicated registers consist of the program counter (PC) , program status (PS) , table base register (TBR) , return pointer (RP) , system stack pointer (SS P) , user stack pointer (USP) , and multiplication and division result registers (MDH/MDL) . (1) Program status (PS) PC PS TBR RP SSP USP MDH MDL XXXX XXXXH (Indeterminate) XXXX XXXXH (Indeterminate) XXXX XXXXH (Indeterminate) XXXX XXXXH (Indeterminate) XXXX XXXXH (Indeterminate) 0000 0000H 000F FC00H 32 bits Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplication and division results resisters Initial value Bit position ILM SCR CCR CCR : Condition Code Register SCR : System Condition Code Register ILM : Interrupt Level Mask

(2) Condition Code Register (CCR) (3) System Condition Code Register (SCR) (4) Interrupt Level Mask Register (ILM) (Bit) Initial value --00XXXXB S I N Z V C (Bit) Initial value XX0B T (Bit) Initial value 01111B ILM4 ILM3 ILM2 ILM1 ILM0

The general-purpose registers are CPU registers R0 to R15. The register are used as the accumulator for operations and as pointers (a field indicating an address) for memory access. The user can specify the purpose for which the general-purpose registers are used. Among 16 general-purpose registers, the following registers assume a special purpose. This enhances some instructions. The initial value of R0 to R14 after a reset is indeterminate. The initial value of R15 is 00000000H (SSP value) . R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP) R12 R13 R14 R15 AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer) XXXX XXXXH XXXX XXXXH 0000 0000H 32-bits Initial value Register bank structure

The FR50 series of devices uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode. (1) Mode Pins Three mode pins (MD2 to MD0) are used to specify the reset mode vector access area. (2) Mode Register (MODR) The data to be written to 0000_7FDH using mode vector fetch is called mode data. MODR is located at 0000_07FDH. After an operation mode has been set in MODR, the device operates in this operation mode. MODR is set only when a reset factor (INIT level) occurs. User programs cannot write data to MODR. < Mode Register (MODR) > [Bits 7 to 3] : (Reserved bits) Always set 00000 at bits 7 to 3. Operation is not guaranteed when other values are set. [Bit 2] : ROMA (internal ROM enable bit) The ROMA bit is used to set whether to validate the internal ROM area (Fbus memory area) . Mode Pins Mode name Reset vector access area Remarks MD2 MD1 MD0 Internal ROM mode vector Internal External ROM mode vector External The mode register is used to set the bus width. remaining settings Reserved ROMA Function Remarks External ROM mode Access to the Fbus area is external. Internal ROM mode Address Initial value 0000 07FDH XXXXXXXX ROMA WTH1 Operation mode setting bit WTH0

[Bits 1 and 0] : WTH1 and WTH0 (bus width/single chip mode specifying bits) The WTH1 and WTH0 bits are used to set the bus width (valid when operation mode is external bus mode) and the single chip mode. When the operation mode is the external bus mode, this value is set at the BW1 and BW0 bits of AMD0 (CS0 area) . (3) Fixed Vector If MB91360 series devices are started in mode MD[2 : 0] = 000, the internal fixed mode vector (FMV = 0x06) and the fixed reset vector are used. The fixed reset vector points to the start address of the internal Boot ROM. This enables access to the F-bus area, to the internal CAN modules and the internal flash memory. See also section Boot ROM. WTH1 WTH0 Function Remarks 8-bit bus width External bus mode 16-bit bus width External bus mode 32-bit bus width External bus mode Single chip mode

How to Read the I/O Map Read/Write attribute Register initial value after a reset (bit initial values) “1” : initial value “1”, “0” : initial value “0”, “x” : initial value “X” (indeterminate) , “” indicates non-existent bits Register name (The register in column 1 is at location 4n, the register in column 2 at 4n+1, and so on.) Location of far left of register (+0) . +1+2, and+3 each increment the loca- tion by one. When performing word access, the register in column 1 is placed at the MSB end of the data. Precautions :
Do not use RMW instructions on registers containing write-only (W) bits. RMW instructions (RMW : read-modify-write) AND Rj, @Ri OR Rj, @Ri EOR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri EORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri EORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BEORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri BEORH #u4, @Ri
The data in reserved areas and areas marked “” is indeterminate. Do not use those ares ! Address Register Internal peripheral ++++0 ++++1 ++++2 ++++3 000014H PDRG[R/W] PDRH[R/W] PDRI[R/W] Port data register XXXXXXXX XXXXXXXX - - - - XXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000000H Reserved Reserved Reserved Reserved T-unit Port Data Register 000004H Reserved Reserved Reserved PDR7 [R/W] -111 - - - - 000008H PDR8 [R/W] XXXXXXXX PDR9 [R/W] XXXXXXX1 PDRB [R/W] - - - - - XXX 00000CH 000010H PDRG [R/W] XXXXXXXX PDRH [R/W] XXXXXXXX PDRI [R/W] X - - - X - - - PDRJ [R/W] XXXXXXXX R-bus Port Data Register 000014H PDRK [R/W] XXXXXXXX PDRL [R/W] XXXXXXXX PDRM [R/W] - - - - XXXX PDRN [R/W] - - XXXXXX 000018H PDRO [R/W] XXXXXXXX PDRP [R/W] - - XXXXX PDRQ [R/W] - - XXXXX PDRR [R/W] XXXXXXXX 00001CH PDRS [R/W] XXXXXXXX 000020H to 00003CH Reserved 000040H EIRR [R/W] 00000000 ENIR [R/W] 00000000 ELVR [R/W] 00000000 00000000 Ext int/NMI 000044H DICR [R/W] - - - - - - - 0 HRCL [R/W, R] 0 - - 11111 CLKR2 [R/W] - - - - - 000 reserved DLYI/I-unit RTC 000048H TMRLR0 [W] XXXXXXXX XXXXXXXX TMR0 [R] XXXXXXXX XXXXXXXX Reload Timer 0 00004CH TMCSR0 [R/W] 000050H TMRLR1 [W] XXXXXXXX XXXXXXXX TMR1 [R] XXXXXXXX XXXXXXXX Reload Timer 1 000054H TMCSR1 [R/W] 000058H TMRLR2 [W] XXXXXXXX XXXXXXXX TMR2 [R] XXXXXXXX XXXXXXXX Reload Timer 2 00005CH TMCSR2 [R/W] 000060H SSR0 [R/W] 00001 - 00 SIDR0 [R/W] XXXXXXXX SCR0 [R/W, W] 00000100 SMR0 [R/W, W] 00 - - 0 - 0 - UART0 000064H ULS0 [R/W] - - - - 0000

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000068H UTIM0/UTIMR0 [R/W] 00000000 00000000 DRCL0 [W] - - - - - - - - UTIMC0 [R/W] 0 - - - 0 - 01 U-TIMER 0 00006CH SSR1 [R/W, R] 00001 - 00 SIDR1 [R/W] XXXXXXXX SCR1 [R/W, W] 00000100 SMR1 [R/W, W] 00 - - 0 - 0 - UART1 000070H ULS1 [R/W] - - - - 0000 000074H UTIM1/UTIMR1 [R/W] 00000000 00000000 DRCL1 [W] - - - - - - - - UTIMC1 [R/W] 0 - - - - - 01 U-TIMER 1 000078H SSR2 [R/W, R] 00001 - 00 SIDR2 [R/W] XXXXXXXX SCR2 [R/W, W] 00000100 SMR2 [R/W, W] 00 - - 0 - 0 - UART2 00007CH ULS2 [R/W] - - - - 0000 000080H UTIM2/UTIMR2 [R/W] 00000000 00000000 DRCL2 [W] - - - - - - - - UTIMC2 [R/W] 0 - - - 0 - 01 U-TIMER2 000084H SMCS0 [R/W, R] 00000010 - - - - 00-0 SES0 [R/W] - - - - - - 00 SDR0 [R/W] 00000000 SIO 0 000088H SMCS1 [R/W, R] 00000010 - - - - 00 - 0 SES1 [R/W] - - - - - - 00 SDR1 [R/W] 00000000 SIO 1 00008CH CDCR0 [R/W] 0 - - - 1111 Reserved CDCR1 [R/W] 0 - - - 1111 Reserved SIO 0/1 Prescaler 000090H Reserved 000094H IBCR [R/W] 00000000 IBSR [R] 00000000 IADR [R/W] -XXXXXXX ICCR [R/W] - - 0XXXXX I2C (old) → new I2C from addr 0x184 000098H IDAR [R/W] XXXXXXXX IDBL [R/W] - - - - - - - 0 00009CH ADMD [R/W, W] - - - X0000 ADCH [R/W] 00000000 ADCS [R/W, W] 0000 - - 00 A/D Converter 0000A0H ADCD [R/W] 000000XX XXXXXXXX ADBL [R/W] - - - - - - - 0 0000A4H DACR [R/W] - - - - - 000 DADR0 [R/W] - - - - - - XX XXXXXXXX DAC 0000A8H DADR1 [R/W] - - - - - - XX XXXXXXXX DDBL [R/W] - - - - - - - 0 0000ACH IOTDBL0 [R/W] - - - - - 000 ICS01 [R/W] 00000000 IOTDBL1 [R/W] - - - - - 000 ICS23 [R/W] 00000000 Input Capture 0, 1, 2, 3 0000B0H IPCP0 [R] XXXXXXXX XXXXXXXX IPCP1 [R] XXXXXXXX XXXXXXXX 0000B4H IPCP2 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 0000B8H OCS01 [R/W] reserved Output Compare 0, 1, 2.3 0000BCH OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP1 [R/W] XXXXXXXX XXXXXXXX 0000C0H OCCP2 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX 0000C4H Reserved 0000C8H TCDT0 [R/W] XXXXXXXX XXXXXXXX TCCS0 [R/W] - 0000000 Free Running Counter 0 for ICU/OCU 0000CCH TCDT1 [R/W] XXXXXXXX XXXXXXXX TCCS1 [R/W] - 0000000 Free Running Counter 1 for ICU/OCU 0000D0H ZPD0 [R/W] 00000010 PWC0 [R/W] - - 000 - - 0 ZPD1 [R/W] 00000010 PWC1 [R/W] 00000 - - 0 SMC 0, 1 0000D4H ZPD2 [R/W] 00000010 PWC2 [R/W] - - 000 - - 0 ZPD3 [R/W] 00000010 PWC3 [R/W] 00000 - - 0 SMC 2, 3 0000D8H PWC20 [R/W] XXXXXXXX PWC10 [R/W] XXXXXXXX PWS20 [R/W] - 0000000 PWS10 [R/W] - - 000000 SMC 0 0000DCH PWC21 [R/W] XXXXXXXX PWC11 [R/W] XXXXXXXX PWS21 [R/W] - 0000000 PWS11 [R/W] - - 000000 SMC 1 0000E0H PWC22 [R/W] XXXXXXXX PWC12 [R/W] XXXXXXXX PWS22 [R/W] - 0000000 PWS12 [R/W] - - 000000 SMC 2 0000E4H PWC23 [R/W] XXXXXXXX PWC13 [R/W] XXXXXXXX PWS23 [R/W] - 0000000 PWS13 [R/W] - - 000000 SMC 3 0000E8H SMDBL0 [R/W] - - - - - - - 0 SMDBL1 [R/W] - - - - - - 0 SMDBL2 [R/W] - - - - - - - 0 SMDBL3 [R/W] - - - - - - - 0 SMC 0, 1, 2, 3 0000ECH SGDBL [R/W] - - - - - - - 0 SGCR [R/W, R] Sound generator 0000F0H SGAR [R/W] 00000000 SGFR [R/W] XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX 0000F4H WTDBL [R/W] - - - - - - - 0 WTCR [R/W, R] 00000000 000 - 0000 Real Time Clock (WatchTimer) 0000F8H WTBR [R/W] - - XXXXXX XXXXXXXX XXXXXXXX 0000FCH WTHR [R/W] - - - 00000 WTMR [R/W] - - 000000 WTSR [R/W] - - 000000 000100H TMRLR3 [W] XXXXXXXX XXXXXXXX TMR3 [R] XXXXXXXX XXXXXXXX Reload Timer 3 000104H TMCSR3 [R/W] - - - - XX - - - - - XXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000108H TMRLR4 [W] XXXXXXXX XXXXXXXX TMR4 [R] XXXXXXXX XXXXXXXX Reload Timer 4 00010CH TMCSR4 [R/W] - - - - XX - - - - - XXXXX 000110H TMRLR5 [W] XXXXXXXX XXXXXXXX TMR5 [R] XXXXXXXX XXXXXXXX Reload Timer 5 000114H TMCSR5 [R/W] - - - - XX - - - - - XXXXX 000118H GCN10 [R/W] 00110010 00010000 PDBL0 [R/W] - - - 00000 GCN20 [R/W] - - - - 0000 PWM Control 0 00011CH GCN11 [R/W] 00110010 00010000 PDBL1 [R/W] - - - 00000 GCN21 [R/W] - - - - 0000 PWM Control 1 000120H PTMR0 [R] 11111111 11111111 PCSR0 [W] XXXXXXXX XXXXXXXX PWM0 000124H PDUT0 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 0000000 - PCNL0 [R/W] 000000 - 0 000128H PTMR1 [R] 11111111 11111111 PCSR1 [W] XXXXXXXX XXXXXXXX PWM1 00012CH PDUT1 [W] XXXXXXXX XXXXXXXX PCNH1 [R/W] 0000000 - PCNL1 [R/W] 000000 - 0 000130H PTMR2 [R] 11111111 11111111 PCSR2 [W] XXXXXXXX XXXXXXXX PWM2 000134H PDUT2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 0000000 - PCNL2 [R/W] 000000 - 0 000138H PTMR3 [R] 11111111 11111111 PCSR3 [W] XXXXXXXX XXXXXXXX PWM3 00013CH PDUT3 [W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 0000000 - PCNL3 [R/W] 000000 - 0 000140H PTMR4 [R] 11111111 11111111 PCSR4 [W] XXXXXXXX XXXXXXXX PWM4 000144H PDUT4 [W] XXXXXXXX XXXXXXXX PCNH4 [R/W] 0000000 - PCNL4 [R/W] 000000 - 0 000148H PTMR5 [R] 11111111 11111111 PCSR5 [W] XXXXXXXX XXXXXXXX PWM5 00014CH PDUT5 [W] XXXXXXXX XXXXXXXX PCNH5 [R/W] 0000000 - PCNL5 [R/W] 000000 - 0 000150H PTMR6 [R] 11111111 11111111 PCSR6 [W] XXXXXXXX XXXXXXXX PWM6 000154H PDUT 6 [W] XXXXXXXX XXXXXXXX PCNH6 [R/W] 0000000 - PCNL6 [R/W] 000000 - 0

: Old and new I2C share this bit. (Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000158H PTMR7 [R] 11111111 11111111 PCSR7 [W] XXXXXXXX XXXXXXXX PWM7 00015CH PDUT7 [W] XXXXXXXX XXXXXXXX PCNH7 [R/W] 0000000 - PCNL7 [R/W] 000000 - 0 000160H Reserved 000164H CMCR [R/W] 11111111 0000000 CMPR [R/W] Clock Modulation 000168H CMLS0 [R/W] 01110111 1111111 CMLS1 [R/W] 01110111 1111111 00016CH CMLS2 [R/W] 01110111 1111111 CMLS3 [R/W] 01110111 1111111 000170H CMLT0 [R/W, R] - - - - -100 00000010 CMLT1 [R/W, R] 11110100 00000010 000174H CMLT2 [R/W] - - - - -100 00000010 CMLT3 [R/W, R] - - - - -100 00000010 000178H CMAC [R/W] 11111111 1111111 CMTS [R] - -000001 01111111 00017CH PDRCR [R/W] - - - - - 000 Power down reset 000180H ACCDBL[R/W] - - - - - - - 0 ACSR [R/W, R] - - - XXX00 Alarm comparator 000184H IBCR2 [R/W] 00000000 IBSR2 [R] 00000000 ITBAH [R/W] - - - - - - 00 ITBAL [R/W] 00000000 I2C (new) (*) old and new I2C share this bit ! 000188H ITMKH [R/W, R] 00 - - - - 11 ITMKL [R/W] 11111111 ISMK [R/W] 01111111 ISBA [R/W] - 0000000 00018CH IDARH [-] 00000000 IDAR2 [R/W] 00000000 ICCR2 [R/W] - 0011111 IDBL2 (*) [R/W] - - - - - - - 0 000190H CUCR [R/W, R] CUTD [R/W] 10000000 00000000 Calibration Unit of 32 kHz oscillator 000194H CUTR1 [R] CUTR2 [R] 00000000 00000000 000198H to 0001F8H Reserved 0001FCH F362MD [R/W] 00000000 F362 Mode Register 000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMAC 000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMAC 00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000228H to 00023CH 000240H DMACR [R/W] 000244H to 0002FCH Reserved 000300H IRBS [R/W, R] 00000000 00000001 00100000 - - - - - - - - Instruction Cache 000304H ISIZE [R/W] - - - - - -11 000308H to 0003E0H Reserved 0003E4H ICHRC [R/W] 0-000000 Instruction Cache 0003E8H to 0003ECH Reserved

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Bit Search Module 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H DDRG [R/W] 00000000 DDRH [R/W] 00000000 DDRI [R/W] - - - -0- - - DDRJ [R/W] 00000000 R-bus Port Direction Register 000404H DDRK [R/W] 00000000 DDRL [R/W] 00000000 DDRM [R/W] - - - -0000 DDRN [R/W] - -000000 000408H DDRO [R/W] 00000000 DDRP [R/W] - - - -0000 DDRQ [R/W] - -000000 DDRR [R/W] 00000000 00040CH DDRS [R/W] 00000000 000410H PFRG [R/W] 00000000 PFRH [R/W] 00000000 PFRI [R/W] - - - -0- - - PFRJ [R/W] 00000000 R-bus Port Function Register 000414H PFRK [R/W] 00000000 PFRL [R/W] 00000000 PFRM [R/W] - - - -0000 PFRN [R/W] - -000000 000418H PFRO [R/W] 00000000 PFRP [R/W] 00000000 PFRQ [R/W] - -000000 PFRR [R/W] 00000000 00041CH PFRS [R/W] 00000000 000420H to 00043CH Reserved 000440H ICR00 [R/W, R] - - -11111 ICR01 [R/W, R] - - -11111 ICR02 [R/W, R] - - -11111 ICR03 [R/W, R] - - -11111 Interrupt Control unit 000444H ICR04 [R/W, R] - - -11111 ICR05 [R/W, R] - - -11111 ICR06 [R/W, R] - - -11111 ICR07 [R/W, R] - - -11111 000448H ICR08 [R/W, R] - - -11111 ICR09 [R/W, R] - - -11111 ICR10 [R/W, R] - - -11111 ICR11 [R/W, R] - - -11111 00044CH ICR12 [R/W, R] - - -11111 ICR13 [R/W, R] - - -11111 ICR14 [R/W, R] - - -11111 ICR15 [R/W, R] - - -11111 000450H ICR16 [R/W, R] - - -11111 ICR17 [R/W, R] - - -11111 ICR18 [R/W, R] - - -11111 ICR19 [R/W, R] - - -11111 000454H ICR20 [R/W, R] - - -11111 ICR21 [R/W, R] - - -11111 ICR22 [R/W, R] - - -11111 ICR23 [R/W, R] - - -11111 000458H ICR24 [R/W, R] - - -11111 ICR25 [R/W, R] - - -11111 ICR26 [R/W, R] - - -11111 ICR27 [R/W, R] - - -11111

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 00045CH ICR28 [R/W, R] - - -11111 ICR29 [R/W, R] - - -11111 ICR30 [R/W, R] - - -11111 ICR31 [R/W, R] - - -11111 Interrupt Control unit 000460H ICR32 [R/W, R] - - -11111 ICR33 [R/W, R] - - -11111 ICR34 [R/W, R] - - -11111 ICR35 [R/W, R] - - -11111 000464H ICR36 [R/W, R] - - -11111 ICR37 [R/W, R] - - -11111 ICR38 [R/W, R] - - -11111 ICR39 [R/W, R] - - -11111 000468H ICR40 [R/W, R] - - -11111 ICR41 [R/W, R] - - -11111 ICR42 [R/W, R] - - -11111 ICR43 [R/W, R] - - -11111 00046CH ICR44 [R/W, R] - - -11111 ICR45 [R/W, R] - - -11111 ICR46 [R/W, R] - - -11111 ICR47 [R/W, R] - - -11111 000470H to 00047CH Reserved 000480H RSRR [R/W, R] 10000000 STCR [R/W] 00110011 TBCR [R/W] X0000X00 CTBR [W] XXXXXXXX Clock Control unit 000484H CLKR [R/W] 00000000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 000488H to 0005FCH Reserved 000600H T-unit Port Direction Register 000604H DDR7 [R/W] 00000000 000608H DDR8 [R/W] 00000000 DDR9 [R/W] 00000000 DDRB [R/W] 00000000 00060CH 000610H T-unit Port Function Register 000614H PFR7 [R/W] 00001111 000618H PFR8 [R/W] 111110-0 PFR9 [R/W] 11110101 PFRB [R/W] 00000000 00061CH 000620H 000624H PFR27 [R/W] 1111-00- 000628H to 00063FH Reserved

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000640H ASR0 [W] 00000000 00000000 AMR0 [W] 11111000 11111111 T-unit 000644H ASR1 [W] 00000000 00000000 AMR1 [W] 00000000 00000000 000648H ASR2 [W] 00000000 00000000 AMR2 [W] 00000000 00000000 00064CH ASR3 [W] 00000000 00000000 AMR3 [W] 00000000 00000000 000650H ASR4 [W] 00000000 00000000 AMR4 [W] 00000000 00000000 000654H ASR5 [W] 00000000 00000000 AMR5 [W] 00000000 00000000 000658H ASR6 [W] 00000000 00000000 AMR6 [W] 00000000 00000000 00065CH ASR7 [W] 00000000 00000000 AMR7 [W] 00000000 00000000 000660H AMD0 [R/W] -00XX111 AMD1 [R/W] -XXXXXXX AMD2 [R/W] - -XXXXXX AMD3 [R/W] - -XXXXXX 000664H AMD4 [R/W] - -XXXXXX AMD5 [R/W] - -XXXXXX AMD6 [R/W] -XXXXXXX AMD7 [R/W] -XXXXXXX 000668H CSE 11000011 00066CH 000670H CHE 11111111 000674H to 0007F8H Reserved 0007FCH MODR [W] XXXXXXXX Mode Register 000800H to 000AFCH Reserved

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000B00H ESTS0 X0000000 ESTS1 XXXXXXXX ESTS2 XXXXXXXX DSU 000B04H ECTL0 0X000000 ECTL1 00000000 ECTL2 000X0000 ECTL3 00000X11 000B08H ECNT0 XXXXXXXX ECNT1 XXXXXXXX EUSA XXX0000X EDTC 0000XXXX 000B0CH EWPT XXXXXXXX XXXXXXXX 000B10H EDTR0 XXXXXXXX XXXXXXXX EDTR1 XXXXXXXX XXXXXXXX 000B14H to 000B1CH 000B20H EIA0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B24H EIA1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B28H EIA2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B2CH EIA3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B30H EIA4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B34H EIA5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B38H EIA6 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B3CH EIA7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B40H EDTA XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B44H EDTM XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B48H EOA0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B4CH EOA1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B50H EPCR XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B54H EPSR XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 000B58H EIAM0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSU 000B5CH EIAM1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B60H EOAM0/EODM0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B64H EOAM1/EODM1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B68H EOD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B6CH EOD1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMAC 001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028H to 003FFCH Reserved 004000H to 006FFFH Reserved

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 007000H FMCS [R/W] 1110X000 Flash Memory Control Register 007004H FMWT [R/W] - -000011 007008H to 00FFFCH Reserved 010000H to 010FFCH (for exact address range see chapter about I-cache) on F362GA and F369GA no cache, but 4 K I-RAM are available I-Cache 4 KB 011000H to 011FFCH Reserved 012000H to 01FFFCH Reserved 020000H to 03BFFCH Reserved 03C000H to 03FFFCH Only first 12 KB are available on F362GA User RAM 16 KB (D-Bus) 040000H to 043FFCH Only first 4 K are available on F362GA Fast RAM 16 KB (F-Bus) 044000H to 0FEFFC Reserved 050000H to 0507FCH Boot ROM 2 KB (F-Bus) 050800H to 07FFF4H reserved

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 080000H to 09FFFCH Sector 0 64 KB Sector 7 64 KB Flash Memory 512 K on F-Bus 0A0000H to 0BFFFC Sector 1 64 KB Sector 8 64 KB 0C0000H to 0DFFFC Sector 2 64 KB Sector 9 64 KB 0E0000H to 0EFFFC Sector 3 32 KB Sector 10 32 KB 0F0000H to 0F3FFCH Sector 4 8 KB Sector 11 8 KB 0F4000H to 0F7FFCH Sector 5 8 KB Sector 12 8 KB 0F8000H to 0FFFF4H Sector 6 16 KB Sector 13 16 KB 0FFFF8H FMV [R] 06 00 00 00H Fixed Reset/Mode Vector 0FFFFCH FRV [R] 00 05 00 00H Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 100000H BVALR0 [R/W] 00000000 00000000 TREQR0 [R/W] 00000000 00000000 CAN 0 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. 100004H TCANR0 [W] 00000000 00000000 TCR0 [R/W] 00000000 00000000 100008H RCR0 [R/W] 00000000 00000000 RRTRR0 [R/W] 00000000 00000000 10000CH ROVRR0 [R/W] 00000000 00000000 RIER0 [R/W] 00000000 00000000 100010H CSR0 [R/W, R] 00000000 00000001 LEIR0 [R/W] 000-0000 100014H RTEC0 [R] 00000000 00000000 BTR0 [R/W] -1111111 11111111 100018H IDER0 [R/W] XXXXXXXX XXXXXXXX TRTRR0 [R/W] 00000000 00000000 10001CH RFWTR0 [R/W] XXXXXXXX XXXXXXXX TIER0 [R/W] 00000000 00000000 100020H AMSR0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100024H AMR00 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100028H AMR10 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10002CH to 100048H GENERAL PURPOSE RAM [R/W] 10004CH IDR00 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100050H IDR10 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100054H IDR20 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100058H IDR30 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10005CH IDR40 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100060H IDR50 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100064H IDR60 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100068H IDR70 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX CAN 0

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 10006CH IDR80 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX CAN 0 100070H IDR90 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100074H IDR100 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100078H IDR110 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10007CH IDR120 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100080H IDR130 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100084H IDR140 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100088H IDR150 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10008CH DLCR00 [R/W] DLCR10 [R/W] 100090H DLCR20 [R/W] DLCR30 [R/W] 100094H DLCR40 [R/W] DLCR50 [R/W] 100098H DLCR60 [R/W] DLCR70 [R/W] 10009CH DLCR80 [R/W] DLCR90 [R/W] 1000A0H DLCR100 [R/W] DLCR110 [R/W] 1000A4H DLCR120 [R/W] DLCR130 [R/W] 1000A8H DLCR140 [R/W] DLCR150 [R/W] 1000ACH DTR00 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000B4H DTR10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000BCH DTR20 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 1000C4H DTR30 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CAN 0 1000CCH DTR40 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000D4H DTR50 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000DCH DTR60 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000E4H DTR70 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000ECH DTR80 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000F4H DTR90 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1000FCH DTR100 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100104H DTR110 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10010CH DTR120 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100114H DTR130 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10011CH DTR140 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100124H DTR150 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10012CH CREG0 [R/W] 00000000 00000110

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 100200H BVALR1 [R/W] 00000000 00000000 TREQR1 [R/W] 00000000 00000000 CAN 1 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. 100204H TCANR1 [W] 00000000 00000000 TCR1 [R/W] 00000000 00000000 100208H RCR1 [R/W] 00000000 00000000 RRTRR1 [R/W] 00000000 00000000 10020CH ROVRR1 [R/W] 00000000 00000000 RIER1 [R/W] 00000000 00000000 100210H CSR1 [R/W, R] 00000000 00000001 LEIR1 [R/W] 000-0000 100214H RTEC1 [R] 00000000 00000000 BTR1 [R/W] -1111111 11111111 100218H IDER1 [R/W] XXXXXXXX XXXXXXXX TRTRR1 [R/W] 00000000 00000000 10021CH RFWTR1 [R/W] XXXXXXXX XXXXXXXX TIER1 [R/W] 00000000 00000000 100220H AMSR1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100224H AMR01 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100228H AMR11 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10022CH to 100248H GENERAL PURPOSE RAM [R/W] 10024CH IDR01 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100250H IDR11 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100254H IDR21[R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100258H IDR31 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX- 10025CH IDR41 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100260H IDR51 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100264H IDR61 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 100268H IDR71 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX CAN 1 10026CH IDR81 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100270H IDR91 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100274H IDR101 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100278H IDR111 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10027CH IDR121 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - - 100280H IDR131 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100284H IDR141 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100288H IDR151 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10028CH DLCR01 [R/W] DLCR11 [R/W] 100290H DLCR21 [R/W] DLCR31 [R/W] 100294H DLCR41 [R/W] DLCR51 [R/W] 100298H DLCR61 [R/W] DLCR71 [R/W] 10029CH DLCR81[R/W] DLCR91 [R/W] 1002A0H DLCR101 [R/W] DLCR111 [R/W] 1002A4H DLCR121 [R/W] DLCR131 [R/W] 1002A8H DLCR141 [R/W] DLCR151 [R/W] 1002ACH DTR01 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 1002B4H DTR11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CAN 1 1002BCH DTR21 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002C4H DTR31 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002CCH DTR41 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002D4H DTR51 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002DCH DTR61 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002E4H DTR71 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002ECH DTR81 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002F4H DTR91 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1002FCH DTR101 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100304H DTR111 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10030CH DTR121 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100314H DTR131 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10031CH DTR141 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 100324H DTR151 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CAN 1 10032CH CREG1 [R/W] 00000000 00000110 100400H BVALR2 [R/W] 00000000 00000000 TREQR2 [R/W] 00000000 00000000 CAN 2 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. 100404H TCANR2 [W] 00000000 00000000 TCR2 [R/W] 00000000 00000000 100408H RCR2 [R/W] 00000000 00000000 RRTRR1 [R/W] 00000000 00000000 10040CH ROVRR2 [R/W] 00000000 00000000 RIER2 [R/W] 00000000 00000000 100410H CSR2 [R/W, R] 00000000 00000001 LEIR2 [R/W] 000-0000 100414H RTEC2 [R] 00000000 00000000 BTR2 [R/W] -1111111 11111111 100418H IDER2 [R/W] XXXXXXXX XXXXXXXX TRTRR2 [R/W] 00000000 00000000 10041CH RFWTR2 [R/W] XXXXXXXX XXXXXXXX TIER2 [R/W] 00000000 00000000 100420H AMSR2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100424H AMR02 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100428H AMR12 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10042CH to 100448H GENERAL PURPOSE RAM [R/W] 10044CH IDR02 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100450H IDR12 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100454H IDR22[R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100458H IDR32 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX- 10045CH IDR42 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 100460H IDR52 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX CAN 2 100464H IDR62 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100468H IDR72 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10046CH IDR82 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100470H IDR92 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100474H IDR102 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100478H IDR112 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10047CH IDR122 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - - 100480H IDR132 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100484H IDR142 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100488H IDR152 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10048CH DLCR02 [R/W] DLCR12 [R/W] 100490H DLCR22 [R/W] DLCR32 [R/W] 100494H DLCR42 [R/W] DLCR52 [R/W] 100498H DLCR62 [R/W] DLCR72 [R/W] 10049CH DLCR82[R/W] DLCR92 [R/W] 1004A0H DLCR102 [R/W] DLCR112 [R/W] 1004A4H DLCR122 [R/W] DLCR132 [R/W] 1004A8H DLCR142 [R/W] DLCR152 [R/W]

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 1004ACH DTR02 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CAN 2 1004B4H DTR12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004BCH DTR22 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004C4H DTR32 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004CCH DTR42 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004D4H DTR52 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004DCH DTR62 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004E4H DTR72 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004ECH DTR82 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004F4H DTR92 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1004FCH DTR102 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100504H DTR112 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10050CH DTR122 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100514H DTR132 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 10051CH DTR142 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CAN 2 100524H DTR152 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10052CH CREG2 [R/W] 00000000 00000110 100600H BVALR3 [R/W] 00000000 00000000 TREQR3 [R/W] 00000000 00000000 CAN 3 Remark : Address range for CAN 0 to CAN 3 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. 100604H TCANR3 [W] 00000000 00000000 TCR3 [R/W] 00000000 00000000 100608H RCR3 [R/W] 00000000 00000000 RRTRR31 [R/W] 00000000 00000000 10060CH ROVRR3 [R/W] 00000000 00000000 RIER3 [R/W] 00000000 00000000 100610H CSR3 [R/W, R] 00000000 00000001 LEIR3 [R/W] 000-0000 100614H RTEC3 [R] 00000000 00000000 BTR3 [R/W] -1111111 11111111 100618H IDER3 [R/W] XXXXXXXX XXXXXXXX TRTRR3 [R/W] 00000000 00000000 10061CH RFWTR3 [R/W] XXXXXXXX XXXXXXXX TIER3 [R/W] 00000000 00000000 100620H AMSR3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100624H AMR03 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100628H AMR13 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10062CH to 100648H GENERAL PURPOSE RAM [R/W] 10064CH IDR03 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100650H IDR13 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100654H IDR23[R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100658H IDR33 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX-

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 10065CH IDR43 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX CAN 3 100660H IDR53 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100664H IDR63 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100668H IDR73 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10066CH IDR83 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100670H IDR93 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100674H IDR103 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100678H IDR113 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10067CH IDR123 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - - 100680H IDR133 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100684H IDR143 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 100688H IDR153 [R/W] XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX 10068CH DLCR032 [R/W] DLCR13 [R/W] 100690H DLCR232 [R/W] DLCR33 [R/W] 100694H DLCR43 [R/W] DLCR53 [R/W] 100698H DLCR63 [R/W] DLCR733 [R/W] 10069CH DLCR83[R/W] DLCR93 [R/W] 1006A0H DLCR103 [R/W] DLCR113 [R/W] 1006A4H DLCR123 [R/W] DLCR133 [R/W] 1006A8H DLCR143 [R/W] DLCR153 [R/W]

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 1006ACH DTR03 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CAN 3 1006B4H DTR13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006BCH DTR23 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006C4H DTR33 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006CCH DTR43 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006D4H DTR53 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006DCH DTR63 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006E4H DTR73 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006ECH DTR83 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006F4H DTR93 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1006FCH DTR103 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100704H DTR113 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10070CH DTR123 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 100714H DTR133 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register Block ++++0 ++++1 ++++2 ++++3 10071CH DTR143 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CAN 3 100724H DTR153 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10072CH CREG3 [R/W] 00000000 00000110

I INTERRUPT CAUSES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTER (Continued) Interrupt Interrupt number Interrupt level *1 Interrupt vector *2 RN Decimal Hexa- decimal Setting Register Register address Offset Default Vector address Reset 0x3FC 0x000FFFFC Mode vector 0x3F8 0x000FFFF8 System reserved 0x3F4 0x000FFFF4 System reserved 0x3F0 0x000FFFF0 System reserved 0x3EC 0x000FFFEC System reserved 0x3E8 0x000FFFE8 System reserved 0x3E4 0x000FFFE4 Co-processor fault trap *4 0x3E0 0x000FFFE0 Co-processor error trap *4 0x3DC 0x000FFFDC INTE instruction *4 0x3D8 0x000FFFD8 Instruction break exception *4 0x3D4 0x000FFFD4 Operand break trap *4 0x3D0 0x000FFFD0 Step trace trap *4 0x3CC 0x000FFFCC NMI interrupt (tool) *4 0x3C8 0x000FFFC8 Undefined instruction exception 0x3C4 0x000FFFC4 NMI request FH fixed 0x3C0 0x000FFFC0 External Interrupt 0 ICR00 0x440 0x3BC 0x000FFFBC External Interrupt 1 ICR01 0x441 0x3B8 0x000FFFB8 External Interrupt 2 ICR02 0x442 0x3B4 0x000FFFB4 External Interrupt 3 ICR03 0x443 0x3B0 0x000FFFB0 External Interrupt 4 ICR04 0x444 0x3AC 0x000FFFAC External Interrupt 5 ICR05 0x445 0x3A8 0x000FFFA8 External Interrupt 6 ICR06 0x446 0x3A4 0x000FFFA4 External Interrupt 7 ICR07 0x447 0x3A0 0x000FFFA0 Reload Timer 0 ICR08 0x448 0x39C 0x000FFF9C Reload Timer 1 ICR09 0x449 0x398 0x000FFF98 Reload Timer 2 ICR10 0x44A 0x394 0x000FFF94 CAN 0 RX ICR11 0x44B 0x390 0x000FFF90 CAN 0 TX/NS ICR12 0x44C 0x38C 0x000FFF8C CAN 1 RX ICR13 0x44D 0x388 0x000FFF88 CAN 1 TX/NS ICR14 0x44E 0x384 0x000FFF84

(Continued) Interrupt Interrupt number Interrupt level *1 Interrupt vector *2 RN Decimal Hexa- decimal Setting Register Register address Offset Default Vector address CAN 2 RX ICR15 0x44F 0x380 0x000FFF80 CAN 2 TX/NS ICR16 0x450 0x37C 0x000FFF7C CAN 3 RX *5 ICR17 0x451 0x378 0x000FFF78 CAN 3 TX/NS *5 ICR18 0x452 0x374 0x000FFF74 PPG 0/1 ICR19 0x453 0x370 0x000FFF70 PPG 2/3 ICR20 0x454 0x36C 0x000FFF6C PPG 4/5 ICR21 0x455 0x368 0x000FFF68 PPG 6/7 ICR22 0x456 0x364 0x000FFF64 Reload Timer 3 ICR23 0x457 0x360 0x000FFF60 Reload Timer 4 ICR24 0x458 0x35C 0x000FFF5C Reload Timer 5 ICR25 0x459 0x358 0x000FFF58 ICU 0/1 ICR26 0x45A 0x354 0x000FFF54 OCU 0/1 ICR27 0x45B 0x350 0x000FFF50 ICU 2/3 ICR28 0x45C 0x34C 0x000FFF4C OCU 2/3 ICR29 0x45D 0x348 0x000FFF48 ADC ICR30 0x45E 0x344 0x000FFF44 Timebase Overflow ICR31 0x45F 0x340 0x000FFF40 Free Running Counter 0 ICR32 0x460 0x33C 0x000FFF3C Free Running Counter 1 ICR33 0x461 0x338 0x000FFF38 SIO 0 *6 ICR34 0x462 0x334 0x000FFF34 SIO 1 *6 ICR35 0x463 0x330 0x000FFF30 Sound Generator ICR36 0x464 0x32C 0x000FFF2C UART 0 RX ICR37 0x465 0x328 0x000FFF28 UART 0 TX ICR38 0x466 0x324 0x000FFF24 UART 1 RX ICR39 0x467 0x320 0x000FFF20 UART 1 TX ICR40 0x468 0x31C 0x000FFF1C UART 2 RX ICR41 0x469 0x318 0x000FFF18 UART 2 TX ICR42 0x46A 0x314 0x000FFF14 I2C*7 ICR43 0x46B 0x310 0x000FFF10 Alarm Comparator ICR44 0x46C 0x30C 0x000FFF0C RTC (Watchtimer) / Calibration Unit ICR45 0x46D 0x308 0x000FFF08 DMA ICR46 0x46E 0x304 0x000FFF04

(Continued) *1 : The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (0x000FFC00) . The TBR is initialized to this value by a reset.After execution of the internal boot ROM TBR is set to 0x00FFC00. *3 : Used by REALOS *4 : System reserved *5 : Only available on MB91FV360GA *6 : DMA to/from SIO only implemented on F369GA. *7 : DMA to/from I2C is not implemented on MB91F362GA. Remarks : The 1-Kbyte area from the address specified in TRB is the EIT vector area. Each vector consists of four bytes. The following formula shows the relationship between the vector number and vector address. vector = TBR + vctofs = TBR + (3FCH−4×vct) vctadr : Vector address vctofs : Vector offset vct : Vector number Interrupt Interrupt number Interrupt level *1 Interrupt vector *2 RN Decimal Hexa- decimal Setting Register Register address Offset Default Vector address Delayed interrupt activation bit ICR47 0x46F 0x300 0x000FFF00 System reserved *3 0x2FC 0x000FFEFC System reserved *3 0x2F8 0x000FFEF8 Security vector 0x2F4 0x000FFEF4 System reserved (ICR51) 0x473 0x2F0 0x000FFEF0 System reserved (ICR52) 0x474 0x2EC 0x000FFEEC System reserved (ICR53) 0x475 0x2E8 0x000FFEE8 System reserved (ICR54) 0x476 0x2E4 0x000FFEE4 System reserved (ICR55) 0x477 0x2E0 0x000FFEE0 System reserved (ICR56) 0x478 0x2DC 0x000FFEDC System reserved (ICR57) 0x479 0x2D8 0x000FFED8 System reserved (ICR58) 0x47A 0x2D4 0x000FFED4 System reserved (ICR59) 0x47B 0x2D0 0x000FFED0 System reserved (ICR60) 0x47C 0x2CC 0x000FFECC System reserved (ICR61) 0x47D 0x2C8 0x000FFEC8 System reserved (ICR62) 0x47E 0x2C4 0x000FFEC4 System reserved (ICR63) 0x47F 0x2C0 0x000FFEC0 Used by the INT instruction. to 255 to FF 0x2BC to 0x000 0x000FFEBC to 0x000FFC00

This section describes the instruction cache memory included in FR50 Family members and it operation. This only applies to MB91FV360GA. (1) General Description The instruction cache is temporary memory. When an external low-speed memory accesses an instruction code, the instruction cache stores the single-accessed code to increase the second and subsequent access speeds.Setting this memory to the RAM mode enables software to directly read and write instruction cache data RAM and tag RAM. (2) Main Body Structure Instruction Cache Structure

FR basic instruction length : 2 bytes
Block arrangement system : 2-way set associative system
Block One way consists of 128 blocks. One block consists of 16 bytes ( = 4 sub-blocks) . One sub-block consists of 4 bytes ( = 1 bus access unit) . 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes Way 1 Way 2 Cache tag Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 0 Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 127 Block 0 Block 127 Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Cache tag Cache tag Cache tag 128 blocks 128 blocks

(3) Control Register Structure IRBS [bits 15 to 12] These bits are used to set the base address of cache RAM at access in the RAM mode. Align cache RAM in units of 4 K bytes. These bits are initialized by INIT. The initial value is the 00012000H address. The ICHCR (I-CacHe Control Register) controls the instruction cache operations. Writing to the ICHCR does not affect caching of instructions fetched within three subsequent cycles. IRBS (32 bits) Initial value Address : 00000300H 00000000B Initial value 00000001B ICR26 Initial value Address : 00000302H 0010 - - - -B Initial value - - - - - - - - B ISIZE (8 bits) Initial value 00000307H - - - - - - 11B ICHCR (8 bits) Initial value 000003E7H 0 - 000000B R R R R R R R R R R R R R R R R R/W R/W R/W IRBS R/W IRBS IRBS IRBS R/W R/W SIZE1 SIZE0 R/W R/W R/W R/W R/W R/W R/W RAM GBLK ALFL EOLK ELKR FLSH ENAB

The Boot ROM is a fixed start-up routine which is located at FF000 (Reset entry) and will therefore be executed after every RST or INIT. The purpose of this ROM is to configure the device after a reset and to provide a simple serial bootloader for programming the embedded Flash memories. The Boot ROM contains three logical parts : (1) Chip Initializations Immediately after each reset, the following settings will be made : CS0 : 200000…2FFFFF, 32 Bit Bus, 1 wait-state (default external access) CS7 : 100000…10FFFF, 16 Bit Bus, 1 wait-state (CAN) In addition, the Table-Base Register will be initialized to 1FFC00 (F361GA only) and the synchronous reset (see TBCR) will be enabled. (2) Check for Bootcondition After the chip initialization, the “Security-Vector” will be checked (Vector #66) . The purpose of this feature is to disable the bootstraploader due to security reasons. The RSRR (reset cause register) will be read and saved. If no power-on reset (external INITX input, RSRR = 0x80) is indicated, a branch to the user application will be initiated (Branch to 1F4000) . If INITX was detected and the “Security-Vector” check okay, the following conditions must be met in order to start the Bootstraploader : Within a certain time, the start-up character “V” must be received via UART0 (9600, 8N1) . The time-out is set to 200 ms. (3) Bootstraploader If the Bootcondition was met, an acknowledge character “F” will be transmitted via UART0 to indicate that the Bootloader is ready to accept commands. 4 different commands are possible : Receive and write to a specified memory block Dump the contents of a specified memory block Initiate a “CALL” to a certain location Re-dump a calculated checksum for verification (4) Configuration Register (F362Mode Register F362MD) This register is used to control which pins of the external bus interface are active, where the pins for the external DMA channel are located and which I2C module is used. address 00001FEH access Initial value R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ASYMCLKT HIZ_D_A HIZ_ECLK HIZ_D_23_16 HIZ_D_15_0 DMASWP IICSEL ADRSWAP R/W

An important property of MCUs and other electronic devices is their electromagnetic compatibility - EMC. Besides a low susceptibility against external interferences, a low radiated emission is desired to avoid interference of adjacent devices. Particularly the system clock and derived signals such as data- and address busses contribute significantly to the radiated emission. The purpose of the clock modulator is to spread the energy of these signals over a wide range of frequencies and thus reducing the amplitudes of the fundamental and harmonic frequencies. With the use of an advanced frequency modulation algorithm, the Fujitsu built in clock modulator can achieve an attenuation of up to 20-25 dB compared to non modulated clock operation. Since the modulator is highly configurable, it can be optimally adjusted to the actual application in order to achieve minimal electromagnetic interference. By default, the modulator is disabled and the MCU is running with unmodulated clock. If you plan to use this feature, please contact Fujitsu.

The I/O port registers consist of the “port data registers (PDR) ”, the “data direction registers (DDR) ” and the “port function registers (PFR) ”. The bits in PDRs correspond to the bits in DDRs and PFRs. Similarly, the register bits correspond to the port pins. The port data registers contain the port I/O data and the data direction registers specify whether the correspond- ing bits (pins) are inputs or outputs. Bits set to “0” are inputs and bits set to “1” are outputs. The port function registers specify whether the port is used as peripheral port or as “I/O” port. Usually bits set to “0” mean I/O port and bits set to “1” mean functional port. In case of analog peripherals there is additional circuitry to ensure that the digital logic is not disturbed by the analog signals. If the analog input function e.g. ADC is enabled the digital input is fixed to “0”.

Input mode (DDR = “0”) PDR read : Reads the level on the corresponding external pin. PDR write : writes the PDR setting value.
Output mode (DDR = “1”) PDR read : Reads the PDR value. PDR write : Outputs the PDR value to the corresponding external pins.

(1) Register configuration Port Data Register (Continued) PDR7 Initial value Access Address : 00000007H 1111XXXXB R/W PDR8 Initial value Access Address : 00000008H XXXXXXXXB R/W PDR9 Initial value Access Address : 00000009H XXXXXXX1B R/W PDRB Initial value Access Address : 0000000BH XXXXXXXXB R/W PDRG Initial value Access Address : 00000010H XXXXXXXXB R/W PDRH Initial value Access Address : 00000011H XXXXXXXXB R/W PDRI Initial value Access Address : 00000012H X - - - X - - -B R/W PDRJ Initial value Access Address : 00000013H XXXXXXXXB R/W PDRK Initial value Access Address : 00000014H XXXXXXXXB R/W PDRL Initial value Access Address : 00000015H XXXXXXXXB R/W PDRM Initial value Access Address : 00000016H - - - - XXXXB R/W PDRN Initial value Access Address : 00000017H - -XXXXXXB R/W PDRO Initial value Access Address : 00000018H XXXXXXXXB R/W P76 P77 P75 P74 P73 P72 P71 P70 P86 P87 P85 P84 P83 P82 P81 P80 P96 P97 P95 P94 P93 P92 P91 P90 PB6 PB7 PB5 PB4 PB3 PB2 PB1 PB0 PG6 PG7 PG5 PG4 PG3 PG2 PG1 PG0 PG6 PG7 PG5 PG4 PG3 PG2 PG1 PG0 PH6 PH7 PH5 PH4 PH3 PH2 PH1 PH0 PI3 P17 PJ6 PJ7 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PK6 PK7 PK5 PK4 PK3 PK2 PK1 PK0 PL6 PL7 PL5 PL4 PL3 PL2 PL1 PL0 PM3 PM2 PM1 PM0 PN5 PN4 PN3 PN2 PN1 PN0 PO6 PO7 PO5 PO4 PO3 PO2 PO1 PO0

(Continued) PDRP Initial value Access Address : 00000019H XXXXXXXXB R/W PDRQ Initial value Access Address : 0000001AH --XXXXXXB R/W PDRR Initial value Access Address : 0000001BH XXXXXXXXB R/W PDRS Initial value Access Address : 0000001CH XXXXXXXXB R/W PP6 PP7 PP5 PP4 PP3 PP2 PP1 PP0 PQ5 PQ4 PQ3 PQ2 PQ1 PQ0 PR6 PR7 PR5 PR4 PR3 PR2 PR1 PR0 PS6 PS7 PS5 PS4 PS3 PS2 PS1 PS0

(Continued) DDR7 Initial value Access Address : 00000607H 00000000B R/W DDR8 Initial value Access Address : 00000608H 00000000B R/W DDR9 Initial value Access Address : 00000609H 00000000B R/W DDRB Initial value Access Address : 0000600BH 00000000B R/W DDRG Initial value Access Address : 00000400H 00000000B R/W DDRH Initial value Access Address : 00000401H 00000000B R/W DDRI Initial value Access Address : 00000402H - - - - 0 - - -B R/W DDRJ Initial value Access Address : 00000403H 00000000B R/W DDRK Initial value Access Address : 00000404H 00000000B R/W DDRL Initial value Access Address : 00000405H 00000000B R/W DDRM Initial value Access Address : 00000406H - - - - 0000B R/W DDRN Initial value Access Address : 00000407H - -000000B R/W DDRO Initial value Access Address : 00000408H 00000000B R/W P76 P77 P75 P74 P73 P72 P71 P70 P86 P87 P85 P84 P83 P82 P81 P80 P96 P97 P95 P94 P93 P92 P91 P90 PB6 PB7 PB5 PB4 PB3 PB2 PB1 PB0 PG6 PG7 PG5 PG4 PG3 PG2 PG1 PG0 PG6 PG7 PG5 PG4 PG3 PG2 PG1 PG0 PH6 PH7 PH5 PH4 PH3 PH2 PH1 PH0 PI3 PJ6 PJ7 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PK6 PK7 PK5 PK4 PK3 PK2 PK1 PK0 PL6 PL7 PL5 PL4 PL3 PL2 PL1 PL0 PM3 PM2 PM1 PM0 PN5 PN4 PN3 PN2 PN1 PN0 PO6 PO7 PO5 PO4 PO3 PO2 PO1 PO0

(Continued) DDRP Initial value Access Address : 00000409H 00000000B R/W DDRQ Initial value Access Address : 0000040AH --000000B R/W DDRR Initial value Access Address : 0000040BH 00000000B R/W DDRS Initial value Access Address : 0000040CH 00000000B R/W PP6 PP7 PP5 PP4 PP3 PP2 PP1 PP0 PQ5 PQ4 PQ3 PQ2 PQ1 PQ0 PR6 PR7 PR5 PR4 PR3 PR2 PR1 PR0 PS6 PS7 PS5 PS4 PS3 PS2 PS1 PS0

Port function registers (PFR) (Continued) PFR7 Initial value Access Address : 00000617H 00001111B R/W PFR8 Initial value Access Address : 00000618H 111110 - -B R/W PFR9 Initial value Access Address : 00000619H 11110101B R/W PFRB Initial value Access Address : 0000061BH 00000000B R/W PFR27 Initial value Access Address : 00000627H 1111 - 00 -B R/W PFRG Initial value Access Address : 00000410H 00000000B R/W PFRH Initial value Access Address : 00000411H 00000000B R/W PFRI Initial value Access Address : 00000412H - - - - 0 - - -B R/W PFRJ Initial value Access Address : 00000413H 00000000B R/W PFRK Initial value Access Address : 00000414H 00000000B R/W PFRL Initial value Access Address : 00000415H 00000000B R/W PFRM Initial value Access Address : 00000416H - - - - 0000B R/W PFRN Initial value Access Address : 00000417H - - 000000B R/W P76 P77 P75 P74 P73 P72 P71 P70 P86 P87 P85 P84 P83 P82 P96 P97 P95 P94 P93 P92 P91 P90 PB6 PB7 PB5 PB4 PB3 PB2 PB1 PB0 P276 P277 P275 P274 P273 P272 P271 P270 PG6 PG7 PG5 PG4 PG3 PG2 PG1 PG0 PH6 PH7 PH5 PH4 PH3 PH2 PH1 PH0 PI3 PJ6 PJ7 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PK6 PK7 PK5 PK4 PK3 PK2 PK1 PK0 PL6 PL7 PL5 PL4 PL3 PL2 PL1 PL0 PM3 PM2 PM1 PM0 PN5 PN4 PN3 PN2 PN1 PN0

(Continued) PFRO Initial value Access Address : 00000418H 00000000B R/W PFRP Initial value Access Address : 00000419H 00000000B R/W PFRQ Initial value Access Address : 0000041AH - - 000000B R/W PFRR Initial value Access Address : 0000041BH 00000000B R/W PFRS Initial value Access Address : 0000041CH 00000000B R/W PO6 PO7 PO5 PO4 PO3 PO2 PO1 PO0 PP6 PP7 PP5 PP4 PP3 PP2 PP1 PP0 PQ5 PQ4 PQ3 PQ2 PQ1 PQ0 PR6 PR7 PR5 PR4 PR3 PR2 PR1 PR0 PS6 PS7 PS5 PS4 PS3 PS2 PS1 PS0

DMA CONTROLLER (DMAC) The DMAC module is used to implement direct memory access (DMA) transfer in FR50 series devices. In a DMA transfer controlled by this module, various types of data can be transferred at high speed without involving the CPU, thus increasing system performance. (1) Hardware Configuration The following are the main components of the DMAC module :

Five independent DMA channels
5-channel independent access control circuit
32-bit address registers (Reload can be specified : Two registers for each channel.)
16-bit transfer count registers (Reload can be specified : One register for each channel.)
4-bit block count registers (One register for each channel)
External transfer request input pins DREQ0, DREQ1, and DREQ2 (only channels 0, 1, and 2)
External transfer request acceptance output pins DACK0, DACK1, and DACK2 (only channels 0, 1, and 2)
DMA termination output pins DEOP0, DEOP1, and DEOP2 (only channels 0, 1, and 2)
Two-cycle transfer (2) Main Functions The following are the main functions of data transfer performed by the module :
Independent data transfer in multiple channels is enabled (5 channels) . a : Priority (channel 0 > channel 1 > channel 2 > channel 3 > channel 4) b : Priority can be alternated between channel 0 and channel 1. c : DMAC start cause
External-only pin input (edge detection/level detection channels 0 to 2 only)
Internal peripheral request (interrupt request is shared, including external interrupts)
Software request (register write) d : Transfer mode
Demand transfer, burst transfer, step transfer, block transfer
Addressing mode 32-bit full address specification (increase, decrease, fixed) (An address increment/decrement size of −255 to +255 can be specified.)
Data types of byte, halfword, and word lengths
Single-shot/reload selectable

(3) Registers Configuration Channel 0 control/status register A Channel 0 control/status register B Channel 1 control/status register A Channel 1 control/status register B Channel 2 control/status register A Channel 2 control/status register B Channel 3 control/status register A Channel 3 control/status register B Channel 4 control/status register A Channel 4 control/status register B Overall control register Channel 0 transfer source address register Channel 0 transfer destination address register Channel 1 transfer source address register Channel 1 transfer destination address register Channel 2 transfer source address register Channel 2 transfer destination address register Channel 3 transfer source address register Channel 3 transfer destination address register Channel 4 transfer source address register Channel 4 transfer destination address register 0000200H 0000204H 0000208H 000020CH 0000210H 0000214H 0000218H 000021CH 0000220H 0000224H 0000240H 0001000H 0001004H 0001008H 000100CH 0001010H 0001014H 0001018H 000101CH 0001020H 0001028H DMACA0 DMACB0 DMACA1 DMACB1 DMACA2 DMACB2 DMACA3 DMACB3 DMACA4 DMACB4 DMACR DMASA0 DMADA0 DMASA1 DMADA1 DMASA2 DMADA2 DMASA3 DMADA3 DMASA4 DMADA4

(4) Block Diagram Read Write Read/Write control To bus controller DMA trnasfer request to bus controller DDNO Access Address Write-back Write-back Selector Selector Selector Counter buffer Counter buffer Address counter Bus control section BLK register DDNO register DMA control DTCR Priority circuit Status transition circuit Counter DMA start cause selection circuit and request acceptance control Write back Buffer Selector Counter Buffer Selector DTC 2-step register DSS [3:0] Peripheral start request/stop External pin start request/stop input input To transfer controller Clear peripheral interrupt Bus control section ERIR, EDIR TYPE, MOD, WS IRQ [4:0] MCLREQ X-bus DADM, DASZ [7:0] DADR SDAM, SASZ [7:0] SADR DSAD 2-step register DDAD 2-step register DMAC 5-channel block diagram

The UART is a serial I/O port for performing asynchronous (stop-start synchronization) communications. The MB91360G series contains three UART channels. (1) Features

Full-duplex, double buffering
Supports asynchronous (stop-start synchronization) communications
Supports multi-processor mode
Fully programmable baud rate The baud rate can be set using an internal timer. (See the U-TIMER section.)
Supports flexible baud rate setting using an external clock
Error detection function (parity, framing, overrun)
Non return to zero (NRZ) transfer signal
Supports DMA transfer activation using an interrupt

(2) Register Configuration Register structure Serial input register (SIDR) Serial output register (SODR) Serial status register (SSR) Serial mode register (SMR) Serial control register (SCR) UART level select register (ULS) Address Bits Initial value SMR 0000 0063H 0000 006FH 0000 007BH 00 - - 0 - 00B ← Access Address Bits Initial value SCR 0000 0062H 0000 006EH 0000 007AH 00000100B ← Access SIDR (R)/SODR (W) SMR SCR R/W R/W Access SSR ULS 8 7 8 bits 8 bits ORE PE FRE RDRF TDRE RIE TIE MD0 MD1 CS0 SCKE P PEN SBL CL A/D REC RXE TXE NSDO NSDI UTDBL UDBL R/W W MD2 R/W MD1 Reserved Reserved CS0 Reserved Reserved Reserved R/W R/W R/W R/W W R/W R/W P R/W PEN SBL CL A/D REC RXE TXE

(3) Block Diagram SI MD1 MD0 CS0 SCKE SOE PEN P SBL CL A/D REC RXE TXE PE ORE FRE RDRF TDRE RIE TIE R - BUS SIDR SODR Control signals Control signals From U-TIMER (Reception data) Start bit detecter Received bit counter Received parity bit counter Clock selection circuit Reception status detecton circuit Reception error occurrence signal for DMA (to DMAC) SMR register SCR register SSR register Receiving clock Reception control circuit Reception Shifter Transmission Shifter SO (Transmission data) Reception completed Start of transmission Reception interrupt (to CPU) SCK (Clock) Transmission interrupt (to CPU) Transmitting clock Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter

U-TIMER (16-bit Timer for UART Baud Rate Generation) The U-timer (U-TIMER) is a 16-bit timer used to generate the baud rate for the UART. The operating frequency of the chip and the U-TIMER reload value can be combined to set a user-defined baud rate. The MB91360G series contains three U-TIMER channels. The intervaltimers can count for a maximum of 216 × φ. (1) Block Diagram UTIMR (reload register) UTIM (U-timer) Clock Load Underflow To UART control f.f. φ (Peripheral clock)

(2) Register Configuration Register structure UTIMR Reload Register UTIMC U Timer Control Register UTIM Address Bits Initial value Access 0-ch 1-ch 2-ch 00000068H 00000074H 00000080H R UTIMR Address Bits Initial value Access 0-ch 1-ch 2-ch 00000068H 00000074H 00000080H W UTIMC Address Initial value Access 0-ch 1-ch 2-ch 0000006BH 00000077H 00000083H 0---0001 R/W UTIMR UTIM W R/W R Access R : Read, W : Write UTIMC DRCL 8 7 b14 b15 b14 b15 UCC1 UNDR Reserved UTST UTCR

The PWM (Pulse Width Modulation) timer can output high-precision pulse waves at an arbitrary cycle and pulse width (duty ratio) . The MB91360G series contains eight PWM timer channels. Each of the channels consists of a 16-bit down- counter, cycle setting register, duty setting register, and pin controller. The control status register for each channel is used to indicate the operation status of the PWM timer. General control registers 1 and 2 are common registers shared by four channels, serving for input and software triggering. (1) Features

The count clock for the 16-bit down-counter can be selected from among the following four types : Internal clocks : φ, φ/4, φ/16, φ/64 (φ : Machine clock for peripherals)
The counter can be initialized to “FFFFH” by a reset or underflow. The 16-bit down-counter causes an underflow when it changes from “0000H” to “FFFFH”.
Each channel has PWM outputs. Eight channels : Eight output pins
Registers Cycle setting register : Data reload register with buffer Data transfer from the buffer is performed either when an activation trigger is detected or when the down-counter causes an underflow (cycle match) . The output is inverted at a cycle match. Duty setting register : Compare register with buffer. The value set in this register is compared to the counter value. The output is inverted when the values match (duty match) .
Pin control A duty match causes a reset to “1” (given priority) . An underflow causes a reset to “0”. The output value fix mode enables output of all “L” or all “H”. The polarity can also be specified.
Interrupt requests can be generated by selecting the following interrupt sources : Activation of the PWM timer (software trigger or trigger input) Occurrence of an underflow (cycle match) Occurrence of a duty match Occurrence of an underflow (cycle match) or duty match
You can set simultaneous activation of two or more channels using software or another interval timer. You can also set restarting the PWM timer during operation.

(2) Register Configuration for Channels 0 to 3 GCN10 Bits GCN20 PDBL0 PTMR PCSR PDUT PCNH PCNL PTMR PCSR PDUT PCNH PCNL PTMR PCSR PDUT PCNH R/W R/W R W W R/W R W W R/W R W W R/W PWM timer ch 0 PWM timer ch 1 PWM timer ch 2 PWM timer ch 3 Address Access Register name 0000011AH 00000126H 0000012EH 00000136H PCNL PTMR PCSR PDUT PCNH PCNL R W W R/W General control register 10 Disable/General control register 20 ch0 timer register ch0 cycle setting register ch0 duty setting register ch0 control status registers ch1 timer register ch1 cycle setting register ch1 duty setting register ch1 control status registers ch2 timer register ch2 cycle setting register ch2 duty setting register ch2 control status registers ch3 timer register ch3 cycle setting register ch3 duty setting register ch3 control status registers 0000013EH 00000118H 00000124H 0000012CH 00000134H 0000013CH 00000122H 0000012AH 00000132H 0000013AH 00000120H 00000128H 00000130H 00000138H

(3) PWM Timer Registers for Channels 4 to 7 GCN11 Bits GCN21 PDBL1 PTMR PCSR PDUT PCNH PCNL PTMR PCSR PDUT PCNH PCNL PTMR PCSR PDUT PCNH R/W R/W R W W R/W R W W R/W R W W R/W PWM timer ch 4 PWM timer ch 5 PWM timer ch 6 PWM timer ch 7 Address Access Register name 0000011EH 00000146H 0000014EH 00000156H PCNL PTMR PCSR PDUT PCNH PCNL R W W R/W General control register 11 Disable/General control register 21 ch4 timer register ch4 cycle setting register ch4 duty setting register ch4 control status registers ch5 timer register ch5 cycle setting register ch5 duty setting register ch5 control status registers ch6 timer register ch6 cycle setting register ch6 duty setting register ch6 control status registers ch7 timer register ch7 cycle setting register ch7 duty setting register ch7 control status registers 0000015EH 0000011CH 00000144H 0000014CH 00000154H 0000015CH 00000142H 0000014AH 00000152H 0000015AH 00000140H 00000148H 00000150H 00000158H

(4) Configuration Diagram of the Entire PWM Timer (5) Configuration Diagram of PWM Timer 1 ch OCPA0 (PWM0) ch0 16-bit reload timer General control register 10 (source selection) Output pins ch1 General control register 20 Disable register 0 TRG input PWM timer ch0 TRG input PWM timer ch1 TRG input PWM timer ch2 TRG input PWM timer ch3 OCPA1 (PWM1) OCPA2 (PWM2) OCPA3 (PWM3) OCPA4 (PWM4) ch2 16-bit reload timer General control register 11 (source selection) ch3 General control register 21 Disable register 1 TRG input PWM timer ch4 TRG input PWM timer ch5 TRG input PWM timer ch6 TRG input PWM timer ch7 OCPA5 (PWM5) OCPA6 (PWM6) OCPA7 (PWM7) φ / 1 φ / 4 φ / 16 φ / 64 Clock TRG input (Internal trigger input) PWM output PCSR PPG mask Enable Software trigger Inverted bit Load PDUT cmp Interrupt selection Edge detection Start Underflow Prescalar 16-bit down-counter Cycle setting register Duty setting register Peripheral clock (φ) S R Q IRQ (Interrupt request signal)

Each 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, a prescaler for generating the internal count clock, and a control register. The 16-bit reload timer can also activate DMA transfer using interrupts. The MB91360G series contains six 16-bit reload timer channels. (1) 16 bit Reloard Timer Register Configuration Control status register (TMCSR) 16-bit timer register (TMR) 16-bit reload register (TMRLR) CSL1 CSL0 RELD INTE UF CNTE TRG

(2) Block diagram RELD INTE UF CNTE TRG OUT CTL. CSL1 CSL0 φ φ φ GATE UF IRQ 16-bit reload register Reload 16-bit down-counter Clock selector R-BUS Clear prescalar PWM (Reload timer 0-ch to 3-ch)* A/D (Reaload timer 4-ch)* * Internally connected Internal clock

BIT SEARCH MODULE The bit search module searches for a “0”, “1”, or change-point in the data written to the input register and returns the position of the detected bit. This section describes the data register for detecting zeros (BSD0) , data register for detecting ones (BSD1) , data register for detecting change-points (BSDC) , and detection result register (BSRR) . a : Data register for detecting zeros (BSD0) b : Date register for detecting ones (BSD1) c : Data register for detecting change points (BSDC) d : Detection Result Register (BSRR) Address Initial value Access 0000 03F0H Indeterminate W Address Initial value Access 0000 03F4H Indeterminate R/W Address Initial value Access 0000 03F8H Indeterminate W Address Initial value Access 0000 03FCH Indeterminate R Register structure Register structure Register structure Register structure

••• Block Diagram of the Bit Search Module D-BUS Input latch Address decoder Detection mode One-detect data conversion Bit search circuit Search result

10-BIT A/D CONVERTER (Successive Approximation Conversion Type) This section provides an overview of the A/D converter, describes the register structure and functions, and describes the operation of the A/D converter. A/D Converter converts analog input voltage into digital values, and provides the following features.

Conversion time : minimum 178 cycles (32 MHz : 5.6 µs, 24 MHz : 7.4 µs, 16 MHz : 11.2 µs) per channel
RC type successive approximation conversion with sample & hold circuit
10-bit resolution
Program selection analog input from 16 channels Single conversion mode : conversion of one selected channel Scan conversion mode : continuous conversion of multiple channels, programmable for up to 16 channels Single conversion mode : Convert the specified channel once only.
Continuous mode : Repeatedly convert the specified channels.
Stop mode : Convert one channel then temporarily halt until the next activation. (Enables synchronization of the conversion start timing.)
A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to memory.
Startup may be by software, external trigger (falling edge) or timer (rising edge)

Channel setting register (ADCH) Mode register (ADMD) Control status register (ADCS) Data register (ADCD) Disable register (ADBL) bit Address : 00009DH bit Address : 00009CH bit Address : 00009FH bit Address : 0000A1H bit Address : 0000A0H bit Address : 0000A3H ADCS ADCH ADMD ADBL ADCD 8 7 8 bit 8 bit ANS2 ANS3 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 MOD1 MOD0 STS1 STS0 INT BUSY INTE PAUS STRT Reserved DBL

••• Block Diagram MPX D/A Converter Sequential comparison register Sample-and-hold circuit Comparator Input circuit ATGX Decoder AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB ANC AND ANE ANF ADCD Data bus A/D data register A/D channel setting register A/D mode register A/D control status register Prescaler ADCH ADMD ADCS Operating clock AVCC AVRH/AVRL AVSS Trigger activation Machine clock (φ) Timer activation Output of 16-bit reload timer 4 (internal connection)

INTERRUPT CONTROLLER An interrupt controller controls interrupt acceptance and arbitration processing. Hardware configuration This module consists of the following :

ICR register
Interrupt priority evaluation circuit
Interrupt level and interrupt number (vector) generator
Hold request cancel request generator Major functions This module has the following major functions :
Detecting an NMI request or interrupt request
Priority evaluation (using the level or number)
Transferring the level of the interrupt cause in the evaluation result (to the CPU)
Transferring the number of the interrupt cause in the evaluation result (to the CPU)
Instructing recovery from stop mode due to an NMI or interrupt level other than 11111 (to the CPU)
Generating a hold request cancel request for the bus master

(1) Register Configuration (Continued) Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : bit 7 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 00000440H 00000441H 00000442H 00000443H 00000444H 00000445H 00000446H 00000447H 00000448H 00000449H 0000044AH 0000044BH 0000044CH 0000044DH 0000044EH 0000044FH 00000450H 00000451H 00000452H 00000453H 00000454H 00000455H 00000456H 00000457H 00000458H 00000459H 0000045AH 0000045BH 0000045CH 0000045DH 0000045EH 0000045FH R R/W R/W R/W R/W

(Continued) Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : bit 7 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 R R/W R/W R/W R/W MHALTI LVL4 LVL3 LVL2 LVL1 LVL0 R R/W R/W R/W R/W R/W ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 HRCL 00000460H 00000461H 00000462H 00000463H 00000464H 00000465H 00000466H 00000467H 00000468H 00000469H 0000046AH 0000046BH 0000046CH 0000046DH 0000046EH 0000046FH 00000045H

(2) Block Diagram R100 R147 (DLYIRQ) LEVEL4 to 0 MHALT1 VCT5 to 0 R-BUS UNMI WAKEUP (1 if LEVEL = 11111) Priority evaluation LEVEL evaluation NMI processing ICR00 VECTOR evaluation LEVEL and VECTOR generation HLDREQ withdrawal request ICR47 NMIRQ (NMI request)

EXTERNAL INTERRUPT/NMI CONTROL BLOCK The external interrupt/NMI controller controls external interrupt requests input from the NMI and INT0 to INT7 pins. Detection of “H” levels, “L” levels, rising edges, or falling edges can be selected (except for the NMI) . The external interrupt/NMI controller can also be used for DMA requests. This section lists the registers of the controller and provides its block diagram. (1) Register configuration of the External Interrupt NMI Controller (2) Block diagram External interruption permission register (ENIR) External interruption factors register (EIRR) Request level setting register (ELVR) Bit Bit Bit Bit EN6 EN7 EN5 EN4 EN3 EN2 EN1 EN0 ER6 ER7 ER5 ER4 ER3 ER2 ER1 ER0 LA7 LB7 LB6 LA6 LB5 LA5 LB4 LA4 LA3 LB3 LB2 LA2 LB1 LA1 LB0 LA0 INT0 to 7 NMIX R bus Interrupt request Enable interrupt request register Gate Request F/F Edge detect circuit External interrupt request register External level register

DELAYED INTERRUPT Delayed Interrupt Control Register (DICR) The delayed interrupt control register (DICR) is a delayed interrupt generator register and is used to generate the task switching interrupt. Structure of the DICR Address Bits Initial value 00000044H - - - - - - - 0 ← Access R/W DLYI

CLOCK GENERATION The MB91V360 generates internal operating clocks as follows :

Base clock generation : Device scales clock source input by 2 (X clock) or oscillates base clock with PLL to generate basic clock (PLL clock)
Generation of each internal clock : Device scales base clock to generate clocks supplied to each block Generation and control of each clock are explained below. Some devices allow the operation of the RTC module based on a separate 32 kHz subclock. See the section about subclock operation for more details. (1) Register Configuration (Continued) RSRR : Reset Source Register, Watchdog Timer Control Register * : varies with reset factor x : not initialized ** : After execution of the program in the internal boot ROM the reset source is visible STCR : Standby Control Register * : Valid only when this initialization is performed simultaneously with initialization by INITX : others same as INIT. bit address : 00000480H access Initial Value (INITX) Initial Value (INIT) Initial Value (RST) After Boot ROM ** bit address : 00000481H access Initial Value (INITX) Initial Value (HSTX) * Initial Value (INIT) Initial Value (RST) R X R X R X R X R/W R/W HSTB R X INIT WDOG ERST SRST WT1 WT0 R/W R/W X R/W R/W X X R/W X X R/W X R/W X SLEEP R/W STOP HIZ SRST OS1 OS0 OSCD2 OSCD1

(Continued) TBCR : Time-based counter control register CTBR : Time-based counter clear register CLKR : Clock source control register WPR Watchdog reset generation postponement register DIVR0 : Base clock division setting register 0 DIVR1 : Base clock division setting register 1 bit address : 00000482H Initial Value (INIT) Initial Value (RST) bit address : 00000483H Initial Value (INIT) Initial Value (RST) bit address : 00000484H Initial Value (INIT) Initial Value (RST) bit address : 00000485H Initial Value (INIT) Initial Value (RST) bit address : 00000486H Initial Value (INIT) Initial Value (RST) bit address : 00000487H Initial Value (INIT) Initial Value (RST) R/W X X R/W X X R/W X X R/W X X R/W X R/W X R/W TBIE R/W TBIF TBC2 TBC1 TBC0 SYNCR SYNCS X X W X X W X X W X X W X X W X X W X X W X X W R/W X R/W X R/W X R/W X R/W X R/W X R/W X PLL1S2 R/W X PLL2S0 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0 R/W X X R/W X X R/W X X R/W X X R/W X X R/W X X R/W X X R/W X X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X

(Continued) CMCR : Clock Control for CAN Modules Subclock RTC32 (CLKR2) This register is used to control the RTC32 mode bit for use in subclock system. address initial 0164H 11111111 address initial 0165H 00000000 address 000046H access initial value bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 PRE6 PRE7 PRE5 PRE4 PRE3 PRE2 PRE1 PRE0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PRES R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 RTC32

(2) Block Diagram R B U S SELCLK X0A X1A Oscillator circuit

4 MHz

[Clock generation block] Stop control CPU clock CLKB Ext. bus clock CLKT Resource clock CLKP MONCLK Clock for RTC Clock for CAN CANCLK Internal reset (RST) Sleep state Stop state Internal reset (INIT) CPU clock division Resource clock division Ext. bus clock division CLKR register PLL1 Clock mod [Stop/sleep control block] Reset occurrence F/F Reset occurrence F/F STCR register State transition control circuit RSRR register [Reset source circuit] WPR register CTBR register TBCR register Watchdog F/F Timer-base counter Overflow detect. F/F [Watchdog control block] Time-base timer interrupt request Interrupt enable

BUS INTERFACE The external bus interface controls the interfaces with the external memory and external I/Os.

Up to 32-bit (4 GB) address output.
Up to eight independent banks provided by chip-select function The banks can be set in 64-KB (minimum) at any position in the logic address space. Can be set to no area
32/16/8 bit bus width setup can be performed for each chip-select area.
Programmable automatic memory wait (up to 7 cycles) insertion
Unused address/data pins can be used as I/O ports. (But see notes below) Note : Chip Select Area CS7 is used for the internal CAN modules. The necessary register settings are done by an internal boot routine. Take care not to overwrite register bits related to this CS area. If the CAN macros which are connected internally to the external bus (also called User Logic Bus) are used, a certain number of data, address and control ports of the external bus interface cannot be configured as general purpose IO ports. (1) Register Configuration (Continued) Area select Registers (ASR0 to ASR7) After execution of the code in the initial boot ROM ASR0 is set to “0x20”, and ASR7 to “0x10”. ASR0 Initial value Access INIT RST 00000640H 0000H 0000H W ASR1 Initial value Access INIT RST 00000644H 0000H XXXXH W ASR2 Initial value Access INIT RST 00000648H 0000H XXXXH W ASR3 Initial value Access INIT RST 0000064CH 0000H XXXXH W ASR4 Initial value Access INIT RST 0000650H 0000H XXXXH W ASR5 Initial value Access INIT RST 00000654H 0000H XXXXH W ASR6 Initial value Access INIT RST 00000658H 0000H XXXXH W ASR7 Initial value Access INIT RST 0000065CH 0000H XXXXH W A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . .

(Continued) Area Mask Register (AMR0 to AMR7) Area Mode Registers (AMD0 to AMD7) CHE (CacHe Enable register) CSE (Chip Select Enable register) AMR0 Initial value Access INIT RST 00000642H FFFFH FFFFH W AMR1 Initial value Access INIT RST 00000646H 0000H XXXXH W AMR2 Initial value Access INIT RST 0000064AH 0000H XXXXH W AMR3 Initial value Access INIT RST 0000064EH 0000H XXXXH W AMR4 Initial value Access INIT RST 0000652H 0000H XXXXH W AMR5 Initial value Access INIT RST 00000656H 0000H XXXXH W AMR6 Initial value Access INIT RST 0000065AH 0000H XXXXH W AMR7 Initial value Access INIT RST 0000065EH 0000H XXXXH W 00000660H 00000111B R / W 00000670H 11111111B R / W 00000668H 00000001B R / W A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . A30 A31 A29 PO4 PO3 A18 A17 A16 . . . . . . . . . RDYE BW1 BW0 WTC2 WTC1 WTC0 CHE6 CHE7 CHE5 CHE4 CHE3 CHE2 CHE1 CHE0 CSE6 CSE7 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0

(2) Block Diagram MUX ADDRESS BUS DATA BUS CS0X to CS7X RDX WR0X, WR1X WR2X, WR3X BRQ BGRNTX RDY CLK write bus read buffer switch A-OUT switch +1 or +2 address buffer ASR ASZ comparator All block control DATA BLOCK EXTERNAL DATA BUS EXTERNAL ADDRESS BUS ADDRESS BLOCK resisters control External pin control section

CAN CONTROLLER This section provides an overview of the CAN Interface, describes the register structure and functions, and describes the operation of the CAN Interface. The CAN controller is a module built into a MB91360G series. The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. The CAN controller has the following features :

Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats
Supports transmitting of data frames by receiving remote frames
16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration
Supports full-bit comparison, full-bit mask and partial bit mask filtering. - Two acceptance mask registers in either standard frame format or extended frame formats
Bit rate programmable from 10 Kbits/s to 1 Mbits/s (when input clock is at 16 MHz) The following sections only describe CAN 0. For the addresses of the registers of the other CAN channels see the IO-Map. The address shown assume that the CS7 area is defined as described in the chapter about the internal Boot ROM.

(1) List of Control Registers List of Control Registers (1) Address Register Abbreviation Access Initial Value CAN0 100000H Message buffer valid register BVALR0 R/W 00000000 00000000 100001H 100002H Transmit request register TREQR0 R/W 00000000 00000000 100003H 100004H Transmit cancel register TCANR0 W 00000000 00000000 100005H 100006H Transmit complete register TCR0 R/W 00000000 00000000 100007H 100008H Receive complete register RCR0 R/W 00000000 00000000 100009H 10000AH Remote request receiving register RRTRR0 R/W 00000000 00000000 10000BH 10000CH Receive overrun register ROVRR0 R/W 00000000 00000000 10000DH 10000EH Receive interrupt enable register RIER0 R/W 00000000 00000000 10000FH 100010H Control status register CSR0 R/W, R 100011H 100012H Last event indicator register LEIR0 R/W 100013H 100014H Receive/transmit error counter RTEC0 R 00000000 00000000 100015H 100016H Bit timing register BTR0 R/W -1111111 11111111 100017H 100018H IDE register IDER0 R/W XXXXXXXX XXXXXXXX 100019H

List of Control Registers (2) Address Register Abbreviation Access Initial Value CAN0 10001AH Transmit RTR register TRTRR0 R/W 00000000 00000000 10001BH 10001CH Remote frame receive waiting register RFWTR0 R/W XXXXXXXX XXXXXXXX 10001DH 10001EH Transmit interrupt enable register TIER0 R/W 00000000 00000000 10001FH 100020H Acceptance mask select register AMSR0 R/W XXXXXXXX XXXXXXXX 100021H 100022H XXXXXXXX XXXXXXXX 100023H 100024H Acceptance mask register 0 AMR00 R/W XXXXXXXX XXXXXXXX 100025H 100026H XXXXX - - - XXXXXXXX 100027H 100028H Acceptance mask register 1 AMR10 R/W XXXXXXXX XXXXXXXX 100029H 10002AH XXXXX - - - XXXXXXXX 10002BH

(2) Message Buffers List of Message Buffers (ID Registers) (1) Address Register Abbreviation Access Initial Value CAN0 10002CH to 10004BH General-purpose RAM R/W XXXXXXXX to XXXXXXXX 10004CH ID register 0 IDR00 R/W XXXXXXXX XXXXXXXX 10004DH 10004EH XXXXX - - - XXXXXXXX 10004FH 100050H ID register 1 IDR10 R/W XXXXXXXX XXXXXXXX 100051H 100052H XXXXX - - - XXXXXXXX 100053H 100054H ID register 2 IDR20 R/W XXXXXXXX XXXXXXXX 100055H 100056H XXXXX - - - XXXXXXXX 100057H 100058H ID register 3 IDR30 R/W XXXXXXXX XXXXXXXX 100059H 10005AH XXXXX - - - XXXXXXXX 10005BH 10005CH ID register 4 IDR40 R/W XXXXXXXX XXXXXXXX 10005DH 10005EH XXXXX - - - XXXXXXXX 10005FH 100060H ID register 5 IDR50 R/W XXXXXXXX XXXXXXXX 100061H 100062H XXXXX - - - XXXXXXXX 100063H 100064H ID register 6 IDR60 R/W XXXXXXXX XXXXXXXX 100065H 100066H XXXXX - - - XXXXXXXX 100067H

List of Message Buffers (ID Registers) (2) Address Register Abbreviation Access Initial Value CAN0 100068H ID register 7 IDR70 R/W XXXXXXXX XXXXXXXX 100069H 10006AH XXXXX - - - XXXXXXXX 10006BH 10006CH ID register 8 IDR80 R/W XXXXXXXX XXXXXXXX 10006DH 10006EH XXXXX - - - XXXXXXXX 10006FH 100070H ID register 9 IDR90 R/W XXXXXXXX XXXXXXXX 100071H 100072H XXXXX - - - XXXXXXXX 100073H 100074H ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX 100075H 100076H XXXXX - - - XXXXXXXX 100077H 100078H ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX 100079H 10007AH XXXXX - - - XXXXXXXX 10007BH 10007CH ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX 10007DH 10007EH XXXXX - - - XXXXXXXX 10007FH 100080H ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX 100081H 100082H XXXXX - - - XXXXXXXX 100083H 100084H ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX 100085H 100086H XXXXX - - - XXXXXXXX 100087H

List of Message Buffers (ID Registers) (3) List of Message Buffers (DLC Registers and Data Registers) (1) Address Register Abbreviation Access Initial Value CAN0 100088H ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX 100089H 10008AH XXXXX - - - XXXXXXXX 10008BH Address Register Abbreviation Access Initial Value CAN0 10008CH DLC register 0 DLCR00 R/W - - - - XXXX 10008DH 10008EH DLC register 1 DLCR10 R/W - - - - XXXX 10008FH 100090H DLC register 2 DLCR20 R/W - - - - XXXX 100091H 100092H DLC register 3 DLCR30 R/W - - - - XXXX 100093H 100094H DLC register 4 DLCR40 R/W - - - - XXXX 100095H 100096H DLC register 5 DLCR50 R/W - - - - XXXX 100097H 100098H DLC register 6 DLCR60 R/W - - - - XXXX 100099H 10009AH DLC register 7 DLCR70 R/W - - - - XXXX 10009BH 10009CH DLC register 8 DLCR80 R/W - - - - XXXX 10009DH 10009EH DLC register 9 DLCR90 R/W - - - - XXXX 10009FH 1000A0H DLC register 10 DLCR100 R/W - - - - XXXX 1000A1H

List of Message Buffers (DLC Registers and Data Registers) (2) Address Register Abbreviation Access Initial Value CAN0 1000A2H DLC register 11 DLCR110 R/W - - - - XXXX 1000A3H 1000A4H DLC register 12 DLCR120 R/W - - - - XXXX 1000A5H 1000A6H DLC register 13 DLCR130 R/W - - - - XXXX 1000A7H 1000A8H DLC register 14 DLCR140 R/W - - - - XXXX 1000A9H 1000AAH DLC register 15 DLCR150 R/W - - - - XXXX 1000ABH 1000ACH to 1000B3H Data register 0 (8 bytes) DTR00 R/W XXXXXXXX to XXXXXXXX 1000B4H to 1000BBH Data register 1 (8 bytes) DTR10 R/W XXXXXXXX to XXXXXXXX 1000BCH to 1000C3H Data register 2 (8 bytes) DTR20 R/W XXXXXXXX to XXXXXXXX 1000C4H to 1000CBH Data register 3 (8 bytes) DTR30 R/W XXXXXXXX to XXXXXXXX 1000CCH to 1000D3H Data register 4 (8 bytes) DTR40 R/W XXXXXXXX to XXXXXXXX 1000D4H to 1000DBH Data register 5 (8 bytes) DTR50 R/W XXXXXXXX to XXXXXXXX 1000DCH to 1000E3H Data register 6 (8 bytes) DTR60 R/W XXXXXXXX to XXXXXXXX 1000E4H to 1000EBH Data register 7 (8 bytes) DTR70 R/W XXXXXXXX to XXXXXXXX 1000ECH to 1000F3H Data register 8 (8 bytes) DTR80 R/W XXXXXXXX to XXXXXXXX 1000F4H to 1000FBH Data register 9 (8 bytes) DTR90 R/W XXXXXXXX to XXXXXXXX

List of Message Buffers (DLC Registers and Data Registers) (3) Configuration Register (CREG) Address Register Abbreviation Access Initial Value CAN0 1000FCH to 100103H Data register 10 (8 bytes) DTR100 R/W XXXXXXXX to XXXXXXXX 100104H to 10010BH Data register 11 (8 bytes) DTR110 R/W XXXXXXXX to XXXXXXXX 10010CH to 100113H Data register 12 (8 bytes) DTR120 R/W XXXXXXXX to XXXXXXXX 100114H to 10011BH Data register 13 (8 bytes) DTR130 R/W XXXXXXXX to XXXXXXXX 10011CH to 100123H Data register 14 (8 bytes) DTR140 R/W XXXXXXXX to XXXXXXXX 100124H to 10012BH Data register 15 (8 bytes) DTR150 R/W XXXXXXXX to XXXXXXXX Address Register Abbreviation Access Initial Value CAN0 10012CH 10012DH Configuration register CREG0 R/W 00000000 00000110

(3) Block Diagram BTR PSC CREG CANCLK CLKT PR PH RSJ TOE NS1,0 NT NIE HALT RS TS CSR RTEC BVALR TREQR TCANR TRTRR RFWTR TCR TIER RCR RIER RRTRR ROVRR AMSR AMR0 AMR1 LEIR IDR0 to 15, DLCR0 to 15, DTR0 to 15, RAM RBFX, TBFX, RDLC, TDLC, IDSEL RBFX IDSEL TBFX TBFX PH1 RX FRMER ACKER BITER ARBLOST STFER RDLC CRCER TDLC TDLC RDLC IDSEL ARBLOST TX BITER, STFER, CRCER, FRMER, ACKER SYNC, TSEG1, TSEG2 TQ (Operating clock) Clock Configuration Clock for CAN transmit/receive operation Clock for External Bus Access External Bus (User Logic Bus) Prescaler 1 to 64 frequency division Bit timing generation Node status change interrupt generation Node status change interrupt Bus state machine IDLE, INT, SUSPND, transmit, receive, ERR, OVRLD Error control Transmitting/ receiving sequencer TBFx, clear Transmitting buffer x decision Data counter Acceptance filter control Error frame generation Overload frame generation Output driver Transmission shift register Stuffing TBFx, set, clear CRC generation ACK generation Transmission complete interrupt generator Transmission complete interrupt RBFx, set CRC generator/ error check Reception complete interrupt generation Reception completed interrupt RBFx, TBFx, set, clear Receive shift register Destuffing/ stuffing error check RBFx, set Arbitration check Bit error check Acceptance filter Receiving buffer x decision Acknowledgment error check Form error check Input latch RAM address generation

D/A CONVERTER This section provides an overview of the D/A converter, describes the register structure and functions, and describes the operarton of D/A converter.This block is an R-2R format D/A converter, having ten-bit resolution. The D/A converter has two channels.Output control can be performed independently for the two channels using the D/A control register. (1) Block Diagram DA DA DA DA DA DA DA DA DA DA DA DA DA DA R-Bus DA DA DA output ch1 DA output ch0 DA DA DA DA DAE1 Standby control 2R 2R R R R DVR DA19 DA18 DA17 DA11 DA10 DAE0 Standby control 2R 2R R R R DVR DA09 DA08 DA07 DA01 DA00

(2) Registers D/A control register (DACR) D/A converter data register (ch 0) (DADR0) D/A converter data register (ch 1) (DADR1) D/A clock control (DDBL) bit Address : 0000A5H bit Address : 0000A6H bit Address : 0000A7H bit Address : 0000A8H bit Address : 0000A9H bit Address : 0000ABH MODE DAE1 DAE0 DA09 DA08 DA06 DA07 DA05 DA04 DA03 DA02 DA01 DA00 DA19 DA18 DA16 DA17 DA15 DA14 DA13 DA12 DA11 DA10 DBL

100 kHz I2C INTERFACE This section describes the functions and operation of the MB91360G series basic I2C interface. This interface allows operation up to 100 kHz and 8-bit-addressing. The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C bus. (1) I2C Interface Features The MB91360G series microcontroller includes a built-in one-channel I2C interface. The I2C interface has the following features.

Master/slave sending and receiving functions
Arbitration function
Clock synchronization function
Slave address/general call address detection function
Transfer direction detection function
Repeated start condition generation and detection function
Bus error detection function

(2) I2C Interface Registers a : Bus Status Register (IBSR) b : Bus Control Register (IBCR) c : Clock control register (ICCR) d : Address Register (IADR) e : Data Register (IDAR) f : Clock Disable Register (IDBL) Bit no. Address : 000095H Read/write Default value Bit no. Address : 000094H Read/write Default value Bit no. Address : 000097H Read/write Default value Bit no. Address : 000096H Read/write Default value Bit no. Address : 000099H Read/write Default value Bit no. Address : 00009BH Read/write Default value ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) RSC ( R ) ( 0 ) BB AL LRB TRX AAS GCA FBT (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) BEIE (R/W) ( 0 ) BER SCC MSS ACK GCAA INTE INT (  ) (  ) (R/W) ( 0 ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  ) EN CS4 CS3 CS2 CS1 CS0 (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (R/W) ( 0 ) (  ) (  ) DBL

(3) I2C Interface Block Diagram ICCR EN ICCR IBSR BB RSC LRB TRX FBT AL IBCR BER BEIE INTE INT IBCR R-bus SCC MSS ACK GCAA IBSR IDAR IADR AAS GCA CS4 CS3 CS2 CS1 CS0 8 16 128 256 Sync Shift clock generator Start-stop condition deector Arbitration lost detectior Interrupt request End Start-stop condition detector Slave address comparator Clock divider 1 Clock selector 1 Clock divider 2 Clock selector 2 First Byte Error I2C enable Clock signal for division Shift clock edge conversion timing Bus busy Repeat start Send/receive Start Master Slave Global call ACK enable GC-ACK enable Last Bit SCL SDA

400 kHz I2C INTERFACE This section describes the functions and operation of the fast I2C interface. The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C bus. (1) Features

Master/slave transmitting and receiving functions
Arbitration function
Clock synchronization function
General call addressing support
Transfer direction detection function
Repeated start condition generation and detection function
Bus error detection function
7 bit addressing as master and slave
10 bit addressing as master and slave
Possibility to give the interface a seven and a ten bit slave address
Acknowledging upon slave address reception can be disabled (Master-only operation)
Address masking to give interface several slave addresses (in 7 and 10 bit mode)
Up to 400 KBit transfer rate
Possibility to use built-in noise filters for SDA and SCL
Can receive data at 400 KBit if R-Bus-Clock is higher than 6 MHz regardless of prescaler setting
Can generate MCU interrupts on transmission and bus error events
Supports being slowed down by a slave on bit and byte level The I2C interface does not support SCL clock stretching on bit level since it can receive the full 400 KBit datarate if the R-Bus-Clock (CLKP) is higher than 6 MHz regardless of the prescaler setting. However, clock stretching on byte level is performed since SCL is pulled low during an interrupt (INT = “1” in IBCR register) .

(2) Block Diagram IDBL DBL Clock disable Clock Divider 1 Clock Selector Clock Divider 2 (by 12) SCL Duty Cycle Generator ICCR IBSR BB RSC LRB TRX ADT AL IBCR BER BEIE INTE INT IBCR R-bus SCC MSS ACK GCAA IBSR IDAR AAS GCA ISMK ITMK ENTB RAL ITMK ITBA ISBA ISMK ENSB CS4 CS3 CS2 CS1 CS0 2 3 4 5 Sync Interrupt Request Start-Stop Condition Generator ACK Generator Slave Address Comparator Bus Observer Arbitration Loss Detector Shift Clock Generator Address Data Bus Error MCU IRQ SCL SDA SCL enable SDA Bus busy R-Bus Clock (CLKP) FB59 Module Clock Supply Repeat start Send/receive Start Master Slave General call ACK enable GC-ACK enable enable 7 bit mode enable 10 bit mode received ad. length Last Bit NSF Noise Filter ICCR

(3) I2C Interface Registers (Continued) a : Bus Control Register (IBCR2) b : Bus Status Register (IBSR2) c : Ten Bit slave Address register (ITBAH, ITBAL) Ten Bit Address high byte Ten Bit Address low byte d : Ten bit slave address Mask register (ITMKH, ITMKL) Ten Bit Address Mask high byte Ten Bit Address Mask low byte e : Seven Bit slave Address register (ISBA) Bit no. Address : 000184H Read/write Default value Bit no. Address : 000185H Read/write Default value Bit no. Address : 000186H Read/write Default value Bit no. Address : 000187H Read/write Default value Bit no. Address : 000188H Read/write Default value Bit no. Address : 000189H Read/write Default value Bit no. Address : 00018BH Read/write Default value (R/W) ( 0 ) ( W ) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) BEIE (R/W) ( 0 ) BER SCC MSS ACK GCAA INTE INT ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) RSC ( R ) ( 0 ) BB AL LRB TRX AAS GCA FBT (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (  ) ( 0 ) TA9 TA8 (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) TA6 (R/W) ( 0 ) TA7 TA5 TA4 TA3 TA2 TA1 TA0 ( R ) ( 0 ) (  ) ( 1 ) (  ) ( 1 ) (  ) ( 1 ) (  ) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) RAL (R/W) ( 0 ) ENTB TM9 TM8 (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) TM6 (R/W) ( 1 ) TM7 TM5 TM4 TM3 TM2 TM1 TM0 (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) SA6 (  ) ( 0 ) SA5 SA4 SA3 SA2 SA1 SA0

(Continued) f : Seven bit slave address Mask register (ISMK) g : Data Register (IDARH, IDAR2) Data register high byte Data register h : Clock control register (ICCR2) i : Clock Disable Register (IDBL2) Bit no. Address : 00018AH Read/write Default value Bit no. Address : 00018CH Read/write Default value Bit no. Address : 00018DH Read/write Default value Bit no. Address : 00018EH Read/write Default value Bit no. Address : 00018FH Read/write Default value (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) SM6 (R/W) ( 0 ) ENSB SM5 SM4 SM3 SM2 SM1 SM0 (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) (R/W) ( 1 ) NSF (  ) ( 0 ) EN CS4 CS3 CS2 CS1 CS0 (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (  ) ( 0 ) (R/W) ( 0 ) (  ) ( 0 ) DBL

16-BIT I/O TIMER The MB91360G Series contains two 16-bit free-running timer modules, two output compare modules, and two input capture modules and supports four input channels and four output channels. The following sections only describes the 16-bit free-running timer, Output Compare 0/1 and Input Capture 0/1. The remaining modules have the identical functions and the register addresses should be found in the I/O map. (1) Function Overview a : 16-bit free-running timer The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The values output from this timer counter are used as the base timer for input capture and output compare.

Four counter clocks are available. Internal clock : φ/4, φ/16, φ/32, φ/64
An interrupt can be generated upon a counter overflow or a match with compare register 0.
The counter value can be initialized to “0000H” upon a reset, software clear, or match with compare register 0. b : Output compare (2 channels per one module) The output compare module consists of two 16-bit compare registers, compare output latch, and control register. When the 16-bit free-running timer value matches the compare register value, the output level is reversed and an interrupt is issued.
The two compare registers can be used independently. Output pins and interrupt flags corresponding to compare registers
Output pins can be controlled based on pairs of the two compare registers. Output pins can be reversed by using the two compare registers.
Initial values for output pins can be set.
Interrupts can be generated upon a compare match. c : Input capture (2 channels per one module) The input capture module consists of two 16-bit capture registers and control registers corresponding to two independent external input pins. The 16-bit free-running timer value can be stored in the capture register and an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin.
The detection edge of an external input signal can be specified. Rising, falling, or both edges
Two input channels can operate independently.
An interrupt can be issued upon a valid edge of an external input signal.

(2) Registers (3) Block Diagram a : 16-bit free-running timer b : 16-bit output compare c : 16-bit input capture TCDT TCCS Timer data register Timer status register 0000CBH 0000C8H OCCP0/1 OCS0 OCS1 Compare register Control status register 0000B8H 0000BCH 0000BEH IPC0/1 ICS0/1 IOTDBL0 Capture register Disable/Control status register 0000ACH 0000B0H 0000B2H TQ Control logic To each block 16-bit timer Compare register 0 Bus TQ Edge selection Edge selection OUT0 Clear OUT1 IN0 Interrupt 16-bit free-run timer Output compare 0 Compare register 1 Output compare 1 Capture register 0 Input caputure 0 Capture register 1 Input caputure 1 IN1

ALARM COMPARATOR This section provides an overview of the Alarm Comparator (Also called Under/Overvoltage Detection) , de- scribes the register structure and functions, and describes the operation of the Alarm Comparator. (1) Block Diagram (2) Registers Alarm comparator - analog part UMQA02 Alarm comparator - digital part ALARM OUT1 PD OUT2 F-MODULE B-MODULE FR51 B0DX ACSR STOP STOP RST CLKP CLKP CLKP RST RB [15:0] RB [15:0] WRCR PMWR RDCR RSLEEP CDBLE IRQ_AC Interrupt logic CK CK AVDD D Q D Q IRQ_AC CDBLE REG RSLEEP DEC Alarm Comparator Clock Disable Register (ACCDBL) Alarm Comparator Status Disable Register (ACSR) Address Bits Initial value 00000180H - - - - - - - 0B ← Access Address Bits Initial value 00000181H -11xxx00B ← Access R/W CDBLE R/W R/W R R R/W R/W R/W OV_EN UV-EN OUT2 OUT1 IRQ IEN PD

POWER DOWN RESET This section provides an overview of the Power Down Reset, and describes the register structure. The power down reset module performs a system reset when VCC goes below a threshold voltage. The reset signal is be disabled and enabled by setting the power down reset control register PDRCR. For low power applications the digital and the analog part of the power down reset control circuit can be disabled. (1) Block Diagram (2) Register PDCOMP IN OUT input stage EN RST PDRSTX S Q R 9-bit LFSR counter READY CLR WR RB [1] (RD bit) PDRCR access initial value (INIT) initial value (RST) X X X X R/W X R/W X R/W X X CDSBLE PD EN

SERIAL I/O INTERFACE (SIO) This section provides an overview of the Serial I/O Interface (SIO) , and describes the register structure. (1) Block Diagram This block is a serial I/O interface that allows data transfer using clock synchronization. The interface consists of a single eight-bit channel. Data can be transferred from the LSB or MSB. MB91360G series contains two Serial I/O units SIO0 and SIO1. This section only describes SIO0. Please see the IO-Map for the register addresses of SIO1. The serial I/O interface operates in two modes :

Internal shift clock mode : Data is transferred in synchronization with the internal clock.
External shift clock mode : Data is transferred in synchronization with the clock supplied via the external pin (SCK) . By manipulating the general-purpose port sharing the external pin (SCK) , data can also be transferred by a CPU instruc tion in this mode. Interrupt request SIN3 (MSB first) D7 to D0 D7 to D0 (LSB first) Read Write Transfer direction selection SOT3 SCK3 Internal clock SMD2 SMD1 SMD0 SIR SIE BUSY STOP STRT MODE BDS SCOE Internal data bus SDR (Serial data register) Control circuit Shift clock counter Internal data bus

(2) Registers Serial mode control status register (SMCS) SIO edge selection/clock disable register (SES) Serial data register (SDR) Address : 000084H Address : 000085H Address : 000086H Address : 000087H SMD1 SMD2 SMD0 SIE SIR BUSY STOP STRT MODE BDS SCOE DBL NEG

SOUND GENERATOR This section provides an overview of the Sound Generator, and describes the register structure. The Sound Generator consists of the Sound Control register, Frequency Data register, Amplitude Data register, Decrement Grade register, Tone Count register, Sound Disable register, PWM pulse generator, Frequency counter, Decrement counter and Tone Pulse counter. (1) Registers Sound Control register (SGCR) Frequency Data register (SGFR) Amplitude Data register (SGAR) Decrement Grade register (SGDR) Tone Count register (SGTR) Sound Disable register (SGDBL) Bit no. Address : 0000EFH Read/write Default value Bit no. Address : 0000EEH Read/write Default value Bit no. Address : 0000F1H Read/write Default value Bit no. Address : 0000F0H Read/write Default value Bit no. Address : 0000F3H Read/write Default value Bit no. Address : 0000F2H Read/write Default value Bit no. Address : 0000EDH Read/write Default value (R/W) ( 0 ) (R/W) ( 0 ) (  ) (  ) (  ) (  ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) TONE INTE INT ST (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) ( R ) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) TST BUSY DEC (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (R/W) ( 0 ) (  ) (  ) DBL

(2) Block Diagram TONE INTE INT ST 1/d DEC CO EN PWM CI DEC CI CO EN CI CO EN CO EN D EN Q SGA SGO IRQ Clock input Prescaler 8-bit PWM pulse generator Frequency counter Toggle flip-flop Reload Reload Amplitude data register Decrement Grade register Decrement counter Decrement grade register Mix Tone pulse counter Tone count register

STEPPER MOTOR CONTROLLER This section provides an overview of the Stepper Motor Control Module, and describe the register structure. The Stepping Motor Controller consists of two PWM Pulse Generators, four motor drivers, Selector Logic and the Zero Rotor Position Detector. The four motor drivers have high output drive capabilities and they can be directly connected to the four ends of two motor coils. The combination of the PWM Pulse Generators and Selector Logic is designed to control the rotation of the motor. A Synchronization mechanism assures the synchronous operations of the two PWMs. The Zero Rotor Position Detector helps CPU obtain feed back information of the rotor movements. The following sections describe the Stepping Motor Controller 0 only. The other controllers have the same functions. The register addresses are found in the I/O map. Note : The Rotor Zero Position Detection capability is protected by a patent from siemens VDO automatic AG and may only be used with VDO’s prior approval. (1) Block Diagram PWM1P0 PWM2P0 PWM1M0 PWM2M0 PWM2M0 Comparator Zero Rotor Position Detector Power down CE CK EN CK EN PWM PWM BS Debounce logic 8-bit counter 1/9 AVCC reference voltage Machine clock Prescaler PWM1 pulse generator Selector PWM1 compare register PWM1 selector register PWM2 pulse generator Selector Load PWM2 compare register PWM2 select register Zero Detect 0 register

(2) Registers PWM Control 0 register (PWC0) Zero Detect 0 register (ZPD0) PWM1 Compare 0 register (PWC10) PWM2 Compare 0 register (PWC20) PWM1 Select register (PWS10) PWM2 Select register (PWS20) PWM Clock Disable register (SMDBL0) Bit no. Address : 0000D1H Read/write Default value Bit no. Address : 0000D0H Read/write Default value Bit no. Address : 0000D9H Read/write Default value Bit no. Address : 0000D8H Read/write Default value Bit no. Address : 0000DBH Read/write Default value Bit no. Address : 0000DAH Read/write Default value Bit no. Address : 0000E8H Read/write Default value (  ) (  ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (  ) (  ) (  ) (  ) (R/W) ( 0 ) (  ) (  ) CE TST (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 1 ) (R/W) ( 0 ) (R/W) ( 0 ) TS PD RS (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (  ) (  ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) BS (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (R/W) ( 0 ) (  ) (  ) DBL

REAL TIME CLOCK This section provides an overview of the Real Time Clock (also called WatchTimer) , describes the register structure and functions.The Real Time Clock (Watch Timer) consists of the Timer Control register, Sub-second register, Second/Minute/Hour registers, 1/2 clock divider, 21bit prescaler and Second/Minute/Hour counters. The Real Time Clock operates as the real-world timer and provides the real-world time information. (1) Block Diagram INTE0 INT0 EN CI EN LOAD CO CO WOT IRQ CO CO INTE1 ST UPDT INT1 INTE2 INT2 INT3 INT3 Oscillation clock 1/2 Clock Divider 21 bit prescaler Sub second register Second counter Minute counter Hour counter 6 bits 6 bits 5 bits Second/Minute/Hour register

(2) Registers (Continued) Timer disable register (WTDBL) Timer control register (WTCR) Sub-second register (WTBR) Second register (WTSR) Bit no. Address : 0000F5H Read/write Default value Bit no. Address : 0000F7H Read/write Default value Bit no. Address : 0000F6H Read/write Default value Bit no. Address : 0000FBH Read/write Default value Bit no. Address : 0000FAH Read/write Default value Bit no. Address : 0000F9H Read/write Default value Bit no. Address : 0000FEH Read/write Default value (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (  ) (R/W) ( 0 ) (  ) (  ) DBL (R/W) ( 0 ) (R/W) ( 0 ) (  ) (  ) ( R ) ( 0 ) (R/W) ( 0 ) (  ) (  ) (R/W) ( 0 ) TST1 (R/W) ( 0 ) TST2 TST0 RUN UPDT ST (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) INT3 (R/W) ( 0 ) INTE3 INTE2 INT2 INTE1 INT1 INTE0 INT0 (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) D14 (R/W) ( X ) D15 D13 D12 D11 D10 (  ) (  ) (  ) (  ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  ) D20 D19 D18 D17 D16 (  ) (  ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  )

(Continued) Minute register (WTMR) Hour register (WTHR) Bit no. Address : 0000FDH Read/write Default value Bit no. Address : 0000FCH Read/write Default value (  ) (  ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  ) (  ) (  ) (  ) (  ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (R/W) ( X ) (  ) (  )

SUBCLOCK The Subclock System provides various power saving modes. The key of the concept is to supply the 32 kHz clock signal only to the Real Time Clock RTC) Module, while the rest of the MCU is provided with 4 MHz clock signal in order to achieve lower power supply current in the RTC32K mode. This behavior can be altered by the configuration input, SELCLK pin to switch the RTC module to operate with the 4 MHz clock. The following sections describe the operation with SELCLK connected to “0” and SELCLK connected to “1” respectively. Note : On MB91F361GA and MB91F362GA SELCLK should always be connected to “1”, subclock operation is not implemented on those devices. (1) Operation of Subclock (SELCLK ==== 0) The next table summarizes the operation states of the components related to the Subclock System.To simplify this table SLEEP modes are not listed but the operation is the same as for RUN modes except that the CPU is stopped. The following table summarizes those operation modes and necessary software settings. It is recommended that PLL2EN is set to “1” after the initialization to start the 32 kHz oscillation and this bit should be kept at “1” during the operation. Otherwise the 32 kHz oscillator does not start. Also bits 9 and 10 of the CLKR register (address 0046H) should always be set to “0” during operation. Mode Power dissipation Operation of components 4 M Osc. 32 K Osc. RTC CPU & Peripheral PLL RUN High Run Run Run Run Stop/Run RTC4M32K Medium Low Run Run Run Stop Stop RTC32K Low Stop Run Run Stop Stop STOP Lowest Stop Stop Stop Stop Stop Mode Software Setting STOP PLL1EN PLL2EN OSCD1 OSCD2 RTC32 RUN 0 or 1 Don’t Care Don’t Care Don’t Care RTC4M32K Don’t Care Don’t Care RTC32K Don’t Care STOP Don’t Care Don’t Care Don’t Care

(2) 4 MHz Real Time Clock Configuration (SELCLK ==== 1) When the SELCLK pad is connected logic level 1, the 32 kHz oscillation is disabled regardless of the software setting. In this configuration, the Real Time Clock Module is supplied with the 4 MHz oscillation clock signal. The following table summaries the modes available in this configuration. (3) Use of Real Time Clock Module There is some additional consideration needed to operate the RTC module to achieve the desired functionality. Because the RTC module is directly connected to the 32 kHz oscillation clock, the oscillation stabilization time has to be taken care of by the software.This can be achieved by using another timer (e.g the Time Base Timer) to trigger the software to start the RTC module (Setting of ST bit to “1”) . It is also important to stop the RTC module before entering the STOP mode. Otherwise, the reactivation from STOP mode results in unpredictable operation of the RTC module. After the reactivation, the oscillation stabilization time has to be measured again by the software, then the RTC module can be restarted. Mode Power dissipation Operation of components 4 M Osc. 32 K Osc. RTC CPU & Peripheral PLL RUN High Run Stop Run Run Stop/Run RTC4M Medium Low Run Stop Run Stop Stop STOP Lowest Stop Stop Stop Stop Stop Mode Software Setting STOP PLL1EN PLL2EN OSCD1 OSCD2 RTC32 RUN 0 or 1 Don’t Care Don’t Care Don’t Care Don’t Care RTC4M Don’t Care Don’t Care Don’t Care Don’t Care STOP Don’t Care Don’t Care Don’t Care Don’t Care

32 kHz CLOCK CALIBRATION UNIT The 32 kHz Clock Calibration Module provides possibilities to calibrate the 32 kHz oscillation clock with respect to the 4 MHz oscillation clock. (1) Description This hardware allows the software to measure time generated by the 32 kHz clock with the 4 MHz clock. By utilizing this hardware in conjunction with software processing, the accuracy of the 32 kHz clock can come closer to that of the 4 MHz clock. The measurement result from the 32 kHz Clock Calibration Module can be processed by the software and the setting required for the Real Time Clock Module can be obtained. This module consists of two timers, one operating with the 32 kHz clock and the other operating with the 4 MHz clock. The 32 kHz timer triggers the 4 MHz timer and resulting 4 MHz timer value is stored in a register. The value stored in this register can be used for the subsequent software processing to calculate the desired Real Time Clock module’s setting. (2) Block Diagram UC18CLK gate gate gate gate sync CLKP ≥ 32 STRT READY RUNS STRT RSLEEPB RSLEEPB STRT SLKPG2 = CLKP | (∼STRT & RSLEEPB) ; OSC4 OSC32 CLKP RB RSLEEP RMW INT *_RD *_WR RST async RST STRT STRTS STRT READY RUN UC18TRD UC18TRR CUTR counter (16 bit) CUTR (24 bit) STRT CUTD CLK32G RB CLKPG CLK4G = OSC4 | ∼ STRT | (READY & −RUNS) ; CLK4G CLKPG2 32 kHz TIMER

32 ≥ 4 RUN RUNS sync 4 ≥ CLKP READY RUNSS1 RUNSS reset READY- PULSE CUCR (3 bit) CUTR (24 bit) CUTD (16 bit) CUTD VC18RBI FC18 reset set STRT set /reset set /reset INTEN INT UC18BUS UC18IO INT_I INT_INT *_RDB *_WRB RSTB RBB RSLEEPB RMWB

(3) Timing 32 kHz STRT (CLKP) STRTS (32 kHz) RUN (32 kHz) RUNS (4 MHz) 32 kHz counter (16 bit)

4 MHz counter (24 bit)

READY (32 kHz) READYPULSE (CLKP) INT (CLKP) new CUTR old CUTR CUTD CUTD CUTD-1

(4) Clocks The module operates with 3 different clocks : The 4 MHz clock OSC4, the 32 kHz clock OSC32 and the Rbus clock CLKP. Synchronization circuits adapt the different domains. All 3 clocks are gated. The 32 kHz and the 4 MHz clock are switched off if STRT is 0. CLKPG is gated by RSLEEP and CLKPG2 by RSLEEP and STRT for the 2 bits, which are set/reset by hardware. The clock frequencies have to fulfill the following requirements : 1.) Clock ratio TOSC32 > 2 × TOSC4 + 3 × TCLKP TOSC4 < 1 / 2 × TOSC32 − 3 / 2 × TCLKP TCLKP < 1 / 3 × TOSC32 − 2 / 3 × TOSC4 2.) The input frequencies must not exceed the values given in next table. Maximum operation frequencies Examples of valid clock ratios which fulfill requirements 1 and 2 CLKP OSC32 OSC4 maximum

32 MHz

31.25 ns

13 MHz

76.9 ns OSC32 OSC4 CLKP maximum operation speed 76.9 ns 31.25 ns standard TDIR mode 500 kHz 2000 ns 31.25 us

2 MHz 500 ns

(5) Register Description a : Calibration Unit Control Register (CUCR) Control Register low byte (CUCRL) b : 32 kHz Timer Data Register (CUTD) 32 kHz Timer Data Register high byte (CUTDH) 32 kHz Timer Data Register low byte (CUTDL) c : 4 MHz Timer Data Register (CUTR)

4 MHz Timer Data Register1 high byte (CUTR1H)

4 MHz Timer Data Register1 low byte (CUTR1L)

4 MHz Timer Data Register2 high byte (CUTR2H)

4 MHz Timer Data Register2 low byte (CUTR2L)

Bit no. Address : 000191H Read/write Default value Bit no. Address : 000192H Read/write Default value Bit no. Address : 000193H Read/write Default value Bit no. Address : 000194H Read/write Default value Bit no. Address : 000195H Read/write Default value Bit no. Address : 000196H Read/write Default value Bit no. Address : 000197H Read/write Default value ( R ) ( 0 ) ( R ) ( 0 ) (R/W) ( 0 ) ( R ) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) ( R ) ( 0 ) STRT INT INTEN (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) TDD14 (R/W) ( 1 ) TDD15 TDD13 TDD12 TDD11 TDD10 TDD9 TDD8 (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) (R/W) ( 0 ) TDD6 (R/W) ( 0 ) TDD7 TDD5 TDD4 TDD3 TDD2 TDD1 TDD0 ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) TDR22 ( R ) ( 0 ) TDR23 TDR21 TDR20 TD19 TDR18 TDR17 TDR16 ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) TDR14 ( R ) ( 0 ) TDR15 TDR13 TDR12 TDR11 TDR10 TDR9 TDR8 ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) ( R ) ( 0 ) TDR6 ( R ) ( 0 ) TDR7 TDR5 TDR4 TD3 TDR2 TDR1 TDR0

FLASH MEMORY MB91360G series devices feature 512 K of embedded flash memory unit derived from the MB29LV400C and the FLASH Memory interface circuit. (1) Out Line of Flash Memory The Flash Memory consists of a flash memory unit derived from the MBM29LV400C and a flash memory interface circuit. Flash Memory :

512 Kword × 8 bit/256 Kword × 16 bit/128 Kword × 32 bit (64 Kbyte×3 + 32 Kbyte + 8 Kbyte×2 + 16 Kbyte) sectors
Uses automatic program algorithm (Embedded Algorithm)
Erase pause/restart function
Detects completion of writing/erasing using data polling or toggle bit functions
Detects completion of writing/erasing by RY/BY pin
Compatible with JEDEC standard commands
Performs minimum of 10,000 write/erase operations
Sector erase function (any combination of sectors)
Sector protect function
Temporary sector protect cancellation function
Allows flash memory interface circuit to write to/erase flash memory both under control of external pin by writer and under control of internal bus by CPU. Embedded Algorithm is a registered trademark of Advanced Micro Devices, Inc.

(2) Block diagrams of Flash Memory a : Block diagram of Flash Memory Figure shows the block diagram of the flash memory unit, which has almost the same configuration as the MBM29LV400C. b : Entire block diagram of Flash Memory Figure shows the entire block diagram of the Flash Memory with the flash memory interface circuit. WE RY/BY buffer CE A0 to A17 A-1 OE BYTE RESET RY/BY Erase circuit Write circuit Control circuit Chip enable/ output enable circuit I/O buffer Data latch Y gate Y decoder cell matrix X decoder address latch STB STB DQ0 to DQ15 Low VCC detection circuit Write/erase pulse timer User Logic bus Ext.Bus I/F Flash memorry interface circuit

4 Mbit flash memory

c : Sector configuration i) write, byte read, half word read ii) long word read Flash Memory mode Other modes 8 bit × 2 7FFFFH FFFFFH Sector 13 16 KB 7C000H FC000H Sector 12 8 KB 7A000H FA000H Sector 11 8 KB 78000H F8000H Sector 10 32 KB 70000H F0000H Sector 9 64 KB 60000H E0000H Sector 8 64 KB 50000H D0000H Sector 7 64 KB 40000H C0000H Sector 6 16 KB 3C000H BC000H Sector 5 8 KB 3A000H BA000H Sector4 8 KB 38000H B8000H Sector 3 32 KB 30000H B0000H Sector 2 64 KB 20000H A0000H Sector 1 64 KB 10000H 90000H Sector 0 64 KB 00000H 80000H MSB LSB Flash Memory mode Other modes 8 bit × 2 8 bit × 2 7FFFFH FFFFFH Sector 13 16 KB Sector 6 16 KB 78000H F8000H Sector 12 8 KB Sector 5 8 KB 74000H F4000H Sector 11 8 KB Sector 4 8 KB 70000H F0000H Sector 10 32 KB Sector 3 32 KB 60000H E0000H Sector 9 64 KB Sector 2 64 KB 40000H C0000H Sector 8 64 KB Sector 1 64 KB 20000H A0000H Sector 7 64 KB Sector 0 64 KB 00000H 80000H

(3) Write/Erase Modes The flash memory can be accessed in two different ways; the flash memory mode allowing write/erase directly from the external pins, and the other modes allowing write/erase from the CPU via the internal bus. These modes are selected by the external mode pins. a : Flash Memory mode The CPU stops when the mode pins are set to 111 while the INITX signal is asserted. The flash memory interface circuit is directly connected to the external bus interface, allowing direct control by the external pins. This mode makes the MCU seem like a standard flash memory at the external pins, and write/erase can be performed using a flash memory programmer. In the flash memory mode all the operations supported by the flash memory automatic algorithm can be used. b : Other modes The flash memory is located in the CS1X area of the CPU memory space and like ordinary mask ROM can be read-accessed and program-accessed from the CPU through the flash memory interface circuit. Writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface circuit. Therefore, this mode allows rewriting even when the MCU is soldered on the target board. The sector protect operations can not be performed in these modes. c : Control signals of flash memory Next table lists the flash memory control signals in the flash memory mode. There is almost a one-to-one correspondence between the flash memory control signals and the external pins of the MBM291V400TA. The VID (12 V) pins required by the sector protect operations are MD0, MD1 and MD2 instead of A9, RESET and OE for the MBM29LV400C. In the flash memory mode, the width of the external data bus can be 8 or 16 bit.

••• MB91F362GA Pins used in flash memory mode A19, A20 should be pulled up, INITX must be low during power on for at least 500 ns. Pins not used in flash memory mode MB91F362GA MBM29LV400C Notes Pin number Normal function Flash Memory mode 1 to 8 D24 to D31 D24 to D31 DQ8 to DQ15 A-1 10 to 24 A1 to A15 A1 to A15 A0 to A14 27 to 30 A16 to A18 A16 to A18 A15 to A17 CS4X CS4X WE CS5X CS5X BYTE RDY RDY OE BGRNTX BGRNTX CE BRQ BRQ RY/BY 111 MD0 VDA9 A9 (VID) 112 MD1 VDRS RESET (VID) 113 MD2 VDOE OE (VID) 115 INITX INITX RESET 201 to 208 D16 to D23 D16 to D23 DQ0 to DQ7 183 to 197, 200 D0 to D15 Output when reading from flash Pull up CS6X TMODEX Must be pulled up 30 to 31 A19 to A20 A19 to A20 Pull up or pull down MB91F362GA Notes Pin number Normal function Pin state 75 to 76 DA0, DA1 output leave open ALARM input pull down 81 to 83 TESTX, CPUTESTX, LTESTX input pull up or leave open (internal pull-up) 114 HSTX input pull up or leave open (internal pull-up) 116 MONCLK output leave open 117 SELCLK input pull up 119, 121 X0, X0A input pull down 120, 122 X1, X1A output leave open 124 CPO output leave open 125 VCI input pull down all other signals input Pull up

••• MB91FV360GA (Continued) MB91FV360GA MBM29LV400C Pin number Normal function Flash Memory mode 202 A-1 310 201 357 257 144 309 256 200 356 308 A10 A10 A11 A11 A10 A12 A12 A11 255 A13 A13 A12 143 A14 A14 A13 199 A15 A15 A14 307 A16 A16 A15 A17 A17 A16 142 A18 A18 A17 140 CS4X CS4X WE 196 CS5X CS5X BYTE CS6X TMODX 305 RDY RDY OE 139 BGRNTX BGRNTX CE BRQ BRQ RY/BY 293 MD0 VDA9 A9 (VID) MD1 VDRS RESET (VID) 239 MD2 VDOE OE (VID) INITX INITX RESET D16 D16 DQ0 D17 D17 DQ1 D18 D18 DQ2 148 D19 D19 DQ3 205 D20 D20 DQ4

(Continued)

••• MB91F369GA a. Pin 70 must be pulled high in Flash Memory Mode. b. Pins 74 and 75 must be pulled low in Flash Memory Mode. c. Functionality as described in the Data Sheet of MBM29LV400C. AVRH must be tight to a high level, ALARM to a low level. All other Pins can be left open during Flash Memory Mode. MB91FV360GA MBM29LV400C Pin number Normal function Flash Memory mode D21 D21 DQ5 D22 D22 DQ6 260 D23 D23 DQ7 312 D24 D24 DQ8 204 D25 D25 DQ9 147 D26 D26 DQ10 D27 D27 DQ11 259 D28 D28 DQ12 203 D29 D29 DQ13 146 D30 D30 DQ14 258 D31 D31 DQ15 MB91F369GA MBM29LV400C Pin number Normal function Flash Memory mode Function in Flash Memory mode MD0 HVDA9 High Volt. A9 (C) A9 (VID) MD1 HVDR5 High Volt. RESET (C) RESET (VID) MD2 HVDOE High Volt. OE (C) OE (VID) INTX RSTX Hardware Reset RESET INT0 RY/BYX Ready/Busy RY/BY INT1 CEX Chip Enable CE INT2 TSTX (a) Flash Test INT3 BYTEX switch 8/16 bit mode BYTE INT4 WEX Write Enable WE INT5 OEX Output Enable OE INT6 ATDIN (b) Access signal ATD INT7 EQIN (b) Access signal EQ 121 to 136 D0 to D15 AQ19 downto AQ4 Address input A19 downto A4 139 to 154 D16 to D31 DQ16 to DQ31 Data input/output DQ0 to DQ15 157 to 160 A0 to A3 AQ0 to AQ3 Address input A0 to A3

(4) Flash Control Status Register (FMCS) Flash Memory Macros used in devices : Normal Flash Macro used in : MB91F362GA Fast Flash Macro used in : MB91FV360GA *: It is not allowed to use RDYEG. Address FV360GA, F362GA : 00007000H Access Initial value value after Boot ROM R/W R/W R R X X R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W FACCEN RDYEG* RDY RDYI WE LPM

(5) Read/Write Access In the flash memory mode, read/write access to the flash memory must be under control of the external pins. However, with the CPU access, there are no special timing constraints on read/write access because the flash memory is controlled by the flash memory interface circuit. In this section, “write access” does not directly mean “program flash memory”. It implies “activation of the flash commands”. a : Read/write access in flash memory mode Next table gives the setting of pins for read/write access in the Flash Memory mode. There is no special problem with control of these pins if connected to a flash memory writer. However, in other cases, timing specifications must be met. Setting Conditions of Pins for Read/Write Access in Flash Memory Mode Note : This table uses pin names from F362GA. Check corresponding pin names of other devices. b : Read access with CPU Operations BGRNTX (CE) RDY (OE) CS4X (WE) A0 to A18 D16 to D31 INIT Read L L H Read address DOUT H Write L H L Write address DIN H Output disable L H H x High-Z H Standby H x x x High-Z H Hardware reset x x x x High-Z L Flash Wait Control Register (FMWT) Address 00007004H Access Initial value value after Boot ROM Normal Flash Macro value after Boot ROM Fast Flash Macro R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FAC1 FAC0 EQINH WTC2 WTC1 WTC0

Normal Flash Macro : Recommended settings Without applying clock modulation When applying clock modulation Example for flash memory read access with 1 cycle for the low time of FACC and 3 wait cycles The minimum value for tFP is 15 ns, for tFACC it is 40 ns. CLKB unmodulated core clock frequency [MHz] FAC1 FAC0 EQINH WTC2 WTC1 WTC0 FACC low cycles/wait cycles FMWT 13H 13H 12H 0.5 / 2 02H 0.5 / 1 01H 0.5 / 1 01H CLKB core clock frequency [MHz] Peak Max frequency FAC1 FAC0 EQINH WTC2 WTC1 WTC0 FACC low cycles/wait cycles FMWT 13H 13H 12H 0.5 / 2 02H 0.5 / 1 01H CLKB FA FWAITR FACC FD 3 wait cycles 1 cycle FACC = "L" tFP tFACC core clock F-bus address F-bus wait FACC for flash F-bus data

Fast Flash Macro : Recommended settings Without applying clock modulation When applying clock modulation Example for flash memory read access with 1 cycle for the high time of ATDIN and 3 wait cycles The minimum value for tWATD is 10 ns, the minimum value for tWEQ is 20 ns. The minimum value for tRC is 40 ns. The maximum value for tACC is tWATD + tWEQ + 5 ns. CLKB unmodulated core clock frequency [MHz] FAC1 FAC0 EQINH WTC2 WTC1 WTC0 ATDIN high cycles/wait cycles FMWT 13H 0.5 / 2 02H 0.5 / 2 02H 0.5 / 1 09H 0.5 / 1 01H 0.5 / 1 01H CLKB core clock frequency [MHz] Peak Max frequency FAC1 FAC0 EQINH WTC2 WTC1 WTC0 ATDIN high cycles/wait cycles FMWT 13H 0.5 / 2 02H 0.5 / 2 12H 0.5 / 1 09H 0.5 / 1 01H 3 wait cycles 1 cycle ATDIN ="H" tWATD tWEQ core clock F-bus address F-bus wait ATDIN for flash EQIN for flash F-bus data tACC tRC CLKB FA FWAITR ATDIN EQIN FD

c : Write access with CPU Recommended settings for WTC2 to WTC0 for write access to the flash memory, FACCEN of FMCS should be set to 1 for writing, so FAC1, FAC0, EQINH register settings then have no meaning for the write operation Without applying clock modulation When applying clock modulation CLKB unmodulated core clock frequency [MHz] WTC2 WTC1 WTC0 Wait cycles FMWT setting not allowed for writing X4H X4H X2H X2H X1H CLKB core clock frequency [MHz] Peak Max frequency WTC2 WTC1 WTC0 Wait cycles FMWT setting not allowed for writing X4H X4H X2H X2H

(6) Automatic Write/Erase Irrespective of the Flash Memory mode or other modes, writing to/erasing the flash memory unit is performed by starting the flash memory automatic algorithm. To start the automatic algorithm, various sequences of write accesses are executed in 1 to 6 cycles. They are called Flash commands. a : Flash Commands There are four commands for starting the automatic algorithm of the Flash Memory unit; Read/Reset, Write, Chip Erase, and Sector Erase. There are also Erase Suspend and Erase Resume commands for the sector erase operation. Next tables give the command sequence lists in the flash memory and other modes. b : Command sequence Command Sequence List (CPU access) Addresses in the table are the values in the CPU memory space. All addresses and data are hexadecimal values, where x is any value and ** may be 08 to 0F. * : Two Read/Reset commands reset Flash memory to the read mode. Command Sequence Write Cycle of Bus Write Cycle of First Bus Write Cycle of Second Bus Write Cycle of Third Bus Read/ Write Cycle of Fourth Bus Write Cycle of Fifth Bus Write Cycle of Sixth Bus Ad- dress Data Ad- dress Data Ad- dress Data Ad- dress Data Ad- dress Data Ad- dress Data Read/ Reset* **xxxx xxF0 Read/ Reset* 5554 xxAA aaa8 xx55 5554 xxF0 RA RD Write 5554 xxAA aaa8 xx55 5554 xxA0 PA (even) PD (half word) Chip Erase 5554 xxAA aaa8 xx55 5554 xx80 5554 xxAA aaa8 xx55 5554 xx10 Sector Erase 5554 xxAA aaa8 xx55 5554 xx80 5554 xxAA aaa8 xx55 SA (even) xx30 Sector Erase Suspend Input of address xxxx or data (xxB0H) suspends sector erasing. Sector Erase Resume Input of address **xxxx or data (xx30H) suspends and resumes sector erasing.

Command Sequence List (Flash Memory Mode) Addresses in the table are values for writer addresses. All addresses and data are hexadecimal values, where x is any value and * may be 0 to 7. RA : Read address PA : Write address. Only even addresses can be specified. SA : Sector address (See next table) . Only even addresses can be specified. RD : Read data PD : Write data. Only word data can be specified. Command Sequence Write Cycle of Bus Write Cycle of First Bus Write Cycle of Second Bus Write Cycle of Third Bus Read/ Write Cycle of Fourth Bus Write Cycle of Fifth Bus Write Cycle of Sixth Bus Ad- dress Data Ad- dress Data Ad- dress Data Ad- dress Data Ad- dress Data Ad- dress Data Read/ Reset* *xxxx Read/ Reset* *aaaa AA *5554 *aaaa RA RD Write *aaaa AA *5554 *aaaa PA (even) PD (word) Chip Erase *aaaa AA *5554 *aaaa *aaaa AA *5554 *aaaa Sector Erase *aaaa AA *5554 *aaaa *aaaa AA *5554 SA (even) Sector Erase Suspend Input of address *xxxx or data (B0H) suspends sector erasing. Sector Erase Resume Input of address *xxxx or data (30H) suspends and resumes sector erasing.

Sector Address for half word mode Sector A18 A17 A16 A15 A14 A13 Address range SA13 7C000H to 7FFFFH SA12 7A000H to 7BFFFH SA11 78000H to 79FFF SA10 70000H to 77FFFH SA9 60000H to 6FFFFH SA8 50000H to 5FFFFH SA7 40000H to 4FFFFH SA6 3C000H to 3FFFFH SA5 3A000H to 3BFFFH SA4 38000H to 39FFFH SA3 30000H to 37FFFH SA2 20000H to 2FFFFH SA1 10000H to 1FFFFH SA0 00000H to 0FFFFH

(7) Connection to Flash Memory The Flash Memory mode of the MB91360G series devices is intended mainly for external connection to a flash memory writer. As indicated in Table Flash Control Signals, there is a slight difference between the external pins of the MB91360G series devices and the MBM29LV400C (4 Mbit flash memory) . Connection to an MBM29LV400C writer requires the socket adapter. flash writer MB91F362GA MB91FV360GA 2.2 kΩ 2.2 kΩ 2.2 kΩ 2.2 kΩ 2.2 kΩ 2.2 kΩ Socket adapter RESET OE A10 INITX RDY MD0 MD1 MD2 MB91F369GA INITX INT5 MD0 MD1 MD2

(8) Notes to Use of Flash Memory Notes on the Flash Memory in MB91360G series devices are given below. a : Input of hardware reset (INITX) To input a hardware reset when the automatic algorithm is not started, where reading is in progress, a minimum of 500 ns should be taken at a low-level width. In this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated. Similarly, to input a hardware reset when the automatic algorithm is activated, where writing/erasing is in progress, a minimum of 50 ns should be taken in a low-level width. In this case, 20 µs are required until data can be read after the executing operation has been terminated to initialize the flash memory. A hardware reset during writing undefined data being written. A hardware reset during erasing may make the sector being erased unusable. b : Canceling software reset, watchdog timer reset, and hardware standby When writing/erasing the flash memory with the CPU access and if reset conditions occur while the automatic algorithm is active, the CPU may run away. This occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset conditions should be inhibited during writing/erasing the Flash Memory. c : Program access to Flash Memory When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory access mode of the CPU set to the internal ROM mode, writing/erasing should be started after switching the program area to another area such as RAM. In this case, when sectors containing interrupt vectors are erased, interrupt processing cannot be executed. For the same reason, all interrupt sources should be disabled while the automatic algorithm is operating. d : Hold function When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed and many cause erroneous writing/erasing. When the acceptance of a hold request is enabled, ensure that the WE bit of the control status register (FMCS) is 0. e : Applying VID Applying VID required for the sector protect operation should always be started and terminated when the supply voltage is on.

(9) Timing Diagrams in Flash Mode Each timing diagram for the external pins of the MB91360G series in the Flash Memory mode is shown below. a : Data read by read access b : Write Data polling Read (WE control) A18 to A0 Address stable High-Z High-Z BGRNTX (CE) RDY (OE) CS4X (WE) D31 to D16 Output defined tRC tAC tOE tDF tCE tOH tOEH 120 ns 120 ns 50 ns 30 ns 120 ns (TOGGLE) 0 ms (Read) A18 to A0 D31 to D16 BGRNTX (CE) RDY (OE) CS4X (WE) Third bus cycle Data Polling 7AAAAH PA PA tWC tAS tAH tRC tWHWH1 tWPH tWP tGHEL tDH tDF tOH tOE tCS tDS tCE DOUT D23 PD A0H VDD (= 5.0 V) PA : Write address PD : Write data D23 : Reverse output of write data DOUT : Output of write data Note : The last two bus cycle sequences out of the four are described.

c : Write Data polling Read (CE control) d : Chip erase/sector erase command sequence A18 to A0 D31 to D16 BGRNTX (CE) RDY (OE) CS4X (WE) VDD (= 5.0 V) Third bus cycle Data Polling 7AAAAH PA PA tWC tAS tWH tAH tWHWH1 tCPH tCP tGHEL tDH tWS tDS DOUT D23 PD A0H PA : Write address PD : Write data D23 : Reverse output of write data DOUT : Output of write data Note : The last two bus cycle sequences out of the four are described. A18 to A0 D31 to D16 VDD BGRNTX (CE) RDY (OE) CS4X (WE) 7AAAAH 75554H 7AAAAH 7AAAAH 75554H SA* tAS tAH tWP tDS tCS tVCS tDH tWPH AAH 55H 80H AAH 55H 10H/30H tGHWL Note : SA is the sector address at sector erasing. 7AAAAH (or 6AAAAH) is the address at chip erasing.

e : Data polling f : Toggle bit g : RY/BY timing during writing/erasing tOEH tCH tOE tCE tDF tEOE tOH tWHWH1 or tWHWH2 BGRNTX (CE) D31 to D16 D23 D23 = Valid data D31 - D16 = Invalid D31 - D16 = Valid data RDY (OE) CS4X (WE) High-Z D23 * : DQ7 is valid data (The device terminates automatic operation) . tOEH tOE BGRNTX (CE) RDY (OE) CS4X (WE) Data (D31 to D16) tOES D22 = Toggle D22 = Toggle D22 = Stop toggling D31 to D16 = Valid * : DQ6 stops toggling (The device terminates automatic operation) . BGRNTX (CE) CS4X (WE) RDY (OE) Rising edge of last write pulse tBUSY Writing or erasing

h : INITX and RY/BY timing i : Enable sector protect/verify sector protect tRP tREADY BRQ (RY/BY) BGRNTX (CE) CS4X (OE) tWPP tVLHT tOE tCSP tOESP tVLHT A18 to A13 MD0 (A9(VID)) MD2 (OE(VID)) 12 V 5 V 12 V 5 V CS4X (WE) RDY (OE) D31 to D16 SAx 01H SAy A7, A2, and A1 SAx : First sector address SAy : Next sector address

j : Temporary sector protect cancellation Sector protect cancellation tVLHT Write/erase command sequence 5 V 12 V 5 V CS4X (WE) BRQ (RY/BY) BGRNTX (CE) MD1 (RESET (VID))

(10) AC Characteristics in Flash Memory Mode The AC specifications for the external pins of the MB91360G series in the Flash Memory mode are shown below. They apply to the case where the user performs read/write access in the Flash Memory mode. They are not needed for access in the normal mode and for use of a flash memory writer. The values are subject to change without prior notice. a : Read access AC Characteristics for Read Access (Under recommended conditions) Note : Sampled, not 100 % tested. Parameter Symbol Test Condi- tions Value Unit Min Typ Max Read cycle time tRC 120 ns Address access time tACC CE = VIL OE = VIL 120 ns CE to data output tCE OE = VIL 120 ns OE to data output tOE ns CE to output floating tDF ns OE to output floating tDF ns Previous cycle data output hold time tOH ns INITX pin to return to read mode tReady µs

b : Write [write/erase command] access (WE control) AC Characteristics for Write Access (WE Control) (Under recommended conditions) *1 : The internal preprogramming time before erasing is not included. *2 : Applies only to sector protection Note : Sampled, not 100 % tested. Parameter Symbol Value Unit Min Typ Max Write cycle time tWC 120 ns Address setup time tAS ns Address hold time tAH ns Data setup time tDS ns Data hold time tDH ns Output enable setup time tOES ns Output enable hold time Read tOEH ns Toggle and data polling ns Read recovery time before write tGHWL ns CE setup time tCS ns CE hold time tCH ns Write pulse width tWP ns Write pulse width High level tWPH ns Write continuation time tWHWH1 µs Sector erase continuation time*1 tWHWH2 s VCC setup time tVCS µs Voltage transition time*2 tVLHL µs Write pulse width*2 tWPP 100 µs OE setup time for validating WE*2 tOESP µs CE setup time for validating WE*2 tCSP µs INIT pulse width tRP 500 ns RY/BY delay until write/erase is enabled tBUSY ns

c : Write [write/erase command] access (CE control) AC Characteristics for Write Access (CE Control) (Under recommended conditions) * : The internal preprogramming time before erasing is not included. Note : Sampled, not 100 % tested. Parameter Symbol Value Unit Min Typ Max Write cycle time tWC 120 ns Address setup time tAS ns Address hold time tAH ns Data setup time tDS ns Data hold time tDH ns Output enable setup time tOES ns Output enable hold time Read tOEH ns Toggle and data polling ns Read recovery time before write tGHWL ns WE setup time tWS ns WE hold time tWH ns CE pulse width tCP ns CE pulse width High level tCPH ns Write continuation time tWHWH1 µs Sector erase continuation time* tWHWH2 1.5 s VCC setup time tVCS µs INIT pulse width tRP 500 ns RY/BY delay until write/erase is enabled tBUSY ns

I ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings *1 : Making full use of the allowed static DC correct into digital I/O will lead to lower values for VIDIG Min. *2 : • Applicable to pins : D0 to D31, A0 to A20, CS0X to CS6X, RDY, BGRNTX, BRQ, RDX, WR0X to WR3X, AS, ALE, CLK, DREQ0, DACK0, DEOP0, INT0 to INT7, SGO, SGA, SDA, SCL, SOT0, SIN0, SCK0, OCPA0 to OCPA3, TX0, TX1, RX0, RX1, SOT3 to SOT4, SIN3 to SIN4, SCK3 to SCK4, LED0 to LED7 (MB91F362GA only) , IN0 to IN3 (MB91F362GA only) , OUT0 to OUT3 (MB91F362GA only) , OCPA4 to OCPA7 (MB91F362GA only) , SOT1 to SOT2 (MB91F362GA only) , SIH1 to SIH2 (MB91F362GA only) , SCK1 to SCK2 (MB91F362GA only) , PWM1P0 to PWM1P3 (MB91F362GA only) , PWM1M0 to PWM1M3 (MB91F362GA only) , PWM2P0 to PWM2P3 (MB91F362GA only) , PWM2M0 to PWM2M3 (MB91F362GA only)

Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the +B input pin open.
Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. (Continued) Parameter Symbol Rating Unit Condition Min Max Digital supply voltage VDD-VSS −0.3 +6.0 V Stepper motor control supply voltage HVDD-HVSS −0.3 +6.5 V Storage temperature Tstg −55 +125 Power consumption PTOT 2500 mW TA = +25°C Digital input voltage VIDIG −0.3*1 +5.8 V VSS = 0 V, VDD = 5 V Analog input voltage VIA −0.3 +5.8 V VSSA = 0 V, VDDA = 5 V Analog supply voltage VDDA-VSSA −0.3 +5.8 V VSSA = 0 V Analog reference voltage VREFH/L-VSSA −0.3 +5.8 V VSSA = 0 V Static DC current into digital I/O II/ODC −2.0 +2.0 mA Static total DC current into digital I/O ∑II/ODC mA

(Continued)

Sample recommended circuits WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions *: This is only valid if the integrated power-down reset circuit is switched-off, else a reset can be triggered at voltages less or equal than 4.5 V (see “23. POWER DOWN RESET”) . WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Condition Min Typ Max Operating temperature TA −40 +85 Supply voltage (Internal voltage regulator) Digital supply VDD - VSS 4.25* 5.25 V VDDCORE = 3.3 V Stepper motor control supply HVDD - HVSS 4.75 5.25 V HVSS = 0 V Analog supply VDDA - VSSA 4.9 5.1 V VSSA = 0 V RAM data retention voltage VDD - VSS 3.0 V VCC P-ch N-ch R
I/O equivalent circuit Protective diode Limiting resistance +B input (0 V to 16 V)

*1 : See “4. Run Mode Current/Power Consumption”. (Continued) Parameter Sym- bol Value Unit Condition Min Typ Max Current consump- tion Run mode Isrun mA TA = 25 °C RTC mode IsRTC 0.5 1.25 500 mA µA fclk = 4 MHz at TA = 25 °C fclk = 32 kHz at TA = 25 °C Stop mode Isstop 200 µA fclk = 0 at TA = 25 °C Stepper motor control H-port output voltage VOHH HVDD − 500 HVDD − 125 mV Iol = ±30 mA, TC = 25 °C VOHL HVSS + 125 HVSS + 500 mV Iol = ±30 mA, TC = 25 °C VOHH HVDD − 500 HVDD − 125 mV Iol = ±27 mA, TC = 85 °C VOHL HVSS + 125 HVSS + 500 mV Iol = ±27 mA, TC = 85 °C VOHH HVDD − 500 HVDD − 125 mV Iol = ±30 mA, TC = −40 °C VOHL HVSS + 125 HVSS + 500 mV Iol = ±30 mA, TC = −40 °C SMC comparator threshold voltage VTHcomp HVDD / 9 − 70 HVDD / 9 HVDD / 9 + 70 mV Slew rate ns Cload = 0 pF Alarm comparator Threshold voltage Over- voltage VTAH 4/5 VDDA − 5% 4/5 VDDA 4/5 VDDA + 5% V (external 4 : 1 divider) Under- voltage VTAL 2/5 VDDA − 5% 2/5 VDDA 2/5 VDDA + 5% V Switching hysteresis V TAHYS 12.5 mV Alarm sense time tAS µs Input resistance Rin MΩat VTAH, VTAL Power down Reset Threshold voltage VTPOR 3.5 4.0 4.5 V Switching hysteresis VTPO- RHYS mV Reset sense time tRS µs Digital outputs Output “H” voltage VOH VDD − 0.5 VDD V Iload = 4mA Output “L” voltage VOL VSS VSS + 0.4 V Iload = −4mA

(Continued) *2 : valid for bidirectional tristate I/O PAD cell Parameter Symbol Value Unit Condition Min Typ Max Digital Inputs*2 CMOS (Type : Q, S, Y, T) High voltage range VIH 0.65 × VDD VDD V Low voltage range VIL VSS 0.25 × VDD V CMOS Schmitt- Trigger (Types : E, F, U) High voltage range VIH 0.8 × VDD VDD V Low voltage range VIL VSS 0.2 × VDD V CMOS Automotive Schmitt- Trigger (Types : A, B, K1, M1, J) High voltage range VIH 0.8 × VDD VDD V Low voltage range VIL VSS 0.5 × VDD V hysteresis voltage 0.5 V CMOS 3/5 V (Type : L, N, High voltage range VIH 0.65 × VDD VDD V Low voltage range VIL VSS 0.25 × VDD V CMOS 3 V (Type : P, W) High voltage range VIH 0.65 × VDD VDD V Low voltage range VIL VSS 0.25 × VDD V Input capaci- tance CIN pF Input leakage current IIL µA TA = 25 °C Pull up resistor Rup1 Rup2 kΩ kΩ Types : E, U Type : S

(Continued) Parameter Symbol Value Unit Condition Min Typ Max ADC inputs Reference voltage input VREFH VREFL VREFL + 3 VSSA VDDA VREFH − 3 V V Input voltage range Vimax Vimin VREFL VREFH V V Input resistance RI 3.6 kΩ Input capacitance CI pF Input leakage current IIL µA Impedance of external output driving the ADC input 4.0 kΩ at sampling time of 1.6 µs DAC analog outputs Output voltage Vout VSSA VDDA V Output impedance Rout 2.9 kΩ external voltage follower required Output capacitance Cout pF Sound generator Output voltage VoutHIGH VoutLOW VDD − 0.5 VSS VDD VSS + 0.4 V V Output current Iout mA PPG Output voltage VoutHIGH VoutLOW VDD − 0.5 VSS VDD VSS + 0.4 V V Output current Iout mA LED Output voltage VoutHIGH VoutLOW VDD − 0.8 VSS + 0.8 V V IoutHIGH = 14 mA IoutLOW = 24 mA I2C Bus Interface (Open Drain Output) Output voltage VoutHIGH VoutLOW VSS VDD VSS + 0.4 V V open drain output Output current Iout mA IoutLOW = 3 mA Lock-up time PLL1 (4 MHz →16 MHz to 64 MHz) 0.1 ms ESD Protection (Human body model MIL883-B compliant) Vsurge kV Rdischarge = 1.5 kΩ Cdischarge = 100 pF

Run Mode Current/Power Consumption The power dissipation during normal operation is determined by the total power dissipation of the internal logic PC, the dissipation from analog modules PA and the power dissipation PIO of the I/O buffers. Among the I/O buffers the dissipation caused by the stepper motor drivers PSMC should be taken into special consideration. So the overall power consumption PD will be calculated as a sum of Pc + PA + PSMC + PIO . (1) Logic Power Consumption The following formula can be used to calculate the maximum core current consumption when the PLL is used depending on the frequency settings for the internal clocks : If clock modulation is used the following value must be added to this result : 0.24 [mA/MHz] × CLKB [MHz]. This results in the following values (higher clock settings are not allowed) : In addition to this power consumption of the MCU core logic the following contributions to the overall power con- sumption have to be considered : (2) Analog Power Consumption To calculate the analog power consumption PA, the current contributions of the active modules have to be multi- plied by the maximum analog supply voltage of 5.1 V-or by the maximum digital supply voltage as in case of the Power down reset. Clock frequencies [MHz] Maximum Core Current Consumption [mA] Logic Power Consumption PC at 5.25 V [mW] Remarks CLKB CLKP CLKT 308 1.70 no clock modulation possible 290 1.52 264 1.40 257 1.35 205 1.08 202 1.06 163 0.86 146 0.77 0.21 no PLL, no clock modulation 0.125 0.125 0.125 0.16 no PLL, no clock modulation Module Typical Current Consumption Maximum Current Consumption Remarks DAC 1 mA / channel current at AVCC ADC 3 mA 7 mA current at AVCC 1.6 mA 2.6 mA current at AVRH Power down reset 0.26 mA 0.5 mA current at Vdd Alarm Comparator 0.31 mA 0.5 mA current at AVCC Zero point detection 0.13 mA 0.25 mA current at AVCC

(3) I/O and SMC Power Consumption SMC drivers : The average current consumption per SMC channel is 38.2 mA, for four channels this results in 152.8 mA. At 2 × 0.5 V this results in 153 mW power consumption PSMC for four channels of stepper motor drivers. Other I/O Buffers : The power dissipation (PIO) (at 5.25 V) of the I/O buffers is represented as the sum of the dynamic power dissipation (PAC) and the static power consumption (PDC) . PIO = PAC × 1.1 + PDC The following table lists values for the calculation of PAC5V and PAC3V : PAC = PIB × In × f × operating rate + POB × On × f × operating rate PDC is the caused by off chip loads which are drawing static currents. PDC = VO × IO × DCN Buffer Type Power Consumption PIB/POB @ 5V to calculate PAC5V Power Consumption PIB/POB @ 3.3V to calculate PAC3V Unit Normal Input 12.4 12.4 µW/MHz (CL in pF) Bidirectional Input 4 mA Bidirectional Output 194 + 25 CL 85.5 + 11 CL 4 mA Output 8 mA Bidirectional Output 353 + 25 CL 154 + 11 CL 8 mA Output PIB : Power Consumption of Input Buffers and Bidirectional Inputs POB : Power Consumption of Output Buffers and Bidirectional Outputs In : Total number of input buffers and bidirectional buffer inputs On : Total number of output buffers and bidirectional buffer outputs f : System frequency Operating rate : 1.0 if all buffers are switched simultaneously at system frequency VO : Output voltage drop - usually 0.4 V IO : Output current - usually 4 mA DCN : Number of output buffers and bidirectional buffers driving off chip loads causing static currents.

Note : F362GA : If the maximum frequency of 64 MHz is set for CLKB and an odd division factor for CLKT (3, 5, 7, 9, 11, 13, 15) has been selected, then the option to create an asymmetrical CLKT must be used (set bit 14 of the F362MD register to “1”) . Clock domain Clock name Max frequency setting Remark Core CLKB under normal operating conditions for supply voltage between 4.25 and 3.5 V Resource bus CLKP Ext. Bus CLKT

A/D Converter
D/A Converter Parameter Symbol Value Unit Remark Min Typ Max Resolution Bit Conversion error ±5.0 LSB overall error Non-linearity ±2.5 LSB Differential Non-linearity ±1.9 LSB Zero Reading voltage V0T AVRL − 3.5 AVRL + 0.5 AVRL + 4.5 LSB Full scale reading voltage VFST AVRH − 5.5 AVRH − 1.5 AVRH + 2.5 LSB Input current IA@VDDA 3.0 7.0 mA Reference voltage current IR 1.6 2.6 mA Conversion time 178 cycles CLKP 1 ms Ripple of supply voltage ±5.0 mV Parameter Symbol Value Unit Remark Min Typ Max Resolution Bit Differential linearity error −0.9 +0.9 LSB

Resolution The smallest change in analog voltage detected by A/D converter.
Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000 0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”) .
Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage.
Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, full- scale transition error and linearity error. (Continued) 3FF 3FE 3FD 004 003 002 001 AVRL AVRH

1.5 LSB’

0.5 LSB’

(measured value) Total error of digital output N = VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}

1 LSB’

[LSB] VOT ’ (Ideal value) = AVRL + 0.5 LSB’ [V] VFST ’ (Ideal value) = AVRH − 1.5 LSB’ [V] VNT : A voltage for causing transition of digital output from (N − 1) to N Total error

(Continued) 3FF 3FE 3FD 004 003 002 001 AVRL AVRH {1 LSB × (N − 1) + VOT} VNT (measured value) VOT (measured value) Digital output Actual conversion characteristic Ideal characteristic Analog input Actual conversion characteristic VFST (measured value) N − 1 AVRL AVRH N − 2 N N + 1 Actual conversion characteristic Actual conversion characteristic Ideal characteristic VNT (measured value) V(N + 1)T (measured value) Digital output Analog input Linearity error of digital output N VNT − {1 LSB × (N − 1) + VOT}

1 LSB

[LSB] Differential linearity error of digital output N = V (N + 1) T − VNT

1 LSB′

−1 [LSB]

1 LSB =

VFST − VOT 1022 [V]

1 LSB’ (ideal value) = AVRH − AVRL

[V] VOT : A voltage for causing transition of digital output from (000) H to (001) H VFST : A voltage for causing transition of digital output from (3FE) H to (3FF) H VNT : A voltage for causing transition of digital output from (N − 1) H to N Linearity error Differential linearity error

Notes on Using A/D Converter Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 4 kΩ. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling.

Error As the absolute value of AVRH decreases, relative error increases. RO RON : 3.6 KΩ Analog input pin Comparator C0 : 30 pF
Analog input Equivalent Circuit

Flash Memory

••• Erase and programming performance 11. AC Characteristics
••• Measurement conditions Load conditions Parameter Symbol Value Unit Min Typ Max Power supply raising slope ∆V/∆t 0.05 V/µs Power supply raising slope tR µs Parameter Condition Value Unit Remarks Min Typ Max Sector erase time TA = + 25 °C, VDD = 5.0 V 15* s Excludes 00H programming prior erasure Chip erase time s Excludes 00H programming prior erasure Half word (16-bit) programming time 3,600* µs Excludes system-level overhead Erase/Program cycle 10,000 cycle Data retention time 100 K h Parameter Symbol Value Unit Conditions “H” level input voltage VIH according to I/O spec V VDD = 4.25 to 5.25 V, TA = −40 to +85 °C “L” level input voltage VIL V “H” level output voltage VOH 0.5 × VDD V “L” level output voltage VOL 0.5 × VDD V “H” level input voltage VIH 3.0 V VDD = 3.0 to 3.6 V, TA = −40 to +85 °C “L” level input voltage VIL V “H” level output voltage VOH 0.5 × VDD V “L” level output voltage VOL 0.5 × VDD V VDD 4.2 V 0.2 V C = 50 pF Output pin

••• External bus clock (VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C) Note : This is only valid for operation without clock modulator The values for tCHCL and tCLCH are heavily dependent on the load connected to the CLK pin. The following diagrams show this dependency for the worst case situation. The first diagram shows the situation for even division ratios between CLKB and CLKT, the second diagram shows this for odd division ratios between CLKB and CLKT (ASYMCLKT bit is not set) . It has to note that when the combination of CLK frequency and load at CLK pin is such that rise or fall times are longer than tCYC / 2 the duty ratio can get worse. Signal Symbol Pin name Value Unit Min Max CLK cycle tCYC CLK tCPT ns CLK rise → CLK fall tCHCL CLK tCYC / 2 − 10 tCYC / 2 + 10 ns CLK fall → CLK rise tCLCH CLK tCYC / 2 − 10 tCYC / 2 + 10 ns CLK tCYC VOH VOH VOL tCHCL tCLCH

Even CLKB/CLKT division ratios : Odd CLKB/CLKT division ratios : 14,0 12,0 10,0 8,0 6,0 4,0 2,0 0,0 pF ns 100 120 5 V 3.3 V deviation of tCHCL from tCYC / 2 versus load 14,0 12,0 10,0 8,0 6,0 4,0 2,0 0,0 pF ns 100 120 5 V 3.3 V deviation of tCHCL from tCYC / 2 versus load

••• External bus interface (VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C) Signal Symbol Pin name Value Unit Min Max CS6X to CS0X delay time tCHCSL CLK CS6X to CS0X ns CS6X to CS0X delay time tCHCSH ns Address delay time tCHAV CLK A20 to A0 ns Data delay time tCHDV CLK D31 to D0 ns RDX delay time tCLRL CLK RDX ns RDX delay time tCLRH ns WR3X to WR0X delay time tCLWL CLK WR3X to WR0X ns WR3X to WR0X delay time tCLWH ns Effective address ⇒ Effect data input time tAVDV A20 to A0 D31 to D0 3 / 2 × tCYC − 30 ns RDX (fall) → Effect data input time tRLDV RDX D31 to D0 tCYC − 20 ns Data set up → RDX (rise) time tDSRH ns RDX (rise) → Data hold time tRHDX ns AS delay time tCHASL AS ns AS delay time tCHASH AS ns

••• RDY (VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C) Signal Symbol Pin name Value Unit Min Max RDY setup tRDYS CLK RDY ns RDY hold tRDYH CLK RDY ns CLK VOH VOH VOL VOL VIL VIH VIH VIL tRDYH tRDYH RDY case 1 RDY case 2 tCYC tRDYS tRDYS

••• BGRNTX (VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C) Signal Symbol Pin name Value Unit Min Max BGRNTX tCHBGL CLK BGRNTX ns BGRNTX tCHBGH ns Bus access enabled BGRNTX falling tXHAL BGRNTX tcyc − 15 tcyc + 15 ns Bus access disabled BGRNTX rising tHAHV tcyc − 15 tcyc + 15 ns CLK VOH tCHBGL VOH VOH VOH tCHBGH BRQ BGRNTX Other Ports tCYC tHAHV tXHAL High-Z

••• DMA (VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C) * : DSTP and DEOP share a pin. The pin is possible to change DSTP and DEOP functions using a port function register. Signal Symbol Pin name Value Unit Min Max DREQ tDRWH DREQ0 5tCYC ns DSTP tDSWH DSTP0* 5tCYC ns DACK tCLDL CLK DACK0 ns tCLDH DEOP tCLEL CLK DEOP0 ns tCLEH CLK DSTP0 DREQ0 DACK0 DEOP0 tCYC tDSWH tDRWH tCLDL tCLDH tCLEL tCLEH

I PACKAGE THERMAL RESISTANCE INFORMATION I ORDERING INFORMATION Package Thermal Resistance [ °°°°C/W] Theta-ja Theta-jc 0 m/s 1 m/s 3 m/s FPT-208P-M04 2.5 PGA-401C-A02 8.5 5.5 FPT-160P-M15 2.5 Part number Package Remarks MB91FV360GACR 401-pin Ceramic PGA (PGA-401C-A02) MB91F362GAPFVS 208-pin Plastic QFP (FPT-208P-M04) MB91F369GAPQS1 160-pin Plastic QFP (FPT-160P-M15)

(Continued) 401-pin ceramic PGA (PGA-401C-A02) 208-pin plastic QFP (FPT-208P-M04) Note : Pins width and pins thickness include plating thickness. 48.26 ± 0.55 (1.900 ± .022) SQ INDEX AREA

1994 FUJITSU LIMITED R401002SC-2-2

2.54 (.100) TYP 0.40 ± 0.10 (.016 ± .004) DIA 45.72 (1.800) REF 1.20 ± 0.25 (.047 ± .010) 5.27 (.207) MAX 3.40 ± 0.40 (.134 ± .016) 1.00 (.039) DIA TYP (4 PLCS) EXTRA INDEX PIN 1.02 (.040) C TYP (4 PLCS) C Dimensions in mm (inches) C 2000 FUJITSU LIMITED F208020S-c-2-3 .148 –.012 +.008 –0.30 +0.20 3.75 Details of "A" part 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) (Stand off) 0.40 +0.10 –0.15 +.004 –.006 .016 0°~8° LEAD No. 104 105 156 157 208 "A" 0.08(.003) 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) M .007 –.003 +.001 –0.08 +0.03 0.17 INDEX (Mounting height) Dimensions in mm (inches)

(Continued) 160-pin plastic QFP (FPT-160P-M15) Note : Pins width and pins thickness include plating thickness. C 2001 FUJITSU LIMITED F160037S-c-2-2 M 0.13(.005) 0.65(.026) 0.10(.004) "A" (Mounting height) Details of "A" part INDEX 121 160 120 –0.07 +0.08 0.32 .013 +.0031 –.0028 –0.03 +0.05 0.17 .007 +.002 –.001 0~8° –0.20 +0.35 3.75 .148 +.014 –.008 0.25(.010) (Stand off) –0.15 +0.10 0.40 .016 +.004 –.006 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) Dimensions in mm (inches)

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0201  FUJITSU LIMITED Printed in Japan

Product Information

F369GA specifications and overview.

Summary

32-BIT RISC MICROCONTROLLER

Description

32-BIT RISC MICROCONTROLLER

Source title F369GA Datasheet(PDF) - fujitsu semiconductor

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