F2976

F2976 IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

High Linearity Broadband SP2T 5MHz to 10GHz F2976 Datasheet © 2017 Integrated Device Technology, Inc. 1 Rev O April 19, 2017

Description

The F2976 is a single5pole double5throw (SP2T) reflective RF switch featuring high linearity and wide bandwidth. This dev ice is optimized from 5MHz to 1.8GHz to support downstream cable modem future migration for DOCSIS 3.1 applications, and operates at up to 10GHz to support a multitude of wireless RF applications. Superb performance is achieved when used in either 50Ω o r 75Ω terminating impedance applications. The F2976 uses a single positive supply voltage of either +3.3V or +5.0V and is compatible with either 1.8V or 3.3V control logic. Competitive Advantage The F2976 provides extremely low insertion loss across the entire bandwidth while providing superb distortion performance. /square4 Optimized for DOCSIS 3.1 applications up to 1.8GHz /square4 Optimized for Wi5Fi applications up to 5.9GHz /square4 Low insertion loss /square4 High isolation /square4 Fast switching /square4 No external matching required Typical Applications /square4 Broadband Cable DOCSIS 3.0 / 3.1 /square4 Set top box /square4 CATV filter bank switching /square4 Wi5Fi /square4 Cellular BTS /square4 General purpose General Features /square4 Supply voltage: +2.5V to +5.25V /square4 1.8V and 3.3V compatible control logic /square4 2mm x 2mm, 125pin TQFN package /square4 540°C to +105°C operating temperature range Features (75Ω) /square4 Low insertion loss: /square4 0.23dB at 204MHz /square4 0.34dB at 1.8GHz /square4 High Isolation: 40dB at 1.8GHz /square4 P0.1dB compression of +37dBm at 204MHz /square4 Second Harmonic: 5100dBc at 204MHz /square4 Third Harmonic: 5120dBc at 204MHz /square4 Composite Second Order Distortion > 100dBc /square4 Composite Triple Beat Distortion > 100dBc Features (50Ω) /square4 Low insertion loss: /square4 0.40dB at 2.4GHz /square4 0.55dB at 8GHz /square4 High Isolation: /square4 34dB at 2.4GHz /square4 High Linearity: /square4 IIP2 +125dBm at 2.4GHz /square4 IIP3 +77dBm at 2.4GHz /square4 P0.1dB compression of +40dBm at 2.4GHz /square4 Second Harmonic: 5100dBc at 2.4GHz /square4 Third Harmonic: 5110dBc at 2.4GHz Block Diagram Figure 1. Block Diagram

Figure 2. Pin Assignments for 2mm x 2mm x 0.5mm 12.pin TQFN, NEG12 – Top View Table 1. Pin Descriptions 1 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 2 RF2 RF2 Port. If this pin is not 0 V DC, then an external coupling capacitor must be used. 3 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 4 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 5 RFC RF Common Port. If this pin is not 0 V DC, then an external coupling capacitor must be used. 6 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 7 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 8 RF1 RF1 Port. If this pin is not 0 V DC, then an external coupling capacitor must be used. 9 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 10 VCTL Logic control pin (see Table 9). vias are also required to achieve the specified RF performance.

for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings

10 MHz < f RF ≤ 25 MHz PABSCW2 32

25 MHz < f RF ≤ 200 MHz PABSCW3 33

200 MHz < f RF ≤ 6000 MHz PABSCW4 34

10 MHz < f RF ≤ 25 MHz PABSPK2 37

25 MHz < f RF ≤ 200 MHz PABSPK3 38

200 MHz < f RF ≤ 6000 MHz PABSPK4 39

EP = Temperature of the exposed paddle. c. 5 % duty cycle of a 4.6ms period.

Table 3. Recommended Operating Conditions Figure 3. Maximum Operating RF Input Power (Z S = Z L = 50Ω)

Table 4. General Specifications applied at RF1 or RF2 and measured at RFC, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by t est. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

© 2017 Integrated Device Technology, Inc . 6 Rev O April 19 , 2017

Electrical Characteristics

Table 5. Electrical Characteristics . 75Ω SPECIFICATION signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are de5embedded, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by t est. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

© 2017 Integrated Device Technology, Inc . 7 Rev O April 19 , 2017 Table 6. Electrical Characteristics . 50Ω SPECIFICATION signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are de5embedded, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by t est. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

© 2017 Integrated Device Technology, Inc . 8 Rev O April 19 , 2017 Table 7. Electrical Characteristics . 50Ω SPECIFICATION signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are de5embedded, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by t est. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

Table 8. Package Thermal Characteristics

© 2017 Integrated Device Technology, Inc . 14 Rev O April 19 , 2017 Control Mode Table 9. Switch Control Truth Table

Application Information

A common V CC power supply should be used for all pins requiring DC pow er. All supply pins should be bypassed with external capac itors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at 0V (+/50.3V) while the supply voltage ramps up or while it returns to zero. Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to control pins 7 and 8 as shown below. Figure 26. Control Pin Interface Schematic

Figure 31. Electrical Schematic (75Ω) clockwise from the F2972 PCB pin 1 marking, for proper assembly.

Figure 32. Electrical Schematic (50Ω) clockwise from the F2972 PCB pin 1 marking, for proper assembly.

Table 10. 75Ω Bill of Material (BOM)

1 Printed Circuit Board [a] F2972 75 Hglyph+C+ PCB IDT

clockwise from the F2972 PCB pin 1 marking, for proper assembly. Table 11. 50Ω Bill of Material (BOM)

1 Printed Circuit Board [a] F2972 50 Hglyph+C+ PCB IDT

clockwise from the F2972 PCB pin 1 marking, for proper assembly.

© 2017 Integrated Device Technology, Inc . 20 Rev O April 19 , 2017 Evaluation Kit (EVKit) Operation External Supply Setup Set up a V CC power supply in the voltage range of 2.5V to 5.25V with the power supply output disabled. For the 75Hglyph+C+ EVKit, connect the disabled Vcc supply connection to J6 pin 2 and GND to J6 pins 1 or 5. For the 50Hglyph+C+ EVKit, connect the disabled Vcc supply connection to J6 pin 3 and GND to J6 pin 1, 2, 4, 6, 8, 9, or 10. Logic Control Setup With the logic control lines disabled set the HIGH and LOW logic levels to satisfy the levels stated in the electrical specifications table. For the 75Hglyph+C+ EVKit, connect the disabled logic control lines to J6 EN (pin 3) and V CTL (pin 4). For the 50Hglyph+C+ EVKit, connect the disabled logic control lines to J6 EN / LS (pin 5) and V CTL (pin 7). See Table 9 for the logic truth table. Turn On Procedure Setup the supplies and EVKit as noted in the External Supply Setup and Logic Control Setup sections above. Enable the V CC supply. Enable the logic control signals. Set the logic settings to achieve the desired Table 9 con figuration. Note that external control logic should not be applied without V CC being present. Turn Off Procedure Set the logic control pins to a logic LOW. Disable the V CC supply.

Figure 33. Package Outline Drawing NEG12 PSC.4642

Figure 34. Recommended Land Pattern NEG12 PSC.4642

© 2017 Integrated Device Technology, Inc . 23 Rev O April 19 , 2017 Marking Diagram 2976 YW Line 1 5 2976 = Abbreviated part number. Line 2 5 Y = Year code. Line 2 5 W = Work week code. Line 2 5 = Sequential alpha for lot traceability.

Ordering Information

Orderable Part Number Package MSL Rating Shipping Packaging Temperature F2 976 NEGK 2mm x 2 mm x 0.5 mm 12 5VFQFP 5N MSL1 Cut Reel 540 °C to +105 °C F2976 NEGK8 2mm x 2 mm x 0. 5mm 12 5VFQFP 5N MSL1 Tape and Reel 540 °C to +105 °C F2976EVBI 575OHM 75 Ω Evaluation Board F2976EVBI 550OHM 50 Ω Evaluation Board

© 2017 Integrated Device Technology, Inc . 24 Rev O April 19 , 2017

Revision History

Revision Revision Date Description of Change Rev O 2017 5Apr 519 Initial Release Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 www.IDT.com Sales 15800534557015 or 408528458200 Fax: 408528452775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to a s “IDT”) reserve the right to modify the products a nd/or specifications described herein at any time, without notice, at IDT's sole discretion. Performan ce specifications and operating parameters of the d escribed products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The inform ation contained herein is provided without represen tation or warranty of any kind, whether express or implied, including, but not limited to, the suitabi lity of IDT's products for any particular purpose, an im plied warranty of merchantability, or non5infringem ent of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property righ ts of IDT or any third parties. IDT's products are not intended for use in applicat ions involving extreme environmental conditions or in life support systems or similar devices where th e failure or malfunction of an IDT product can be reasonably expected to significantly affect the hea lth or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other cou ntries. Other trademarks used herein are the property of IDT or their respective third party own ers. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of In tegrated Device Technology, Inc. All rights reserved.