F2972

F2972 IDT | Alldatasheet

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High Linearity Broadband SP2T 5MHz to 10GHz F2972 Datasheet © 2017 Integrated Device Technology, Inc . 1 Rev O April 19 , 2017

Description

The F2972 is a singleMpole doubleMthrow (SP2T) reflective RF switch featuring high linearity and wide bandwidth. This dev ice is optimized from 5MHz to 1.8GHz to support downstream cable modem future migration for DOCSIS 3.1 applications, and operates at up to 10GHz to support a multitude of wireless RF applications. Superb performance is achieved when used in either 50Ω o r 75Ω terminating impedance applications. The F2972 uses a single positive supply voltage of either +3.3V or +5.0V and is compatible with either 1.8V or 3.3V control logic. Competitive Advantage The F2972 provides extremely low insertion loss across the entire bandwidth while providing superb distortion performance. /square4 Optimized for DOCSIS 3.1 applications up to 1.8GHz /square4 Optimized for WiMFi applications up to 5.9GHz /square4 Low insertion loss /square4 High isolation /square4 Fast switching /square4 No external matching required Typical Applications /square4 Broadband cable DOCSIS 3.0 / 3.1 /square4 Set top box /square4 CATV filter bank switching /square4 WiMFi /square4 Cellular BTS /square4 General purpose General Features /square4 Supply voltage: +2.5V to +5.25V /square4 1.8V and 3.3V compatible control logic /square4 2mm x 2mm, 12Mpin TQFN package Features (75Ω) /square4 Low insertion loss: /square4 0.23dB at 204MHz /square4 0.34dB at 1.8GHz /square4 High Isolation: 40dB at 1.8GHz /square4 P0.1dB compression of +37dBm at 204MHz /square4 Second Harmonic: M100dBc at 204MHz /square4 Third Harmonic: M120dBc at 204MHz /square4 Composite Second Order Distortion > 100dBc /square4 Composite Triple Beat Distortion > 100dBc Features (50Ω) /square4 Low insertion loss: /square4 0.40dB at 2.4GHz /square4 0.55dB at 8GHz /square4 High Isolation: /square4 34dB at 2.4GHz /square4 High Linearity: /square4 IIP2 +125dBm at 2.4GHz /square4 IIP3 +77dBm at 2.4GHz /square4 P0.1dB compression of +40dBm at 2.4GHz /square4 Second Harmonic: M100dBc at 2.4GHz /square4 Third Harmonic: M110dBc at 2.4GHz Block Diagram Figure 1. Block Diagram

Figure 2. Pin Assignments for 2mm x 2mm x 0.5mm 12fpin TQFN, NEG12 – Top View Table 1. Pin Descriptions 1 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 2 RF C RF Common Port. If this pin is not 0 V DC, then an external coupling capacitor must be used. 3 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 4 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 5 RF1 RF1 Port. If this pin is not 0 V DC, then an external coupling capacitor must be used. 6 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 2.5V through a 500kΩ resistor. 10 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. 11 RF2 RF2 Port. If this pin is not 0 V DC, then an external coupling capacitor must be used. 12 GND Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias. vias are also required to achieve the specified RF performance.

for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings

10 MHz < f RF ≤ 25 MHz PABSCW2 32

25 MHz < f RF ≤ 200 MHz PABSCW3 33

200 MHz < f RF ≤ 6000 MHz PABSCW4 34

10 MHz < f RF ≤ 25 MHz PABSPK2 37

25 MHz < f RF ≤ 200 MHz PABSPK3 38

200 MHz < f RF ≤ 6000 MHz PABSPK4 39

a. In a 50 8glyphV3V s ystem , dBmV = dBm [50 Ω] + 47. In a 758glyphV3V system, dBmV = dBm [75Ω] + 48.75. EP = Temperature of the exposed paddle. c. 5% duty cycle of a 4.6ms period.

Table 3. Recommended Operating Conditions Figure 3. Maximum Operating RF Input Power (Z S = Z L = 50Ω)

Table 4. General Specifications applied at RF1 or RF2 and measured at RFC, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by t est. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

© 2017 Integrated Device Technology, Inc . 6 Rev O April 19 , 2017

Electrical Characteristics

Table 5. Electrical Characteristics f 75Ω SPECIFICATION signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are deMembedded, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

© 2017 Integrated Device Technology, Inc . 7 Rev O April 19 , 2017 Table 6. Electrical Characteristics f 50Ω SPECIFICATION signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are deMembedded, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by t est. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

© 2017 Integrated Device Technology, Inc . 8 Rev O April 19 , 2017 Table 7. Electrical Characteristics f 50Ω SPECIFICATION signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are deMembedded, unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by t est. b. Items in min/max columns that are not bold italics are guaranteed by design characterization.

Table 8. Package Thermal Characteristics

© 2017 Integrated Device Technology, Inc . 14 Rev O April 19 , 2017 Control Mode Table 9. Switch Control Truth Table

Application Information

A common V CC power supply should be used for all pins requiring DC pow er. All supply pins should be bypassed with external capac itors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at 0V (+/M0.3V) while the supply voltage ramps up or while it returns to zero. Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to control pins 7 and 8 as shown below. Figure 26. Control Pin Interface Schematic

Figure 31. Electrical Schematic (75Ω)

Figure 32. Electrical Schematic (50Ω)

Table 10. 75Ω Bill of Material (BOM)

1 Printed Circuit Board F2972 75 8glyphV3V PCB IDT

Table 11. 50Ω Bill of Material (BOM)

1 Printed Circuit Board F2972 50 8glyphV3V PCB IDT

© 2017 Integrated Device Technology, Inc . 20 Rev O April 19 , 2017 Evaluation Kit (EVKit) Operation External Supply Setup Set up a V CC power supply in the voltage range of 2.5V to 5.25V with the power supply output disabled. For the 758glyphV3V EVKit, connect the disabled Vcc supply connection to J6 pin 2 and GND to J6 pins 1 or 5. For the 508glyphV3V EVKit, connect the disabled Vcc supply connection to J6 pin 3 and GND to J6 pin 1, 2, 4, 6, 8, 9, or 10. Logic Control Setup With the logic control lines disabled set the HIGH and LOW logic levels to satisfy the levels stated in the electrical specifications table. For the 758glyphV3V EVKit, connect the disabled logic control lines to J6 EN (pin 3) and V CTL (pin 4). For the 508glyphV3V EVKit, connect the disabled logic control lines to J6 EN / LS (pin 5) and V CTL (pin 7). See Table 9 for the logic truth table. Turn On Procedure Setup the supplies and EVKit as noted in the External Supply Setup and Logic Control Setup sections above. Enable the V CC supply. Enable the logic control signals. Set the logic setting to achieve the desired Table 9 con figuration. Note that external control logic should not b e applied without V CC being present. Turn Off Procedure Set the logic control pins to a logic LOW. Disable the V CC supply.

Figure 33. Package Outline Drawing NEG12 PSCf4642

Figure 34. Recommended Land Pattern NEG12 PSCf4642

© 2017 Integrated Device Technology, Inc . 23 Rev O April 19 , 2017 Marking Diagram 2972 YW Line 1 M 2972 = Abbreviated part number. Line 2 M Y = Year code. Line 2 M W = Work week code. Line 2 M = Sequential alpha for lot traceability.

Ordering Information

Orderable Part Number Package MSL Rating Shipping Packaging Temperature F2 972NEGK 2mm x 2 mm x 0.5 mm 12 MVFQFP MN MSL1 Cut Reel M40°C to +105 °C F2972NEGK8 2mm x 2 mm x 0. 5mm 12MVFQFP MN MSL1 Tape and Reel M40°C to +105 °C F2972EVBI M75OHM 75 Ω Evaluation Board F2972EVBI M50OHM 50 Ω Evaluation Board

6024 Silver Creek Valley Road

San Jose, CA 95138 www.IDT.com Sales 1M800M345M7015 or 408M284M8200 Fax: 408M284M2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to a s “IDT”) reserve the right to modify the products a nd/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and ope rating parameters of the described products are det ermined in an independent state and are not guarant eed to perform the same way when installed in custo mer products. The information contained herein is provided withou t representation or warranty of any kind, whether e xpress or implied, including, but not limited to, t he suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or nonMinfringement of the inte llectual property rights of others. This document i s presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applicat ions involving extreme environmental conditions or in life support systems or similar devices where th e failure or malfunction of an IDT product can be r easonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written ag reement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other cou ntries. Other trademarks used herein are the proper ty of IDT or their respective third party owners. For datasheet type d efinitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of In tegrated Device Technology, Inc. All rights reserve d F2972 Datasheet © 2017 Integrated Device Technology, Inc. 24 Rev O April 19 , 2017

Revision History

Revision Revision Date Description of Change Rev O 2017 MApr M19 Initial Release