F2950

F2950 RENESAS | Alldatasheet

Document overview

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Technical content

Features

 Low insertion loss: 0.58dB at 2.5GHz  High isolation: 44dB at 2.5GHz  Excellent linearity:  IIP3 +69dBm at 2.4GHz and 5.9GHz  IIP2 +115dBm at 2.4GHz  IIP2 +117dBm at 5.9GHz  Second Harmonic: -93dBc at 5.9GHz  Third Harmonic: -85dBc at 5.9GHz  Typical switching speed: 170ns  Supply voltage: +2.7V to +5.5V  1.8V and 3.3V compatible control logic  -40°C to +105°C operating temperature range  1.5mm x 1.5mm, 6-pin DFN package Block Diagram Figure 1. Block Diagram

Figure 2. Pin Assignments for 1.5mm x 1.5mm x 0.55mm DFN, NEG6 – Top View Table 1. Pin Descriptions 1 VCTL Logic control pin. See Table 7 for logic control states. coupling capacitor must be used. 3 VCC Power supply. Bypass to GND with capacitors as close as possible to the pin. 5 GND Ground. Ground this pin as close to the device as possible. vias are also required to achieve the specified RF performance.

conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings [a] TEP is the temperature of the exposed paddle. [b] 5% duty cycle of 4.6ms period in a 50Ω environment.

Table 3. Recommended Operating Conditions [a] Functional with reduced performance for 2.3V ≤ VCC < 2.7V. Figure 3. Maximum RF Input Operating Power vs. RF Frequency (ZS = ZL = 50Ω)

© 2017 Integrated Device Technology, Inc. 5 Rev O August 8, 2017

Electrical Characteristics

Table 4. Electrical Characteristics embedded, unless otherwise noted. [a] Items in min/max columns in bold italics are guaranteed by test. [b] Items in min/max columns that are not bold italics are guaranteed by design characterization.

© 2017 Integrated Device Technology, Inc. 6 Rev O August 8, 2017 Table 5. Electrical Characteristics embedded, unless otherwise noted. Peak transient during switching. [a] Items in min/max columns in bold italics are guaranteed by test. [b] Items in min/max columns that are not bold italics are guaranteed by design characterization. for the maximum RF input power. [d] Spurious due to on-chip negative voltage generator. Spurious fundamental is approximately 5.7MHz. [e] fRF = 1GHz. Rise and fall time of VCTL = 20ns.

Table 6. Package Thermal Characteristics

© 2017 Integrated Device Technology, Inc. 11 Rev O August 8, 2017 Control Mode Table 7. Switch Control Truth Table

Application Information

The VCTL control pin includes no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH. Power Supplies A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and caus e them to fail. Supply voltage change or transients should have a slew rate slower than 1V / 20µs. In addition, all control pins should remain at 0V (± 0.3V) while the supply voltage ramps up or while it returns to zero. Control Pin Interface If a clean control signal cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of the control pin is recommended. Figure 17. Control Pin Signal Integrity Improvement Circuit

Figure 20. Electrical Schematic Table 8. Bill of Material (BOM)

1 Printed Circuit Board F2950 EVKit IDT

© 2017 Integrated Device Technology, Inc. 14 Rev O August 8, 2017 Evaluation Kit (EVKit) Operation External Supply Setup Set up a VCC power supply in the voltage range of 2.7V to 5.5V with the power supply output disabled. Connect the disabled VCC supply connection to J6 pin 3 or 5 and GND to J6 pin 2, 4, 6, or 8. Logic Control Setup With the logic control line disabled, set the logic HIGH and LOW levels to satisfy the levels stated in the electrical specifications table. Connect the disabled logic control line to VCTL (pin 1 of J6) and GND to J6 pin 2, 4, 6, or 8. Turn On Procedure Set up the supplies and EVKit as noted in the “External Supply Setup” and “Logic Control Setup” sections above. Enable the VCC supply. Enable the logic control signal. Set the VCTL logic setting to achieve the desired Table 7 configuration. Note that the VCT L control logic should not be applied without V CC being present. Enable any RF signal. Turn Off Procedure Disable any applied RF signal. Set VCTL to GND. Disable the VCC supply.

Figure 21. Package Outline Drawing – NEG6 Package

Figure 22. Recommended Land Pattern – NEG6 Package

© 2017 Integrated Device Technology, Inc. 17 Rev O August 8, 2017 Marking Diagram YBA 1. Line 1: Y = last digit of the year, BA = sequential letters for traceability purposes 2. Line 2: Pin 1 dot, 2 = F2950 part number code

Ordering Information

Orderable Part Number Package MSL Rating Shipping Packaging Temperature F2950NEGK 1.5mm x 1.5mm x 0.55mm NEG6 DFN MSL1 Cut Tape -40°C to +105°C F2950NEGK8 1.5mm x 1.5mm x 0.55mm NEG6 DFN MSL1 Reel -40°C to +105°C F2950EVBI Evaluation Board

© 2017 Integrated Device Technology, Inc. 18 Rev O August 8, 2017

Revision History

Revision Revision Date Description of Change Rev O August 8, 2017 Initial Release Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the ri ght to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are d etermined in an independent state and are not guaranteed to perform the same way when installed in customer pro ducts. The information contained herein is provided without representation or warranty of any kind, whether express or implie d, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantabil ity, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in a pplications involving extreme environmental conditions or in life support systems or similar devices where the failure or mal function of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT pr oduct in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Fo r datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.

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