F28M35H52C1RFPT.B

F28M35H52C TI | Alldatasheet

Document overview

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Technical content

F28M35x Concerto™ Microcontrollers

1 Features

• Master Subsystem — Arm® Cortex®-M3 – Up to 100 MHz – Embedded memory
• Up to 512KB of flash (ECC)
• Up to 32KB of RAM (ECC or parity)
• Up to 64KB of shared RAM
• 2KB of IPC Message RAM – Five Universal Asynchronous Receiver/ Transmitters (UARTs) – Four Synchronous Serial Interfaces (SSIs) and a Serial Peripheral Interface (SPI) – Two Inter-integrated Circuits (I2Cs) – Universal Serial Bus On-the-Go (USB-OTG) + PHY – 10/100 ENET 1588 MII – Two Controller Area Network, D_CAN, modules (pin-bootable) – 32-channel Micro Direct Memory Access (µDMA) – Dual security zones (128-bit password per zone) – External Peripheral Interface (EPI) – Micro Cyclic Redundancy Check (µCRC) module – Four general-purpose timers – Two watchdog timer modules – Three external interrupts – Endianness: little endian
• Clocking – On-chip crystal oscillator and external clock input – Dynamic Phase-Locked Loop (PLL) ratio changes supported
• 1.2-V digital, 1.8-V analog, 3.3-V I/O design
• Interprocessor Communications (IPC) – 32 handshaking channels – Four channels generate IPC interrupts – Can be used to coordinate transfer of data through IPC Message RAMs
• Up to 74 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins – Glitch-free I/Os
• Control Subsystem — TMS320C28x 32-bit CPU – Up to 150 MHz – C28x core hardware built-in self-test – Embedded memory
• Up to 512KB of flash (ECC)
• Up to 36KB of RAM (ECC or parity)
• Up to 64KB of shared RAM
• 2KB of IPC Message RAM – IEEE-754 single-precision Floating-Point Unit (FPU) – Viterbi, Complex Math, CRC Unit (VCU) – Serial Communications Interface (SCI) – SPI – I2C – 6-channel Direct Memory Access (DMA) – Nine Enhanced Pulse Width Modulator (ePWM) modules
• 18 outputs (16 high-resolution) – Six 32-bit Enhanced Capture (eCAP) modules – Three 32-bit Enhanced Quadrature Encoder Pulse (eQEP) modules – Multichannel Buffered Serial Port (McBSP) – EPI – One security zone (128-bit password) – Three 32-bit timers – Endianness: little endian
• Analog Subsystem – Dual 12-bit Analog-to-Digital Converters (ADCs) – Up to 2.88 MSPS – Up to 20 channels – Four Sample-and-Hold (S/H) circuits – Up to six comparators with 10-bit Digital-to- Analog Converter (DAC)
• Package – 144-Pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP)
• Temperature options: – T: –40°C to 105°C Junction – S: –40°C to 125°C Junction – Q: –40°C to 125°C Free-Air (AEC Q100 qualification for automotive applications)

2 Applications

• Automated sorting equipment
• CNC control
• Central inverter
• String inverter
• AC drive control module
• Servo drive control module
• AC-input BLDC motor drive
• DC-input BLDC motor drive
• Industrial AC-DC
• Three phase UPS F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

3 Description

The Concerto family is a multicore system-on-chip microcontroller unit (MCU) with independent communication and real-time control subsystems. The F28M35x family of devices is the first series in the Concerto family. The communications subsystem is based on the industry-standard 32-bit Arm Cortex-M3 CPU and features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, Controller Area Network (CAN), UART, SSI, I2C, and an external interface. The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x floating-point CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and encoders and captures—all as implemented by TI’s TMS320C2000™ Entry performance MCUs and Premium performance MCUs . In addition, the C28-CPU has been enhanced with the addition of the VCU instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms. A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC), parity, and code secure memory, as well as documentation to assist with system-level industrial safety certification. Device Information PART NUMBER(1) PACKAGE BODY SIZE F28M35H52CRFP HTQFP (144) 20.0 mm × 20.0 mm F28M35H22CRFP HTQFP (144) 20.0 mm × 20.0 mm F28M35M52CRFP HTQFP (144) 20.0 mm × 20.0 mm F28M35E20BRFP HTQFP (144) 20.0 mm × 20.0 mm (1) For more information on these devices, see Mechanical, Packaging, and Orderable Information. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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3.1 Functional Block Diagram

(parity) RAM 8KB (parity) BOOT ROM 64KB GPIO_MUX1 GP TIMER (4) uCRCI C (2)2 I C2 SSI (4)UART (5) USB+PHY (OTG) EMAC WDOG (2)NMI WDOG 1.2-V VREG 1.8-V VREG SECURE RAM 8KB (ECC) SECURE RAM 8KB (ECC) AHB BUS APB BUS S0 S7 SHARED RAM (parity)– 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB MTOC MSG RAM (parity) 2KB CTOM MSG RAM (parity) 2KB IPC INTER- PROC COMM M3 SYSTEM BUS uDMA BUS RAM 8KB (parity) RAM 8KB (parity) SECURE FLASH 512KB (ECC) BOOT ROM 64KB SECURE RAM 8KB (ECC) SECURE RAM 8KB (ECC) TIMER (3)XINT (3) EPWM (9)NMI WDOG EQEP (3)ECAP (6) McBSPSCI SPI GPIO_MUX1 RAM 2KB (ECC) RAM 2KB (ECC) C28 CPU BUS C28 DMA BUS 16- BIT PF2 32- BIT PF1 32- BIT PF3 C28 CPU C28 FPU C28 VCU C28 DMA M3 CPU NVIC MPUM3 BUS MA TRIX uDMA I-CODE BUS D-CODE BUS

66 PINS

ADC_1 MODULE ADC_2 MODULE GPIO_MUX2

10 PINS

AIO_MUX2 AIO_MUX1

8 PINS

+ DAC UNITS MEM32 TO AHB BUS BRIDGE ANALOG COMMON INTERFACE BUS C28 CPU/DMA ACCESS TO EPI EPI INTER- PROC COMM CAN (2) RESETS NMI CLOCKS SECURITY DEBUG FREQ GASKET SECURE FLASH 512KB (ECC) Copyright © 2017, Texas Instruments Incorporated A. Some peripherals are not available on the F28M35Mx and F28M35Ex devices. Figure 3-1. Functional Block Diagram www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.7 Thermal Resistance Characteristics for RFP

8.9 Internal Voltage Regulation and Power-On-

10.1 Device and Development Support Tool

11 Mechanical, Packaging, and Orderable

F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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4 Revision History

Changes from June 23, 2020 to February 1, 2021 (from Revision K (June 2020) to Revision L (February 2021)) Page www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

5 Device Comparison

Table 5-1 lists the features of the F28M35x devices. Table 5-1. Device Comparison FEATURE TYPE (1) H52C H52C-Q1 H22C M52C M22C E20B Master Subsystem — Arm Cortex-M3 Speed (MHz) (2) – 100 100 75 75 60 Flash (ECC) (KB) – 512 256 512 256 256 RAM (ECC) (KB) – 16 16 16 16 16 RAM (Parity) (KB) – 16 16 16 16 16 IPC Message RAM (Parity) (KB) – 2 2 2 2 2 Security Zones – 2 2 2 2 2 10/100 ENET 1588 MII 0 Yes Yes Yes Yes No USB OTG FS 0 Yes Yes Yes Yes No SSI/SPI 0 4 4 4 4 4 UART 0 5 5 5 5 5 I2C 0 2 2 2 2 2 CAN (3) 0 2 2 2 2 2 µDMA 0 32-ch 32-ch 32-ch 32-ch 32-ch EPI (4) 0 1 1 1 1 1 µCRC module 0 1 1 1 1 1 General-Purpose Timers – 4 4 4 4 4 Watchdog Timer modules – 2 2 2 2 2 Control Subsystem — C28x Speed (MHz) (2) 150 150 75 75 60 FPU Yes VCU Yes Flash (ECC) (KB) 512 256 512 256 256 RAM (ECC) (KB) 20 20 20 20 20 RAM (Parity) (KB) 16 16 16 16 16 IPC Message RAM (Parity) (KB) 2 2 2 2 2 Security Zones 1 1 1 1 1 ePWM modules 2 9: 18 outputs High-Resolution PWM (HRPWM) outputs 2 16 outputs eCAP modules/PWM outputs 0 6 (32-bit) eQEP modules 0 3 (32-bit) Fault Trip Zones – 12 on any of 64 GPIO pins McBSP/SPI 1 1 1 1 1 1 SCI 0 1 1 1 1 1 SPI 0 1 1 1 1 1 I2C 0 1 1 1 1 1 DMA 0 6-ch 6-ch 6-ch 6-ch 6-ch EPI (4) 0 1 1 1 1 1 32-Bit Timers – 3 3 3 3 3 Shared Shared RAM (Parity) (KB) 64 64 64 64 0 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 5-1. Device Comparison (continued) FEATURE TYPE (1) H52C H52C-Q1 H22C M52C M22C E20B 12-Bit ADC 1 MSPS (5) Conversion Time (5) 347 ns 347 ns 347 ns 347 ns 433 ns Channels 10 10 10 10 10 Sample-and-Hold 2 2 2 2 2 12-Bit ADC 2 MSPS (5) Conversion Time (5) 347 ns 347 ns 347 ns 347 ns 433 ns Channels 10 10 10 10 10 Sample-and-Hold 2 2 2 2 2 Comparators with Integrated DACs 0 6 6 6 6 6 Voltage Regulator Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125°C) Clocking See Section 8.10 Additional Safety Master Subsystem 2 Watchdogs, NMI Watchdog: CPU, Memory Control Subsystem NMI Watchdog: CPU, Memory Shared Critical Register and I/O Function Lock Protection; RAM Fetch Protection Packaging Package Type 144-Pin RFP PowerPAD HTQFP Yes Yes Yes Yes Yes Junction Temperature (TJ) T: –40°C to 105°C – Yes Yes Yes Yes Yes S: –40°C to 125°C – Yes Yes Yes Yes Yes Q: –40°C to 150°C (6) – Yes No No No No Free-Air Temperature (TA) Q: –40°C to 125°C (6) – Yes No No No No (1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides. (2) The maximum frequency at which the Cortex-M3 core can run is 100 MHz. The clock divider before the Cortex-M3 core can only take values of /1, /2, or /4. For this reason, when the C28x is configured to run at the maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 is 75 MHz. If the Cortex-M3 is configured to run at 100 MHz, the maximum frequency of the C28x is limited to 100 MHz. (3) The CAN module uses the popular IP known as D_CAN. This document uses the names “CAN” and “D_CAN” interchangeably to reference this peripheral. (4) Single EPI arbitrated between masters in Master and Control Subsystems. (5) An integer divide ratio must be maintained between the C28x and ADC clock frequencies. All MSPS and Conversion Time values are based on the maximum C28x clock frequency. (6) "Q" refers to AEC Q100 qualification for automotive applications. Table 5-2. Possible Speed Combinations for Cortex-M3 and C28x Cores Cortex-M3 75 MHz 100 MHz 75 MHz 60 MHz C28x 150 MHz 100 MHz 75 MHz 60 MHz www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

5.1 Related Products

For information about other devices in this family of products, see the following link: F28M36x Concerto™ Microcontrollers The F28M3x series of microcontrollers brings together connectivity and control by combining an Arm Cortex-M3 core with the C28x core on to one device. With F28M3x, applications such as solar inverters and industrial control can keep the benefits of separating the communication and control portions while maintaining a single- chip solution. In addition, F28M3x microcontrollers enable safety certifications in your system through enhanced hardware and safety features. The F28M36x family of devices is the second series in the Concerto family. TMS320F2838x Microcontrollers With Connectivity Manager The TMS320F2838x is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed- loop control applications. The F2838x supports a dual-core C28x architecture along with a new Connectivity Manager that offloads critical communication tasks, significantly boosting system performance. The integrated analog and control peripherals with advanced connectivity peripherals like EtherCAT and Ethernet also let designers consolidate real-time control and real-time communications architectures, reducing requirements for multicontroller systems. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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6 Terminal Configuration and Functions

6.1 Pin Diagram

Figure 6-1 shows the 144-pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack pin assignments. 108 2 3 4 5 P A0_GPIO0 GPIO135/COMP5OUT (A) 109 144 1 10 1 1 1 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 120 121 PG5_GPIO45 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 6 7 8 9 10 1 112 13 14 15 16 17 18 19 20 21 22 23 23 24 25 26 27 27 28 29 30 31 32 33 34 35 36 10710610510410310210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 V DD18V DDIO V DDIOXRS P A1_GPIO1P A2_GPIO2P A3_GPIO3P A4_GPIO4 V DDIO V DD12 P A5_GPIO5P A6_GPIO6P A7_GPIO7PB0_GPIO8 FL T1V DDIO PB1_GPIO9PB2_GPIO10PB3_GPIO1 1 FL T2 PE6_GPIO30PE7_GPIO31 V DD12 V DDIO PB6_GPIO14PB7_GPIO15PD2_GPIO18 PD3_GPIO19PB4_GPIO12PB5_GPIO13PE2_GPIO26PE3_GPIO27 V DDIO PH3_GPIO51PH2_GPIO50 PC4_GPIO68 PC5_GPIO69 PC6_GPIO70 PC7_GPIO71 PH0_GPIO48 PH1_GPIO49 PE0_GPIO24 VDDIO PE1_GPIO25 PH4_GPIO52 PH5_GPIO53 PF4_GPIO36 PG0_GPIO40 PG1_GPIO41 PF5_GPIO37 PG7_GPIO47 PJ6_GPIO62 VDDIO VDD12 PJ5_GPIO61 PJ4_GPIO60 VDD12 VDDIO PJ3_GPIO59 PJ2_GPIO58 PJ1_GPIO57 PJ0_GPIO56 PD5_GPIO21 PD4_GPIO20 VDD12 VDDIO PD7_GPIO23 PF6_GPIO38 PG6_GPIO46 PG2_GPIO42 PD6_GPIO22V DDIO V DD12 PE5_GPIO29PE4_GPIO28PG3_GPIO43PH6_GPIO54PH7_GPIO55PF3_GPIO35PF2_GPIO34EMU0TDOTRSTEMU1TMSTDITCKV DD12 NCV DDIO X1V SSOSC X2V DDIO PJ7_GPIO63PD1_GPIO17V DD12 V DDIO VREG12ENPD0_GPIO16PF1_GPIO33PF0_GPIO32V DDIO V DDIO V DDIO V DD18 GPIO134 GPIO133/COMP4OUT GPIO132/COMP3OUT VREG18EN ADC1INB7 ADC1INB4 ADC1INB3 ADC1INB0 VSSA1 VDDA1 ADC1VREFHI ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ADC2INA7 ADC2INA6 ADC2INA4 ADC2INA3 ADC2INA2 ADC2INA0 ADC2VREFHI VDDA2 VSSA2 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 GPIO128 GPIO129/COMP1OUT GPIO130/COMP6OUT GPIO131/COMP2OUT ARS A. All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 8.11. B. See Section 6.2.1, Signal Descriptions, for the complete multiplexed signal names. Figure 6-1. 144-Pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack (Top View) www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

The exposed lead frame die pad of the PowerPAD package serves two functions: to remove heat from the die and to provide ground path for the digital ground (analog ground is provided through dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB because this will provide both the digital ground path and good thermal conduction path. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD package. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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6.2 Signal Descriptions

Section 6.2.1 describes the signals.

6.2.1 Signal Descriptions

TERMINAL(1) I/O/Z (2)

DESCRIPTION

(3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1 ADC1VREFHI 120 I ADC1 External High Reference – used only when in ADC external reference mode. ADC1VREFLO see VSSA1 I ADC1 External Low Reference – used only when in ADC external reference mode. ADC1INA0 121 I ADC1 Group A, Channel 0 input ADC1INA2 122 I ADC1 Group A, Channel 2 input 4 mACOMPA1 I Comparator Input A1 AIO2 I/O Digital AIO2 ADC1INA3 123 I ADC1 Group A, Channel 3 input ADC1INA4 124 I ADC1 Group A, Channel 4 input 4 mACOMPA2 I Comparator Input A2 AIO4 I/O Digital AIO4 ADC1INA6 125 I ADC1 Group A, Channel 6 input 4 mACOMPA3 I Comparator Input A3 AIO6 I/O Digital AIO6 ADC1INA7 126 I ADC1 Group A, Channel 7 input ADC1INB0 117 I ADC1 Group B, Channel 0 input ADC1INB3 116 I ADC1 Group B, Channel 3 input ADC1INB4 115 I ADC1 Group B, Channel 4 input 4 mACOMPB2 I Comparator Input B2 AIO12 I/O Digital AIO12 ADC1INB7 114 I ADC1 Group B, Channel 7 input ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2 ADC2VREFHI 133 I ADC2 External High Reference – used only when in ADC external reference mode. ADC2VREFLO see VSSA2 I ADC2 External Low Reference – used only when in ADC external reference mode. ADC2INA0 132 I ADC2 Group A, Channel 0 input ADC2INA2 131 I ADC2 Group A, Channel 2 input 4 mACOMPA4 I Comparator Input A4 AIO18 I/O Digital AIO18 ADC2INA3 130 I ADC2 Group A, Channel 3 input ADC2INA4 129 I ADC2 Group A, Channel 4 input 4 mACOMPA5 I Comparator Input A5 AIO20 I/O Digital AIO20 ADC2INA6 128 I ADC2 Group A, Channel 6 input 4 mACOMPA6 I Comparator Input A6 AIO22 I/O Digital AIO22 ADC2INA7 127 I ADC2 Group A, Channel 7 input ADC2INB0 136 I ADC2 Group B, Channel 0 input ADC2INB3 137 I ADC2 Group B, Channel 3 input www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. ADC2INB4 138 I ADC2 Group B, Channel 4 input 4 mACOMPB5 I Comparator Input B5 AIO28 I/O Digital AIO28 ADC2INB7 139 I ADC2 Group B, Channel 7 input ADC Modules Analog Power and Ground VDDA1 119 3.3-V Analog Module 1 Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. VDDA2 134 3.3-V Analog Module 2 Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. VSSA1 118 Analog ground for ADC1, ADC1VREFLO, COMP1– 3, and DAC1–3 VSSA2 135 Analog ground for ADC2, ADC2VREFLO, COMP4– 6, and DAC4–6 Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only) GPIO128 140 I/O General-purpose input/output 128 PU 4 mA GPIO129 141 I/O General-purpose input/output 129 PU 4 mA COMP1OUT O Compare result from Analog Comparator 1 GPIO130 142 I/O General-purpose input/output 130 PU 4 mA COMP6OUT O Compare result from Analog Comparator 6 GPIO131 143 I/O General-purpose input/output 131 PU 4 mA COMP2OUT O Compare result from Analog Comparator 2 GPIO132 112 I/O General-purpose input/output 132 PU 8 mA COMP3OUT O Compare result from Analog Comparator 3 GPIO133 111 I/O General-purpose input/output 133 PU 4 mA COMP4OUT O Compare result from Analog Comparator 4 GPIO134 110 I/O General-purpose input/output 134 PU 4 mA GPIO135 (4) 109 I/O General-purpose input/output 135 PU 8 mA COMP5OUT O Compare result from Analog Comparator 5 GPIO Group 1 and Peripheral Signals PA0_GPIO0 I/O/Z General-purpose input/output 0 PU 4 mA M_U0RX I UART-0 receive data M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port M_U1RX I UART-1 receive data C_EPWM1A O Enhanced PWM-1 output A PA1_GPIO1 I/O/Z General-purpose input/output 1 PU 4 mA M_U0TX O UART-0 transmit data M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port M_U1TX O UART-1 data transmit M_SSI1FSS I/O SSI-1 frame C_EPWM1B O Enhanced PWM-1 output B C_ECAP6 I/O Enhanced Capture-6 input/output PA2_GPIO2 I/O/Z General-purpose input/output 2 PU 4 mA M_SSI0CLK I/O SSI-0 clock M_MIITXD2 O EMAC MII transmit data bit 2 C_EPWM2A O Enhanced PWM-2 output A F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PA3_GPIO3 I/O/Z General-purpose input/output 3 PU 4 mA M_SSI0FSS I/O SSI-0 frame M_MIITXD1 O EMAC MII transmit data bit 1 M_SSI1CLK I/O SSI-1 clock C_EPWM2B O Enhanced PWM-2 output B C_ECAP5 I/O Enhanced Capture-5 input/output PA4_GPIO4 I/O/Z General-purpose input/output 4 PU 4 mA M_SSI0RX I SSI-0 receive data M_MIITXD0 O EMAC MII transmit data bit 0 M_CAN0RX I CAN-0 receive data C_EPWM3A O Enhanced PWM-3 output A PA5_GPIO5 I/O/Z General-purpose input/output 5 PU 4 mA M_SSI0TX O SSI-0 transmit data M_MIIRXDV I EMAC MII receive data valid M_CAN0TX O CAN-0 transmit data C_EPWM3B O Enhanced PWM-3 output B C_MFSRA I McBSP-A receive frame sync C_ECAP1 I/O Enhanced Capture-1 input/output PA6_GPIO6 I/O/Z General-purpose input/output 6 PU 4 mA M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port M_CCP1 I/O Capture/Compare/PWM-1 (General-purpose Timer) M_MIIRXCK I EMAC MII receive clock M_CAN0RX I CAN-0 receive data M_USB0EPEN O USB-0 external power enable (optionally used in host mode) M_MIITXD3 O EMAC MII transmit data bit 3 C_EPWM4A O Enhanced PWM-4 output A C_EPWMSYNCO O Enhanced PWM-4 external sync pulse PA7_GPIO7 I/O/Z General-purpose input/output 7 PU 4 mA M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port M_CCP4 I/O Capture/Compare/PWM-4 (General-purpose Timer) M_MIIRXER I EMAC MII receive error M_CAN0TX O CAN-0 transmit data M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_MIIRXD1 I EMAC MII receive data 1 C_EPWM4B O Enhanced PWM-4 output B C_MCLKRA I McBSP-A receive clock C_ECAP2 I/O Enhanced Capture-1 input/output www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PB0_GPIO8 I/O/Z General-purpose input/output 8 PU 4 mA M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_U1RX I UART-1 data receive data M_SSI2TX O SSI-2 transmit data M_CAN1TX O CAN-1 transmit data M_U4TX O UART-4 transmit data C_EPWM5A O Enhanced PWM-5 output A C_ADCSOCAO O ADC start-of-conversion A PB1_GPIO9 I/O/Z General-purpose input/output 9 PU 4 mA M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_CCP1 I/O Capture/Compare/PWM-1 (General-purpose Timer) M_U1TX O UART-1 transmit data M_SSI2RX I SSI-2 receive data C_EPWM5B O Enhanced PWM-5 output B C_ECAP3 I/O Enhanced Capture-3 input/output PB2_GPIO10 I/O/Z General-purpose input/output 10 PU 4 mA M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) M_SSI2CLK I/O SSI-2 clock M_CAN1RX I CAN-1 receive data M_U4RX I UART-4 receive data C_EPWM6A O Enhanced PWM-6 output A C_ADCSOCBO O ADC start-of-conversion B PB3_GPIO11 I/O/Z General-purpose input/output 11 PU 4 mA M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_SSI2FSS I/O SSI-2 frame M_U1RX I UART-1 receive data C_EPWM6B O Enhanced PWM-6 output B C_ECAP4 I/O Enhanced Capture-4 input/output PB4_GPIO12 I/O/Z General-purpose input/output 12 PU 4 mA M_U2RX I UART-2 receive data M_CAN0RX I CAN-0 receive data M_U1RX I UART-1 receive data M_EPI0S23 I/O EPI-0 signal 23 M_CAN1TX O CAN-1 transmit data M_SSI1TX O SSI-1 transmit data C_EPWM7A O Enhanced PWM-7 output A F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PB5_GPIO13 I/O/Z General-purpose input/output 13 PU 4 mA M_CCP5 I/O Capture/Compare/PWM-5 (General-purpose Timer) M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_CAN0TX O CAN-0 transmit data M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_U1TX O UART-1 transmit data M_EPI0S22 I/O EPI-0 signal 22 M_CAN1RX I CAN-1 receive data M_SSI1RX I SSI-1 receive data C_EPWM7B O Enhanced PWM-7 output B PB6_GPIO14 I/O/Z General-purpose input/output 14 PU 4 mA M_CCP1 I/O Capture/Compare/PWM-1 (General-purpose Timer) M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) M_CCP5 I/O Capture/Compare/PWM-5 (General-purpose Timer) M_EPI0S37 (5) I/O EPI-0 signal 37 M_MIICRS I EMAC MII carrier sense M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port M_U1TX O UART-1 transmit data M_SSI1CLK I/O SSI-1 clock C_EPWM8A O Enhanced PWM-8 output A PB7_GPIO15 I/O/Z General-purpose input/output 15 PU 4 mA M_EXTNMI I Cortex-M3 external nonmaskable interrupt M_MIIRXD1 I EMAC MII receive data 1 M_EPI0S36 (5) I/O EPI-0 signal 36 M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port M_U1RX I UART-1 receive data M_SSI1FSS I/O SSI-1 frame C_EPWM8B O Enhanced PWM-8 output B www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PD0_GPIO16 102 I/O/Z General-purpose input/output 16 PU 4 mA M_CAN0RX I CAN-0 receive data M_U2RX I UART-2 receive data M_U1RX I UART-1 receive data M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) M_MIIRXDV I EMAC MII receive data valid M_MIIRXD2 I EMAC MII receive data 2 M_SSI0TX O SSI-0 transmit data M_CAN1TX O CAN-1 transmit data M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) C_SPISIMOA I/O SPI-A slave in, master out PD1_GPIO17 I/O/Z General-purpose input/output 17 PU 4 mA M_CAN0TX O CAN-0 transmit data M_U2TX O UART-2 transmit data M_U1TX O UART-1 transmit data M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) M_MIITXER O EMAC MII transmit error M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_MIICOL I EMAC MII collision detect M_SSI0RX I SSI-0 receive data M_CAN1RX I CAN-1 receive data M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) C_SPISOMIA I/O SPI-A master in, slave out PD2_GPIO18 I/O/Z General-purpose input/output 18 PU 4 mA M_U1RX I UART-1 receive data M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) M_CCP5 I/O Capture/Compare/PWM-5 (General-purpose Timer) M_EPI0S20 I/O EPI-0 signal 20 M_SSI0CLK I/O SSI-0 clock M_U1TX O UART-1 transmit data M_CAN0RX I CAN-0 receive data C_SPICLKA I/O SPI-A clock F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PD3_GPIO19 I/O/Z General-purpose input/output 19 PU 4 mA M_U1TX O UART-1 transmit data M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_EPI0S21 I/O EPI-0 signal 21 M_SSI0FSS I/O SSI-0 frame M_U1RX I UART-1 receive data M_CAN0TX O CAN-0 transmit data C_SPISTEA I/O SPI-A slave transmit enable PD4_GPIO20 I/O/Z General-purpose input/output 20 PU 4 mA M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_MIITXD3 O EMAC MII transmit data 3 M_EPI0S19 I/O EPI-0 signal 19 M_U3TX O UART-3 transmit data M_CAN1TX O CAN-1 transmit data C_EQEP1A I Enhanced QEP-1 input A C_MDXA O McBSP-A transmit data PD5_GPIO21 I/O/Z General-purpose input/output 21 PU 6 mA M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_CCP4 I/O Capture/Compare/PWM-4 (General-purpose Timer) M_MIITXD2 O EMAC MII transmit data 2 M_U2RX I UART-2 receive data M_EPI0S28 I/O EPI-0 signal 28 M_U3RX I UART-3 receive data M_CAN1RX I CAN-1 receive data C_EQEP1B I Enhanced QEP-1 input B C_MDRA I McBSP-A receive data PD6_GPIO22 I/O/Z General-purpose input/output 22 PU 6 mA M_MIITXD1 O EMAC MII transmit data 1 M_U2TX O UART-2 transmit data M_EPI0S29 I/O EPI-0 signal 29 M_I2C1SDA I/OD I2C-0 data open-drain bidirectional port M_U1TX O UART-1 transmit data C_EQEP1S I/O Enhanced QEP-1 strobe C_MCLKXA O McBSP-A transmit clock www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PD7_GPIO23 I/O/Z General-purpose input/output 23 PU 6 mA M_CCP1 I/O Capture/Compare/PWM-1 (General-purpose Timer) M_MIITXD0 O EMAC MII transmit data 0 M_EPI0S30 I/O EPI-0 signal 30 M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port M_U1RX I UART-1 receive data C_EQEP1I I/O Enhanced QEP-1 index C_MFSXA O McBSP-A transmit frame sync PE0_GPIO24 I/O/Z General-purpose input/output 24 PU 4 mA M_SSI1CLK I/O SSI-1 clock M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_EPI0S8 I/O EPI-0 signal 8 M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_SSI3TX O SSI-3 transmit data M_CAN0RX I CAN-1 receive data M_SSI1TX O SSI-1 transmit data C_ECAP1 I/O Enhanced Capture-1 input/output C_EQEP2A I Enhanced QEP-2 input A PE1_GPIO25 I/O/Z General-purpose input/output 25 PU 4 mA M_SSI1FSS I/O SSI-1 frame M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) M_EPI0S9 I/O EPI-0 signal 9 M_SSI3RX I SSI-3 receive data M_CAN0TX O CAN-1 transmit data M_SSI1RX O SSI-1 receive data C_ECAP2 I/O Enhanced Capture-2 input/output C_EQEP2B I Enhanced QEP-2 input B PE2_GPIO26 I/O/Z General-purpose input/output 26 PU 4 mA M_CCP4 I/O Capture/Compare/PWM-4 (General-purpose Timer) M_SSI1RX I SSI-1 receive data M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_EPI0S24 I/O EPI-0 signal 24 M_SSI3CLK I/O SSI-3 clock M_U2RX I UART-2 receive data M_SSI1CLK I/O SSI-1 clock C_ECAP3 I/O Enhanced Capture-3 input/output C_EQEP2I I/O Enhanced QEP-2 index F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PE3_GPIO27 I/O/Z General-purpose input/output 27 PU 4 mA M_CCP1 I/O Capture/Compare/PWM-1 (General-purpose Timer) M_SSI1TX O SSI-1 transmit data M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) M_EPI0S25 I/O EPI-0 signal 25 M_SSI3FSS I/O SSI-3 frame M_U2TX O UART-2 transmit data M_SSI1FSS I/O SSI-1 frame C_ECAP4 I/O Enhanced Capture-4 input/output C_EQEP2S I/O Enhanced QEP-2 strobe PE4_GPIO28 I/O/Z General-purpose input/output 28 PU 4 mA M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_U2TX O UART-2 transmit data M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_MIIRXD0 I EMAC MII receive data 0 M_EPI0S34 (5) I/O EPI-0 signal 34 M_U0RX I UART-0 receive data M_EPI0S38 (5) I/O EPI-0 signal 38 M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) C_SCIRXDA I SCI-A receive data PE5_GPIO29 I/O/Z General-purpose input/output 29 PU 4 mA M_CCP5 I/O Capture/Compare/PWM-5 (General-purpose Timer) M_EPI0S35 (5) I/O EPI-0 signal 35 M_MIITXER O EMAC MII transmit error M_U0TX O UART-0 transmit data M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) C_SCITXDA O SCI-A transmit data PE6_GPIO30 I/O/Z General-purpose input/output 30 PU 4 mA M_MIIMDIO I/O EMAC management data input/output M_CAN0RX I CAN-0 receive data C_EPWM9A O Enhanced PWM-9 output A PE7_GPIO31 I/O/Z General-purpose input/output 31 PU 4 mA M_MIIRXD3 I EMAC MII receive data 3 M_CAN0TX O CAN-0 transmit data C_EPWM9B O Enhanced PWM-9 output B www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PF0_GPIO32 104 I/O/Z General-purpose input/output 32 PU 4 mA M_CAN1RX I CAN-1 receive data M_MIIRXCK I EMAC MII receive clock M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port M_TRACED2 O Trace data 2 C_I2CASDA I/OD I2C-A data open-drain bidirectional port C_SCIRXDA I SCI-A receive data C_ADCSOCAO O ADC start-of-conversion A (6) PF1_GPIO33 103 I/O/Z General-purpose input/output 33 PU 4 mA M_CAN1TX O CAN-1 transmit data M_MIIRXER I EMAC MII receive error M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port M_TRACED3 O Trace data 3 C_I2CASCL I/OD I2C-A clock open-drain bidirectional port C_EPWMSYNCO O Enhanced PWM sync out C_ADCSOCBO O ADC start-of-conversion B (6) PF2_GPIO34 I/O/Z General-purpose input/output 34 PU 4 mA M_MIIPHYINTR I EMAC PHY MII interrupt M_EPI0S32 (5) I/O EPI-0 signal 32 M_SSI1CLK I/O SSI-1 clock M_TRACECLK O Trace clock M_XCLKOUT O External output clock C_ECAP1 I/O Enhanced Capture-1 input/output C_SCIRXDA I SCI-A receive data C_XCLKOUT O External output clock Bmode_pin4 I Boot mode pin 4 PF3_GPIO35 I/O/Z General-purpose input/output 35 PU 4 mA M_MIIMDC I EMAC management data clock M_EPI0S33 (5) I/O EPI-0 signal 33 M_SSI1FSS I/O SSI-1 frame M_U0TX O UART-0 transmit data M_TRACED0 O Trace data 0 C_SCITXDA O SCI-A transmit data Bmode_pin3 I Boot mode pin 3 PF4_GPIO36 I/O/Z General-purpose input/output 36 PU 4 mA M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_MIIMDIO I/O EMAC management data input/output M_EPI0S12 I/O EPI-0 signal 12 M_SSI1RX I SSI-1 receive data M_U0RX I UART-0 receive data C_SCIRXDA I SCI-A receive data F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PF5_GPIO37 I/O/Z General-purpose input/output 37 PU 4 mA M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_MIIRXD3 I EMAC MII receive data 3 M_EPI0S15 I/O EPI-0 signal 15 M_SSI1TX O SSI-1 transmit data C_ECAP2 I/O Enhanced Capture-2 input/output PF6_GPIO38 I/O/Z General-purpose input/output 38. If configured as an output, place a capacitor with a value of 56 pF or greater near the pin. If configured as an input, place a series resistor with a value equal to 1 kΩ or greater near the pin. See the F28M35x Concerto™ MCUs Silicon Errata for details. NOTE: For this pin, only the USB0VBUS function is available on silicon revision 0 devices (GPIO and the four other functions listed are not available). PU 4 mA M_USB0VBUS Analog USB0 VBUS power (5-V tolerant) M_CCP1 I/O Capture/Compare/PWM-1 (General-purpose Timer) M_MIIRXD2 I EMAC MII receive data 2 M_EPI0S38 (5) I/O EPI-0 signal 38 PF7_GPIO39 No Pin No Pin General-purpose input/output 39 is not pinned out. PG0_GPIO40 I/O/Z General-purpose input/output 40 PU 4 mA M_U2RX I UART-2 receive data M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) M_EPI0S13 I/O EPI-0 signal 13 M_MIIRXD2 I EMAC MII receive data 2 M_U4RX I UART-4 receive data PG1_GPIO41 I/O/Z General-purpose input/output 41 PU 4 mA M_U2TX O UART-2 transmit data M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port M_EPI0S14 I/O EPI-0 signal 14 M_MIIRXD1 I EMAC MII receive data 1 M_U4TX O UART-4 transmit data PG2_GPIO42 I/O/Z General-purpose input/output 42 PU 4 mA M_USB0DM Analog USB0 data minus M_MIICOL I EMAC MII collision detect M_EPI0S39 (5) I/O EPI-0 signal 39 PG3_GPIO43 I/O/Z General-purpose input/output 43 PU 4 mA M_MIICRS I EMAC MII carrier sense M_MIIRXDV I EMAC MII receive data valid M_TRACED1 O Trace data 1 Bmode_pin1 I Boot mode pin 1 PG4_GPIO44 No Pin No Pin General-purpose input/output 44 is not pinned out. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PG5_GPIO45 I/O/Z General-purpose input/output 45 PU 4 mA M_USB0DP Analog USB0 data plus M_CCP5 I/O Capture/Compare/PWM-5 (General-purpose Timer) M_MIITXEN O EMAC MII transmit enable M_EPI0S40 (5) I/O EPI-0 signal 40 PG6_GPIO46 I/O/Z General-purpose input/output 46. If configured as an output, place a capacitor with a value of 56 pF or greater near the pin. If configured as an input, place a series resistor with a value equal to 1 kΩ or greater near the pin. See the F28M35x Concerto™ MCUs Silicon Errata for details. NOTE: For this pin, only the USB0ID function is available on silicon revision 0 devices (GPIO and the three other functions listed are not available). PU 4 mA M_USB0ID Analog USB0 ID (5-V tolerant) M_MIITXCK I EMAC MII transmit clock M_EPI0S41 (5) I/O EPI-0 signal 41 PG7_GPIO47 I/O/Z General-purpose input/output 47 PU 6 mA M_MIITXER O EMAC MII transmit error M_CCP5 I/O Capture/Compare/PWM-5 (General-purpose Timer) M_EPI0S31 I/O EPI-0 signal 31 Bmode_pin2 I Boot mode pin 2 PH0_GPIO48 I/O/Z General-purpose input/output 48 PU 4 mA M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) M_MIIPHYRST O EMAC PHY MII reset M_EPI0S6 I/O EPI-0 signal 6 M_SSI3TX O SSI-3 transmit data C_ECAP5 I/O Enhanced Capture-5 input/output PH1_GPIO49 I/O/Z General-purpose input/output 49 PU 4 mA M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) M_EPI0S7 I/O EPI-0 signal 7 M_MIIRXD0 I EMAC MII receive data 0 M_SSI3RX I SSI-3 receive data C_ECAP6 I/O Enhanced Capture-6 input/output PH2_GPIO50 I/O/Z General-purpose input/output 50 PU 4 mA M_EPI0S1 I/O EPI-0 signal 1 M_MIITXD3 O EMAC MII transmit data 3 M_SSI3CLK I/O SSI-3 clock C_EQEP1A I Enhanced QEP-1 input A F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PH3_GPIO51 I/O/Z General-purpose input/output 51 PU 4 mA M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) M_EPI0S0 I/O EPI-0 signal 0 M_MIITXD2 O EMAC MII transmit data 2 M_SSI3FSS I/O SSI-3 frame C_EQEP1B I Enhanced QEP-1 input B PH4_GPIO52 I/O/Z General-purpose input/output 52 PU 4 mA M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_EPI0S10 I/O EPI-0 signal 10 M_MIITXD1 O EMAC MII transmit data 1 M_SSI1CLK I/O SSI-1 clock M_U3TX O UART-3 transmit data C_EQEP1S I/O Enhanced QEP-1 strobe PH5_GPIO53 I/O/Z General-purpose input/output 53 PU 4 mA M_EPI0S11 I/O EPI-0 signal 11 M_MIITXD0 O EMAC MII transmit data 0 M_SSI1FSS I/O SSI-1 frame M_U3RX I UART-3 receive data C_EQEP1I I/O Enhanced QEP-1 index PH6_GPIO54 I/O/Z General-purpose input/output 54 PU 4 mA M_EPI0S26 I/O EPI-0 signal 26 M_MIIRXDV I EMAC MII receive data valid M_SSI1RX I SSI-1 receive data M_MIITXEN O EMAC MII transmit enable M_SSI0TX O SSI-0 transmit data C_SPISIMOA I/O SPI-A slave in, master out C_EQEP3A I Enhanced QEP-1 input A PH7_GPIO55 I/O/Z General-purpose input/output 55 PU 4 mA M_MIIRXCK I EMAC MII receive clock M_EPI0S27 I/O EPI-0 signal 27 M_SSI1TX O SSI-1 transmit data M_MIITXCK I EMAC MII transmit clock M_SSI0RX I SSI-0 receive data C_SPISOMIA I/O SPI-A master in, slave out C_EQEP3B I Enhanced QEP-3 input B PJ0_GPIO56 I/O/Z General-purpose input/output 56 PU 4 mA M_MIIRXER I EMAC MII receive error M_EPI0S16 I/O EPI-0 signal 16 M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port M_SSI0CLK I/O SSI-0 clock C_SPICLKA I/O SPI-A clock C_EQEP3S I/O Enhanced QEP-3 strobe www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PJ1_GPIO57 I/O/Z General-purpose input/output 57 PU 4 mA M_EPI0S17 I/O EPI-0 signal 17 M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port M_MIIRXDV I EMAC MII receive data valid M_SSI0FSS I/O SSI-0 frame C_SPISTEA I/O SPI-A slave transmit enable C_EQEP3I I/O Enhanced QEP-3 index PJ2_GPIO58 I/O/Z General-purpose input/output 58 PU 4 mA M_EPI0S18 I/O EPI-0 signal 18 M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_MIIRXCK I EMAC MII receive clock M_SSI0CLK I/O SSI-0 clock M_U0TX O UART-0 transmit data C_MCLKRA I McBSP-A receive clock C_EPWM7A O Enhanced PWM-7 output A PJ3_GPIO59 I/O/Z General-purpose input/output 59 PU 4 mA M_EPI0S19 I/O EPI-0 signal 19 M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) M_MIIMDC O EMAC management data clock M_SSI0FSS I/O SSI-0 frame M_U0RX I UART-0 receive data C_MFSRA I McBSP-A receive frame sync C_EPWM7B O Enhanced PWM-7 output B PJ4_GPIO60 I/O/Z General-purpose input/output 60 PU 6 mA M_EPI0S28 I/O EPI-0 signal 28 M_CCP4 I/O Capture/Compare/PWM-4 (General-purpose Timer) M_MIICOL I EMAC MII collision detect M_SSI1CLK I/O SSI-1 clock C_EPWM8A O Enhanced PWM-8 output A PJ5_GPIO61 I/O/Z General-purpose input/output 61 PU 6 mA M_EPI0S29 I/O EPI-0 signal 29 M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_MIICRS I EMAC MII carrier sense M_SSI1FSS I/O SSI-1 frame C_EPWM8B O Enhanced PWM-8 output B F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PJ6_GPIO62 I/O/Z General-purpose input/output 62 PU 6 mA M_EPI0S30 I/O EPI-0 signal 30 M_CCP1 I/O Capture/Compare/PWM-1 (General-purpose Timer) M_MIIPHYINTR I EMAC PHY MII interrupt M_U2RX I UART-2 receive data C_EPWM9A O Enhanced PWM-9 output A PJ7_GPIO63 I/O/Z General-purpose input/output 63 PU 4 mA M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) M_MIIPHYRST O EMAC PHY MII reset M_U2TX O UART-2 transmit data C_EPWM9B O Enhanced PWM-9 output B PC0_GPIO64 No Pin No Pin General-purpose input/output 64 is not pinned out. PC1_GPIO65 No Pin No Pin General-purpose input/output 65 is not pinned out. PC2_GPIO66 No Pin No Pin General-purpose input/output 66 is not pinned out. PC3_GPIO67 No Pin No Pin General-purpose input/output 67 is not pinned out. PC4_GPIO68 I/O/Z General-purpose input/output 68 PU 4 mA M_CCP5 I Capture/Compare/PWM-5 (General-purpose Timer) M_MIITXD3 O EMAC MII transmit data 3 M_CCP2 I Capture/Compare/PWM-2 (General-purpose Timer) M_CCP4 I Capture/Compare/PWM-4 (General-purpose Timer) M_EPI0S2 I/O EPI-0 signal 2 M_CCP1 I Capture/Compare/PWM-1 (General-purpose Timer) PC5_GPIO69 I/O/Z General-purpose input/output 69 PU 4 mA M_CCP1 I Capture/Compare/PWM-1 (General-purpose Timer) M_CCP3 I Capture/Compare/PWM-3 (General-purpose Timer) M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) M_EPI0S3 I/O EPI-0 signal 3 PC6_GPIO70 I/O/Z General-purpose input/output 70 PU 4 mA M_CCP3 I Capture/Compare/PWM-3 (General-purpose Timer) M_U1RX I UART-1 receive data M_CCP0 I Capture/Compare/PWM-0 (General-purpose Timer) M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_EPI0S4 I/O EPI-0 signal 4 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. PC7_GPIO71 I/O/Z General-purpose input/output 71 PU 4 mA M_CCP4 I Capture/Compare/PWM-4 (General-purpose Timer) M_CCP0 I Capture/Compare/PWM-0 (General-purpose Timer) M_U1TX O UART-1 transmit data M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_EPI0S5 I/O EPI-0 signal 5 Resets XRS 4 I/OD Digital Subsystem Reset (in) and Watchdog/ Power-on Reset (out). In most applications, TI recommends that the XRS pin be tied with the ARS pin. The Digital Subsystem has a built-in POR circuit, and during a power-on condition, this pin is driven low by the Digital Subsystem. This pin is also driven low by the Digital Subsystem when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If needed, an external circuitry may also drive this pin to assert device reset. In this case, this pin should be driven by an open-drain device. A noise filtering circuit can be connected to this pin. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the Digital Subsystem to terminate execution. The Cortex-M3 program counter points to the address contained at the location 0x00000004. The C28 program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. PU 4 mA ARS 144 I/OD Analog Subsystem Reset (in) and Power-on Reset (out). TI recommends that the ARS pin be tied with the XRS pin. The Analog Subsystem has a built- in POR circuit, and during a power-on condition, this pin is driven low by the Analog Subsystem. If needed, an external circuitry may also drive this pin to assert a device reset. In this case, TI recommends that this pin be driven by an open-drain device. Regardless of the source, the Analog Subsystem reset causes the digital logic associated with the Analog Subsystem, to enter reset state. The output buffer of this pin is an open-drain with an internal pullup. PU 4 mA Clocks X1 93 I External oscillator input or on-chip crystal-oscillator input. To use the on-chip oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. See Figure 8-7. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. X2 95 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. See Figure 8-7. VSSOSC 94 Clock Oscillator Ground Pin. Use this pin to connect the GND of external crystal load capacitors or the ground pin of 3-terminal ceramic resonators with built-in capacitors. Do not connect to board ground. See Figure 8-7. XCLKIN see PJ7_GPIO63 I External oscillator input. This pin feeds a clock from an external 3.3-V oscillator to internal USB PLL module and to the CAN peripherals. XCLKOUT see PF2_GPIO34 O/Z External oscillator output. This pin outputs a clock divided-down from the internal PLL System Clock. The divide ratio is defined in the XPLLCLKCFG register. Boot Pins Bmode_pin1 see PG3_GPIO43 I One of four boot mode pins. Bmode_pin1 selects a specific configuration source from which the Concerto device boots on start-up. PU Bmode_pin2 see PG7_GPIO47 I One of four boot mode pins. Bmode_pin2 selects a specific configuration source from which the Concerto device boots on start-up. PU Bmode_pin3 see PF3_GPIO35 I One of four boot mode pins. Bmode_pin3 selects a specific configuration source from which the Concerto device boots on start-up. PU Bmode_pin4 see PF2_GPIO34 I One of four boot mode pins. Bmode_pin4 selects a specific configuration source from which the Concerto device boots on start-up. PU JTAG TRST 85 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active-low test pin and must be maintained low during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. PD TCK 89 I JTAG test clock TMS 87 I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. PU TDI 88 I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. PU TDO 84 O JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. 4 mA www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. EMU0 83 I/O/Z Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7- kΩ resistor is generally adequate. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the JTAG debug probe to connect to the device and to modify FLASH contents. PU 4 mA EMU1 86 I/O/Z Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7- kΩ resistor is generally adequate. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the JTAG debug probe to connect to the device and to modify FLASH contents. PU 4 mA ITM Trace (Arm Instrumentation Trace Macrocell) TRACED0 see PF3_GPIO35 O ITM Trace data 0 4 mA TRACED1 see PG3_GPIO43 O ITM Trace data 1 4 mA TRACED2 see PF0_GPIO32 O ITM Trace data 2 4 mA TRACED3 see PF1_GPIO33 O ITM Trace data 3 4 mA TRACECLK see PF2_GPIO34 O ITM Trace clock 4 mA F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. Test Pins FLT1 16 I/O FLASH Test Pin 1. Reserved for TI. Must be left unconnected. FLT2 21 I/O FLASH Test Pin 2. Reserved for TI. Must be left unconnected. Internal Voltage Regulator Control VREG18EN 113 Internal 1.8-V VREG Enable/Disable for VDD18. Pull low to enable the internal 1.8-V voltage regulator (VREG18), pull high to disable VREG18. PD VREG12EN 101 Internal 1.2-V VREG Enable/Disable for VDD12. Pull low to enable the internal 1.2-V voltage regulator (VREG12), pull high to disable VREG12. PD Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators VDDIO 107 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. When the 1.2-V VREG is enabled (by pulling the VREG12EN pin low), these pins also supply power to the Digital Subsystem. When the 1.8-V VREG is enabled (by pulling the VREG18EN pin low), these pins also supply power to the Analog Subsystem. VDDIO 10 VDDIO 25 VDDIO 34 VDDIO 44 VDDIO 54 VDDIO 59 VDDIO 105 VDDIO 3 VDDIO 67 VDDIO 74 VDDIO 92 VDDIO 100 VDDIO 96 VDDIO 17 VDDIO 2 VDDIO 106 Digital Logic Power Pins (Analog Subsystem) VDD18 1 1.8-V Digital Logic Power Pins (associated with the Analog Subsystem) - no supply needed when using internal VREG18. Tie with 1.2-µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time. VDD18 108 Digital Logic Power Pins (Master and Control Subsystems) VDD12 24 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 250-nF (minimum) to 750-nF (maximum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time. VDD12 55 VDD12 66 VDD12 99 VDD12 75 VDD12 58 VDD12 11 VDD12 90 Digital Logic Ground (Analog, Master, and Control Subsystems) www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TERMINAL(1) I/O/Z (2) (3) OUTPUT BUFFER STRENGTHNAME RFP PIN NO. VSS PWR PAD Digital Ground Power Pad (located on the bottom of the chip) No Connect Pins NC 91 This pin is a "no connect" (that is, this pin is not connected to any circuitry internal to the device). (1) Throughout this table, Master Subsystem signals are denoted by the color blue; Control Subsystem signals are denoted by the color green; and Analog Subsystem signals are denoted by the color orange. (2) I = Input, O = Output, Z = High Impedance, OD = Open Drain (3) PU = Pullup, PD = Pulldown

• GPIO_MUX1 pullups can be enabled or disabled by Cortex-M3 software (disabled on reset).
• GPIO_MUX2 pullups can be enabled or disabled by C28x software (disabled on reset).
• AIO_MUX1 and AIO_MUX2 terminals do not have pullups or pulldowns.
• All other pullups are always enabled ( XRS, ARS, TMS, TDI, EMU0, EMU1).
• All pulldowns are always enabled ( VREG18EN, VREG12EN, TRST). (4) All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 8.11. (5) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. (6) Output from the Concerto ePWM is meant for the external ADC (if present). F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Supply voltage VDDIO (I/O and Flash) with respect to VSS –0.3 4.6 VVDD18 with respect to VSS –0.3 2.5 VDD12 with respect to VSS –0.3 1.5 Analog voltage VDDA with respect to VSSA –0.3 4.6 V Input voltage VIN (3.3 V) –0.3 4.6 V Output voltage VO –0.3 4.6 V Supply ramp rate VDDIO, VDD18, VDD12, VDDA with respect to VSS 105 V/s Input clamp current IIK (VIN < 0 or VIN > VDDIO)(3) –20 20 mA Output clamp current IOK (VO < 0 or VO > VDDIO) –20 20 mA Free-Air temperature TA –40 125 °C Junction temperature(4) TJ –40 150 °C Storage temperature(4) Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ±2 mA. (4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see Semiconductor and IC Package Thermal Metrics.

7.2 ESD Ratings – Automotive

F28M35H52C in 144-pin RFP package V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) All pins ±2000 V Charged device model (CDM), per AEC Q100-011 All pins ±500 Corner pins on 144-pin RFP: 1, 36, 37, 72, 73, 108, 109, 144 ±750 (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 ESD Ratings – Commercial

F28M35H52C, F28M35H22C, F28M35M52C, F28M35M22C, F28M35E20B in 144-pin RFP package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.4 Recommended Operating Conditions

Device supply voltage, I/O, VDDIO (1) 2.97 3.3 3.63 V Device supply voltage, Analog Subsystem, VDD18 (when internal VREG is disabled and 1.8 V is supplied externally) 1.71 1.8 1.995 V Device supply voltage, Master and Control Subsystems, VDD12 (when internal VREG is disabled and 1.2 V is supplied externally) 1.14 1.2 1.32 V Supply ground, VSS 0 V Analog supply voltage, VDDA (1) 2.97 3.3 3.63 V Analog ground, VSSA 0 V Device clock frequency (system clock) Master Subsystem H52C, H22C 2 100 MHzM52C, M22C 2 75 E20B 2 60 Device clock frequency (system clock) Control Subsystem H52C, H22C 2 150 MHzM52C, M22C 2 75 E20B 2 60 Junction temperature, TJ T version –40 105 °CS version(2) –40 125 Q version (AEC Q100 qualification)(2) –40 150 Free-Air temperature, TA Q version (AEC Q100 qualification) –40 125 °C (1) VDDIO and VDDA should be maintained within approximately 0.3 V of each other. (2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded Processors for more information. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.5 Power Consumption Summary

7.5.1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK

VREG ENABLED VREG DISABLED IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX Operational (1) (RAM) The following Cortex-M3 peripherals are exercised:

• I2C1
• SSI1, SSI2
• UART0, UART1, UART2
• CAN0
• USB
• µDMA
• Timer0, Timer1
• µCRC
• WDOG0, WDOG1
• Flash
• Internal Oscillator 1, Internal Oscillator 2 The following C28x peripherals are exercised:
• McBSP
• eQEP1, eQEP2
• eCAP1, eCAP2, eCAP3, eCAP4
• SCI-A
• SPI-A
• I2C
• DMA
• VCU
• FPU
• Flash The following Analog peripherals are exercised:
• ADC1, ADC2
• Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 – 325 mA – 40 mA – 25 mA – 225 mA – 65 mA – 40 mA SLEEP IDLE
• PLL is on.
• Cortex-M3 CPU is not executing.
• M3SSCLK is on.
• C28CLKIN is on.
• C28x CPU is not executing.
• C28CPUCLK is off.
• C28SYSCLK is on. – 146 mA – 2 mA – 20 mA – 110 mA – 11 mA – 2 mA www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

VREG ENABLED VREG DISABLED IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX SLEEP STANDBY

• PLL is on.
• Cortex-M3 CPU is not executing.
• M3SSCLK is on.
• C28CLKIN is off.
• C28x CPU is not executing.
• C28CPUCLK is off.
• C28SYSCLK is off. – 126 mA – 2 mA – 20 mA – 90 mA – 11 mA – 2 mA DEEP SLEEP STANDBY
• PLL is off.
• Cortex-M3 CPU is not executing.
• M3SSCLK is 32 kHz.
• C28CLKIN is off.
• C28x CPU is not executing.
• C28CPUCLK is off.
• C28SYSCLK is off. – 76 mA – 2 mA – 5 mA – 60 mA – 7 mA – 2 mA (1) The following is done in a loop:
• Code is running out of RAM.
• All I/O pins are left unconnected.
• All the communication peripherals are exercised in loop-back mode.
• USB – Only logic is exercised by loading and unloading FIFO.
• µDMA does memory-to-memory transfer.
• DMA does memory-to-memory transfer.
• VCU – CRC calculated and checked.
• FPU – Float operations performed.
• ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
• Timers and Watchdog serviced.
• eCAP in APWM mode generates 36.6-kHz output on 4 pins.
• ADC performs continuous conversion.
• FLASH is continuously read and in active state.
• XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.5.2 Current Consumption at 100-MHz C28x SYSCLKOUT and 100-MHz M3SSCLK

VREG ENABLED VREG DISABLED IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX Operational (1) (RAM) The following Cortex-M3 peripherals are exercised:

• I2C1
• SSI1, SSI2
• UART0, UART1, UART2
• CAN0
• USB
• µDMA
• Timer0, Timer1
• µCRC
• WDOG0, WDOG1
• Flash
• Internal Oscillator 1, Internal Oscillator 2 The following C28x peripherals are exercised:
• McBSP
• eQEP1, eQEP2
• eCAP1, eCAP2, eCAP3, eCAP4
• SCI-A
• SPI-A
• I2C
• DMA
• VCU
• FPU
• Flash The following Analog peripherals are exercised:
• ADC1, ADC2
• Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 – 295 mA – 40 mA – 20 mA – 200 mA – 65 mA – 40 mA (1) The following is done in a loop:
• Code is running out of RAM.
• All I/O pins are left unconnected.
• All the communication peripherals are exercised in loop-back mode.
• USB – Only logic is exercised by loading and unloading FIFO.
• µDMA does memory-to-memory transfer.
• DMA does memory-to-memory transfer.
• VCU – CRC calculated and checked.
• FPU – Float operations performed.
• ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
• Timers and Watchdog serviced.
• eCAP in APWM mode generates 36.6-kHz output on 4 pins.
• ADC performs continuous conversion.
• FLASH is continuously read and in active state. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

• XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.5.3 Current Consumption at 75-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK

VREG ENABLED VREG DISABLED IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX Operational (1) (RAM) The following Cortex-M3 peripherals are exercised:

• I2C1
• SSI1, SSI2
• UART0, UART1, UART2
• CAN0
• USB
• µDMA
• Timer0, Timer1
• µCRC
• WDOG0, WDOG1
• Flash
• Internal Oscillator 1, Internal Oscillator 2 The following C28x peripherals are exercised:
• McBSP
• eQEP1, eQEP2
• eCAP1, eCAP2, eCAP3, eCAP4
• SCI-A
• SPI-A
• I2C
• DMA
• VCU
• FPU
• Flash The following Analog peripherals are exercised:
• ADC1, ADC2
• Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 – 275 mA – 40 mA – 25 mA – 175 mA – 65 mA – 40 mA (1) The following is done in a loop:
• Code is running out of RAM.
• All I/O pins are left unconnected.
• All the communication peripherals are exercised in loop-back mode.
• USB – Only logic is exercised by loading and unloading FIFO.
• µDMA does memory-to-memory transfer.
• DMA does memory-to-memory transfer.
• VCU – CRC calculated and checked.
• FPU – Float operations performed.
• ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
• Timers and Watchdog serviced.
• eCAP in APWM mode generates 36.6-kHz output on 4 pins.
• ADC performs continuous conversion.
• FLASH is continuously read and in active state. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

• XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.5.4 Current Consumption at 60-MHz C28x SYSCLKOUT and 60-MHz M3SSCLK

VREG ENABLED VREG DISABLED IDDIO (2) IDDA IDD18 IDD12 IDDIO (2) IDDA TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX Operational (1) (RAM) The following Cortex-M3 peripherals are exercised:

• I2C1
• SSI1, SSI2
• UART0, UART1, UART2
• CAN0
• USB
• µDMA
• Timer0, Timer1
• µCRC
• WDOG0, WDOG1
• Flash
• Internal Oscillator 1, Internal Oscillator 2 The following C28x peripherals are exercised:
• McBSP
• eQEP1, eQEP2
• eCAP1, eCAP2, eCAP3, eCAP4
• SCI-A
• SPI-A
• I2C
• DMA
• VCU
• FPU
• Flash The following Analog peripherals are exercised:
• ADC1, ADC2
• Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 – 250 mA – 40 mA – 20 mA – 155 mA – 65 mA – 40 mA (1) The following is done in a loop:
• Code is running out of RAM.
• All I/O pins are left unconnected.
• All the communication peripherals are exercised in loop-back mode.
• USB – Only logic is exercised by loading and unloading FIFO.
• µDMA does memory-to-memory transfer.
• DMA does memory-to-memory transfer.
• VCU – CRC calculated and checked.
• FPU – Float operations performed.
• ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
• Timers and Watchdog serviced.
• eCAP in APWM mode generates 36.6-kHz output on 4 pins.
• ADC performs continuous conversion.
• FLASH is continuously read and in active state. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

• XCLKOUT is turned off. (2) IDDIO current is dependent on the electrical loading on the I/O pins. Note The peripheral-I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If the clocks to all the peripherals are turned on at the same time, the current drawn by the device will be more than the numbers specified in the current consumption tables F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Low-level input voltage (3.3 V) VSS – 0.3 VDDIO * 0.3 V VIH High-level input voltage (3.3 V) VDDIO * 0.7 VDDIO + 0.3 V VOL Low-level output voltage IOL = IOL MAX VDDIO * 0.2 V VOH High-level output voltage IOH = IOH MAX VDDIO * 0.8 V IOH = 50 μA VDDIO – 0.2 IIL Input current (low level) Pin with pullup enabled VDDIO = 3.3 V, VIN = 0 V All GPIO pins –50 –230 μA XRS pin –50 –230 ARS pin –100 –400 Pin with pulldown enabled VDDIO = 3.3 V, VIN = 0 V ±2(1) IIH Input current (high level) Pin with pullup enabled VDDIO = 3.3 V, VIN = VDDIO ±2(1) μA Pin with pulldown enabled VDDIO = 3.3 V, VIN = VDDIO 50 200 IOL Low-level output sink current, VOL = VOL(MAX) All GPIO/AIO pins 4 mA Group 2(2) 8 IOH High-level output source current, VOH = VOH(MIN) All GPIO/AIO pins –4 mA Group 2(2) –8 IOZ Output current, pullup or pulldown disabled VO = VDDIO or 0 V ±2(1) μA CI Input capacitance 2 pF Digital Subsystem POR reset release delay time Time after POR event is removed to XRS release 50 µs Analog Subsystem POR reset release delay time Time after POR event is removed to ARS release 400 800 µs VREG VDD18 output Internal VREG18 on 1.77 1.935 V VREG VDD12 output Internal VREG12 on 1.2 V (1) For GPIO38 and GPIO46 (USB OTG pins), this parameter is ±8 µA. (2) Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1, PD0_GPIO16, AIO7, AIO4. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.7 Thermal Resistance Characteristics for RFP PowerPAD Package

°C/W(1) AIR FLOW (lfm)(2) RΘJC Junction-to-case thermal resistance 6.3 0 RΘJB Junction-to-board thermal resistance 4.4 0 RΘJA (High k PCB) Junction-to-free air thermal resistance 18.8 0 11.5 150 10.0 250 8.6 500 PsiJT Junction-to-package top 0.3 0 0.2 150 0.3 250 0.3 500 PsiJB Junction-to-board 4.8 0 4.6 150 4.5 250 4.4 500 (1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements (2) lfm = linear feet per minute

7.8 Thermal Design Considerations

Based on the end-application design and operational profile, the I DD12, I DD18, and I DDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (T A) varies with the end application and product design. The critical factor that affects reliability and functionality is T J, the junction temperature, not the ambient temperature. Hence, care should be taken to keep T J within the specified limits. T case should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. For more details about thermal metrics and definitions, see Semiconductor and IC Package Thermal Metrics. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9 Timing and Switching Characteristics

7.9.1 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO135, are glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above V DDIO should be applied to any digital pin (for analog pins, this value is 0.7 V above V DDA) before powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. V V (3.3 V) DDIO DDA, VDD12, VDD18 th(boot-mode)(C) X1/X2 XRS (D) Boot-Mode Pins XCLKOUT I/O Pins User-code dependent User-code dependent Boot-ROM execution starts Peripheral/GPIO function Based on boot code GPIO pins as input GPIO pins as input (state depends on internal PU/PD) tOSCST User-code dependent Address/Data/ Control (Internal) Address/data valid, internal boot-ROM code execution phase User-code execution phasetd(EX) tw(RSL2) tw(RSL1) (A) (B) Figure 7-1. Power-On Reset A. Upon power up, PLLSYSCLK is OSCCLK/8. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32 during this phase. B. Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at the pin until explicitly configured by user code. C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled. D. The XRS pin will be driven low by on-chip POR circuitry until the VDDIO voltage crosses the POR threshold. (The POR threshold is lower than the operating voltage requirement.) To allow the external clock to stabilize, the XRS pin may also need to be driven low by the system for additional time. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.1.1 Reset ( XRS) Timing Requirements

th(boot-mode) (1) Hold time for boot-mode pins 14000tc(M3C) cycles tw(RSL2) Pulse duration, XRS low 32tc(OCK) cycles (1) The minimum hold time for boot mode pins is 23 times longer for silicon revision 0 devices.

7.9.1.2 Reset ( XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulse duration, XRS driven by device 600 μs tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OCK) cycles td(EX) Delay time, address/data valid after XRS high 32tc(OCK) cycles tINTOSCST Start-up time, internal zero-pin oscillator 3 μs tOSCST (1) On-chip crystal-oscillator start-up time 2 ms (1) Dependent on crystal/resonator and board design. th(boot-mode)(A) tw(RSL2) X1/X2 XRS Boot-Mode Pins XCLKOUT I/O Pins Address/Data/ Control (Internal) Boot-ROM Execution Starts User-Code Execution Starts User-Code Dependent User-Code Execution Phase User-Code Dependent User-Code Execution Peripheral/GPIO Function User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) GPIO Pins as Input Peripheral/GPIO Function td(EX) A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled. Figure 7-2. Warm Reset

7.9.1.3 Power Management and Supervisory Circuit Solutions

LDO selection depends on the total power consumed in the end application. Go to the Power management product folder to select a device and to access reference designs, technical documents, support and training. The Power management guide is also available for download. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.2 Clock Specifications

This section provides the frequencies and timing requirements of the input clocks; PLL lock times; frequencies of the internal clocks; and the frequency and switching characteristics of the output clock.

7.9.2.1 Changing the Frequency of the Main PLL

When configuring the PLL, it should be locked twice in a row. The PLL will be ready to use in the system when the xPLLSTS[xPLLLOCKS] bit is set after the second lock. The SysCtlClockPllConfig () function in sysctl.c, found in controlSUITE™, may be referenced as an example of a proper PLL initialization sequence. For additional information, see the "Clock Control" section of the Concerto F28M35x Technical Reference Manual.

7.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times

X1 or X1/X2 input clock pins, and the USB PLL operates from the XCLKIN input clock pin.

7.9.2.2.1 Input Clock Frequency

f(OSC) Frequency, X1/X2, from external crystal or resonator 2 20 MHz f(OCI) Frequency, X1, from external oscillator (PLL enabled) 2 30 MHz f(OCI) Frequency, X1, from external oscillator (PLL disabled) 2 100 MHz f(XCI) Frequency, XCLKIN, from external oscillator 2 60 MHz Table 7-1. Crystal Equivalent Series Resistance (ESR) Requirements CRYSTAL FREQUENCY (MHz) (1) MAXIMUM ESR (Ω) (CL1/2 = 12 pF) MAXIMUM ESR (Ω) (CL1/2 = 24 pF) 2 175 375 4 100 195 6 75 145 8 65 120 10 55 110 12 50 95 14 50 90 16 45 75 18 45 65 20 45 50 (1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.

7.9.2.2.2 Crystal Oscillator Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Start-up time(1) f = 20 MHz; ESR MAX = 50 Ω; CL1 = CL2 = 24 pF, C0 = 7 pF 2 ms (1) Start-up time is dependent on the crystal and tank circuit components. It is recommended that the crystal vendor characterize the application with the chosen crystal. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.2.2.3 X1 Timing Requirements - PLL Enabled(1)

tf(OCI) Fall time, X1 6 ns tr(OCI) Rise time, X1 6 ns tw(OCL) Pulse duration, X1 low as a percentage of tc(OCI) 45% 55% tw(OCH) Pulse duration, X1 high as a percentage of tc(OCI) 45% 55% (1) The possible Main PLL configuration modes are shown in Table 8-19 to Table 8-22.

7.9.2.2.4 X1 Timing Requirements - PLL Disabled

tf(OCI) Fall time, X1 Up to 20 MHz 6 ns

20 MHz to 100 MHz 2

tr(OCI) Rise time, X1 Up to 20 MHz 6 ns tw(OCL) Pulse duration, X1 low as a percentage of tc(OCI) 45% 55% tw(OCH) Pulse duration, X1 high as a percentage of tc(OCI) 45% 55%

7.9.2.2.5 XCLKIN Timing Requirements - PLL Enabled

MIN(1) MAX UNIT tf(XCI) Fall time, XCLKIN 6 ns tr(XCI) Rise time, XCLKIN 6 ns tw(XCL) Pulse duration, XCLKIN low as a percentage of tc(XCI) 45% 55% tw(XCH) Pulse duration, XCLKIN high as a percentage of tc(XCI) 45% 55% (1) The possible USB PLL configuration modes are shown in Table 8-23 and Table 8-24.

7.9.2.2.6 XCLKIN Timing Requirements - PLL Disabled

tf(XCI) Fall time, XCLKIN Up to 20 MHz 6 ns tr(XCI) Rise time, XCLKIN Up to 20 MHz 6 ns tw(XCL) Pulse duration, XCLKIN low as a percentage of tc(XCI) 45% 55% tw(XCH) Pulse duration, XCLKIN high as a percentage of tc(XCI) 45% 55%

7.9.2.2.7 PLL Lock Times

t(PLL) Lock time, Main PLL (X1, from external oscillator) 2000(1) input clock cycles t(USB) Lock time, USB PLL (XCLKIN, from external oscillator) 2000(1) input clock cycles (1) For example, if the input clock to the PLL is 10 MHz, then a single PLL lock time is 100 ns × 2000 = 200 µs. This defines the time of a single write to the PLL configuration registers until the xPLLSTS[xPLLLOCKS] bit is set. The PLL should be locked twice to ensure a good PLL output frequency is present. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.2.3 Output Clock Frequency and Switching Characteristics

the switching characteristics of the output clock from the F28M35x devices, XCLKOUT.

7.9.2.3.1 Output Clock Frequency

f(XCO) Frequency, XCLKOUT 2 37.5 MHz

7.9.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tf(XCO) Fall time, XCLKOUT 5 ns tr(XCO) Rise time, XCLKOUT 5 ns tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns (1) A load of 40 pF is assumed for these parameters. (2) H = 0.5tc(XCO)

7.9.2.4 Internal Clock Frequencies

Section 7.9.2.4 provides the clock frequencies for the internal clocks of the F28M35x devices.

7.9.2.4.1 Internal Clock Frequencies (150-MHz Devices)

f(USB) Frequency, USBPLLCLK 60 MHz f(PLL) Frequency, PLLSYSCLK 2 150 MHz f(OCK) Frequency, OSCCLK 2 100 MHz f(M3C) Frequency, M3SSCLK 2 100(1) MHz f(ADC) Frequency, ASYSCLK 2 37.5 MHz f(SYS) Frequency, C28SYSCLK 2 150(1) MHz f(HSP) Frequency, C28HSPCLK 2 150(1) MHz f(LSP) Frequency, C28LSPCLK(2) 2 37.5(3) 150(1) MHz f(10M) Frequency, 10MHzCLK 10 MHz f(32K) Frequency, 32KHzCLK 32 kHz (1) An integer divide ratio must be maintained between the C28x and Cortex-M3 clock frequencies. For example, when the C28x is configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 will be 75 MHz. See Figure 8-10 and Figure 8-12 to see the internal clocks and clock divider options. (2) Lower LSPCLK will reduce device power consumption. (3) This is the default reset value if C28SYSCLK = 150 MHz. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.3 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width)

7.9.3.1 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document.

7.9.3.2 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document. Z0 = 50 /c87 (A) TD = 6 ns OUTPUT UNDER TEST 20 pF 15 /c8725 /c87 DEVICE PIN (B) DATA SHEET TIMING REFERENCE POINT TESTER PIN ELECTRONICS CONCERTO DEVICE TRANSMISSION LINE 20 pF A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 7-3. 3.3-V Test Load Circuit F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.4 Flash Timing – Master Subsystem

7.9.4.1 Master Subsystem – Flash/OTP Endurance

Nf Flash endurance for the array (write/erase cycles) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 1 write

7.9.4.2 Master Subsystem – Flash Parameters

PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT Program Time(2) 128 data bits + 16 ECC bits 40 300 µs 16K sector 160 320 ms 64K sector 640 1280 ms Erase Time(3) at < 25 cycles 16K sector 25 50 ms 64K sector 35 60 Erase Time(3) at 50k cycles 16K sector 115 4000 ms 64K sector 130 4000 IDDP (4) (5) VDD current consumption during Erase/Program cycle VREG disabled 105 mA IDDIOP (4) (5) VDDIO current consumption during Erase/Program cycle 55 IDDIOP (4) (5) VDDIO current consumption during Erase/Program cycle VREG enabled 195 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Program time includes overhead of the Flash state machine but does not include the time to transfer the following into RAM:

• Code that uses Flash API to program the Flash
• Flash API itself
• Flash data to be programmed In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used. Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does. Erase time includes Erase verify by the CPU and does not involve any data transfer. (3) Erase time includes Erase verify by the CPU. (4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (5) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral.

7.9.4.3 Master Subsystem – Flash/OTP Access Timing

PARAMETER(1) MIN MAX UNIT ta(f) Flash access time 25 ns ta(OTP) OTP access time 50 ns (1) Access time numbers shown in this table are before device characterization. Final numbers will be published in the data sheet for the fully qualified production device.

7.9.4.4 Master Subsystem – Flash Data Retention Duration

PARAMETER TEST CONDITIONS MIN MAX UNIT tretention Data retention duration TJ = 85°C 20 years www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.4.5 Master Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies

SYSCLKOUT (MHz) SYSCLKOUT (ns) WAIT STATE 100 10 2 90 11.11 2 80 12.5 1 70 14.29 1 60 16.67 1 50 20 1 40 25 0 30 33.33 0 20 50 0 10 100 0 The equation to compute the Flash wait state in Section 7.9.4.5 is as follows: RWAIT 1= SYSCLK (MHz) 40 (MHz) round up to the next integer, or 1, whichever is larger. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.5 Flash Timing – Control Subsystem

7.9.5.1 Control Subsystem – Flash/OTP Endurance

Nf Flash endurance for the array (write/erase cycles) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 1 write

7.9.5.2 Control Subsystem – Flash Parameters

PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT Program Time(2) 128 data bits + 16 ECC bits 40 300 µs 16K sector 120 240 ms 64K sector 480 960 ms Erase Time(3) at < 25 cycles 16K sector 25 50 ms 64K sector 35 60 Erase Time(3) at 50k cycles 16K sector 105 4000 ms 64K sector 120 4000 IDDP (4) (5) VDD current consumption during Erase/Program cycle VREG disabled mA IDDIOP (4) (5) VDDIO current consumption during Erase/Program cycle 55 IDDIOP (4) (5) VDDIO current consumption during Erase/Program cycle VREG enabled 150 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Program time includes overhead of the Flash state machine but does not include the time to transfer the following into RAM:

• Code that uses Flash API to program the Flash
• Flash API itself
• Flash data to be programmed In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used. Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does. Erase time includes Erase verify by the CPU and does not involve any data transfer. (3) Erase time includes Erase verify by the CPU. (4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. (5) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral.

7.9.5.3 Control Subsystem – Flash/OTP Access Timing

PARAMETER(1) MIN MAX UNIT ta(f) Flash access time 25 ns ta(OTP) OTP access time 50 ns (1) Access time numbers shown in this table are before device characterization. Final numbers will be published in the data sheet for the fully qualified production device.

7.9.5.4 Control Subsystem – Flash Data Retention Duration

PARAMETER TEST CONDITIONS MIN MAX UNIT tretention Data retention duration TJ = 85°C 20 years www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 7-2. Control Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies SYSCLKOUT (MHz) SYSCLKOUT (ns) WAIT STATE 150 6.7 3 140 7.14 3 130 7.7 3 120 8.33 2 110 9.1 2 100 10 2 90 11.11 2 80 12.5 1 70 14.29 1 60 16.67 1 50 20 1 40 25 0 30 33.33 0 20 50 0 10 100 0 The equation to compute the Flash wait state in Table 7-2 is as follows: RWAIT 1= SYSCLK (MHz) 40 (MHz) round up to the next integer, or 1, whichever is larger. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.6 GPIO Electrical Data and Timing

7.9.6.1 GPIO - Output Timing

7.9.6.1.1 General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tr(GPO) Rise time, GPIO switching low to high All GPIOs 8 ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 8 ns tfGPO Toggling frequency, GPIO pins 25 MHz GPIO tf(GPO) tr(GPO) Figure 7-4. General-Purpose Output Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.6.2 GPIO - Input Timing

7.9.6.2.1 General-Purpose Input Timing Requirements

tw(SP) Sampling period QUALPRD = 0 1tc(SCO) cycles QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles tw(GPI) (2) Pulse duration, GPIO low/high Synchronous mode 2tc(SCO) cycles With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles (1) "n" represents the number of qualification samples as defined by GPxQSELn register. (2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal. GPIO Signal Sampling Window 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 SYSCLKOUT (A) GPxQSELn = 1,0 (6 samples) (D) Output From Qualifier QUALPRD = 1 (SYSCLKOUT/2) tw(IQSW) tw(SP) (SYSCLKOUT cycle * 2 * QUALPRD) * 5 (C) Sampling Period determined by GPxCTRL[QUALPRD] (B) A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled). B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins. C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. Figure 7-5. Sampling Mode F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.6.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT. Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0 Sampling frequency = SYSCLKOUT, if QUALPRD = 0 Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0 In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT. Sampling period = SYSCLKOUT cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register. Case 1: Qualification using 3 samples Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0 Case 2: Qualification using 6 samples Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0 GPIOxn SYSCLK tw(GPI) Figure 7-6. General-Purpose Input Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.6.4 Low-Power Mode Wakeup Timing

Figure 7-7 shows the timing diagram for IDLE mode.

7.9.6.4.1 IDLE Mode Timing Requirements

MIN(1) MAX UNIT tw(WAKE-INT) Pulse duration, external wake-up signal Without input qualifier 2tc(SCO) cycles With input qualifier 5tc(SCO) + tw(IQSW)

7.9.6.4.2 IDLE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN MAX UNIT td(WAKE-IDLE) Delay time, external wake signal to program execution resume (2) Wake-up from Flash

• Flash module in active state Without input qualifier 20tc(SCO) cycles With input qualifier 20tc(SCO) + tw(IQSW) Wake-up from Flash
• Flash module in sleep state Without input qualifier 1050tc(SCO) cycles With input qualifier 1050tc(SCO) + tw(IQSW)
• Wake-up from SARAM Without input qualifier 20tc(SCO) cycles With input qualifier 20tc(SCO) + tw(IQSW) (2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up) signal involves additional latency.

7.9.6.4.3 IDLE Entry and Exit Timing Diagram

(internal) WAKE INT (A)(B) td(WAKE-IDLE) tw(WAKE-INT) A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS. B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 7-7. IDLE Entry and Exit Timing F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.6.4.4 STANDBY Mode Timing Requirements

tw(WAKE-INT) Pulse duration, external wake-up signal Without input qualification 3tc(OSCCLK) cycles With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK) (1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

7.9.6.4.5 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles td(WAKE-STBY) Delay time, external wake signal to program execution resume(1)

• Wake up from flash – Flash module in active state Without input qualifier 100tc(SCO) cycles With input qualifier 100tc(SCO) + tw(WAKE-INT)
• Wake up from flash – Flash module in sleep state Without input qualifier 1125tc(SCO) cycles With input qualifier 1125tc(SCO) + tw(WAKE-INT)
• Wake up from SARAM Without input qualifier 100tc(SCO) cycles With input qualifier 100tc(SCO) + tw(WAKE-INT) (1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.6.4.6 STANDBY Entry and Exit Timing Diagram

td(WAKE-STBY) XCLKOUT STANDBY Normal ExecutionSTANDBY Flushing Pipeline (A) (B) (C) (D) (E) (F) Device Status td(IDLE-XCOL) X1/X2 or X1 or XCLKIN Wake-up Signal (G) tw(WAKE-INT) A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:

• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number then it will fail. It is recommended to enter STANDBY mode from SARAM without an XINTF access in progress. C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. D. The external wake-up signal is driven active. E. After a latency period, the STANDBY mode is exited. F. Normal execution resumes. The device will respond to the interrupt (if enabled). G. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 7-8. STANDBY Entry and Exit Timing Diagram F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.6.4.7 HALT Mode Timing Requirements

tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) (1) cycles tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles (1) See Section 7.9.1.2 for an explanation of toscst.

7.9.6.4.8 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles tp PLL lock-up time 131072tc(OSCCLK) cycles td(WAKE-HALT) Delay time, PLL lock to program execution resume

• Wake up from flash – Flash module in sleep state 1125tc(SCO) cycles
• Wake up from SARAM 35tc(SCO) cycles www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.9.6.4.9 HALT Entry and Exit Timing Diagram

td(IDLE−XCOL) XCLKOUT HALT HALT Wake-up Latency Flushing Pipeline (A) (B) (C) (D) (E) (G) (F) PLL Lock-up Time Normal Execution Oscillator Start-up Time Device Status X1/X2 or XCLKIN GPIOn (H) td(WAKE-HALT) tw(WAKE-GPIO) tp A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off and the CLKIN to the core is stopped:

• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF access in progress. C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be taken to maintain a low noise environment before entering and during HALT mode. E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles. These 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this duration even when the PLL is disabled). F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after a latency. G. Normal operation resumes. H. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 7-9. HALT Wake-Up Using GPIOn F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.9.7 External Interrupt Electrical Data and Timing

7.9.7.1 External Interrupt Timing Requirements

MIN(1) MAX UNIT tw(INT) (2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles (2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.

7.9.7.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1) PARAMETER MIN MAX UNIT td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles

7.9.7.3 External Interrupt Timing Diagram

XNMI, XINT1, XINT2 Address bus (internal) tw(INT) td(INT) Figure 7-10. External Interrupt Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.10 Analog and Shared Peripherals

Concerto Shared Peripherals are accessible from both the Master Subsystem and the Control Subsystem. The Analog Shared Peripherals include two 12-bit ADCs (Analog-to-Digital Converters), and six Comparator + DAC (10-bit) modules. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other analog registers, such as the ADC Configuration and Comparator Registers, are accessible by the C28x CPU only. The Digital Shared Peripherals include the IPC peripheral and the EPI. IPC is accessible by both CPUs; EPI is accessible by both CPUs and both DMAs. IPC is used for sending and receiving synchronization events between Master and Control subsystems to coordinate execution of software running on both processors, or exchanging of data between the two processors. EPI is used by this device to communicate with external memory and other devices. For detailed information on the processor peripherals, see the Concerto F28M35x Technical Reference Manual.

7.10.1 Analog-to-Digital Converter

Figure 7-11 shows the internal structure of each of the two ADC peripherals that are present on Concerto. Each ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion trigger, set the sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read 16 result registers. The 16 ADC channels can be used independently or in pairs, based on the assignments inside the SAMPLEMODE register. Pairing up the channels allows two analog inputs to be sampled simultaneously— thereby, increasing the overall conversion performance.

7.10.1.1 Sample Mode

Each ADC has 16 programmable channels that can be independently programmed for analog-to-digital conversion when corresponding bits in the SAMPLEMODE register are set to Sequential Mode. For example, if bit 2 in the SAMPLEMODE register is set to 0, ADC channels 4 and 5 are set to sequential mode. Both the SOC4CTL and SOC5CTL registers can then be programmed to configure channels 4 and 5 to independently perform analog-to-digital conversions with results being stored in the RESULT4 and RESULT5 registers. "Independently" means that channel 4 may use a different SOC trigger, different analog input, and different sampling window than the trigger, input, and window assigned to channel 5. The 16 programmable channels for each ADC may also be grouped in 8 channel pairs when corresponding bits in the SAMPLEMODE register are set to Simultaneous Mode. For example, if bit 2 in the SAMPLEMODE register is set to 1, ADC channels 4 and 5 are set to Simultaneous Mode. The SOC4CTL register now contains configuration parameters for both channel 4 and channel 5, and the SOC5CTL register is ignored. While channel 4 and channel 5 are still using dedicated analog inputs (now selected as pairs in the CHSEL field of SOC4CTL), they both share the same SOC trigger and Sampling Window, with the results being stored in the RESULT4 and RESULT5 registers. The Simultaneous mode is made possible by two sample-and-hold units present in each ADC. Each sample-and-hold unit has its own mux for selecting analog inputs (see Figure 7-11 ). By programming the SAMPLEMODE register, the 16 available channels can be configured as 16 independent channels, 8 channel pairs, or any combination thereof (for example, 10 sequential channels and 3 simultaneous pairs). F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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AIO_MUX MUX GPIO SOC0CTL REG SOC1CTL REG SOC2CTL REG SOC3CTL REG SOC4CTL REG SOC5CTL REG SOC6CTL REG SOC7CTL REG SOC8CTL REG SOC9CTL REG SOC10CTL REG SOC11CTL REG SOC12CTL REG SOC13CTL REG SOC14CTL REG SOC15CTL REGADC CONTROL ADC INTERUPT CONTROL TRIGS(8:1) EOC(15:0) SOCx TRIGGER CONTROL ADC_INT(8:1) SOC(15:0) STORE RESULT ASEL INTSOCSEL1 REG INTSOCSEL2 REG INTSEL1N2 REG INTSEL3N4 REG INTSEL5N6 REG INTSEL7N8 REG SOCPRICTL REG SAMPLEMODE REG ADCCTL1 REG 12-BIT ADC CONVERTER REV REG OFFTRIM REG REFTRIM REG S / H A S / H B INTFLG REG INTFLGCLR REG INTOVF REG INTOVFCLR REG SOCFLG REG SOCFRC REG SOCOVF REG SOCOVFCLR REG SOCSHSEL REGSEL ADCINT1 ADCINT2 BSEL ANALOG BUS ADC_INA0 ADC_INA2 ADC_INA3 ADC_INA4 ADC_INA6 ADC_INA7 ADC_INB0 ADC_INB3 ADC_INB4 ADC_INB7 ACIB RESULT0 REG RESULT1 REG RESULT2 REG RESULT3 REG RESULT4 REG RESULT5 REG RESULT6 REG RESULT7 REG RESULT8 REG RESULT9 REG RESULT10 REG RESULT11 REG RESULT12 REG RESULT13 REG RESULT14 REG RESULT15 REG N/C A B ACIB (ANALOG COMMON INTERFACE BUS) ADCCTL1 REG VREFLOCONV N/C N/C N/C (1) CURRENTLY DEFAULT IS “NO CONNECT”, CHANGE ADDCCTL1 REGI STER TO CONNECT TO VREFLO Figure 7-11. ADC

7.10.1.2 Start-of-Conversion Triggers

There are eight external SOC triggers that go to each of the two ADC modules (from the Control Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers derived from EOC interrupts inside each ADC module (ADCINT1 and ADCINT2). Registers INTSOCSEL1 and 2 are used to configure each of the 16 ADC channels for internal or external SOC sources. If internal SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select whether the internal source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel, the TRIGSEL field of the corresponding SOCxCTL register selects which of the eight external triggers is used for SOC in that channel. One analog-to-digital conversion can be performed at a time by the 12-bit ADC. The analog-to-digital conversion priority is managed according to the state of the PRICTL register.

7.10.1.3 Analog Inputs

Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group having a dedicated mux and sample-and-hold unit (see Figure 7-11). Mux A selects one of six possible analog inputs through AIO MUX. Mux B selects one of five possible analog inputs—four external inputs through AIO MUX, and one from the internal VREFLO signal, which is currently tied to the Analog Ground. The Mux A and Mux B inputs can be simultaneously or sequentially sampled by the two sample-and-hold units according to the sampling window chosen in the SOCxCTL register for the corresponding channel. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.10.1.4 ADC Result Registers and EOC Interrupts

Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for ADC2). The 16 ADCx channels can be programmed through the INTSELxNy registers to trigger up to eight ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both the Master Subsystem and the Control Subsystem, announcing that the Result Registers are ready to be read by a CPU or DMA (see Figure 8-3). F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.10.1.5 ADC Electrical Data and Timing

7.10.1.5.1 ADC Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 Bits ADC clock 2 37.5 MHz Sample Window 7 64 ADC clocks ACCURACY INL (Integral nonlinearity) –4 4 LSB DNL (Differential nonlinearity) –1 1.5 LSB Offset error Executing a single self- recalibration –20 0 20 LSB Executing periodic self- recalibration –4 0 4 Overall gain error with internal reference –60 60 LSB Overall gain error with external reference –40 40 LSB Channel-to-channel offset variation –4 4 LSB Channel-to-channel gain variation –4 4 LSB VREFLO input current –100 µA VREFHI input current 100 µA ANALOG INPUT Analog input voltage with internal reference 0 3.3 V Analog input voltage with external reference VREFLO VREFHI V VREFLO input voltage VSSA 0.66 V VREFHI input voltage 2.64 VDDA V Input capacitance 5 pF Input leakage current ±2 μA ADDITIONAL ADC SNR 65 dB ADC SINAD 62 dB ADC THD (50 kHz) –65 dB ENOB (SNR) 10.1 Bits SFDR 66 dB

7.10.1.5.2 External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO) cycles

7.10.1.5.3 ADCSOCAO or ADCSOCBO Timing Diagram

tw(ADCSOCL) Figure 7-12. ADCSOCAO or ADCSOCBO Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.10.2 Comparator + DAC Units

Figure 7-13 shows the internal structure of the six analog Comparator + DAC units present in Concerto devices. Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of the A input is greater than that of the B input, or a value of ‘0’ when the opposite is true. The six A inputs and two B inputs come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10-bit digital-to-analog units that are present in each comparator DAC. The 10-bit value for each DAC unit is programmed in the respective DACVAL register. Another comparator register, COMPCTL, can be programmed to select the source of the B input, to enable or disable the comparator circuit, to invert comparator output, to synchronize comparator output to C28x SYSCLK, and to select the qualification period (number of clock cycles). All six output signals from the six comparators can be routed out to the device pins through GPIO_MUX2 pin mux. GPIO_MUX2 MUX GPIO AIO_MUX1 MUX GPIO AIO_MUX2 COMPCTL REG SYNC / QUAL C28SYSCLK QUALSEL COMPSTS SYNCSELCOMPINVCOMPDACE COMPSTS REG COMP2 COMPA(1) COMPA(2) COMPB(2) COMPA(3) COMPA(4) COMPA(5) COMPB(5) COMPA(6) COMPOUT(1) COMPOUT(2) COMPOUT(3) COMPOUT(4) COMPOUT(5) COMPOUT(6) COMP1 MUX GPIO 10-BIT DAC2 DACVAL REG DACVAL(8:0) VDDA VSSA COMPSOURCE COMP2 0 0 V V = ( DACVAL * ( VDDA -VSSA ) ) / 1023 COMP = 0 WHEN VOLTAGE A < VOLTAGE B COMP = 1 WHEN VOLTAGE A > VOLTAGE B DAC1 COMP3 DAC3 COMP4 DAC4 COMP5 DAC5 COMP6 DAC6 N/C N/C N/C N/C Figure 7-13. Comparator + DAC Units

7.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing

7.10.2.1.1 Electrical Characteristics of the Comparator/DAC

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNITS Comparator Comparator Input Range VSSA – VDDA V Comparator response time to GPIO 30 ns Input Offset ±5 mV Input Hysteresis(1) 35 mV DAC DAC Output Range VSSA – VDDA V F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNITS DAC resolution 10 bits DAC settling time See Figure 7-14 DAC Gain –1.5% DAC Offset 10 mV Monotonic Yes INL ±3 LSB (1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback resistance between the output of the comparator and the noninverting input of the comparator. Settling Time (ns) 100 200 300 400 500 600 700 800 900 1000 1100 0 50 100 150 200 250 300 350 400 450 500 DAC Step Size (Codes)

15 Codes 7 Codes 3 Codes 1 CodeDAC Accuracy

Figure 7-14. DAC Settling Time www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.10.3 Interprocessor Communications

Figure 7-15 shows the internal structure of the IPC peripheral used to synchronize program execution and exchange of data between the Cortex-M3 and the C28x CPU. IPC can be used by itself when synchronizing program execution or it can be used in conjunction with Message RAMs when coordinating data transfers between processors. In either case, the operation of the IPC is the same. There are two independent sides to the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master). The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. The MTOC IPC typically sends events to the Control Subsystem by using the following registers: MTOCIPCSET, MTOCIPCFLG/ MTOCIPCSTS 1, and MTOCIPCACK. Each of the 32 bits of these registers represents 32 independent channels through which the Cortex-M3 CPU can send up to 32 events to the C28x CPU through software handshaking. Additionally, the first 4 bits of the MTOCIPC registers are supplemented with interrupts. To send an event through channel 2 from Cortex-M3 to C28x, for example, the Cortex-M3 and C28x CPUs use bit 2 of the MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers. The handshake starts with the Cortex- M3 polling bit 2 of the MTOCIPCFLG register to make sure bit 2 is ‘0’. Next, the Cortex-M3 writes a ‘1’ into bit 2 of the MTOCIPCSET register to start the handshake. In the mean time, the C28x is continually polling the MTOCIPCSTS register while waiting for the message. As soon as the Cortex-M3 writes ‘1’ to bit 2 of the MTOCIPCSET register, bit 2 of MTOCIPCFLG/MTOCIPCSTS also turns ‘1’, thus announcing the event to the C28x. As soon as the C28x CPU reads a ‘1’ from the MTOCIPCSTS register, the C28x CPU should acknowledge by writing a ‘1’ to bit 2 of the MTOCIPCACK register, which in turn, clears bit 2 of the MTOCIPCFLG/MTOCIPCSTS register, enabling the Cortex-M3 to send another message. Because the first four channels (bits 0, 1, 2, 3) are backed up by interrupts, both processors in the above example can use IPC interrupt 2 instead of polling to increase performance. A similar handshake is also used when sending data (not just event) from the Master Subsystem to the Control Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the Cortex-M3 should first load the MTOC Message RAM with a block of data that is to be made available to the C28x. In the second additional step, the C28x should read the data before setting a bit in the MTOCIPCACK register. This way, no data gets lost during multiple data transfers through a given block of the message RAM. The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. The CTOM IPC typically sends events to the Master Subsystem by using the following three registers: CTOMIPCSET, CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The process is exactly the same as that for the MTOC IPC communication above. 1 Physically, MTOCIPCFLG/MTOCIPCSTS is one register, but it is referred to as the MTOCIPCFLG register when the Cortex-M3 CPU reads it, and as the MTOCIPCSTS register when the C28x CPU reads it. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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(31:0) ACK(31:0) STS(31:0) MTOC MSG RAM MTOC IPC CTOMCTOM CTOMIPCSET REG CTOMIPCSACK REG CTOMIPCSTS REG CTOMIPCSFLG REG STS(31:0) ACK(31:0) RDDATA (31:0) FLG(31:0) SET(31:0) WRDATA (31:0) CTOM MSG RAMCTOM IPC C28x CPUPIE INTRSSTS(3:0) CPU NVIC CTOM IPC INT (3:0) STS(3:0)INTRS ACK REG STS REG SET REG 0 031 CTOM_CH31 CTOM_CH30 CTOM_CH29CTOM_CH2 CTOM_CH1 CTOM_CH0 . . . . . . . . . FLG REG

32 CTOM IPC CHANNELS

(3:0) MTOC_CH0MTOC_CH1MTOC_CH2MTOC_CH29MTOC_CH30MTOC_CH31 SET REG FLG REG ACK REG0 031 . . . . . . . . . STS REG

32 MTOC IPC CHANNELS

PHYSICALLY THIS IS ONE REGISTER WITH TWO DIFFERENT NAMES – FLG FOR THE M3 AND STS FOR THE C28 PHYSICALLY THIS IS ONE REGISTER WITH TWO DIFFERENT NAMES – FLG FOR THE C28 AND STS FOR THE M3 Figure 7-15. IPC

7.10.4 External Peripheral Interface

The EPI provides a high-speed parallel bus for interfacing external peripherals and memory. EPI is accessible from both the Master Subsystem and the Control Subsystem. EPI has several modes of operation to enable glueless connectivity to most types of external devices. Some EPI modes of operation conform to standard microprocessor address/data bus protocols, while others are tailored to support a variety of fast custom interfaces, such as those communicating with field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). The EPI peripheral can be accessed by the Cortex-M3 CPU, the Cortex-M3 DMA, the C28x CPU, and the C28x DMA over the high-performance AHB bus. The Cortex-M3 CPU and the µDMA drive AHB bus cycles directly through the Cortex-M3 Bus Matrix. The C28x CPU and DMA also connect to the Cortex-M3 Bus Matrix, but not directly. Before entering the Cortex-M3 Bus Matrix, the native C28x CPU and DMA bus cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the Cortex-M3 Bus Matrix, the Cortex-M3 bus cycles may have to compete with C28x bus cycles for access to the AHB bus on the way to the EPI peripheral. See Figure 7-16 to see how EPI interfaces to the Concerto Master Subsystem, the Concerto Control Subsystem, Resets, Clocks, and Interrupts. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

The Control Subsystem has no direct access to EPI in silicon revision 0 devices. Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration between the Cortex-M3 and C28x bus cycles is fixed-priority with Cortex-M3 having higher priority than C28x, or the C28x having the option to own the Bus Matrix for a fixed period of time (window)—effectively stalling all Cortex-M3 accesses during that time. Another EPI register inside the Cortex-M3 Bus Matrix is the Memory Protection Register, which enables assignments of chip-select spaces to Cortex-M3 or C28x EPI accesses (or both). The assignments of chip-select spaces prevent a bus cycle (from any processor) that does not own a given chip- select space, from getting through to EPI. The Real-time Window registers are the only EPI-related registers that are configurable by the C28x. The Memory Protection Register is configurable only by the Cortex-M3 CPU, as are all configuration registers inside the EPI peripheral. Figure 7-16 shows the EPI registers and how they relate to individual blocks within the EPI. Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO; therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes full. Read cycles can be handled in two different ways: blocking read cycles and nonblocking read cycles. Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall the CPU or DMA until the bus transaction completes. Nonblocking read cycles are triggered when a non-zero value is written into a Read Data Register. A non-zero value being written into a Read Data register triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or DMA) according to values stored inside the Read Address Register and the Read Size Register. The incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of nonblocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU or DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into the other end of the NBR FIFO. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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GPIO_MUX1 EPI AHB BUS M3 BUS MA TRIX uDMA HOST BUS INTERFACESDRAM INTERFACEGENERAL-PURPOSE INTERFACE BAUD RATE CONTROL AHB BUS INTERFACE EPI MUX

42 PINS

GPIOCSEL REGSDRAM CFG REG GPIOCSEL REGHB-8 CONFIG2 REGGPIOCSEL REGGP CONFIG2 REG GPIOCSEL REGHB-8 CONFIG REG 8-BIT MODE GPIOCSEL REG GPIOCSEL REG 16-BIT MODE HB-16 CONFIG2 REG HB-16 CONFIG REGGPIOCSEL REGGP CONFIG REG GPIOCSEL REGEPI ADDR MAP REG EPI BAUD REG READ FIFO CNT REG FIFO LEVEL SEL REG EPI CONFIG REG EPI ST ATUS REG READ FIFO REG 8X32 NBR FIFO4X32 WR FIFO READ FIFO ALIAS 1 READ FIFO ALIAS 2 READ FIFO ALIAS 3 READ FIFO ALIAS 4 READ FIFO ALIAS 5 READ FIFO ALIAS 6 READ FIFO ALIAS 7 C28 CPU C28 DMA CPU APB BUS RTWEPIREG REG RTWEPICNTR REG RTWEPIWD REG CEPIST ATUS REG MEMPROT REG MEM32 TO AHB BUS BRIDGE CONVERTS C28 CPU/DMA BUS CYCLES TO M3 AHB BUS CYCLES MEM32 TO AHB BUS BRIDGE FREQ GASKET REAL-TIME WINDOW MODE ALLOWS UNINTERRUPTED ACCESS TO EPI FROM C28 CPU/DMA, WHILE STALLING M3 CPU/DMA CYCLES THE M3 FREQUENCY GASKET REDUCES AHB BUS ACCESS FREQUENCY FOR C28 CPU/DMA CYCLES BY FACTOR OF 2 OR FACTOR OF 4 MEMORY PROTECTION LOGIC ASSIGNS CS SPACES TO C28 ONLY, M3 ONLY, OR BOTH NVIC PIE WR FIFO CNT REG EPI REQ EPI EPI CHAN 20 CHAN 22 VECT# 69 INT12/INTx.6 MASK INT ST AT REG ERR INT ST AT /CLR INT MASK REG RAW INT ST AT REG EPI INTERRUPT INTERRUPT SOURCES EPI RD DATA0 REG EPI RD ADDR0 REG EPI RD SIZE0 REG EPI RD DATA1 REG EPI NONBLOCKING ACCESS REGISTERS M3SSCLK EPI RD ADDR0 REG EPI RD SIZE0 REG WRITE FIFO READ (NONBLOCKING) NON-FIFO READ (BLOCKING) Figure 7-16. EPI EPI can directly interrupt the Cortex-M3 CPU, the Cortex-M3 uDMA, and the C28x CPU (but not the C28x DMA) through the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move data to and from EPI. There are four EPI Interrupt registers that control various facets of interrupt generation, clearing, and masking. The EPI Interrupt can trigger µDMA to perform reads and writes through DMA Channels 20 and 22. If a CPU is the intended recipient, the Cortex-M3 CPU is interrupted by NVIC vector 69, and the C28x CPU is interrupted through the INT12/INTx6 vector to the PIE. During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be remapped to different addresses according to values stored in the EPI Address Map Register in conjunction with the most significant bit of the incoming address. The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the Host Bus Mode (including 8-bit and 16-bit versions).

7.10.4.1 EPI General-Purpose Mode

The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose Mode from the 8-bit and 16-bit Host Bus Modes. Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The slave device responding to the bus cycles may use this signal to recognize related words of data and to speed up their www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

transfers. The frame lengths are programmable and may vary from 1 to 30 clocks, depending on the clocking mode used. Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping. A free-running EPI clock requires another method for determining when data is live, such as the frame pin or RD/WR strobes. These and numerous other aspects of the General-Purpose Mode are controlled through the General-Purpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block. See Figure 7-17 for a snapshot of the General-Purpose Mode registers, modes, and features. For more detailed maps of the General-Purpose Mode, see Table 7-3. EPI CONFIG REG MODE = GEN PURP READY SIGNAL ADDRESS RANGE DATA SIZE ASIZE = 3 ASIZE = 0 A0 – A18 A0 – A10 A0 – A2 N/A YES YES YES NO GP CONFIG REG DSIZE = 0 DSIZE = 3 RDYEN = 1 A0 – A2 YES 24 A0 – A10 YES 16 A0 – A18 YES 8 FRMPIN = 1 RDYEN = 0 FRAME SIGNAL YES NO A0 – A19 NO 8 A0 – A19 NO 8 YES NO ASIZE = 2 DSIZE = 1 ASIZE = 1 DSIZE = 2 RDYEN = X FRMPIN = X A0 – A3 NO 24 A0 – A3 NO 24 A0 – A11 NO 16 A0 – A11 NO 16 YES NO YES NO YES NO YES NO NO RDYEN = 1 FRMPIN = 0 RDYEN = 0 RDYEN = 1 FRMPIN = 1 RDYEN = 0 RDYEN = 1 FRMPIN = 0 RDYEN = 0 RDYEN = 1 FRMPIN = 1 RDYEN = 0 RDYEN = 1 FRMPIN = 0 RDYEN = 0 Figure 7-17. EPI General-Purpose Modes F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 7-3. EPI MODES – General-Purpose Mode (EPICFG/MODE = 0x0) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x GENERAL- PURPOSE SIGNAL (D8, A20) GENERAL- PURPOSE SIGNAL (D16, A12) GENERAL- PURPOSE SIGNAL (D24, A4) GENERAL- PURPOSE SIGNAL (D30, NO ADDR) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 D8 D8 D8 PE0_GPIO24 EPI0S9 A1 D9 D9 D9 PE1_GPIO25 EPI0S10 A2 D10 D10 D10 PH4_GPIO52 EPI0S11 A3 D11 D11 D11 PH5_GPIO53 EPI0S12 A4 D12 D12 D12 PF4_GPIO36 EPI0S13 A5 D13 D13 D13 PG0_GPIO40 EPI0S14 A6 D14 D14 D14 PG1_GPIO41 EPI0S15 A7 D15 D15 D15 PF5_GPIO37 EPI0S16 A8 A0 D16 D16 PJ0_GPIO56 EPI0S17 A9 A1 D17 D17 PJ1_GPIO57 EPI0S18 A10 A2 D18 D18 PJ2_GPIO58 EPI0S19 A11 A3 D19 D19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A12 A4 D29 D29 PD2_GPIO18 EPI0S21 A13 A5 D21 D21 PD3_GPIO19 EPI0S22 A14 A6 D22 D22 PB5_GPIO13 EPI0S23 A15 A7 D23 D23 PB4_GPIO12 EPI0S24 A16 A8 A0 D24 PE2_GPIO26 EPI0S25 A17 A9 A1 D25 PE3_GPIO27 EPI0S26 A18 A10 A2 D26 PH6_GPIO54 EPI0S27 A19/RDY A11/RDY A3/RDY D27 PH7_GPIO55 EPI0S28 WR WR WR D28 PD5_GPIO21 PJ4_GPIO60 EPI0S29 RD RD RD D29 PD6_GPIO22 PJ5_GPIO61 EPI0S30 FRAME FRAME FRAME D30 PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK CLK CLK D31 PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.10.4.2 EPI SDRAM Mode

The EPI SDRAM Mode combines high performance, low cost, and low pin use to access up to 512 megabits (Mb) of external memory. Main features of the EPI SDRAM interface are:

• Supports x16 (single data rate) SDRAM
• Supports low-cost SDRAMs up to 64 megabytes (MB) [or 512Mb]
• Includes automatic refresh and access to all banks, rows
• Includes Sleep/STANDBY Mode to keep contents active with minimal power drain
• Multiplexed address/data interface for reduced pin count See Figure 7-18 for a snapshot of the SDRAM Mode registers and supported memory sizes. For more detailed maps of the SDRAM Mode, see Table 7-4. EPI CONFIG REG MODE = SDRAM SDRAM CFG REG SDRAM SIZE DATA SIZE SIZE = 0 SIZE = 1 SIZE = 2 SIZE = 3

64 MBit

128 MBit

256 MBit

512 MBit

Figure 7-18. EPI SDRAM Mode F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 7-4. EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x COLUMN/ROW ADDRESS DATA (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 A0 D0 PH3_GPIO51 EPI0S1 A1 D1 PH2_GPIO50 EPI0S2 A2 D2 PC4_GPIO68 EPI0S3 A3 D3 PC5_GPIO69 EPI0S4 A4 D4 PC6_GPIO70 EPI0S5 A5 D5 PC7_GPIO71 EPI0S6 A6 D6 PH0_GPIO48 EPI0S7 A7 D7 PH1_GPIO49 EPI0S8 A8 D8 PE0_GPIO24 EPI0S9 A9 D9 PE1_GPIO25 EPI0S10 A10 D10 PH4_GPIO52 EPI0S11 A11 D11 PH5_GPIO53 EPI0S12 A12 D12 PF4_GPIO36 EPI0S13 BA0 D13 PG0_GPIO40 EPI0S14 BA1 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S16 DQML PJ0_GPIO56 EPI0S17 DQMH PJ1_GPIO57 EPI0S18 CAS PJ2_GPIO58 EPI0S19 RAS PD4_GPIO20 PJ3_GPIO59 EPI0S28 WE PD5_GPIO21 PJ4_GPIO60 EPI0S29 CS PD6_GPIO22 PJ5_GPIO61 EPI0S30 CKE PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK PG7_GPIO47 EPI0S20 x PD2_GPIO18 EPI0S21 x PD3_GPIO19 EPI0S22 x PB5_GPIO13 EPI0S23 x PB4_GPIO12 EPI0S24 x PE2_GPIO26 EPI0S25 x PE3_GPIO27 EPI0S26 x PH6_GPIO54 EPI0S27 x PH7_GPIO55 EPI0S32 x PF2_GPIO34 PC0_GPIO64 EPI0S33 x PF3_GPIO35 PC1_GPIO65 EPI0S34 x PE4_GPIO28 EPI0S35 x PE5_GPIO29 EPI0S36 x PB7_GPIO15 PC3_GPIO67 EPI0S37 x PB6_GPIO14 PC2_GPIO66 EPI0S38 x PF6_GPIO38 PE4_GPIO28 EPI0S39 x PG2_GPIO42 EPI0S40 x PG5_GPIO45 EPI0S41 x PG6_GPIO46 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.10.4.3 EPI Host Bus Mode

There are two versions of the EPI Host Bus Mode: an 8-bit version (HB-8) and a 16-bit version (HB-16). Section

7.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode

The 8-Bit Host Bus (HB-8) Mode uses fewer data pins than the 16-Bit Host Bus (HB-16) Mode; hence, more pins are available for address. The HB-8 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-8 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-8 Mode, two additional registers are used to select address/data muxing, chip selects, and other options. These registers are the HB-8 Configuration Register and the HB-8 Configuration2 Register. See Figure 7-19 for a snapshot of HB-8 registers, modes, and features. HB8 CONFIG2 REGEPI CONFIG REG MODE = HB-8 HP8 CONFIG REG MODE = NOMUX MODE = MUXED MODE = FIFO CSCFG = 2 CS CSCFG = ALE + 2 CS N/A N/A NO NO READY SIGNAL ADDRESS RANGE DATA SIZE CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A19 A0 – A19 A0 – A18 A0 – A17 NO NO NO NO CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A27 A0 – A27 A0 – A26 A0 – A25 NO NO NO NO Figure 7-19. EPI 8-Bit Host Bus Mode The HB-8 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-8 Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (Chip Select) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Muxed Mode, see Table 7-5. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 7-5. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Muxed (EPIHB16CFG/MODE = 0x0) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 A8 A8 A8 A8 PE0_GPIO24 EPI0S9 A9 A9 A9 A9 PE1_GPIO25 EPI0S10 A10 A10 A10 A10 PH4_GPIO52 EPI0S11 A11 A11 A11 A11 PH5_GPIO53 EPI0S12 A12 A12 A12 A12 PF4_GPIO36 EPI0S13 A13 A13 A13 A13 PG0_GPIO40 EPI0S14 A14 A14 A14 A14 PG1_GPIO41 EPI0S15 A15 A15 A15 A15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (Chip Select) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Non-Muxed Mode, see Table 7-6. Table 7-6. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 A0 A0 A0 PE0_GPIO24 EPI0S9 A1 A1 A1 A1 PE1_GPIO25 EPI0S10 A2 A2 A2 A2 PH4_GPIO52 EPI0S11 A3 A3 A3 A3 PH5_GPIO53 EPI0S12 A4 A4 A4 A4 PF4_GPIO36 EPI0S13 A5 A5 A5 A5 PG0_GPIO40 EPI0S14 A6 A6 A6 A6 PG1_GPIO41 EPI0S15 A7 A7 A7 A7 PF5_GPIO37 EPI0S16 A8 A8 A8 A8 PJ0_GPIO56 EPI0S17 A9 A9 A9 A9 PJ1_GPIO57 EPI0S18 A10 A10 A10 A10 PJ2_GPIO58 EPI0S19 A11 A11 A11 A11 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A12 A12 A12 A12 PD2_GPIO18 EPI0S21 A13 A13 A13 A13 PD3_GPIO19 EPI0S22 A14 A14 A14 A14 PB5_GPIO13 EPI0S23 A15 A15 A15 A15 PB4_GPIO12 EPI0S24 A16 A16 A16 A16 PE2_GPIO26 EPI0S25 A17 A17 A17 A17 PE3_GPIO27 EPI0S26 A18 A18 A18 CS0 PH6_GPIO54 EPI0S27 A19 A19 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 7-6. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For more detailed maps of the HB-8 FIFO Mode, see Table 7-7. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 7-7. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S8 x x PE0_GPIO24 EPI0S9 x x PE1_GPIO25 EPI0S10 x x PH4_GPIO52 EPI0S11 x x PH5_GPIO53 EPI0S12 x x PF4_GPIO36 EPI0S13 x x PG0_GPIO40 EPI0S14 x x PG1_GPIO41 EPI0S15 x x PF5_GPIO37 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 PJ3_GPIO59 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 EPI0S32 x x PF2_GPIO34 PC0_GPIO64 EPI0S31 x x PG7_GPIO47 EPI0S33 x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x PE4_GPIO28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode

The 16-Bit Host Bus (HB-16) Mode uses fewer address pins than the 8-Bit Host Bus (HB-8) Mode; hence, more pins are available for data. The HB-16 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-16 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-16 Mode, two additional registers are used to select address/data muxing, byte selects, chip selects, and other options. These registers are the HB-16 Configuration Register and the HB-16 Configuration2 Register. See Figure 7-20 for a snapshot of HB-16 registers, modes, and features. HB16 CONFIG2 REGEPI CONFIG REG MODE = HB-16 HP16 CONFIG REG MODE = NOMUX MODE = MUXED MODE = FIFO BSEL = DON’T CARE CSCFG = 2 CS CSCFG = ALE + 2 CS N/A N/A NO NO BSEL = NO CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS CSCFG = 3 CS CSCFG = 4 CS READY SIGNAL A0 – A11 ADDRESS RANGE A0 – A11 A0 – A10 A0 – A9 A0 – A18 A0 – A16 NO YES YES YES YES YES DATA SIZE BSEL = YES CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS CSCFG = 3 CS CSCFG = 4 CS A0 – A9 A0 – A9 A0 – A8 A0 – A7 A0 – A16 A0 – A14 NO YES YES YES YES YES BSEL = NO CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A27 A0 – A27 A0 – A26 A0 – A25 NO NO NO NO BSEL = YES CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A25 A0 – A25 A0 – A24 A0 – A23 NO NO NO NO Figure 7-20. EPI 16-Bit Host Bus Mode www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (Chip Select) signals to enable one of four external peripherals; and two BSEL (Byte Select) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For more detailed maps of the HB-16 Muxed Mode without Byte Selects, see Table 7-8. For more detailed maps of the HB-16 Muxed Mode with Byte Selects, see Table 7-9. Table 7-8. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 7-8. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Table 7-9. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 7-9. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 BSEL0 PE2_GPIO26 EPI0S25 A25 A25 BSEL0 BSEL1 PE3_GPIO27 EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (Chip Select) signals to enable one of four external peripherals; and two BSEL (Byte Select) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to 32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 10 additional pins to extend the address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without Byte Selects, see Table 7-10 and Table 7-11. For detailed maps of HB-16 Non-Muxed Modes with Byte Selects, see Table 7-12 and Table 7-13. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 7-10. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 A8 PE2_GPIO26 EPI0S25 A9 A9 A9 A9 PE3_GPIO27 EPI0S26 A10 A10 A10 CS0 PH6_GPIO54 EPI0S27 A11 A11 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 7-11. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH THREE CHIP SELECTS (CSCFG = 0x7) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH FOUR CHIP SELECTS (CSCFG = 0x5) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S25 A9 PE3_GPIO27 EPI0S25 A9 PE3_GPIO27 EPI0S26 A10 PH6_GPIO54 EPI0S26 A10 PH6_GPIO54 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S40 A15 PG5_GPIO45 EPI0S35 A16 PE5_GPIO29 EPI0S41 A16 PG6_GPIO46 EPI0S40 A17 PG5_GPIO45 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S41 A18 PG6_GPIO46 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIO28 EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 7-12. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ADDRESS LATCH ENABLE (CSCFG = 0x0) WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) WITH ALE AND TWO CHIP SELECTS (CSCFG = 0x3) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 BSEL0 PE2_GPIO26 EPI0S25 A9 A9 BSEL0 BSEL1 PE3_GPIO27 EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 7-13. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH THREE CHIP SELECTS (CSCFG = 0x7) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH FOUR CHIP SELECTS (CSCFG = 0x5) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S40 A9 PG5_GPIO45 EPI0S40 A9 PG5_GPIO45 EPI0S41 A10 PG6_GPIO46 EPI0S41 A10 PG6_GPIO46 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S25 BSEL0 PE3_GPIO27 EPI0S35 A16 PE5_GPIO29 EPI0S26 BSEL1 PH6_GPIO54 EPI0S25 BSEL0 PE3_GPIO27 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S26 BSEL1 PH6_GPIO54 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIO28 EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For detailed maps of the HB-16 FIFO Mode, see Table 7-14. Table 7-14. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 PF5_GPIO37 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x x PF2_GPIO34 PC0_GPIO64 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 PJ3_GPIO59 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 7-14. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH ONE CHIP SELECT (CSCFG = 0x1) WITH TWO CHIP SELECTS (CSCFG = 0x2) (AVAILABLE GPIOMUX_1 MUXING CHOICES FOR EPI) EPI0S31 x x PG7_GPIO47 EPI0S33 x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x PE4_GPIO28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46

7.10.4.4 EPI Electrical Data and Timing

The signal names in Figure 7-21 through Figure 7-29 are defined in Table 7-15. Table 7-15. Signals in Figure 7-21 Through Figure 7-29 SIGNAL DESCRIPTION AD Address/Data Address Address output ALE Address latch enable BAD Bank Address/Data BSEL0, BSEL1 Byte select CAS Column address strobe CKE Clock enable CLK, Clock Clock Command Command signal CS Chip select Data Data signals DQMH Data mask high DQML Data mask low Frame Frame signal iRDY Ready input Muxed Address/Data Multiplexed Address/Data RAS Row address strobe RD/ OE Read enable/Output enable WE, WR Write enable F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.10.4.4.1 EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless

Otherwise Noted) (see Figure 7-21, Figure 7-22, and Figure 7-23) NO. PARAMETER MIN MAX UNIT E1 tc(CK) Cycle time, SDRAM clock 20 ns E2 tw(CKH) Pulse duration, SDRAM clock high 10 ns E3 tw(CKL) Pulse duration, SDRAM clock low 10 ns E4 td(CK-OV) Delay time, clock to output valid –5 5 ns E5 td(CK-OIV) Delay time, clock to output invalid –5 5 ns E6 td(CK-OZ) Delay time, clock to output high-impedance –5 5 ns E7 tsu(AD-CK) Setup time, input before clock 10 ns E8 th(CK-AD) Hold time, input after clock 0 ns E9 tPU Power-up time 100 µs E10 tpc Precharge time, all banks 20 ns E11 trf Autorefresh 66 ns E12 tMRD Program mode register 40 ns

7.10.4.4.2 EPI SDRAM Timing Diagrams

(EPI0S31) CKE (EPI0S30) Command DQMH, DQML (EPI0S[17:16]) AD1 1, AD[9:0] (EPI0S[1 1,9:0] AD10 (EPI0S[10]) BAD[1:0] (EPI0S[14:13]) AD [15,12] (EPI0S [15,12]) NOP PRE NOP AREF NOP PRE NOP AREF NOP LOAD Code All Banks Single Bank Code E9 E10 E1 1 E12 E1 E2 E3 NOP AREF NOP Active Row Row Bank A. If CS is high at clock high time, all applied commands are NOP. B. The Mode register may be loaded before the autorefresh cycles if desired. C. JEDEC and PC100 specify three clocks. D. Outputs are ensured High-Z after command is issued. Figure 7-21. SDRAM Initialization and Load Mode Register Timing Row Column Data 0 Data 1 ... Data n CLK (EPI0S31) CKE (EPI0S30) CS (EPI0S29) WE (EPI0S28) RAS (EPI0S19) CAS (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Activate NOP NOP Read NOP Burst T erm AD [15:0] driven in AD [15:0] driven out AD [15:0] driven out E4 E5 E6 Figure 7-22. SDRAM Read Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Row Column-1 Data 0 Data 1 ... Data n CLK (EPI0S31) CKE (EPI0S30) CS (EPI0S29) WE (EPI0S28) RAS (EPI0S19) CAS (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Activate NOP NOP Write Burst T erm AD [15:0] driven out AD [15:0] driven out E4 E5 E6 Figure 7-23. SDRAM Write Timing F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.10.4.4.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating

Conditions (Unless Otherwise Noted) (see Figure 7-24, Figure 7-25, Figure 7-26, and Figure 7-27) NO. PARAMETER MIN TYP MAX UNIT E16 td(WR-WDATAV) Delay time, WR to write data valid 5 ns E17 td(WRIV-DATA) Delay time, WR invalid to data 2 EPI clocks E18 td(CS-OV) Delay time, CS to output valid –5 5 ns E19 td(CS-OIV) Delay time, CS to output invalid –5 5 ns E20 tw(STL) Pulse duration, WR/ RD strobe low 2 EPI clocks E22 tw(ALEH) Pulse duration, ALE high 1 EPI clocks E23 tw(CSL) Pulse duration, CS low 4 EPI clocks E24 td(ALE-ST) Delay time, ALE rising to WR/ RD strobe falling 2 EPI clocks E25 td(ALE-ADHZ) Delay time, ALE falling to Address/Data high-impedance 1 EPI clocks

7.10.4.4.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements(1)

(see Figure 7-24 and Figure 7-26) NO. MIN MAX UNIT E14 tsu(RDATA) Setup time, read data 10 ns E15 th(RDATA) Hold time, read data 0 ns (1) Setup time for FEMPTY and FFULL signals from clock edge is 2 system clocks (MIN).

7.10.4.4.5 EPI Host-Bus 8/16 Mode Timing Diagrams

( )EPI0S30 CS (EPI0S30) WR ( )EPI0S29 RD□OE / ( )EPI0S28 Address Data E15 E18 E18 E14 E19E20 E24 E22 E23 BSEL0□BSEL1/ (A) A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-24. Host-Bus 8/16 Mode Read Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

( )EPI0S30 CS ( )EPI0S30 WR ( )EPI0S29 RD□OE / ( )EPI0S28 Address Data E18 E18 E16 E20 E17 E19 E22 E23 E24 BSEL0□BSEL1/ (A) A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-25. Host-Bus 8/16 Mode Write Timing Address Data ALE ( )EPI0S30 CS (EPI0S30) WR ( )EPI0S29 RD□OE / ( )EPI0S28 E15 E18 E18 E14 E19 E20 E22 E23 BSEL0□BSEL1/ (A) Muxed Address/Data E25 E24 A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-26. Host-Bus 8/16 Mode Muxed Read Timing ALE ( )EPI0S30 CS ( )EPI0S30 WR ( )EPI0S29 RD□OE / ( )EPI0S28 E18 E18 E16 E20 E19 E22 E23 E24 BSEL0/BSEL1 (A) DataMuxed Address/Data Address A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only. Figure 7-27. Host-Bus 8/16 Mode Muxed Write Timing F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.10.4.4.6 EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions

(Unless Otherwise Noted) (see Figure 7-28) NO. PARAMETER MIN MAX UNIT E26 tw(CKH) Pulse duration, general-purpose clock high 10 ns E27 tw(CKL) Pulse duration, general-purpose clock low 10 ns E30 td(CK-OV) Delay time, falling clock edge to output valid –5 5 ns E31 td(CK-OIV) Delay time, falling clock edge to output invalid –5 5 ns E33 tc(CK) Cycle time, general-purpose clock 20 ns

7.10.4.4.7 EPI General-Purpose Interface Timing Requirements (see Figure 7-28 and Figure 7-29)

NO. MIN MAX UNIT E28 tsu(IN-CK) Setup time, input signal before rising clock edge 10 ns E29 th(CK-IN) Hold time, input signal after rising clock edge 0 ns E32 tsu(IRDY-CK) Setup time, iRDY assertion or deassertion before falling clock edge 10 ns

7.10.4.4.8 EPI General-Purpose Interface Timing Diagrams

( )EPI0S31 Frame (EPI0S30) RD ( )EPI0S29 WR ( )EPI0S28 Address Data E29 E30 Write A. This figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0, the RD2CYC bit is clear, and the WR2CYC bit is clear. Figure 7-28. General-Purpose Mode Read and Write Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

( )EPI0S31 Frame (EPI0S30) RD ( )EPI0S29 iRDY ( )EPI0S27 Address Data E32 E32 Figure 7-29. General-Purpose Mode iRDY Timing F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.11 Master Subsystem Peripherals

Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the Cortex- M3 CPU/µDMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB peripherals include EMAC, two I2Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG, and a µCRC module (Cyclic Redundancy Check). The Cortex-M3 CPU/µDMA also have access to Analog (Result Registers only) and Shared peripherals (see Section 7.10). For detailed information on the processor peripherals, see the Concerto F28M35x Technical Reference Manual.

7.11.1 Synchronous Serial Interface

This device has four SSI modules. Each SSI has a Master or Slave interface for synchronous serial communication with peripheral devices that have Texas Instruments™ SSIs, SPI, or Freescale™ serial format. The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories, allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. The SSI also supports µDMA transfers. The transmit and receive FIFOs can be programmed as destination/source addresses in the µDMA module. An µDMA operation is enabled by setting the appropriate bit or bits in the SSIDMACTL register. Figure 7-30 shows the SSI peripheral.

7.11.1.1 Bit Rate Generation

The SSI includes a programmable bit-rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing-down the input clock (SysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register. The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register. The frequency of the output clock SSIClk is defined by: SSIClk = SysClk / [CPSDVSR * (1 + SCR)] Note For master mode, the system clock must be at least four times faster than SSIClk, with the restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must be at least 12 times faster than SSIClk. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX1 CONTROL / ST ATUS INTR CONTROL SSICR0 REG SSICR1 REG SSISR REG SSIRIS REG SSIICR REG SSIIM REG SSIPERIPHLD4 REG CPU REGISTER ACCESS M3SSCLK SSI M3CLKENBx M3 CLOCKS uDMA M3 NVICSSIxIRQ SSIPERIPHLD5 REG SSIPERIPHLD6 REG SSIPCELLID0 REG SSIPCELLID1 REG SSIPCELLID2 REG SSIPCELLID3 REG SSIPERIPHLD0 REG SSIPERIPHLD1REG SSIPERIPHLD2 REG SSIPERIPHLD3 REG SSIPERIPHLD7 REG SSIMIS REG SSIDMACTL REG DMA CONTROL SSICPSR REG CLOCK PRESCALER SSIxCLK INTxREQ DMAxREQ TX FIFO ST AT RX FIFO ST AT IDENTIFICA TION REGISTERS INTR TX/RX FIFO ACCESS TX FIFO (8 16)/c180 RX FIFO (8 16)/c180 SSIDR REG Figure 7-30. SSI

7.11.1.2 Transmit FIFO

The transmit FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. The CPU writes data to the FIFO through the SSI Data (SSIDR) register, and data is stored in the FIFO until the data is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO before serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates a transaction, the slave transmits the 8th most recent value in the transmit FIFO. If less than eight values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then "0" is transmitted. Care should be taken to ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or an µDMA request when the FIFO is empty.

7.11.1.3 Receive FIFO

The receive FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered before parallel loading into the attached slave or master receive FIFO, respectively.

7.11.1.4 Interrupts

The SSI can generate interrupts when the following conditions are observed:

• Transmit FIFO service (when the transmit FIFO is half full or less)
• Receive FIFO service (when the receive FIFO is half full or more)
• Receive FIFO time-out
• Receive FIFO overrun
• End of transmission F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI generates a single interrupt request to the controller regardless of the number of active interrupts. Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt Mask (SSIIM) register. Setting the appropriate mask bit enables the interrupt. The individual outputs, along with a combined interrupt output, allow the use of either a global interrupt service routine or modular device drivers to handle interrupts. The transmit and receive dynamic data-flow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers. The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a "1" to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns before the interrupt is actually cleared, or the ISR may be reactivated unnecessarily. The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to complete. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.11.1.5 Frame Formats

Each data frame is between 4 bits and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. The following basic frame types can be selected:

• Texas Instruments Synchronous Serial
• Freescale SPI For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is used to provide a receive time-out indication that occurs when the receive FIFO still contains data after a time-out period.

7.11.2 Universal Asynchronous Receiver/Transmitter

This device has five UART modules. The CPU accesses data, control, and status information. The UART also supports µDMA transfers. Each UART performs functions of parallel-to-serial and serial-to-parallel conversions. Each of the five UART modules is similar in functionality to a 16C550 UART, but is not register-compatible. The UART is configured for transmit and receive through the TXE bit and the RXE bit, respectively, of the UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed before the UART stops. The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. Figure 7-31 shows the UART peripheral.

7.11.2.1 Baud-Rate Generation

The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register, and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD, and BRDF is the fractional part, separated by a decimal place). BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate) where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in UARTCTL is clear) or 8 (if HSE is set). The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 8x or 16x the baud rate [referred to as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. TX FIFO (8 16)/c180 TRANSMITTER UxRX UxTX PIN PIN GPIO_MUX1 RX FIFO (8 16)/c180 CONTROL/ ST ATUS UARTDR REG INTR CONTROL UARTCR0 REG UARTCR1 REG UARTSR REG UARTRIS REG UARTICR REG UARTIM REG UARTPERIPHLD4 CPU REGISTER ACCESS M3SSCLK UART UARTCLKENBx M3 CLOCKSM3 NVICUARTxIRQ UARTPERIPHLD5 UARTPERIPHLD6 UARTPCELLID0 UARTPCELLID1 UARTPCELLID2 UARTPCELLID3 UARTPERIPHLD0 UARTPERIPHLD1 UARTPERIPHLD2 UARTPERIPHLD3 UARTPERIPHLD7 UARTMIS REG UARTDMACTL REG DMA CONTROL UARTIBRD REG BAUDE RATE GENERATOR INTxREQ TX FIFO ST AT RX FIFO ST AT IDENTIFICA TION REGISTERS INTR UARTIFLS REG UARTFBRD REG XCLK UARTxCLK uDMA DMAxREQ TX/RX FIFO ACCESS RECEIVER (WITH SIR RECEIVE DECODER) (WITH SIR TRANSMIT ENCODER) Figure 7-31. UART

7.11.2.2 Transmit and Receive Logic

The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO.

7.11.2.3 Data Transmission and Reception

Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra 4 bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, a data frame starts transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is nonempty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx signal is continuously "1"), and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or the fourth cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL). www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, 1 bit period later), according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO along with any error bits associated with that word.

7.11.2.4 Interrupts

The UART can generate interrupts when the following conditions are observed:

• Overrun Error
• Break Error
• Parity Error
• Framing Error
• Receive Time-out
• Transmit (when the condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
• Receive (when the condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register. The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status is always visible through the UART Raw Interrupt Status (UARTRIS) register. Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a "1" to the corresponding bit in the UART Interrupt Clear (UARTICR) register. The receive time-out interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a "1" is written to the corresponding bit in the UARTICR register. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.11.3 Cortex-M3 Inter-Integrated Circuit

This device has two Cortex-M3 I2C peripherals. The Cortex-M3 I2C bus provides bidirectional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The microcontroller includes two I2C modules, providing the ability to interact (both transmit and receive) with other I2C devices on the bus. The two Cortex-M3 I2C modules include the following features:

• Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation
• Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive
• Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
• Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode Figure 7-32 shows the Cortex-M3 I2C peripheral.

7.11.3.1 Functional Overview

Each I2C module comprises both master and slave functions. For proper operation, the SDA and SCL pins must be configured as open-drain signals. The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bidirectional serial data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines are high. Every transaction on the I2C bus is 9 bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, the receiver can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.

7.11.3.2 Available Speed Modes

The I2C bus can run in either standard mode (100 Kbps) or fast mode (400 Kbps). The selected mode should match the speed of the other I2C devices on the bus. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX1 I C SLAVE CORE CPU REGISTER ACCESS M3SSCLK I C (M3) M3CLKENBx M3 CLOCKSM3 NVICI2CxIRQ I2CxCLK INTR I2CSCL_M I2CSDA_M I2CSCL_S I2CSDA_S I C CONTROL I2CMSA REG I2CMCS REG I2CMDR REG I2CMTPR REG I2CMIMR REG I2CMRISREG I2CMMIS REG I2CMICR REG I2CMCR REG I2CSIMR REG I2CSDR REG I2CSMIS REG I2CSICR REG I2CSRISREG I2CSOAR REG I2CSCSR REG Figure 7-32. I2C (Cortex-M3)

7.11.3.3 I2C Electrical Data and Timing

7.11.3.3.1 I2C Timing

TEST CONDITIONS MIN MAX UNIT fSCL SCL clock frequency I2C clock module frequency is between

7 MHz and 12 MHz and I2C prescaler

and clock divider registers are configured appropriately 400 kHz vil Low level input voltage 0.3 VDDIO V Vih High level input voltage 0.7 VDDIO V Vhys Input hysteresis 0.05 VDDIO V Vol Low level output voltage 3 mA sink current 0 0.4 V tLOW Low period of SCL clock I2C clock module frequency is between and clock divider registers are configured appropriately 1.3 μs tHIGH High period of SCL clock I2C clock module frequency is between and clock divider registers are configured appropriately 0.6 μs lI Input current with an input voltage between 0.1 VDDIO and 0.9 VDDIO MAX –10 10 μA F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.11.4 Cortex-M3 Controller Area Network

The CAN module uses the popular IP known as D_CAN. This document uses the names “CAN” and “D_CAN” interchangeably to reference this peripheral. This device has two Cortex-M3 CAN peripherals. CAN is a serial communications protocol that efficiently supports distributed real-time control with a high level of security. The CAN module supports bit rates up to 1 Mbit/s and is compliant with the ISO11898-1 (CAN 2.0B) protocol specification. CAN implements the following features:

• CAN protocol version 2.0 part A, B
• Bit rates up to 1 Mbit/s
• Multiple clock sources
• 32 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM parity check mechanism
• Two interrupt lines
• Global power down and wakeup support Figure 7-33 shows the Cortex-M3 CAN peripheral.

7.11.4.1 Functional Overview

CAN performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbit/s. Additional transceiver hardware is required for the connection to the physical layer (CAN bus). For communication on a CAN network, individual message objects can be configured. The message objects and identifier masks are stored in the Message RAM. All functions concerning the handling of messages are implemented in the message handler. Those functions are: acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of transmission requests. The register set of the CAN is accessible directly by the CPU through the module interface. These registers are used to control/configure the CAN Core and the message handler, and to access the message RAM. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX1 CPU REGISTER ACCESS M3SSCLK CAN (M3) M3CLKENBx M3 CLOCKSM3 NVICCANxIRQ CANxCLK INTR

32 MESSAGE

OBJECT ACCESS (IFX) MODULE INTERFACE Figure 7-33. CAN (Cortex-M3)

7.11.5 Cortex-M3 Universal Serial Bus Controller

This device has one Cortex-M3 USB controller. The USB controller operates as a full-speed or low-speed function controller during point-to-point communications with the USB Host, Device, or OTG functions. The controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Thirty-two endpoints, which comprised of 2 hardwired endpoints for control transfers (one endpoint for IN and one endpoint for OUT) and 30 endpoints defined by firmware, along with a dynamic sizable FIFO, support multiple packet queuing. DMA access to the FIFO allows minimal interference from system software. Software-controlled connect and disconnect allow flexibility during USB device start-up. The controller complies with the Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) of the OTG standard. The USB controller includes the following features:

• Complies with USB-IF certification standards
• USB 2.0 full-speed (12-Mbps) and low-speed (1.5-Mbps) operation
• Integrated PHY
• Four transfer types: Control, Interrupt, Bulk, and Isochronous
• 32 endpoints: – One dedicated control IN endpoint and one dedicated control OUT endpoint – 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size
• VBUS droop and valid ID detection and interrupt
• Efficient transfers using DMA: – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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• Electrical specifications are compliant with the USB Specification Rev. 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of the USB system are integrated within the Concerto microcontroller and are specific to its design. Figure 7-34 shows the USB peripheral.

7.11.5.1 Functional Description

The USB controller provides full OTG negotiation by supporting both the SRP and the HNP. The SRP allows devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used after the initial session request protocol has powered the bus and provides a method to determine which end of the cable will act as the Host controller. When the device is connected to non-OTG peripherals or devices, the controller can detect which cable end was used and provides a register to indicate if the controller should act as the Host controller or the Device controller. This indication and the mode of operation are handled automatically by the USB controller. This autodetection allows the system to use a single A/B connector instead of having both A and B connectors in the system, and supports full OTG negotiations with other OTG devices. In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers. The USB controller can be configured to act as either a dedicated Host or Device, in which case, the USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal. Note When the USB is used, the system clock frequency (SYSCLK) must be at least 20 MHz. CPU REGISTER ACCESS M3SSCLK USBCLKENB M3 CLOCKSM3 NVIC USBMAC_IRQ INTR USB uDMA DMAxREQ TX/RX FIFO ACCESS USBMAC REQ PIN USB0DM PIN PIN PIN GPIO_MUX1 PACKET ENCODE PACKET DECODE CRC GEN/CHECK PACKET ENCODE / DECODE CYCLE CONTROL RX BUFF RX BUFF TX BUFF TX BUFF FIFO RAM CONTROLLER TRANSMIT RECEIVE EP 0-31 CONTROL COMBINE ENDPOINTS HOST TRANSACTION SCHEDULER ENDPOINT CONTROLCPU INTERFACE INTERRUPT CONTROL EP REGISTER DECODER COMMON REGS CYCLE CONTROL FIFO DECODER DAT A SYNC HNP / SRP TIMERS UTM SYNCHRONIZATION PIN PIN USB0DP USB0VBUS USB0ID USB0EPEN USB0PFLT PHY USBPLLCLK (5V TOLERANT) (5V TOLERANT) Figure 7-34. USB www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 107 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.11.6 Cortex-M3 Ethernet Media Access Controller

The Cortex-M3 EMAC conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. This device has one Ethernet Media Access Controller. The EMAC module has the following features:

• Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant
• Multiple operational modes – Full- and half-duplex 100-Mbps – Full- and half-duplex 10-Mbps – Power-saving and power-down modes
• Highly configurable: – Programmable MAC address – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts
• IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
• Efficient transfers using the Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive channel request asserted on packet receipt – Transmit channel request asserted on empty transmit FIFO Figure 7-35 shows the EMAC peripheral.

7.11.6.1 Functional Overview

The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. The MAC resides inside the device, and the PHY outside of the device. These layers correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the Ethernet Controller through the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the external PHY layer through an internal Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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GPIO_MUX1 INTR CONTROL MACIACK REG CPU REGISTER ACCESS M3SSCLK EMAC EMACCLKENB M3 CLOCKSM3 NVICEMAC_IRQ MACIM REG EMACTX_REQ INTR MACRIS REG uDMA DMAxREQ TX/RX FIFO ACCESS TIMER SUPPORT MACTS REG INDIVIDUAL ADDRESS MACIA0 REG MACIA1 REG RECEIVE CONTROL MACRCTL REG MACNP REG DATA ACCESS MACDDATA REG TRANSMIT CONTROL MACTHR REG MACTR REG MACTCTL REG MII CONTROL MACMDV REG MACMTXD REG MACMCTL REG MACMRXD REG MADIX REG TRANSMIT FIFO RECEIVE FIFO MDIO EMACRX_REQ MIITXCLK MIITXD(3:0) MIITXEN PIN PIN MIICOL PIN PIN PIN MIIRXCLK MIIRXD(3:0) MIIRXER PIN PIN MIIRXDV PIN MDIO_CK MDIO_D PIN PIN MACMAR REG Figure 7-35. EMAC

7.11.6.2 MII Signals

The individual EMAC and Management Data Input/Output (MDIO) signals for the MII interface are summarized in Table 7-16. Table 7-16. EMAC and MDIO Signals for MII Interface SIGNAL TYPE(1) DESCRIPTION MIITXCK I Transmit clock. The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MIITXD and MIITXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation. MIITXER O This pin is always driven low from the MAC controller on the device. MIITXD[3-0] O Transmit data. The transmit data pins are a collection of four data signals comprising 4 bits of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MIITXCLK and are valid only when MIITXEN is asserted. MIITXEN O Transmit enable. The transmit enable signal indicates that the MIITXD pins are generating nibble data for use by the PHY. MIITXEN is driven synchronously to MIITXCLK. MIICOL I Collision detected. In half-duplex operation, the MIICOL pin is asserted by the PHY when the PHY detects a collision on the network. The MIICOL pin remains asserted while the collision condition persists. This signal is not necessarily synchronous to MIITXCLK or MIIRXCLK. In full-duplex operation, the MIICOL pin is used for hardware transmit flow control. Asserting the MIICOL pin will stop packet transmissions; packets in the process of being transmitted when MIICOL is asserted will complete transmission. The MIICOL pin should be held low if hardware transmit flow control is not used. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 7-16. EMAC and MDIO Signals for MII Interface (continued) SIGNAL TYPE(1) DESCRIPTION MIICRS I Carrier sense. In half-duplex operation, the MIICRS pin is asserted by the PHY when the network is not idle in either transmit or receive. The pin is deasserted when both transmit and receive are idle. This signal is not necessarily synchronous to MIITXCLK or MIIRXCLK. In full-duplex operation, the MIICRS pin should be held low. MIIRXCK I Receive clock. The receive clock is a continuous clock that provides the timing reference for receive operations. The MIIRXD, MIIRXDV, and MIIRXER signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation. MIIRXD[3-0] I Receive data. The receive data pins are a collection of four data signals comprising 4 bits of data. MRDX0 is the least-significant bit. The signals are synchronized by MIIRXCLK and are valid only when MIIRXDV is asserted. MIIRXDV I Receive data valid. The receive data valid signal indicates that the MIIRXD pins are generating nibble data for use by the EMAC. MIIRXDV is driven synchronously to MIIRXCLK. MIIRXER I Receive error. The receive error signal is asserted for one or more MIIRXCLK periods to indicate that an error was detected in the received frame. The MIIRXER signal being asserted is meaningful only during data reception when MIIRXDV is active. MDIO_CK O Management data clock. The MDIO data clock is sourced by the MDIO module on the system. MDIO_CK is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO Control Register (CONTROL). MDIO_D I/O Management data input output. The MDIO data pin drives PHY management data into and out of the PHY by way of an access frame that consists of start-of-frame, read/write indication, PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles, at which time the pin is an input for read operations. (1) I = Input, O = Output, I/O = Input/Output F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.11.6.3 EMAC Electrical Data and Timing

7.11.6.3.1 Timing Requirements for MIITXCK (see Figure 7-36)

NO.

100 Mbps 10 Mbps

1 tc(TXCK) Cycle time, MIITXCK (25 MHz) 40 40 ns Cycle time, MIITXCK (2.5 MHz) 400 400 2 tw(TXCKH) Pulse duration, MIITXCK high 16 24 196 204 ns 3 tw(TXCKL) Pulse duration, MIITXCK low 16 24 196 204 ns

7.11.6.3.2 MIITXCK Timing Diagrams

Figure 7-36. 100/10Mb/s MII Transmit Clock Timing

7.11.6.3.3 Timing Requirements for MIIRXCK (see Figure 7-37)

NO. 1 tc(RXCK) Cycle time, MIIRXCK (25 MHz) 40 40 ns Cycle time, MIIRXCK (2.5 MHz) 400 400 2 tw(RXCKH) Pulse duration, MIIRXCK high 16 24 196 204 ns 3 tw(RXCKL) Pulse duration, MIIRXCK low 16 24 196 204 ns

7.11.6.3.4 MIIRXCK Timing Diagram

Figure 7-37. 100/10Mb/s MII Receive Clock Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.11.6.3.5 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC

MII Transmit (see Figure 7-38) NO. PARAMETER MIN MAX UNIT 1 td(TXCKH-MTXDV) Delay time, MIITXCK high to transmit selected signals valid 5 25 ns

7.11.6.3.6 EMAC MII Transmit Timing Diagram

MIITXD[3:0], MIITXEN Figure 7-38. 100/10Mb/s MII Transmit Timing

7.11.6.3.7 Timing Requirements for EMAC MII Receive (see Figure 7-39)

NO. MIN NOM MAX UNIT 1 tsu(MRXDV-RXCKH) Setup time, receive selected signals valid before MIIRXCK high 8 ns 2 th(RXCKH-MRXDV) Hold time, receive selected signals valid after MIIRXCK high 7 ns

7.11.6.3.8 EMAC MII Receive Timing Diagram

MIIRXD[3:0], MIIRXDV, MIIRXER (Inputs) Figure 7-39. 100/10Mb/s MII Receive Timing F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.11.6.4 MDIO Electrical Data and Timing

7.11.6.4.1 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for

MDIO_CK (see Figure 7-40) NO. PARAMETER MIN MAX UNIT 1 tc(MCK) Cycle time, MDIO_CK (2.5 MHz) 400 400 ns 2 tw(MCKH) Pulse duration, MDIO_CK high 196 204 ns 3 tw(MCKL) Pulse duration, MDIO_CK low 196 204 ns

7.11.6.4.2 MDIO_CK Timing Diagram

MDIO_CK Figure 7-40. MII Serial Management Timing

7.11.6.4.3 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO

as Output (see Figure 7-41) NO. PARAMETER MIN MAX UNIT 1 td(MCKH-MDV) Delay time, MDIO_CK high to MDIO_D valid 5 25 ns

7.11.6.4.4 MDIO as Output Timing Diagram

MDIO_CK MDIO_D Figure 7-41. MII Serial Management Timing – MDIO as Output

7.11.6.4.5 Timing Requirements for MDIO as Input (see Figure 7-42)

NO. MIN NOM MAX UNIT 4 tsu(MDV-MCKH) Setup time, MDIO_D valid before MDIO_CK high 20 ns 5 th(MCKH-MDV) Hold time, MDIO_D valid after MDIO_CK high 7 ns

7.11.6.4.6 MDIO as Input Timing Diagram

MDIO_CK MDIO_D (Input) Figure 7-42. MII Serial Management Timing – MDIO as Input www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.12 Control Subsystem Peripherals

Control Subsystem peripherals are accessible from the C28x CPU through the C28x Memory Bus, and from the C28x DMA through the C28x DMA Bus. They include one NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI, McBSP, I2C), and three types of Control Peripherals (ePWM, eQEP, eCAP). Additionally, the C28x CPU/DMA also have access to the EPI, and to Analog and Shared peripherals (see Section 7.10). For detailed information on the processor peripherals, see the Concerto F28M35x Technical Reference Manual.

7.12.1 High-Resolution PWM and Enhanced PWM Modules

There are nine PWM modules in the Concerto device. Eight of these are of the HRPWM type with high- resolution control on both A and B signal outputs, and one is of the ePWM type. The HRPWM modules have all the features of the ePWM plus they offer significantly higher PWM resolution (time granularity on the order of 150 ps). Figure 7-43 shows the eight HRPWM modules (PWM 1–8) and one ePWM module (PWM 9). The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output SYNCO1 comes from the ePWM1 module and is stretched by 8 HSPCLK cycles before entering GPIO_MUX1. There are two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from GPTRIP1–12 (from GPIO_MUX1), ECCDBLERR signal (from C28x Local and Shared RAM), and PIEERR signal from the C28x CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1), EQEPERR (from the eQEP peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the C28x CPU). There are 9 SOCA PWM outputs and 9 SOCB PWM outputs—a pair from each PWM module. The 9 SOCA outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as a single SOCAO signal. The 9 SOCB outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs from PWM1–PWM9 also go to the Analog Subsystem, where they can be selected to become conversion triggers to ADC modules. The nine PWM modules also drive two other sets of outputs which can interrupt the C28x CPU through the C28x PIE block. These are nine EPWMINT interrupts and nine EPWMTZINT trip-zone interrupts. See Figure 7-44 for the internal structure of the HRPWM and ePWM modules. The green-colored blocks are common to both ePWM and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution blocks. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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GPIO_MUX1 PULSE STRETCH

32 HSPCLK CYCLES

ECCDBLERR EMUSTOP CLOCKFAILGPTRIP(1-12) GPTRIP7 GPTRIP8 GPTRIP9 GPTRIP10 GPTRIP11 GPTRIP12 ECAP1INP ECAP2INP ECAP3INP ECAP4INP ECAP5INP ECAP6INP PULSE STRETCH

8 HSPCLK CYCLES

LEGEND: ECAP ECAP ECAP ECAP ECAP ECAP EPWM (9:1) B EPWM (9:1) A ECAP(6:1) EQEP 1 EQEP 2 EQEP3 EQEP(3:1)INT ECAP(6:1)INT EPWM (9:1) TZINT EPWM (9:1) INT EQEP1A EQEP1B EQEP1S EQEP1I EQEP2A EQEP2B EQEP2S EQEP2I EQEP3A EQEP3B EQEP3S EQEP3I SOCA (9:1) SOCB(9:1) CPCLKCR0 REG TRIPIN1 TRIPIN2 TRIPIN3 TRIPIN4 TRIPIN5 TRIPIN6 TRIPIN7 TRIPIN8 TRIPIN9 TRIPIN10 TRIPIN11 TRIPIN12 TRIPIN13 TRIPIN14 TRIPIN15 GPTRIP1 GPTRIP2 GPTRIP3 GPTRIP4 GPTRIP5 GPTRIP6 GPTRIP7 GPTRIP8 GPTRIP9 GPTRIP10 GPTRIP11 GPTRIP12 ECCDBLERR PIEERR GPTRIP6 SYNCI TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 GPTRIP1 GPTRIP2 GPTRIP3 EQEPERR CLOCKFAIL EMUSTOP PIEERR SHARED RAMC28x LOCAL RAM SYNCO ‘0’ SYNCI GPIO_MUX1 PWM PWM PWM PWM PWM PWM PWM PWM PWM SYNCO EPWM ECAP EQEP Copyright © 2017, Texas Instruments Incorporated Figure 7-43. PWM, eCAP, eQEP www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

(TB) COUNTER COMPARE (CC) ACTION QUALIFIER (AQ) DEAD BAND (DB) PWM CHOPPER (PC) DIGITAL COMPARE (DC) TRIP ZONE (TZ) EVENT TRIGGER (ET) CTR=PRD CTR_DIR CTR=ZER DCAEVT1.SYNC DCBEVT1.SYNC CTR=CMPA CTR=CMPB SYNCI SYNCO (1) SWFSYNC SYNCI DCBEVT1.SOC DCAEVT1.SOC CTR=PRDCTR=ZER EPWM_A EPWM_INT EPWM_B TRIPIN(15:1) SOCA SOCB TBCLK C28SYSCLK HiRES CONTROL CMPB CMPA PHS FEDREDDCAEVT1.SYNC DCBEVT1.SYNC CNTRL CAL TBCTR (15:0) TBCLK CTR=ZER CTR=PRD TBCTR (15:0) TZ (6:1) EPWM_TZINT TBCLKSYNC PRD DCBEVT1.SOC DCAEVT1.SOC C28SYSCLK HiRES PWM (HRPWM) EPWM_INT SYNCI CTR=CMPA CTR=CMPB CTR=CMPC CTR=CMPD CTR= CMPB CTR=ZER CTR=PRD CTR_DIR DCAEVT1.FORCE DCAEVT2.FORCE DCAEVT1.INTER DCAEVT2.INTER DCBEVT1.FORCE DCBEVT2.FORCE DCBEVT1.INTER DCBEVT2.INTER (1) SYNCO OUTPUTS FROM PWM MODULES 3,6 AND 9 ARE NOT CONNECTED , THUS THEY ARE NOT USEABLE. Copyright © 2017, Texas Instruments Incorporated Figure 7-44. Internal Structure of PWM

7.12.1.1 HRPWM Electrical Data and Timing

7.12.1.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)

PARAMETER MIN TYP MAX UNIT Micro Edge Positioning (MEP) step size(1) 150 310 ps (1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher temperature and lower voltage and decrease with lower temperature and higher voltage. Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation. 7.12.1.2 ePWM Electrical Data and Timing characteristics. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.12.1.2.1 ePWM Timing Requirements MIN(1) MAX UNIT tw(SYCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles 7.12.1.2.2 ePWM Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tw(PWM) Pulse duration, PWMx output high/low 20 ns tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles td(PWM)tza Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low no pin load 25 ns td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.12.1.2.3 Trip-Zone Input Timing

MIN(1) MAX UNIT tw(TZ) Pulse duration, TZx input low Asynchronous 1tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles PWM (B) TZ (A) SYSCLK tw(TZ) td(TZ-PWM)HZ A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6 B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 7-45. PWM Hi-Z Characteristics F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.12.2 Enhanced Capture Module

There are six identical eCAP modules in Concerto devices: eCAP1, 2, 3, 4, 5, and 6. Each eCAP module represents one complete capture channel. Its main function is to accurately capture the timings of external events. One can also use eCAP modules for PWM, when they are not being used for input captures. This secondary function is selected by flipping the CAP/APWM bit of the ECCTL2 Register. For PWM function, the counter operates in count-up mode, providing a time base for asymmetrical pulse width (PWM) waveforms. The CAP1 and CAP2 registers become the period and compare registers, respectively; while the CAP3 and CAP4 registers become the shadow registers of the main period and capture registers, respectively. The left side of Figure 7-46 shows internal components associated with the capture block, and the right side depicts the PWM block. The two blocks share a set of four registers that are used in both Capture and PWM modes. Other components include the Counter block that uses the SYNCIN and SYNCOUT ports to synchronize with other modules; and the Interrupt Trigger and Flag Control block that sends Capture, PWM, and Counter events to the C28x PIE block through the ECAPxINT output. There are six ECAPxINT interrupts—one for each eCAP module. The eCAP peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers. 7.12.2.1 eCAP Electrical Data and Timing characteristics. 7.12.2.1.1 eCAP Timing Requirement MIN(1) MAX UNIT tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles 7.12.2.1.2 eCAP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tw(APWM) Pulse duration, APWMx output high/low 20 ns www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX1 PWM MODE MODE SELECT CAPTURE CONTROL INTERRUPT TRIGGER AND FLAG CONTROL CEVT (4:1) (CAPTURE EVENTS) 4 4 C28x PIE LD1 LD2 LD3 LD4 CTR_OVF CTRPHS REG CTR=PER CTR=CMP PRD(31:0) CMP(31:0) CTR(31:0) RST DELTA MODE TSCTR REGCOUNTER SYNC IN EPWM1 OR OTHER ECAP PERIPHERALS SYNC OUT OTHER ECAP PERIPHERALS C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK ECAPxENCLK MASTER SUBSYSTEM CTR_OVF ECAPx ECCTL2 REG ECAPxINT SYNCIN SYNCOUT ECAPx Copyright © 2017, Texas Instruments Incorporated Figure 7-46. eCAP

7.12.3 Enhanced Quadrature Encoder Pulse Module

The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and speed information from rotating machines used in high-performance motion and position-control systems. There are three Type 0 eQEP modules in each Concerto device. Each eQEP peripheral comprises five major functional blocks: Quadrature Capture Unit (QCAP), Position Counter/Control Unit (PCCU), Quadrature Decoder (QDU), Unit Time Base for speed and frequency measurement (UTIME), and Watchdog timer for detecting stalls (QWDOG). The C28x CPU controls and communicates with these modules through a set of associated registers (see Figure 7-47 ). The eQEP peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers. Each eQEP peripheral connects through the GPIO_MUX1 block to four device pins. Two of the four pins are always inputs, while the other two can be inputs or outputs, depending on the operating mode. The PCCU block of each eQEP also drives one interrupt to the C28x PIE. There is a total of three EQEPxINT interrupts—one from each of the three eQEP modules. 7.12.3.1 eQEP Electrical Data and Timing characteristics. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.12.3.1.1 eQEP Timing Requirements MIN(1) MAX UNIT tw(QEPP) QEP input period Asynchronous(2)/synchronous 2tc(SCO) cycles With input qualifier 2[1tc(SCO) + tw(IQSW)] cycles tw(INDEXH) QEP Index Input High time Asynchronous(2)/synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(INDEXL) QEP Index Input Low time Asynchronous(2)/synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBH) QEP Strobe High time Asynchronous(2)/synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBL) QEP Strobe Input Low time Asynchronous(2)/synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles (2) Refer to the F28M35x Concerto™ MCUs Silicon Errata for limitations in the asynchronous mode. 7.12.3.1.2 eQEP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SCO) cycles QCPRD REG QCTMR REG QWDTMR REG QWDPRD REG QUTMR REG QUPRD REG QFLG REG QEPCTL REG QEPSTS REG REGISTERS USED BY MULTIPLE UNITS OCTMRLAT REG QCPRDLAT REG QPOSILAT REG QPOSLAT REG QPOSSLAT REG QPOSMAX REG QPOSCNT REG QPOSINIT REG QCLR REG QEINT REG QFRC REG QPOSCTL REG QPOSCMP REG QDECCTL REG UTIME QWDOG 1632 1632 32 QCAPCTL REG POSITION COUNTER/CONTROL UNIT ( PCCU ) QUADRATURE CAPTURE UNIT ( QCAP ) QUADRATURE DECODER ( QDU ) EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE QCLK WDTOUT UTOUT QDIR QI QS PHE PCSOUT PIN EQEPxS EQEPxI EQEPxB /XDIR EQEPxA /XCLK PIN PIN PIN GPIO_MUX1 C28x PIE EQEPxINT C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK EQEPxENCLK MASTER SUBSYSTEM EQEPx Copyright © 2017, Texas Instruments Incorporated Figure 7-47. eQEP www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.12.4 C28x Inter-Integrated Circuit Module

This device has one C28x I2C peripheral. The I2C provides an interface between a Concerto device and devices compliant with the NXP® I2C-bus specification and user manual (UM10204) and connected by way of an I2C bus. External components attached to this 2-wire serial bus can transmit 1-bit to 8-bit data to and receive 1-bit to 8-bit data from the device through the I2C module. Note A unit of data transmitted or received by the I2C module can have fewer than 8 bits; however, for convenience, a unit of data is called a data byte in this section. The number of bits in a data byte is selectable through the BC bits of the mode register, I2CMDR. The I2C module has the following features:

• Compliance with the NXP I2C-bus specification and user manual (UM10204): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit-and-receive and receive-and-transmit mode – Data transfer rate of from 10 Kbps up to 400 Kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable or disable capability
• Free data format mode The I2C module does not support:
• High-speed mode (Hs-mode)
• CBUS-compatibility mode Figure 7-48 shows the C28x I2C peripheral. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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GPIO_MUX1 I C (C28) I2CINT1A INTR TX FIFO RX FIFO I2CXSR REG I2CDRR REG I2CRXR REG I2CDXR REG I2CIER REG C28x PIE I2CINT2A C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK I2CA_ENCLK MASTER SUBSYSTEM SLAVE CLOCK SYNCHRONIZER INTERRUPT CONTROL AND ARBITRATION CLOCK PRESCALER I2CCLK I2COAR REG I2CCLKL REG I2CCLKH REG I2CCNT REG I2CSAR REG I2CMDR REG I2CISRC REG I2CPSC REG I2CFFTX REG I2CFFRX REG MASTER CLOCK DIVIDER MODE AND STATUS REGISTERS I2CSTR REG I2CCLK REGISTER ACCESS CLK TX/RX LOGIC Figure 7-48. I2C (C28x)

7.12.4.1 Functional Overview

Each device connected to an I2C Bus is recognized by a unique address. Each device can operate as either a transmitter or a receiver, depending on the function of the device. A device connected to the I2C Bus can also be considered as the master or the slave when performing data transfers. A master device is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. During this transfer, any device addressed by this master is considered a slave. The I2C module supports the multi-master mode, in which one or more devices capable of controlling an I2C Bus can be connected to the same I2C Bus. For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL). These two pins carry information between the C28x device and other devices connected to the I2C Bus. The SDA and SCL pins both are bidirectional. They each must be connected to a positive supply voltage using a pullup resistor. When the bus is free, both pins are high. The driver of these two pins has an open-drain configuration to perform the required wired-AND function. There are two major transfer techniques: 1. Standard Mode: Send exactly n data values, where n is a value you program in an I2C module register. 2. Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new START condition. The I2C module consists of the following primary blocks:

• A serial interface: one data pin (SDA) and one clock pin (SCL)
• Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the SDA pin and the CPU
• Control and status registers
• A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs.

7.12.4.2 Clock Generation

The device clock generator receives a signal from an external clock source and produces an I2C input clock with a programmed frequency. The I2C input clock is equivalent to the CPU clock and is then divided twice more inside the I2C module to produce the module clock and the master clock. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 123 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.12.4.3 I2C Electrical Data and Timing

7.12.4.3.1 I2C Timing

TEST CONDITIONS MIN MAX UNIT fSCL SCL clock frequency I2C clock module frequency is between and clock divider registers are configured appropriately 400 kHz vil Low level input voltage 0.3 VDDIO V Vih High level input voltage 0.7 VDDIO V Vhys Input hysteresis 0.05 VDDIO V Vol Low level output voltage 3 mA sink current 0 0.4 V tLOW Low period of SCL clock I2C clock module frequency is between and clock divider registers are configured appropriately 1.3 μs tHIGH High period of SCL clock I2C clock module frequency is between and clock divider registers are configured appropriately 0.6 μs lI Input current with an input voltage between 0.1 VDDIO and 0.9 VDDIO MAX –10 10 μA F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.12.5 C28x Serial Communications Interface

This device has one SCI peripheral. SCI is a two-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit baud-select register. Features of the SCI module include:

• Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin Note Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates
• Data-word format – One start bit – Data-word length programmable from 1 to 8 bits – Optional even/odd/no parity bit – One or two stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format Note All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect.
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO Figure 7-49 shows the C28x SCI peripheral. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 125 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX1 SCI (C28) SCIRXINA INTR C28x PIE C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK SCIA_ENCLK MASTER SUBSYSTEM C28LSPCLK /14 TXSHF REG RXSHF REG SCITXINA REGISTER ACCESS TX FIFO RX FIFO RX INTERRUPT LOGIC TX INTERRUPT LOGIC SCIRXBUF REG SCITXBUF REG SCIPRI REG SCIFFTXA REG SCIFFRXA REG SCICCRA REG SCRXST REG SCICTL2 REG SCIRXEMUA REG SCICTL1A REG BAUD-RATE GEN SCIHBAUD REG SCILBAUD REG TX DELAY SCEFFCT REG AUTO-BAUD DETECT LOGIC TX/RX LOGIC Figure 7-49. SCI (C28x)

7.12.5.1 Architecture

The major elements used in full-duplex operation include:

• A transmitter (TX) and its major registers: – SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be transmitted – TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto the SCITXD pin, 1 bit at a time
• A receiver (RX) and its major registers: – RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time – SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU registers
• A programmable baud generator
• Data-memory-mapped control and status registers enable the CPU to access the I2C module registers and FIFOs. The SCI receiver and transmitter can operate either independently or simultaneously.

7.12.5.2 Multiprocessor and Asynchronous Communication Modes

The SCI has two multiprocessor protocols: the idle-line multiprocessor mode and the address-bit multiprocessor mode. These protocols allow efficient data transfer between multiple processors. The SCI offers the UART communications mode for interfacing with many popular peripherals. The asynchronous mode requires two lines to interface with many standard devices such as terminals and printers that use RS-232-C formats. Data transmission characteristics include:

• One start bit
• One to eight data bits F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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• An even/odd parity bit or no parity bit
• One or two stop bits with a programmed frequency

7.12.6 C28x Serial Peripheral Interface

This device has one C28x SPI. The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit- transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The port supports a 16-level, receive-and-transmit FIFO for reducing CPU servicing overhead. The SPI module features include:

• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin Note All four pins can be used as GPIO, if the SPI module is not used.
• Two operational modes: master and slave
• Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the maximum speed of the I/O buffers used on the SPI pins.
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
• Twelve SPI module control registers: Located in control register frame beginning at address 7040h. Note All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (bits 7 −0), and the upper byte (bits 15 −8) is read as zeros. Writing to the upper byte has no effect.
• 16-level transmit and receive FIFO
• Delayed transmit control Figure 7-50 shows the C28x SPI peripheral. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 127 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX1 SPI (C28) SPIRXINA INTR TX FIFO (1) RX FIFO (1) C28x PIE C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK SPIA_ENCLK MASTER SUBSYSTEM SPI BIT RATEC28LSPCLK /14 RX INTERRUPT LOGIC SPITXINA TX INTERRUPT LOGIC REGISTER ACCESS SPICCR REG SPICTL REG SPIST REG SPIBRR REG SPIRXEMU REG SPIRXBUF REG SPITXBUF REG SPIDAT REG SPIFFTX REG SPIFFRX REG SPIFFCT REG SPIPRI REG PIN SPICLKA SPISTEA PIN TX DELAY TX/RX LOGIC (1) RX FIFO AND TX FIFO CAN BE BYPASSED BY CONFIGURING BIT SPIF FENA OF THE SPIFFTX REGISTER Figure 7-50. SPI (C28x)

7.12.6.1 Functional Overview

The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive data simultaneously. The application software determines whether the data is meaningful or dummy data. There are three possible methods for data transmission:

• Master sends data; slave sends dummy data
• Master sends data; slave sends data
• Master sends dummy data; slave sends data The master can initiate a data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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7.12.6.2 SPI Electrical Data and Timing

This section contains both Master Mode and Slave Mode timing data.

7.12.6.2.1 Master Mode Timing

mode timing (clock phase = 1). Figure 7-51 and Figure 7-52 show the timing waveforms. NO.(1) (2) (3) (4) (5) PARAMETER BRR EVEN BRR ODD UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns 2 tw(SPC1)M Pulse duration, SPICLK first pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M + 0.5tc(LSPCLK) – 10 0.5tc(SPC)M + 0.5tc(LSPCLK) + 10 ns 3 tw(SPC2)M Pulse duration, SPICLK second pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M – 0.5tc(LSPCLK) – 10 0.5tc(SPC)M – 0.5tc(LSPCLK) + 10 ns 4 td(SIMO)M Delay time, SPICLK to SPISIMO valid 10 10 ns 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK) – 10 ns 8 tsu(SOMI)M Setup time, SPISOMI before SPICLK 35 35 ns 9 th(SOMI)M Hold time, SPISOMI valid after SPICLK 0 0 ns 23 td(SPC)M Delay time, SPISTE active to SPICLK 1.5tc(SPC)M – 3tc(SYSCLK) – 10 1.5tc(SPC)M – 3tc(SYSCLK) – 10 ns 24 td(STE)M Delay time, SPICLK to SPISTE inactive 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK) – 10 ns (1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1) (3) tc(LCO) = LSPCLK cycle time (4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX. (5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 129 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

(clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is V alid SPISTE 23 24 Figure 7-51. SPI Master Mode External Timing (Clock Phase = 0) F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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NO.(1) (2) (3) (4) (5) PARAMETER BRR EVEN BRR ODD UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns 2 tw(SPC1)M Pulse duration, SPICLK first pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M – 0.5tc(LSPCLK) – 10 0.5tc(SPC)M – 0.5tc(LSPCLK) + 10 ns 3 tw(SPC2)M Pulse duration, SPICLK second pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M + 0.5tc(LSPCLK) – 10 0.5tc(SPC)M + 0.5tc(LSPCLK) + 10 ns 6 td(SIMO)M Delay time, SPISIMO valid to SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LSPCLK) – 10 ns 7 tv(SIMO)M Valid time, SPISIMO valid after SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK) – 10 ns 10 tsu(SOMI)M Setup time, SPISOMI before SPICLK 35 35 ns 11 th(SOMI)M Hold time, SPISOMI valid after SPICLK 0 0 ns 23 td(SPC)M Delay time, SPISTE active to SPICLK 2tc(SPC)M – 3tc(SYSCLK) – 10 2tc(SPC)M – 3tc(SYSCLK) – 10 ns 24 td(STE)M Delay time, SPICLK to SPISTE inactive 0.5tc(SPC) – 10 0.5tc(SPC) – 0.5tc(LSPCLK) – 10 ns (1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX. (4) tc(LCO) = LSPCLK cycle time (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is V alid 23 24 SPISTE Figure 7-52. SPI Master Mode External Timing (Clock Phase = 1) www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.12.6.2.2 Slave Mode Timing

timing (clock phase = 1). Figure 7-53 and Figure 7-54 show the timing waveforms. NO. (1) (2) (4) (3) (5) PARAMETER MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns 13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns 14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns 15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 35 ns 16 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns 19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns 20 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns 25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns 26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) tc(LCO) = LSPCLK cycle time (4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX. (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid SPISTE Figure 7-53. SPI Slave Mode External Timing (Clock Phase = 0) F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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NO. (1) (2) (3) (4) PARAMETER MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns 13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns 14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns 17 td(SOMI)S Delay time, SPICLK to SPISOMI valid 35 ns 18 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns 21 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns 22 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns 25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns 26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX. (4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid 21 18 SPISTE Data ValidData Valid 1413 25 26 Figure 7-54. SPI Slave Mode External Timing (Clock Phase = 1) www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 133 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.12.7 C28x Multichannel Buffered Serial Port

This device provides one high-speed McBSP that allows direct interface to codecs and other devices. The CPU accesses data, control, and status information. The MCBSP also supports µDMA transfers. The McBSP consists of a data-flow path and a control path connected to external devices by six pins. Data is communicated to devices interfaced with the McBSP through the data transmit (DX) pin for transmission and through the data receive (DR) pin for reception. Control information in the form of clocking and frame synchronization is communicated through the following pins: CLKX (transmit clock), CLKR (receive clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization). The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible through the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX through the transmit shift registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers (RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows simultaneous movement of internal and external data communications. DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is 8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant bits. The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads instead of the CLKR and FSR pins. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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McBSP features include:

• Full-duplex communication
• Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
• Independent clocking and framing for reception and transmission
• The capability to send interrupts to the CPU and to send DMA events to the DMA controller
• 128 channels for transmission and reception
• Multichannel selection modes that enable or disable block transfers in each of the channels
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D and D/A devices
• Support for external generation of clock signals and frame-synchronization signals
• A programmable sample rate generator for internal generation and control of clock signals and frame synchronization signals
• Programmable polarity for frame-synchronization pulses and clock signals
• Direct interface to: – T1/E1 framers – IOM-2 compliant devices – AC97-compliant devices (the necessary multi-phase frame capability is provided) – I2S compliant devices – SPI devices
• A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits Note A value of the chosen data size is referred to as a serial word or word in this section. Elsewhere, word is used to describe a 16-bit value.
• µ-law and A-law companding
• The option of transmitting/receiving 8-bit data with the LSB first
• Status bits for flagging exception/error conditions
• ABIS mode is not supported Figure 7-55 shows the C28x McBSP peripheral. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX1 MRINTA INTR C28x PIE C28x CPU ALL REG ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK MCBSPA_ENCLK MASTER SUBSYSTEM C28LSPCLK /14 MXINTA REG ACCESS PIN MFSRA MCLKRA PIN MDRA PIN PIN MFSXA MCLKXA PIN MDXA PIN C28 DMA DRR / DXR REG ACCESS DRR1 REG DRR2 REG DXR2 REG DXR1 REG EXPAND COMPRESS RBR REG RSR REG XSR REG SPCR2 REG SPCR1 REG SRGR2 REG SRGR1 REG SPCR2 REG SPCR1 REG XCR2 REG XCR1 REG GENERATION AND CONTROL OF CLOCK AND FRAME SYNC PERIPH LOGIC RX/TX INTERRUPT LOGIC MFFINT REG MCR2 REG RCERA REG RCERB REG RCERC REG RCERD REG RCERE REG RCERF REG RCERG REG RCERH REG XCERA REG XCERB REG XCERC REG XCERD REG XCERE REG XCERF REG XCERG REG XCERH REG MCR1 REG PCR REG MULTI - CHANNEL SELECTION MCBSP (128 CHAN) Figure 7-55. McBSP (C28x)

7.12.7.1 McBSP Electrical Data and Timing

7.12.7.1.1 McBSP Transmit and Receive Timing

NO.(1) (2) MIN MAX UNIT McBSP module clock (CLKG, CLKX, CLKR) range 1 kHz 25 (3) MHz McBSP module cycle time (CLKG, CLKX, CLKR) range 40 ns 1 ms M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 7 ns M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 18 ns CLKR ext 2 M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 0 ns CLKR ext 6 M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 18 ns CLKR ext 5 M18 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 0 ns CLKR ext 3 M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 18 ns CLKX ext 2 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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NO.(1) (2) MIN MAX UNIT M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 0 ns CLKX ext 6 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed. (3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (30 MHz). www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

over recommended operatin xcg conditions (unless otherwise noted)(1) (2) NO. PARAMETER MIN MAX UNIT M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5 (3) D + 5 (3) ns M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5 (3) C + 5 (3) ns M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int 0 4 ns CLKR ext 3 27 M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int 0 4 ns CLKX ext 3 27 M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance following last data bit CLKX int 8 ns CLKX ext 14 M7 td(CKXH-DXV) Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. CLKX int 9 ns CLKX ext 28 Delay time, CLKX high to DX valid. Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes. DXENA = 0 CLKX int 8 CLKX ext 14 DXENA = 1 CLKX int P + 8 CLKX ext P + 14 M8 ten(CKXH-DX) Enable time, CLKX high to DX driven. Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes. DXENA = 0 CLKX int 0 ns CLKX ext 6 DXENA = 1 CLKX int P CLKX ext P + 6 M9 td(FXH-DXV) Delay time, FSX high to DX valid. Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. DXENA = 0 FSX int 8 ns FSX ext 14 DXENA = 1 FSX int P + 8 FSX ext P + 14 M10 ten(FXH-DX) Enable time, FSX high to DX driven. Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. DXENA = 0 FSX int 0 ns FSX ext 6 DXENA = 1 FSX int P FSX ext P + 6 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. (3) C = CLKRX low pulse width = P D = CLKRX high pulse width = P F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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(n−2)Bit (n−1) (n−3)(n−2)Bit (n−1) (n−4)(n−3)(n−2)Bit (n−1) M18M17 M18M17 M17 M18 M16M15 M4M4 M14 M13 M3, M12 M1, M11 M2, M12 (RDATDLY=10b) DR (RDATDLY=01b) DR (RDATDLY=00b) DR FSR (ext) FSR (int) CLKR Figure 7-56. McBSP Receive Timing M10 (XDATDLY=10b) DX (XDATDLY=01b) DX (XDATDLY=00b) DX Bit (n−1)Bit 0 Bit (n−1) (n−3)(n−2)Bit 0 (n−2)Bit (n−1)Bit 0 M20 M13 M3, M12 M1, M11 M2, M12 FSX (ext) FSX (int) CLKX M5M5 M19 Figure 7-57. McBSP Transmit Timing www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 139 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

7.12.7.1.2 McBSP as SPI Master or Slave Timing

NO.(1) MASTER SLAVE UNIT MIN MAX MIN MAX M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P + 10 ns M33 tc(CKX) Cycle time, CLKX 2P(2) 16P ns (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0) NO. PARAMETER MASTER SLAVE UNIT MIN MAX MIN MAX M24 th(CKXL-FXL) Hold time, FSX low after CLKX low 2P(1) ns M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P ns M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX M30 M31 DR M28 M24 M29 M25 LSB MSBM32 M33 Figure 7-58. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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NO.(1) MASTER SLAVE UNIT MIN MAX MIN MAX M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P + 10 ns M42 tc(CKX) Cycle time, CLKX 2P(2) 16P ns (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0) NO. PARAMETER MASTER SLAVE UNIT MIN MAX MIN MAX M34 th(CKXL-FXL) Hold time, FSX low after CLKX low P ns M35 td(FXL-CKXH) Delay time, FSX low to CLKX high 2P(1) ns M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low P + 6 7P + 6 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M35 M37 M40M39 M38 M34 LSB MSBM41 M42 Figure 7-59. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

NO.(1) MASTER SLAVE UNIT MIN MAX MIN MAX M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P + 10 ns M52 tc(CKX) Cycle time, CLKX 2P(2) 16P ns (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1) NO. PARAMETER MASTER SLAVE UNIT MIN MAX MIN MAX M43 th(CKXH-FXL) Hold time, FSX low after CLKX high 2P(1) ns M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P ns M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG M51 M50 M47 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M44 M48 M49 M43 LSB MSB M52 Figure 7-60. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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NO.(1) MASTER SLAVE UNIT MIN MAX MIN MAX M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P + 10 ns M61 tc(CKX) Cycle time, CLKX 2P(2) 16P ns (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1) NO.(1) PARAMETER MASTER(2) SLAVE UNIT MIN MAX MIN MAX M53 th(CKXH-FXL) Hold time, FSX low after CLKX high P ns M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P(1) ns M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high P + 6 7P + 6 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG (2) C = CLKX low pulse width = P D = CLKX high pulse width = P Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M54 M58 M56 M53 M55 M59 M57 LSB MSBM60 M61 Figure 7-61. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 143 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8 Detailed Description

The Concerto MCU comprises three subsystems: the Master Subsystem, the Control Subsystem, and the Analog Subsystem. While the Master and Control Subsystem each have dedicated local memories and peripherals, they can also share data and events through shared memories and peripherals. The Analog Subsystem has two ADC converters and six Analog Comparators. Both the Master and Control Subsystems access the Analog Subsystem through the Analog Common Interface Bus (ACIB). The NMI Blocks force communication of critical events to the Master and Control Subsystem processors and their Watchdog Timers. The Reset Block responds to Watchdog Timer NMI Reset, External Reset, and other events to initialize subsystem processors and the rest of the chip to a known state. The Clocking Blocks support multiple low-power modes where clocks to the processors and peripherals can be slowed down or stopped in order to manage power consumption. Note Throughout this document, the Master Subsystem is denoted by the color blue; the Control Subsystem is denoted by the color green; and the Analog Subsystem is denoted by the color orange. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.1 Memory Maps

Map.

8.1.1 Control Subsystem Memory Map

Table 8-1. Control Subsystem M0, M1 RAM C DMA ACCESS(1) C ADDRESS (x16 ALIGNED)(1) CONTROL SUBSYSTEM M0, M1 RAM SIZE (BYTES) no 0000 0000 – 0000 03FF M0 RAM (ECC) 2K no 0000 0400 – 0000 07FF M1 RAM (ECC) 2K (1) The letter "C" refers to the Control Subsystem. Table 8-2. Control Subsystem Peripheral Frame 0 C DMA ACCESS(1) C ADDRESS (x16 ALIGNED)(1) CONTROL SUBSYSTEM PERIPHERAL FRAME 0 (INCLUDES ANALOG) SIZE (BYTES) 0000 0800 – 0000 087F Reserved no 0000 0880 – 0000 0890 Control Subsystem Device Configuration Registers (Read Only) 34 0000 0891 – 0000 0ADF Reserved no 0000 0AE0 – 0000 0AEF C28x CSM Registers 32 0000 0AF0 – 0000 0AFF Reserved yes 0000 0B00 – 0000 0B0F ADC1 Result Registers 32 0000 0B10 – 0000 0B3F Reserved yes 0000 0B40 – 0000 0B4F ADC2 Result Registers 32 0000 0B50 – 0000 0BFF Reserved no 0000 0C00 – 0000 0C07 CPU Timer 0 16 no 0000 0C08 – 0000 0C0F CPU Timer 1 16 no 0000 0C10 – 0000 0C17 CPU Timer 2 16 0000 0C18 – 0000 0CDF Reserved no 0000 0CE0 – 0000 0CFF PIE Registers 64 no 0000 0D00 – 0000 0DFF PIE Vector Table 512 no 0000 0E00 – 0000 0EFF PIE Vector Table Copy (Read Only) 512 0000 0F00 – 0000 0FFF Reserved no 0000 1000 – 0000 11FF C28x DMA Registers 1K 0000 1200 – 0000 16FF Reserved no 0000 1700 – 0000 177F Analog Subsystem Control Registers 256 no 0000 1780 – 0000 17FF Hardware BIST Registers 256 0000 1800 – 0000 3FFF Reserved (1) The letter "C" refers to the Control Subsystem. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 145 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-3. Control Subsystem Peripheral Frame 3 C DMA ACCESS(1) C ADDRESS (x16 ALIGNED)(1) CONTROL SUBSYSTEM PERIPHERAL FRAME 3 SIZE (BYTES) M ADDRESS (BYTE-ALIGNED)(2) µDMA ACCESS no 0000 4000 – 0000 4181 C28x Flash Control Registers 772 0000 4182 – 0000 42FF Reserved no 0000 4300 – 0000 4323 C28x Flash ECC Error Log Registers 72 0000 4324 – 0000 43FF Reserved no 0000 4400 – 0000 443F M Clock Control Registers(2) 128 400F B800 – 400F B87F no 0000 4440 – 0000 48FF Reserved no 0000 4900 – 0000 497F RAM Configuration Registers 256 400F B200 – 400F B2FF no 0000 4980 – 0000 49FF Reserved no 0000 4A00 – 0000 4A7F RAM ECC/Parity/Access Error Log Registers 256 400F B300 – 400F B3FF no 0000 4A80 – 0000 4DFF Reserved no 0000 4E00 – 0000 4E3F CtoM and MtoC IPC Registers 128 400F B700 – 400F B77F no 0000 4E40 – 0000 4FFF Reserved yes 0000 5000 – 0000 503F McBSP-A 128 0000 5040 – 0000 50FF Reserved yes 0000 5100 – 0000 517F EPWM1 (Hi-Resolution) 256 yes 0000 5180 – 0000 51FF EPWM2 (Hi-Resolution) 256 yes 0000 5200 – 0000 527F EPWM3 (Hi-Resolution) 256 yes 0000 5280 – 0000 52FF EPWM4 (Hi-Resolution) 256 yes 0000 5300 – 0000 537F EPWM5 (Hi-Resolution) 256 yes 0000 5380 – 0000 53FF EPWM6 (Hi-Resolution) 256 yes 0000 5400 – 0000 547F EPWM7 (Hi-Resolution) 256 yes 0000 5480 – 0000 54FF EPWM8 (Hi-Resolution) 256 yes 0000 5500 – 0000 557F EPWM9 256 0000 5580 – 0000 57FF Reserved (1) The letter "C" refers to the Control Subsystem. (2) The letter "M" refers to the Master Subsystem. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-4. Control Subsystem Peripheral Frame 1 C DMA ACCESS(1) C ADDRESS (x16 ALIGNED)(1) CONTROL SUBSYSTEM PERIPHERAL FRAME 1 SIZE (BYTES) 0000 5800 – 0000 59FF Reserved no 0000 5A00 – 0000 5A1F ECAP1 64 no 0000 5A20 – 0000 5A3F ECAP2 64 no 0000 5A40 – 0000 5A5F ECAP3 64 no 0000 5A60 – 0000 5A7F ECAP4 64 no 0000 5A80 – 0000 5A9F ECAP5 64 no 0000 5AA0 – 0000 5ABF ECAP6 64 0000 5AC0 – 0000 5AFF Reserved no 0000 5B00 – 0000 5B3F EQEP1 128 no 0000 5B40 – 0000 5B7F EQEP2 128 no 0000 5B80 – 0000 5BBF EQEP3 128 0000 5BC0 – 0000 5F7F Reserved no 0000 5F80 – 0000 5FFF C GPIO Group 1 Registers(1) 256 0000 6000 – 0000 63FF Reserved no 0000 6400 – 0000 641F COMP1 Registers 64 no 0000 6420 – 0000 643F COMP2 Registers 64 no 0000 6440 – 0000 645F COMP3 Registers 64 no 0000 6460 – 0000 647F COMP4 Registers 64 no 0000 6480 – 0000 649F COMP5 Registers 64 no 0000 64A0 – 0000 64BF COMP6 Registers 64 0000 64C0 – 0000 6F7F Reserved no 0000 6F80 – 0000 6FFF C GPIO Group 2 Registers and AIO Mux Registers(1) 256 (1) The letter "C" refers to the Control Subsystem. Table 8-5. Control Subsystem Peripheral Frame 2 C DMA ACCESS(1) C ADDRESS (x16 ALIGNED)(1) CONTROL SUBSYSTEM PERIPHERAL FRAME 2 SIZE (BYTES) 0000 7000 – 0000 70FF Reserved no 0000 7010 – 0000 702F C28x System Control Registers 64 0000 7030 – 0000 703F Reserved no 0000 7040 – 0000 704F SPI-A 32 no 0000 7050 – 0000 705F SCI-A 32 no 0000 7060 – 0000 706F NMI Watchdog Interrupt Registers 32 no 0000 7070 – 0000 707F External Interrupt Registers 32 0000 7080 – 0000 70FF Reserved no 0000 7100 – 0000 717F ADC1 Configuration Registers (Only 16-bit read/write access supported) 256 no 0000 7180 – 0000 71FF ADC2 Configuration Registers (Only 16-bit read/write access supported) 256 0000 7200 – 0000 78FF Reserved no 0000 7900 – 0000 793F I2C-A 128 0000 7940 – 0000 7FFF Reserved (1) The letter "C" refers to the Control Subsystem. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 147 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-6. Control Subsystem RAMs C DMA ACCESS(1) C ADDRESS (x16 ALIGNED)(1) CONTROL SUBSYSTEM RAMS SIZE (BYTES) M ADDRESS (BYTE-ALIGNED)(2) µDMA ACCESS no 0000 8000 – 0000 8FFF L0 RAM (ECC, Secure) 8K no 0000 9000 – 0000 9FFF L1 RAM (ECC, Secure) 8K yes 0000 A000 – 0000 AFFF L2 RAM (Parity, Interleaving) 8K yes 0000 B000 – 0000 BFFF L3 RAM (Parity, Interleaving) 8K yes 0000 C000 – 0000 CFFF S0 RAM (Parity, Shared) 8K 2000 8000 – 2000 9FFF yes yes 0000 D000 – 0000 DFFF S1 RAM (Parity, Shared) 8K 2000 A000 – 2000 BFFF yes yes 0000 E000 – 0000 EFFF S2 RAM (Parity, Shared) 8K 2000 C000 – 2000 DFFF yes yes 0000 F000 – 0000 FFFF S3 RAM (Parity, Shared) 8K 2000 E000 – 2000 FFFF yes yes 0001 0000 – 0001 0FFF S4 RAM (Parity, Shared) 8K 2001 0000 – 2001 1FFF yes yes 0001 1000 – 0001 1FFF S5 RAM (Parity, Shared) 8K 2001 2000 – 2001 3FFF yes yes 0001 2000 – 0001 2FFF S6 RAM (Parity, Shared) 8K 2001 4000 – 2001 5FFF yes yes 0001 3000 – 0001 3FFF S7 RAM (Parity, Shared) 8K 2001 6000 – 2001 7FFF yes 0001 4000 – 0003 F7FF Reserved yes 0003 F800 – 0003 FBFF CtoM MSG RAM (Parity) 2K 2007 F000 – 2007 F7FF yes read only yes read only 0003 FC00 – 0003 FFFF MtoC MSG RAM (Parity) 2K 2007 F800 – 2007 FFFF yes 0004 0000 – 0004 7FFF Reserved no 0004 8000 – 0004 8FFF L0 RAM - ECC Bits 8K no 0004 9000 – 0004 9FFF L1 RAM - ECC Bits 8K no 0004 A000 – 0004 AFFF L2 RAM - Parity Bits 8K no 0004 B000 – 0004 BFFF L3 RAM - Parity Bits 8K no 0004 C000 – 0004 CFFF S0 RAM - Parity Bits 8K 2008 8000 – 2008 9FFF no no 0004 D000 – 0004 DFFF S1 RAM - Parity Bits 8K 2008 A000 – 2008 BFFF no no 0004 E000 – 0004 EFFF S2 RAM - Parity Bits 8K 2008 C000 – 2008 DFFF no no 0004 F000 – 0004 FFFF S3 RAM - Parity Bits 8K 2008 E000 – 2008 FFFF no no 0005 0000 – 0005 0FFF S4 RAM - Parity Bits 8K 2009 0000 – 2009 1FFF no no 0005 1000 – 0005 1FFF S5 RAM - Parity Bits 8K 2009 2000 – 2009 3FFF no no 0005 2000 – 0005 2FFF S6 RAM - Parity Bits 8K 2009 4000 – 2009 5FFF no no 0005 3000 – 0005 3FFF S7 RAM - Parity Bits 8K 2009 6000 – 2009 7FFF no 0005 4000 – 0007 EFFF Reserved no 0007 F000 – 0007 F3FF M0 RAM - ECC Bits 2K no 0007 F400 – 0007 F7FF M1 RAM - ECC Bits 2K no 0007 F800 – 0007 FBFF CtoM MSG RAM - Parity Bits 2K 200F F000 – 200F F7FF no no 0007 FC00 – 0007 FFFF MtoC MSG RAM - Parity Bits 2K 200F F800 – 200F FFFF no 0008 0000 – 0009 FFFF Reserved (1) The letter "C" refers to the Control Subsystem. (2) The letter "M" refers to the Master Subsystem. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-7. Control Subsystem Flash, ECC, OTP, Boot ROM C DMA ACCESS(1) C ADDRESS (x16 ALIGNED)(1) CONTROL SUBSYSTEM FLASH, ECC, OTP, BOOT ROM SIZE (BYTES) M ADDRESS (BYTE-ALIGNED)(2) µDMA ACCESS no 0010 0000 – 0010 1FFF Sector N (not available for 256KB Flash configuration) 16K no 0010 2000 – 0010 3FFF Sector M (not available for 256KB Flash configuration) 16K no 0010 4000 – 0010 5FFF Sector L (not available for 256KB Flash configuration) 16K no 0010 6000 – 0010 7FFF Sector K (not available for 256KB Flash configuration) 16K no 0010 8000 – 0010 FFFF Sector J (not available for 256KB Flash configuration) 64K no 0011 0000 – 0011 7FFF Sector I (not available for 256KB Flash configuration) 64K no 0011 8000 – 0011 FFFF Sector H (not available for 256KB Flash configuration) 64K no 0012 0000 – 0012 7FFF Sector G 64K no 0012 8000 – 0012 FFFF Sector F 64K no 0013 0000 – 0013 7FFF Sector E 64K no 0013 8000 – 0013 9FFF Sector D 16K no 0013 A000 – 0013 BFFF Sector C 16K no 0013 C000 – 0013 DFFF Sector B 16K no 0013 E000 – 0013 FFFF Sector A (CSM password in the high address) 16K 0014 0000 – 001F FFFF Reserved no 0020 0000 – 0020 7FFF Flash - ECC Bits (1/8 of Flash used = 64KB) 64K 0020 8000 – 0024 01FF Reserved no 0024 0200 – 0024 03FF TI one-time programmable (OTP) memory 1K 0024 0400 – 002F FFFF Reserved yes 0030 0000 – 003F 7FFF EPI0 (External Peripheral/Memory Interface)(3) 2M(4) 6000 0000 – DFFF FFFF yes no 003F 8000 – 003F FFFF C28x Boot ROM (64KB) 64K (1) The letter "C" refers to the Control Subsystem. (2) The letter "M" refers to the Master Subsystem. (3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices. (4) The Control Subsystem has less address reach to EPI memory than the Master Subsystem. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 149 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.1.2 Master Subsystem Memory Map

Table 8-8. Master Subsystem Flash, ECC, OTP, Boot ROM µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM SIZE (BYTES) no 0000 0000 – 0000 FFFF Boot ROM - Dual-mapped to 0x0100 0000 (Both maps access same physical location.) 64K 0001 0000 – 001F FFFF Reserved no 0020 0000 – 0020 3FFF Sector N (Zone 1 CSM password in the low address.) 16K no 0020 4000 – 0020 7FFF Sector M 16K no 0020 8000 – 0020 BFFF Sector L 16K no 0020 C000 – 0020 FFFF Sector K 16K no 0021 0000 – 0021 FFFF Sector J 64K no 0022 0000 – 0022 FFFF Sector I (not available for 256KB Flash configuration) 64K no 0023 0000 – 0023 FFFF Sector H (not available for 256KB Flash configuration) 64K no 0024 0000 – 0024 FFFF Sector G (not available for 256KB Flash configuration) 64K no 0025 0000 – 0025 FFFF Sector F (not available for 256KB Flash configuration) 64K no 0026 0000 – 0026 FFFF Sector E 64K no 0027 0000 – 0027 3FFF Sector D 16K no 0027 4000 – 0027 7FFF Sector C 16K no 0027 8000 – 0027 BFFF Sector B 16K no 0027 C000 – 0027 FFFF Sector A (Zone 2 CSM password in the high address.) 16K 0028 0000 – 005F FFFF Reserved no 0060 0000 – 0060 FFFF Flash - ECC Bits (1/8 of Flash used = 64KB) 64K 0061 0000 – 0068 047F Reserved no 0068 0480 – 0068 07FF TI OTP 896 no 0068 0800 OTP – Security Lock 4 0068 0804 Reserved 0068 0808 Reserved no 0068 080C OTP – Zone 2 Flash Start Address 4 no 0068 0810 OTP – Ethernet Media Access Controller (EMAC) Address 0 4 no 0068 0814 OTP – EMAC Address 1 4 0068 0818 Reserved no 0068 081C Main Oscillator Clock Frequency 4 0068 0820 Reserved no 0068 0824 Alternate Boot mode Pin Configuration 4 0068 0828 Reserved no 0068 082C OTP ENTRY POINT 4 0068 0830 – 0070 00FF Reserved no 0070 0100 – 0070 0102 OTP – ECC Bits – Application Use (1/8 of OTP used = 3 Bytes) 3 0070 0103 – 00FF FFFF Reserved no 0100 0000 – 0100 FFFF Boot ROM – Dual-mapped to 0x0000 0000 (Both maps access same physical location.) 64K 0101 0000 – 03FF FFFF Reserved F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-8. Master Subsystem Flash, ECC, OTP, Boot ROM (continued) µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM SIZE (BYTES) no 0400 0000 – 07FF FFFF ROM/Flash/OTP/Boot ROM – Mirror-mapped for µCRC. Accessing this area of memory by the µCRC peripheral will cause an access in 0000 0000 – 03FF FFFF memory space. Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not dual-mapped ROM address) Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF (Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register, when reading a block of data.) 64M 0800 0000 – 1FFF FFFF Reserved (1) The letter "M" refers to the Master Subsystem. Table 8-9. Master Subsystem RAMs µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM RAMS SIZE (BYTES) C ADDRESS (x16 ALIGNED)(2) C DMA ACCESS(2) no 2000 0000 – 2000 1FFF C0 RAM (ECC, Secure) 8K no 2000 2000 – 2000 3FFF C1 RAM (ECC, Secure) 8K yes 2000 4000 – 2000 5FFF C2 RAM (Parity) 8K yes 2000 6000 – 2000 7FFF C3 RAM (Parity) 8K yes 2000 8000 – 2000 9FFF S0 RAM (Parity, Shared) 8K 0000 C000 – 0000 CFFF yes yes 2000 A000 – 2000 BFFF S1 RAM (Parity, Shared) 8K 0000 D000 – 0000 DFFF yes yes 2000 C000 – 2000 DFFF S2 RAM (Parity, Shared) 8K 0000 E000 – 0000 EFFF yes yes 2000 E000 – 2000 FFFF S3 RAM (Parity, Shared) 8K 0000 F000 – 0000 FFFF yes yes 2001 0000 – 2001 1FFF S4 RAM (Parity, Shared) 8K 0001 0000 – 0001 0FFF yes yes 2001 2000 – 2001 3FFF S5 RAM (Parity, Shared) 8K 0001 1000 – 0001 1FFF yes yes 2001 4000 – 2001 5FFF S6 RAM (Parity, Shared) 8K 0001 2000 – 0001 2FFF yes yes 2001 6000 – 2001 7FFF S7 RAM (Parity, Shared) 8K 0001 3000 – 0001 3FFF yes 2001 8000 – 2007 EFFF Reserved yes read only 2007 F000 – 2007 F7FF CtoM MSG RAM (Parity) 2K 0003 F800 – 0003 FBFF yes yes 2007 F800 – 2007 FFFF MtoC MSG RAM (Parity) 2K 0003 FC00 – 0003 FFFF yes read only no 2008 0000 – 2008 1FFF C0 RAM - ECC Bits 8K no 2008 2000 – 2008 3FFF C1 RAM - ECC Bits 8K no 2008 4000 – 2008 5FFF C2 RAM - Parity Bits 8K no 2008 6000 – 2008 7FFF C3 RAM - Parity Bits 8K no 2008 8000 – 2008 9FFF S0 RAM - Parity Bits 8K 0004 C000 – 0004 CFFF no no 2008 A000 – 2008 BFFF S1 RAM - Parity Bits 8K 0004 D000 – 0004 DFFF no no 2008 C000 – 2008 DFFF S2 RAM - Parity Bits 8K 0004 E000 – 0004 EFFF no no 2008 E000 – 2008 FFFF S3 RAM - Parity Bits 8K 0004 F000 – 0004 FFFF no no 2009 0000 – 2009 1FFF S4 RAM - Parity Bits 8K 0005 0000 – 0005 0FFF no no 2009 2000 – 2009 3FFF S5 RAM - Parity Bits 8K 0005 1000 – 0005 1FFF no no 2009 4000 – 2009 5FFF S6 RAM - Parity Bits 8K 0005 2000 – 0005 2FFF no no 2009 6000 – 2009 7FFF S7 RAM - Parity Bits 8K 0005 3000 – 0005 3FFF no 2009 8000 – 200F EFFF Reserved no 200F F000 – 200F F7FF CtoM MSG RAM - Parity Bits 2K 0007 F800 – 0007 FBFF no no 200F F800 – 200F FFFF MtoC MSG RAM - Parity Bits 2K 0007 FC00 – 0007 FFFF no 2010 0000 – 21FF FFFF Reserved www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 151 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-9. Master Subsystem RAMs (continued) µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM RAMS SIZE (BYTES) C ADDRESS (x16 ALIGNED)(2) C DMA ACCESS(2) yes 2200 0000 – 23FF FFFF Bit Banded RAM Zone (Dedicated address for each RAM bit of Cortex-M3 RAM blocks above) 32M yes 2400 0000 – 27FF FFFF All RAM Spaces – Mirror- Mapped for µCRC. Accessing this memory by the µCRC peripheral will cause an access to 2000 0000 – 23FF FFFF memory space. (Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register when reading a block of data.) 64M 2800 0000 – 3FFF FFFF Reserved (1) The letter "M" refers to the Master Subsystem. (2) The letter "C" refers to the Control Subsystem. Table 8-10. Master Subsystem Peripherals µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM PERIPHERALS SIZE (BYTES) C ADDRESS (x16 ALIGNED)(2) C DMA ACCESS(2) yes 4000 0000 – 4000 0FFF Watchdog Timer 0 Registers 4K yes 4000 1000 – 4000 1FFF Watchdog Timer 1 Registers 4K 4000 2000 – 4000 3FFF Reserved yes 4000 4000 – 4000 4FFF M GPIO Port A (APB Bus)(1) 4K yes 4000 5000 – 4000 5FFF M GPIO Port B (APB Bus)(1) 4K yes 4000 6000 – 4000 6FFF M GPIO Port C (APB Bus)(1) 4K yes 4000 7000 – 4000 7FFF M GPIO Port D (APB Bus)(1) 4K yes 4000 8000 – 4000 8FFF SSI0 4K yes 4000 9000 – 4000 9FFF SSI1 4K yes 4000 A000 – 4000 AFFF SSI2 4K yes 4000 B000 – 4000 BFFF SSI3 4K yes 4000 C000 – 4000 CFFF UART0 4K yes 4000 D000 – 4000 DFFF UART1 4K yes 4000 E000 – 4000 EFFF UART2 4K yes 4000 F000 – 4000 FFFF UART3 4K yes 4001 0000 – 4001 0FFF UART4 4K 4001 1000 – 4001 FFFF Reserved no 4002 0000 – 4002 07FF I2C0 Master 2K no 4002 0800 – 4002 0FFF I2C0 Slave 2K no 4002 1000 – 4002 17FF I2C1 Master 2K no 4002 1800 – 4002 1FFF I2C1 Slave 2K 4002 2000 – 4002 3FFF Reserved yes 4002 4000 – 4002 4FFF M GPIO Port E (APB Bus)(1) 4K yes 4002 5000 – 4002 5FFF M GPIO Port F (APB Bus)(1) 4K yes 4002 6000 – 4002 6FFF M GPIO Port G (APB Bus)(1) 4K yes 4002 7000 – 4002 7FFF M GPIO Port H (APB Bus)(1) 4K 4002 8000 – 4002 FFFF Reserved F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-10. Master Subsystem Peripherals (continued) µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM PERIPHERALS SIZE (BYTES) C ADDRESS (x16 ALIGNED)(2) C DMA ACCESS(2) yes 4003 0000 – 4003 0FFF GP Timer 0 4K yes 4003 1000 – 4003 1FFF GP Timer 1 4K yes 4003 2000 – 4003 2FFF GP Timer 2 4K yes 4003 3000 – 4003 3FFF GP Timer 3 4K 4003 4000 – 4003 CFFF Reserved yes 4003 D000 – 4003 DFFF M GPIO Port J (APB Bus)(1) 4K

4003 E000 – 4003 FFFF Reserved

yes 4004 8000 – 4004 8FFF ENET MAC0 4K 4004 9000 – 4004 FFFF Reserved yes 4005 0000 – 4005 0FFF USB MAC0 4K 4005 1000 – 4005 7FFF Reserved yes 4005 8000 – 4005 8FFF M GPIO Port A (AHB Bus)(1) 4K yes 4005 9000 – 4005 9FFF M GPIO Port B (AHB Bus)(1) 4K yes 4005 A000 – 4005 AFFF M GPIO Port C (AHB Bus)(1) 4K yes 4005 B000 – 4005 BFFF M GPIO Port D (AHB Bus)(1) 4K yes 4005 C000 – 4005 CFFF M GPIO Port E (AHB Bus)(1) 4K yes 4005 D000 – 4005 DFFF M GPIO Port F (AHB Bus)(1) 4K yes 4005 E000 – 4005 EFFF M GPIO Port G (AHB Bus)(1) 4K yes 4005 F000 – 4005 FFFF M GPIO Port H (AHB Bus)(1) 4K yes 4006 0000 – 4006 0FFF M GPIO Port J (AHB Bus)(1) 4K 4006 1000 – 4006 FFFF Reserved no 4007 0000 – 4007 3FFF CAN0 16K no 4007 4000 – 4007 7FFF CAN1 16K 4007 8000 – 400C FFFF Reserved no 400D 0000 – 400D 0FFF EPI0 (Registers only) 4K 400D 1000 – 400F 9FFF Reserved no 400F A000 – 400F A303 M Flash Control Registers(1) 772 400F A304 – 400F A5FF Reserved no 400F A600 – 400F A647 M Flash ECC Error Log Registers(1) 72 400F A648 – 400F AFFF Reserved no 400F B000 – 400F B1FF Reserved no 400F B200 – 400F B2FF RAM Configuration Registers 256 0000 4900 – 0000 497F no no 400F B300 – 400F B3FF RAM ECC/Parity/Access Error Log Registers 256 0000 4A00 – 0000 4A7F no no 400F B400 – 400F B5FF M CSM Registers(1) 512 no 400F B600 – 400F B67F µCRC 128 400F B680 – 400F B6FF Reserved no 400F B700 – 400F B77F CtoM and MtoC IPC Registers 128 0000 4E00 – 0000 4E3F no 400F B780 – 400F B7FF Reserved no 400F B800 – 400F B87F M Clock Control Registers(1) 128 0000 4400 – 0000 443F no no 400F B880 – 400F B8BF M LPM Control Registers(1) 64 no 400F B8C0 – 400F B8FF M Reset Control Registers(1) 64 no 400F B900 – 400F B93F Device Configuration Registers 64 0000 0880 – 0000 0890 (Read Only) 400F B940 – 400F B97F Reserved www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 153 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-10. Master Subsystem Peripherals (continued) µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM PERIPHERALS SIZE (BYTES) C ADDRESS (x16 ALIGNED)(2) C DMA ACCESS(2) no 400F B980 – 400F B9FF M Write Protect Registers(1) 128 no 400F BA00 – 400F BA7F M NMI Registers(1) 128 400F BA80 – 400F BAFF Reserved no 400F BB00 – 400F BBFF Reserved 400F BC00 – 400F EFFF Reserved no 400F F000 – 400F FFFF µDMA Registers 4K 4010 0000 – 41FF FFFF Reserved yes 4200 0000 – 43FF FFFF Bit Banded Peripheral Zone (Dedicated address for each register bit of Cortex-M3 peripherals above.) 32M 4400 0000 – 4FFF FFFF Reserved (1) The letter "M" refers to the Master Subsystem. (2) The letter "C" refers to the Control Subsystem. Table 8-11. Master Subsystem Analog and EPI µDMA ACCESS M ADDRESS (BYTE-ALIGNED)(1) MASTER SUBSYSTEM ANALOG AND EPI SIZE (BYTES) C ADDRESS (x16 ALIGNED)(2) C DMA ACCESS(2) 5000 0000 – 5000 15FF Reserved yes 5000 1600 – 5000 161F ADC1 Result Registers 32 5000 1620 – 5000 167F Reserved yes 5000 1680 – 5000 169F ADC2 Result Registers 32 5000 16A0 – 5FFF FFFF Reserved yes 6000 0000 – DFFF FFFF EPI0 (External Peripheral/Memory Interface) 2G 0030 0000 – 003F 7FFF(3) (4) yes (1) The letter "M" refers to the Master Subsystem. (2) The letter "C" refers to the Control Subsystem. (3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices. (4) The Control Subsystem has less address reach to EPI memory than the Master Subsystem. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-12. Cortex-M3 Private Bus µDMA ACCESS Cortex-M3 ADDRESS (BYTE-ALIGNED) Cortex-M3 PRIVATE BUS SIZE (BYTES) no E000 0000 – E000 0FFF ITM (Instrumentation Trace Macrocell) 4K no E000 1000 – E000 1FFF DWT (Data Watchpoint and Trace) 4K no E000 2000 – E000 2FFF FPB (Flash Patch and Breakpoint) 4K E000 3000 – E000 E007 Reserved no E000 E008 – E000 E00F System Control Block 8 no E000 E010 – E000 E01F System Timer 16 E000 E020 – E000 E0FF Reserved no E000 E100 – E000 E4EF Nested Vectored Interrupt Controller (NVIC) 1008 E000 E4F0 – E000 ECFF Reserved no E000 ED00 – E000 ED3F System Control Block 64 E000 ED40 – E000 ED8F Reserved no E000 ED90 – E000 EDB8 Memory Protection Unit 41 E000 EDB9 – E000 EEFF Reserved no E000 EF00 – E000 EF03 Nested Vectored Interrupt Controller 4 E000 EF04 – FFFF FFFF Reserved Note MPU is not available on silicon revision 0 devices. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 155 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.2 Identification

Table 8-13. Device Identification Registers NAME C ADDRESS (x16 ALIGNED)(1) M ADDRESS (BYTE ALIGNED)(2) DESCRIPTION DID0.REVID 400F E000 – 400F E001 Device Identification 0 Register - Revision_ID REVID 0x0000 0883 REVID - Current Revision ID of device Silicon Revision Number REVID 0 0 A 1 B 1 E 5 DID1.PARTNO 400F E006 Device Identification 1 Register - Part_Number PARTID.PARTNO 0x0000 0882 C28x Device PARTID Register - Device Part Number Device PARTNO (M3/C28x) F28M35E20B1 0x49 F28M35M52C1 0x4A F28M35M22C1 0x50 F28M35H52C1 0x54 F28M35H22C1 0x5A (1) The letter "C" refers to the Control Subsystem. (2) The letter "M" refers to the Master Subsystem. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.3 Master Subsystem

The Master Subsystem includes the Cortex-M3 CPU, µDMA, Nested Vectored Interrupt Controller (NVIC), Cortex-M3 Peripherals, and Local Memory. Additionally, the Cortex-M3 CPU and µDMA can access the Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and read ADC Result Registers through the Analog Common Interface Bus. The Master Subsystem can also receive events from the NMI block and send events to the Resets block. Figure 8-1 shows the Master Subsystem.

8.3.1 Cortex-M3 CPU

The 32-bit Cortex-M3 processor offers high performance, fast interrupt handling, and access to a variety of communication peripherals (including Ethernet and USB). The Cortex-M3 features a Memory Protection Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus bridge adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses that connect to the Boot ROM and Flash. Other data is typically routed through the Cortex-M3 System Bus connected to the local RAMs. The System Bus also goes to the Shared Resources block (also accessible by the Control Subsystem) and to the Analog Subsystem through the ACIB. Another bus bridge allows bus cycles from both the Cortex-M3 System Bus and those of the µDMA bus to access the Master Subsystem peripherals (through the APB bus or the AHP bus). Most of the interrupts to the Cortex-M3 CPU come from the NVIC, which manages the interrupt requests from peripherals and assigns handling priorities. There are also several exceptions generated by Cortex-M3 CPU that can return to the Cortex-M3 as interrupts after being prioritized with other requests inside the NVIC. In addition to programmable priority interrupts, there are also three levels of fixed-priority interrupts of which the highest priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets block. The next highest priority, level-2, is assigned to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault) interrupt is assigned to level-1 priority, and this interrupt is caused by one of the error condition exceptions (Memory Management, Bus Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not properly serviced. The Cortex-M3 CPU has two low-power modes: Sleep and Deep Sleep. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 157 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

EPI I C (2)2 SSI (4)UART (5)USB + PHY (OTG) EMAC CAN (2) GP TIMER (4) uCRC WDOG (2)NMI WDOG M3 NMI NVIC (NESTED VECTORED INTERRUPT CONTROLLER) BOOT ROM uDMA RESETS MPU / BRIDGE SECURE FLASH (ECC) FLASHUNCERR BUSFAULTBUS CNTRL/FAULT LOGIC LOCAL MEMORY MEMORY MNGMT FLFSMFLSINGER ANALOG SUBSYSTEM EXCEPTIONS FROM M3 CORE M3NMIINT M3PORRST M3HRDFLT INSTRUCTIONS D-CODE BUS M3 SYSTEM BUS AHB BUS APB BUS I-CODE BUS CPU M3SYSRST UART (5:1) REQ SSI (3:0) REQ USB MAC REQ EPI REQ GPTA/B (3:0) (3:0) REQ EMACRX EMACTX REQ M3DBGRST M3WDRST (1:0) M3NMIRST M3SWRST M3NMI USAGE FAULT SVCALL DBG MONITOR PENDING SV SYS TICK PROGRAM- MABLE PRIORITY INTERRUPTS FIXED PRIORITY INTERRUPTS GPIO_MUX1 DMA INTRS DAT A INTERRUPTS APB BUS (REG ACCESS ONLY) NVIC M3NMIINT ADC INT (8:1) M3NMIINT EOC INTERRUPTS M3 PERIPHERALS UART (1:5) IRQ SSI (0:3) IRQ I2C (1:0) IRQ CAN0/1 (1:0) (1:0) IRQ USB MAC IRQ EPI IRQ GPTA/B (3:0) (3:0) IRQ GPIO (S:A) IRQ WDT (1:0) IRQ EMAC IRQ DMA SW IRQ DMA ERR IRQ PERIPHERAL I/O s RAMUNCERR S0-S7 SHARED RAM (parity) MTOC MSG RAM (parity) CTOM MSG RAM (parity) SHARED RESOURCES CONTROL SUBSYSTEM uDMA BUS CTOM IPC (4:1) IPC REGS FREQ GASKET BUS BRIDGE C2 - C3 RAM (parity) SECURE C0/C1 RAM (ECC) RAMUNCERRRAMACCVIOL RAMSINGERR Figure 8-1. Master Subsystem

8.3.2 Cortex-M3 DMA and NVIC

The Cortex-M3 direct memory access (µDMA) module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the Cortex-M3 CPU. The NVIC manages and prioritizes interrupt handling for the Cortex-M3 CPU. The Cortex-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the µDMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the data transfer, following which an IRQ request may be sent from the µDMA to the NVIC to announce to the Cortex-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral, REQ/DONE will directly drive IRQ to the NVIC so that the Cortex-M3 CPU can transfer the data. For those peripherals that are not supported by the µDMA, IRQs are supplied directly to the NVIC, bypassing the DMA. This case is true for both Watchdogs, CANs, I2Cs, and the Analog-to-Digital Converters sending ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the µDMA or the NVIC (only to the Resets block).

8.3.3 Cortex-M3 Interrupts

Table 8-14 shows all interrupt assignments for the Cortex-M3 processor. Most interrupts (16–107) are associated with interrupt requests from Cortex-M3 peripherals. The first 15 interrupts (1–15) are processor exceptions generated by the Cortex-M3 core itself. These processor exceptions are detailed in Table 8-15. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-14. Interrupts from NVIC to Cortex-M3 INTERRUPT NUMBER (BIT IN INTERRUPT REGISTERS) VECTOR NUMBER VECTOR ADDRESS OR OFFSET DESCRIPTION – 0–15 0x0000.0000–0x0000.003C Processor exceptions 0 16 0x0000.0040 GPIO Port A 1 17 0x0000.0044 GPIO Port B 2 18 0x0000.0048 GPIO Port C 3 19 0x0000.004C GPIO Port D 4 20 0x0000.0050 GPIO Port E 5 21 0x0000.0054 UART0 6 22 0x0000.0058 UART1 7 23 0x0000.005C SSI0 8 24 0x0000.0060 I2C0 9–17 25–33 – Reserved 18 34 0x0000.0088 Watchdog Timers 0 and 1 19 35 0x0000.008C Timer 0A 20 36 0x0000.0090 Timer 0B 21 37 0x0000.0094 Timer 1A 22 38 0x0000.0098 Timer 1B 23 39 0x0000.009C Timer 2A 24 40 0x0000.00A0 Timer 2B 25–27 41–43 – Reserved 28 44 0x0000.00B0 System Control 29 45 0x0000.00B4 Reserved 30 46 0x0000.00B8 GPIO Port F 31 47 0x0000.00BC GPIO Port G 32 48 0x0000.00C0 GPIO Port H 33 49 0x0000.00C4 UART2 34 50 0x0000.00C8 SSI1 35 51 0x0000.00CC Timer 3A 36 52 0x0000.00D0 Timer 3B 37 53 0x0000.00D4 I2C1 38–41 54–57 – Reserved 42 58 0x0000.00E8 Ethernet Controller 44 60 0x0000.00F0 USB 45 61 – Reserved 46 62 0x0000.00F8 µDMA Software 47 63 0x0000.00FC µDMA Error 48–52 64–68 – Reserved 53 69 0x0000.0114 EPI 54 70 0x0000.0118 GPIO Port J 55–56 71–72 – Reserved 57 73 0x0000.0124 SSI 2 58 74 0x0000.0128 SSI 3 59 75 0x0000.012C UART3 60 76 0x0000.0130 UART4 61–63 77–79 – Reserved www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 159 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-14. Interrupts from NVIC to Cortex-M3 (continued) INTERRUPT NUMBER (BIT IN INTERRUPT REGISTERS) VECTOR NUMBER VECTOR ADDRESS OR OFFSET DESCRIPTION 64 80 0x0000.0140 CAN0 INT0 65 81 0x0000.0144 CAN0 INT1 66 82 0x0000.0148 CAN1 INT0 67 83 0x0000.014C CAN1 INT1 68–71 84–87 – Reserved 72 88 0x0000.0160 ADCINT1 73 89 0x0000.0164 ADCINT2 74 90 0x0000.0168 ADCINT3 75 91 0x0000.016C ADCINT4 76 92 0x0000.0170 ADCINT5 77 93 0x0000.0174 ADCINT6 78 94 0x0000.0178 ADCINT7 79 95 0x0000.017C ADCINT8 80 96 0x0000.0180 CTOMIPC1 81 97 0x0000.0184 CTOMIPC2 82 98 0x0000.0188 CTOMIPC3 83 99 0x0000.018C CTOMIPC4 84–87 100–103 – Reserved 88 104 0x0000.01A0 RAM Single Error 89 105 0x0000.01A4 System / USB PLL Out of Lock 90 106 0x0000.01A8 M3 Flash Single Error 91 107 0x0000.01AC Reserved 92–133 108–149 – Reserved F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-15. Exceptions from Cortex-M3 Core to NVIC EXCEPTION TYPE PRIORITY (1) VECTOR NUMBER VECTOR ADDRESS OR OFFSET (2) ACTIVATION – – 0 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset. Reset –3 (highest) 1 0x0000.0004 Asynchronous Nonmaskable Interrupt (NMI) –2 2 0x0000.0008 Asynchronous On Concerto devices activated by clock fail condition, C28 PIE error, external M3GPIO NMI input signal, and C28 NMI WD time-out reset. Hard Fault –1 3 0x0000.000C – Memory Management programmable(3) 4 0x0000.0010 Synchronous Bus Fault programmable(3) 5 0x0000.0014 Synchronous when precise and asynchronous when imprecise. On Concerto devices activated by memory access errors and RAM and flash uncorrectable data errors. Usage Fault programmable(3) 6 0x0000.0018 Synchronous – – 7–10 – Reserved SVCall programmable(3) 11 0x0000.002C Synchronous Debug Monitor programmable(3) 12 0x0000.0030 Synchronous – – 13 – Reserved PendSV programmable(3) 14 0x0000.0038 Asynchronous SysTick programmable(3) 15 0x0000.003C Asynchronous Interrupts programmable (4) 16 and above 0x0000.0040 and above Asynchronous (1) 0 is the default priority for all the programmable priorities (2) See the "Vector Table" subsection of the "Exception Model" section in the Cortex-M3 Processor chapter of the Concerto F28M35x Technical Reference Manual. (3) See SYSPRI1 in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual. (4) See PRIn registers in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual.

8.3.4 Cortex-M3 Vector Table

Each peripheral interrupt of Table 8-14 is assigned an address offset containing the location of the peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 16–107). Similarly, each exception interrupt of Table 8-15 (including Reset) is also assigned an address offset containing the location of the exception interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 1–15). In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table location 0. Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000 0200 to 0x3FFF FE00. When configuring the VTABLE register, the offset must be aligned on a 512-byte boundary. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.3.5 Cortex-M3 Local Peripherals

The Cortex-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose Timers, four SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB + PHY, EPI, and µCRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus (Advanced High- Performance Bus). The EPI peripheral is also accessible from the Control Subsystem. The remaining peripherals are accessible through the APB Bus (Advanced Peripheral Bus). The APB and AHB bus cycles originate from the CPU System Bus or the µDMA Bus through a bus bridge. While the Cortex-M3 CPU has access to all the peripherals, the µDMA has access to most, with the exception of the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The Cortex-M3 peripherals connect to the Concerto device pins through GPIO_MUX1. Most of the peripherals also generate event signals for the µDMA and the NVIC. The Watchdogs receive M3SWRST from the NVIC (triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI Watchdog receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets block. See Section 7.11 for more information on the Cortex-M3 peripherals.

8.3.6 Cortex-M3 Local Memory

The Local Memory includes Boot ROM; Secure Flash with ECC; Secure C0/C1 RAM with ECC; and C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both accessible through the I-CODE and D-CODE Buses. Flash registers can also be accessed by the Cortex-M3 CPU through the APB Bus. All Local Memory is accessible from the Cortex-M3 CPU; the C2/C3 RAM is also accessible by the µDMA. Two types of error correction events can be generated during access of the Local Memory: uncorrectable errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a Bus Fault Exception to the Cortex-M3 CPU. The less critical single errors go to the NVIC where they can result in maskable interrupts to the Cortex-M3 CPU.

8.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals

There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem. The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity Error Checking. The Message RAMs and the Shared RAMs can be accessed by the Cortex-M3 CPU and µDMA. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA. The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling). The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem. The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The Cortex-M3 CPU accesses the ACIB through the System Bus, and the µDMA through the µDMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers between CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition to managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem (as well as to the Control Subsystem). The eight F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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EOC sources from ADC1 and the eight EOC sources from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations in both the Master Subsystem and the Control Subsystem. See Section 7.10 for more information on shared resources and analog peripherals.

8.4 Control Subsystem

The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block, DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals through the Analog Common Interface Bus. Figure 8-2 shows the Control Subsystem.

8.4.1 C28x CPU/FPU/VCU

The F28M35x Concerto MCU family is a member of the TMS320C2000 MCU platform. The Concerto C28x CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Entry performance MCUs, combined with a single-precision (32-bit) IEEE 754 FPU of TI’s existing Premium performance MCUs. Each F28M35x device is a very efficient C/C++ engine, enabling users to develop their system control software in a high-level language. Each F28M35x device also enables math algorithms to be developed using C/C++. The device is equally efficient at DSP math tasks and at system control tasks. The 32 × 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. With the addition of the fast interrupt response with automatic context save of critical registers, the device is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special conditional store operations further improve performance. The VCU extends the capabilities of the C28x CPU and C28x+FPU processors by adding additional instructions to accelerate Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms. No changes have been made to existing instructions, pipeline, or memory bus architecture. Therefore, programs written for the C28x are completely compatible with the C28x+VCU. There are two events generated by the FPU block that go to the C28x PIE: LVF and LUV. Inside PIE, these and other events from C28x peripherals and memories result in 12 PIE interrupts PIEINTS[12:1] into the C28x CPU. The C28x CPU also receives three additional interrupts directly (instead of through PIE) from Timer 1 (TINT1), from Timer 2 (TINT2), and from the NMI block (C28uNMIINT). The C28x has two low-power modes: IDLE and STANDBY. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 163 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

TIMER (3)XINT (3)EPWM (9) NMIWDOGEQEP (3) ECAP (6)McBSP I C2 SCI SPI PIE (PERIPHERAL INTERRUPT EXPANSION) C28x DMA ANALOG SUBSYSTEM GPIO_MUX1 GPIO_MUX1 C28x NMI EQEP ERR SOC TRIGGERS EOC INTERRUPTS ADCINT (8:1) DINTCH (6:1) TINT 0,1,2 ADCINT (4:1) GPTRIP (12:1) GPTRIP (12:7) GPTRIP (6:4) PIENMIERR C28NMIRST C28 CPU BUS C28 DMA BUS C28x CPU C28x FPU C28x VCU PIEINTRS (12:1) C28x LOCAL MEMORY TINT1 TINT2 C28NMIINTC28NMI BOOT ROM L2/L3 RAM (parity) SECURE FLASH (ECC) SECURE L0/L1 RAM (ECC) RAMUNCERR RAMACCVIOL FLASHUNCERR S0-S7 SHARED RAM (parity) MTOC MSG RAM (parity) IPC REGS CTOM MSG RAM (parity) MASTER SUBSYSTEM M0/M1 RAM (ECC) C28x NMI LUFLVFFLFSMFLSINGERR RAMSINGERRMTOCIPC (4:1) SHARED RESOURCES GPIO_MUX1 XINT 1,2,3 MXINTA, MRINTA SOCA (9:1), SOCB(9:1)SOCA (9:1), SOCB(9:1) TINT 0,1,2 XINT 2 ECCDBLERR ECCDBLERR LPMWAKE M3 NMI C28x PERIPHERALS RAMUNCERR M3 CLOCKS CLOCKFAIL LPM WAKEUP RESETS EPWM(9:1)TZINT EPWM(9:1)INT EQEP(3:1)INT ECAP(6:1)INT SPIRXINTA, SPITXINTA SCIRXINTA, SCITXINTA GPIO_MUX1 SOCBOSOCAO SYNCO PERIPHERAL I/O s FREQ GASKET BUS BRIDGE EPI I2CINT1A, I2CINT2A GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) Figure 8-2. Control Subsystem

8.4.2 C28x Core Hardware Built-In Self-Test

The Concerto microcontroller C28x CPU core includes a HWBIST feature for testing the CPU core logic for errors. Tests using HWBIST can be initiated through a software library provided by TI.

8.4.3 C28x Peripheral Interrupt Expansion

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F28M35x, 66 of the possible 96 interrupts are used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the 96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block. See Table 8-16 for PIE interrupt assignments. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-16. PIE Peripheral Interrupts CPU INTERRUPTS(1) PIE INTERRUPTS INT1 C28.LPMWAKE (C28LPM) 0x0D4E TINT0 (TIMER 0) 0x0D4C Reserved 0x0D4A XINT2 0x0D48 XINT1 0x0D46 Reserved 0x0D44 ADCINT2 (ADC) 0x0D42 ADCINT1 (ADC) 0x0D40 INT2 EPWM8_TZINT (ePWM8) 0x0D5E EPWM7_TZINT (ePWM7) 0x0D5C EPWM6_TZINT (ePWM6) 0x0D5A EPWM5_TZINT (ePWM5) 0x0D58 EPWM4_TZINT (ePWM4) 0x0D56 EPWM3_TZINT (ePWM3) 0x0D54 EPWM2_TZINT (ePWM2) 0x0D52 EPWM1_TZINT (ePWM1) 0x0D50 INT3 EPWM8_INT (ePWM8) 0x0D6E EPWM7_INT (ePWM7) 0x0D6C EPWM6_INT (ePWM6) 0x0D6A EPWM5_INT (ePWM5) 0x0D68 EPWM4_INT (ePWM4) 0x0D66 EPWM3_INT (ePWM3) 0x0D64 EPWM2_INT (ePWM2) 0x0D62 EPWM1_INT (ePWM1) 0x0D60 INT4 EPWM9_TZINT (ePWM9) 0x0D7E Reserved 0x0D7C ECAP6_INT (eCAP6) 0x0D7A ECAP5_INT (eCAP5) 0x0D78 ECAP4_INT (eCAP4) 0x0D76 ECAP3_INT (eCAP3) 0x0D74 ECAP2_INT (eCAP2) 0x0D72 ECAP1_INT (eCAP1) 0x0D70 INT5 EPWM9_INT (ePWM9) 0x0D8E Reserved 0x0D8C Reserved 0x0D8A Reserved 0x0D88 Reserved 0x0D86 EQEP3_INT (eQEP3) 0x0D84 EQEP2_INT (eQEP2) 0x0D82 EQEP1_INT (eQEP1) 0x0D80 INT6 Reserved 0x0D9E Reserved 0x0D9C MXINTA (McBSPA) 0x0D9A MRINTA (McBSPA) 0x0D98 Reserved 0x0D96 Reserved 0x0D94 SPITXINTA (SPIA) 0x0D92 SPIRXINTA (SPIA) 0x0D90 INT7 Reserved 0x0DAE Reserved 0x0DAC DINTCH6 (C28 DMA) 0x0DAA DINTCH5 (C28 DMA) 0x0DA8 DINTCH4 (C28 DMA) 0x0DA6 DINTCH3 (C28 DMA) 0x0DA4 DINTCH2 (C28 DMA) 0x0DA2 DINTCH1 (C28 DMA) 0x0DA0 INT8 Reserved 0x0DBE Reserved 0x0DBC Reserved 0x0DBA Reserved 0x0DB8 Reserved 0x0DB6 Reserved 0x0DB4 I2CINT2A (I2CA) 0x0DB2 I2CINT1A (I2CA) 0x0DB0 INT9 Reserved 0x0DCE Reserved 0x0DCC Reserved 0x0DCA Reserved 0x0DC8 Reserved 0x0DC6 Reserved 0x0DC4 SCITXINTA (SCIA) 0x0DC2 SCIRXINTA (SCIA) 0x0DC0 INT10 ADCINT8 (ADC) 0x0DDE ADCINT7 (ADC) 0x0DDC ADCINT6 (ADC) 0x0DDA ADCINT5 (ADC) 0x0DD8 ADCINT4 (ADC) 0x0DD6 ADCINT3 (ADC) 0x0DD4 ADCINT2 (ADC) 0x0DD2 ADCINT1 (ADC) 0x0DD0 INT11 Reserved 0x0DEE Reserved 0x0DEC Reserved 0x0DEA Reserved 0x0DE8 MTOCIPCINT4 (IPC) 0x0DE6 MTOCIPCINT3 (IPC) 0x0DE4 MTOCIPCINT2 (IPC) 0x0DE2 MTOCIPCINT1 (IPC) 0x0DE0 INT12 LUF (C28FPU) 0x0DFE LVF (C28FPU) 0x0DFC EPI_INT (EPI) 0x0DFA C28RAMACCVIOL (Memory) 0x0DF8 C28RAMSINGER R (Memory) 0x0DF6 Reserved 0x0DF4 C28FLSINGERR (Memory) 0x0DF2 XINT3 (Ext. Int. 3) 0x0DF0 (1) Out of the 96 possible interrupts, 66 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: 1) No peripheral within the group is asserting interrupts. 2) No peripheral interrupts are assigned to the group (example PIE group 11). www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.4.4 C28x Direct Memory Access

The C28x DMA module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as the data is transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into blocks for optimal CPU processing. The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to notify the CPU when a DMA transfer has either started or completed. Five of the six channels are exactly the same, while Channel 1 has one additional feature: the ability to be configured at a higher priority than the others.

8.4.5 C28x Local Peripherals

The C28x local peripherals include an NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI, McBSP, I2C), an EPI, and three types of Control Peripherals (ePWM, eQEP, eCAP). All peripherals are accessible by the C28x CPU through the C28x Memory Bus. Additionally, the McBSP and ePWM are accessible by the C28x DMA Bus. The EPI peripheral is also accessible from the Master Subsystem. The Serial Port Peripherals and the Control Peripherals connect to the pins in Concerto through the GPIO_MUX1 block. Internally, the C28x peripherals generate events to the PIE block, C28x DMA, and the Analog Subsystem. The C28x NMI Watchdog receives a C28NMI event from the NMI block and sends a counter time-out event to the Cortex-M3 NMI block and the Resets block to flag a potentially critical condition. The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and EPWMxB. These events include ECCDBLERR event from the C28x Local Memory, PIENMIERR and EMUSTOP events from the C28x CPU, and up to 12 trips from GPIO_MUX1. See Section 7.12 for more information on C28x peripherals.

8.4.6 C28x Local Memory

The C28x Local Memory includes Boot ROM; Secure Flash with ECC; Secure L0/L1 RAM with ECC; L2/L3 RAM with Parity Error Checking; and M0/M1 with ECC. All local memories are accessible from the C28x CPU; the L2/L3 RAM is also accessible by the C28x DMA. Two types of error correction events can be generated during access of the C28x Local Memory: uncorrectable errors and single errors. The uncorrectable errors propagate to the NMI block where they can become the C28NMI to the C28x NMI Watchdog and the C28NMIINT nonmaskable interrupt to the C28x CPU. The less critical single errors go to the PIE block where they can become maskable interrupts to the C28x CPU.

8.4.7 C28x Accessing Shared Resources and Analog Peripherals

There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into the Shared Resources and the Analog Subsystem. The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have Parity-Error Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA. The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling). The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem. See Section 7.10 for more information on shared resources and analog peripherals. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.5 Analog Subsystem

The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through the C28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between CPU/DMA bus cycles of the C28x Subsystem with those of the Cortex-M3 Subsystem. In addition to managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control Subsystem. There are 22 possible Start-Of-Conversion (SOC) sources from the C28x Subsystem that are mapped to a total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2). Going the other way, eight End-Of-Conversion (EOC) sources from ADC1 and eight EOC sources from ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same eight go to the C28x DMA. The Concerto MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2); six Analog Comparators + DAC units; and an ACIB to facilitate analog data communications with the two digital subsystems of Concerto (Cortex-M3 and C28x). Figure 8-3 shows the Analog Subsystem.

8.5.1 ADC1

The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are currently pinned out. The analog channels are internally preassigned to two Sample-and-Hold (S/H) units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in ADC1 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC1 result registers. See Section 7.10.1 for more information on ADC peripherals.

8.5.2 ADC2

The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are currently pinned out. The analog channels are internally preassigned to two S/H units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in the ADC2 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC2 result registers. See Section 7.10.1 for more information on ADC peripherals. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 167 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

GPIO_MUX2 MUX GPIO COMPOUT (6:1) COMPB2COMPA1 COMPA2 COMPA3 ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 MUXGPIO AIO_MUX2 10 MUXGPIO AIO_MUX1 10 EOC INTER- RUPTS (8:1) ADC ADC ANALOG COMMON INTERFACE BUS ADC1INT (8:1) ADC2INT (8:1) SOC TRIG- GERS (8:1) TRIGS (8:1) TRIGS (8:1) GPIO EPWM (9) TIMER (3) TINT (2:0) ADCEXTTRIG SOC (9:1) A SOC (9:1) B C28x CPU C28x DMA CPU uDMA C28 CPU BUS C28 DMA BUS uDMA BUS SYSTEM BUS ADCINT(8:1) ADCINT (4:1) CCIBST ATUS REG MCIBST ATUS REG ANALOG BUS ANALOG BUS COMPB5COMPA4 COMPA5 COMPA6 VDDA (3.3V) VSSA (0V) TRIG8SEL REG TRIG7SEL REG TRIG2SEL REG TRIG1SEL REG . . . COMPARATOR + DAC UNITS Figure 8-3. Analog Subsystem

8.5.3 Analog Comparator + DAC

There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs, resulting in six digital comparison outputs. The external analog inputs that are being compared in the comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be mapped to six out of eight available pins. To use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before they can be assigned to selected 12 ePWM Trip Inputs. See Section 7.10.2 for more information on the analog comparator + DAC.

8.5.4 Analog Common Interface Bus

The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the Cortex- M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex-M3 uses its System Bus and the µDMA Bus to read from ADC Result registers. The C28x uses its Memory Bus and the DMA bus to access ADC Result registers and other registers of the Analog Subsystem. The ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the Master/Control Subsystem side of ACIB to access the ADC and Analog Comparator registers on the Analog Subsystem side. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems. The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines because it is unlikely that any application would need all 16 interrupts at the same time. Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22 possible trigger sources to each SOC trigger. There are two registers that provide status of ACIB to the Master Subsystem and to the Control Subsystem. The Cortex-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems. The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.6 Master Subsystem NMIs

The Cortex-M3 NMI Block generates an M3NMIINT nonmaskable interrupt to the Cortex-M3 CPU and an M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or outside the Concerto MCU. When able to respond to the M3NMIINT interrupt, the Cortex-M3 CPU may address the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an M3NMIRST reset signal is sent to the Resets block. The inputs to the Cortex-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR, EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x NMI Watchdog; C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog counter from counting out. PIENMIERR indicates that an error condition was generated during the NMI vector fetch from the C28x PIE block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or signature mismatch error has been detected. The Cortex-M3 NMI block can be accessed through the Cortex-M3 NMI configuration registers—including the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively. Figure 8-4 shows the Cortex-M3 NMI and C28x NMI.

8.7 Control Subsystem NMIs

The C28x NMI Block generates a C28NMIINT nonmaskable interrupt to the C28x CPU and a C28NMI event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI condition and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the C28NMIRST reset signal is sent to the Resets block and the Cortex-M3 NMI Block, where the Cortex-M3 NMI Block can generate an NMI to the Cortex-M3 processor. The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR, PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared). PIENMIERR indicates that an error condition was generated during NMI vector fetch from the C28x PIE block. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or signature mismatch error has been detected. The C28x NMI block can be accessed through the C28x NMI configuration registers—including the CNMIFLG, CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively. Figure 8-4 shows the Cortex-M3 NMI and C28x NMI. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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GPIO_MUX ANALOG SUBSYSTEM CLOCKS SHARED RAM C28x LOCAL RAM C28x FLASH 1.2V VREG C28x NMI WDOG RESETS M3 NMI WDOG CLOCKFAIL M3EXTNMI RAMUNCERR C28NMI PIENMIERR M3NMI ACIBERR M3NMIRST VREGWARN M3NMIINT C28NMIINT C28NMIRST NMI C28NMIRSTC28NMI M3NMIRSTM3NMI FLASHUNCERR M3 WDOG (2) M3WDRST (1:0) M3WDRST (1:0) C28NMIRST BIST C28x BIST M3BISTERR C28BISTERR C28BISTERR M3BISTERR M3BISTERR C28BISTERR Figure 8-4. Cortex-M3 NMI and C28x NMI

8.8 Resets

The Concerto MCU has two external reset pins: XRS for the Master and Control Subsystems and ARS for the Analog Subsystem. TI recommends that these two pins be externally tied together with a board signal trace. The XRS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control Subsystems. A reset pulse can also be driven out of the XRS pin by the Power-On Reset (POR) block of the Master and Control Subsystems (see Section 8.9). A reset pulse can be driven out of the XRS pin when the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog time-out. There are some requirements on the XRS pin: 1. During power up, the XRS pin must be held low for at least eight X1 cycles after the input clock is stable. This requirement is to enable the entire device to start from a known condition. 2. TI recommends that no voltage larger than 0.7 V be applied to any pin before powering up the device. Voltages applied to pins on an unpowered device can lead to unpredictable results. The ARS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A reset pulse can be driven out of the ARS pin by the POR block of the Analog Subsystem. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 171 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Figure 8-5 shows the resets.

8.8.1 Cortex-M3 Resets

The Cortex-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR or the M3SYSRST reset signal. In both cases, the Cortex-M3 CPU restarts program execution from the address provided by the reset entry in the vector table. A register can later be referenced to determine the source of the reset. The M3SYSRST signal also propagates to the Cortex-M3 peripherals and the rest of the Cortex-M3 Subsystem. The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The M3WDOGS is set in response to time-out conditions of the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. In addition to driving M3SYSRST, these two resets also propagate to the C28x Subsystem and the Analog Subsystem. The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the C28x Subsystem from the Cortex-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface Bus. In addition to driving reset signals to other parts of the chip, the Cortex-M3 can also detect a C28SYSRST reset being set inside the C28x Subsystem by reading the CRES bit of the CRESSTS register. Cortex-M3 software can also set bits in the SRCR register to selectively reset individual Cortex-M3 peripherals, provided they are enabled inside the DC (Device Configuration) register. The Reset Cause register (MRESC) can be read to find out if the latest reset was caused by External Reset, POR, Watchdog Timer 0, Watchdog Timer 1, or Software Reset from NVIC. ARS PIN NMI WDOG SUBSYSTEM CPU NVIC M3 WDOG (0) M3 WDOG (1) M3DBGRST M3SWRST SHARED RESOURCES ANALOG SUBSYSTEM C28x NMI WDOG C28x CPU C28x SUBSYSTEM M3SYSRST ‘0’ DEGLITCH SYNC M3WDOGS XRS PIN M3SSCLK ARS PIN DC REG POR XRS XRS XRS ACIBRST SRXRST M3SYSRST M3PORRST C28RSTIN POR C28SYSRST RESET INPUT SIGNAL ST ATUS XRS( SETS DEFAULT VALUES ) FLASH PUMP XRS CRESCNF REG DEVICECNF REG CRESSTS REG C28SYSRST C28NMIWD M3WDOGS ACIBRSTM3RSNIN SOFTWARE JT AG CONTROLLER MRESC REG CONTAINS RESET CAUSES PERIPHERAL SOFTWARE RESETS ACIBRST SRCR REG GLOBAL PERIPHERAL ENABLES XRS GPIO_MUX C28x BIST M3 BIST MLBISTRST CLBISTRST VOL T AGE REGULA TION AND POWER-ON-RESET Figure 8-5. Resets F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.8.2 C28x Resets

The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the address provided at the top of the Boot ROM Vector Table. The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex-M3 Subsystem to selectively reset the C28x Subsystem from Cortex-M3 software. The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin by reading the DEVICECNF register.

8.8.3 Analog Subsystem and Shared Resources Resets

Both the Analog Subsystem and the resources shared between the C28x and Cortex-M3 subsystems (IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog Subsystem is also reset by the internal ACIBRST signal from the Cortex-M3 Subsystem and the external ARS pin, (should be externally tied to the XRS pin), which can be reset by the POR circuitry. The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a software- generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the Analog Subsystem and the Shared Resources. Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is reset by M3SYSRST.

8.8.4 Device Boot Sequence

The boot sequence of Concerto is used to configure the Master Subsystem and the Control Subsystem for execution of application code. The boot sequence involves both internal resources, and resources external to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factory-programmed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code (C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected Cortex-M3 and C28x peripherals for loading the application code into the Master and Control Subsystems. The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by device power up, external reset, debugger reset, software reset, Cortex-M3 watchdog reset, or Cortex-M3 NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and then both bootloaders work in tandem to configure the device, load application code for both processors (if not already in the Flash), and branch the execution of each processor to a selected location in the application code. Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the Control Subsystem, the C-Bootloader enters the C28x processor into the IDLE mode (to wait for the M-Bootloader to wake up the C28x processor later through the MTOCIPC1 interrupt). Next, the M-Bootloader reads four GPIO pins (see Table 8-17) to determine the boot mode for the rest of the M-Bootloader operation. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 173 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-17. Master Subsystem Boot Mode Selection BOOT MODE NO.(1) MASTER SUBSYSTEM BOOT MODES PF2_GPIO34 (Bmode_pin4) (2) (3) PF3_GPIO35 (Bmode_pin3) (2) PG7_GPIO47 (Bmode_pin2) (2) PG3_GPIO43 (Bmode_pin1) (2)

0 Boot from Parallel GPIO 0 0 0 0

1 Boot to Master Subsystem RAM 0 0 0 1

2 Boot from Master Subsystem serial peripherals

(UART0/SSI0/I2C0) 0 0 1 0

3 Boot from Master Subsystem CAN interface 0 0 1 1

4 Boot from Master Subsystem Ethernet interface 0 1 0 0

5 Not supported (Defaults to Boot-to-Flash) 0 1 0 1

(5) Boot-to-OTP 0 1 1 0

7 Boot to Master Subsystem Flash memory 0 1 1 1

(4) Not supported (Defaults to Boot-to-Flash) 1 0 0 0 (4) Boot from Master Subsystem serial peripheral – SSI0 Master 1 0 0 1 (4) Boot from Master Subsystem serial peripheral – I2C0 Master 1 0 1 0 (4) Not supported (Defaults to Boot-to-Flash) 1 0 1 1 (4) Not supported (Defaults to Boot-to-Flash) 1 1 0 0 (4) Not supported (Defaults to Boot-to-Flash) 1 1 0 1 (4) Not supported (Defaults to Boot-to-Flash) 1 1 1 0 (4) Not supported (Defaults to Boot-to-Flash) 1 1 1 1 (1) Silicon revision A allows the user to change the GPIO pins used to determine the boot mode. Silicon revision 0 does not have this option. See the Concerto F28M35x Technical Reference Manual for additional information. (2) By default, GPIO terminals are not pulled up (they are floating). (3) On silicon revision 0, PF2_GPIO34 is a "don't care". So, the state of PF2_GPIO34 should not affect boot mode selection. (4) Boot Modes 8–15 are not supported on silicon revision 0. (5) Supported only in TMS version. On all other versions, this mode defaults to Boot-to-Flash. Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the Master Flash memory. This branching requires that the Master Flash be already programmed with valid code; otherwise, a hard fault exception is generated and the Cortex-M3 goes back to the above reset sequence. (Therefore, for a factory-fresh device, the M-Bootloader will be in a continuous reset loop until the JTAG debug probe is connected and a debug session started.) If the Master Subsystem Flash has already been programmed, the application code will start execution. Typically, the Master Subsystem application code will then establish data communication with the C28x [through the IPC (Interprocessor Communications peripheral)] to coordinate the rest of the boot process with the Control Subsystem. Following reset, the internal pullup resistors on GPIOs are disabled. Therefore, Boot Mode 15, for example, will typically require four external pullups. Boot Mode 1 causes the Master boot program to branch to Cortex-M3 RAM, where the Cortex-M3 processor starts executing code that has been preloaded earlier. Typically, this mode is used during development of application code meant for Flash, but which has to be first tested running out of RAM. In this case, the user would typically load the application code into RAM using the debugger, and then issue a debugger reset, while setting the four boot pins to 0001b. From that point on, the rest of the boot process on the Master Subsystem side is controlled by the application code. Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external peripheral before branching to the application code. This process is different from the process in Boot Modes 1, 7, and 15, where the application code was either already programmed in Flash or loaded into RAM by the JTAG debug probe. If the boot mode selection pins are set to 0000b, the M-Bootloader (running out of M-Boot ROM) will start uploading the Master application code from preselected Parallel GPIO_MUX pins. If the boot pins are set to 0010b, the application code will be loaded from the Master Subsystem UART0, SSI0, or I2C0 peripheral. (SSI0 and I2C0 are configured to work in Slave mode in this Boot Mode.) If the boot pins are set to 0011b, the application code will be loaded from the Master Subsystem CAN interface. Furthermore, if the boot pins are set to 0100b, the application code will be loaded through the Master Subsystem Ethernet interface; the IOs used in this Boot Mode are compatible with the F28M35x device. If the boot pins are set to 1001b or 1010b, then the F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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application code will be loaded through the SSI0 or I2C0 interface, respectively. SSI0 and I2C0 loaders work in Master Mode in this boot mode. Regardless of the type of boot mode selected, once the Master application code is resident in Master Flash or RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the application code takes over control from the M-Bootloader, and the boot process continues as prescribed by the application code. At this stage, the Master application program typically establishes communication with the C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the C28x to go into IDLE mode. To wake the Control Subsystem out of IDLE mode, the Master application issues the Master-to-Control- IPC-interrupt 1 (MTOCIPCINT1). Once the data communication has been established through the IPC, the boot process can now also continue on the Control Subsystem side. The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to branch to preloaded code in RAM (development mode), or to upload the Control application code from one of several available peripherals (see Table 8-18). As before, once the Control application code is in place (in Flash or RAM), the C-Bootloader branches to Flash or RAM, and from that point on, the application code takes over. Table 8-18. Control Subsystem Boot Mode Selection CONTROL SUBSYSTEM BOOT MODES MTOCIPCBOOTMODE REGISTER VALUE DESCRIPTION BOOT_FROM_RAM 0x0000 0001 Upon receiving this command from the Master Subsystem, C-Boot ROM will branch to the Control Subsystem RAM entry point location and start executing code from there. BOOT_FROM_FLASH 0x0000 0002 Upon receiving this command, C-Boot ROM will branch to the Control Subsystem FLASH entry point and start executing code from there. BOOT_FROM_SCI 0x0000 0003 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem SCI peripheral. BOOT_FROM_SPI 0x0000 0004 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem SPI interface. BOOT_FROM_I2C 0x0000 0005 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem I2C interface. BOOT_FROM_PARALLEL 0x0000 0006 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem GPIO. The boot process can be considered completed once the Cortex-M3 and C28x are both running out of their respective application programs. Following the boot sequence, the C-Bootloader is still available to interpret and act upon an assortment of IPC commands that can be issued from the Master Subsystem to perform a variety of configuration, housekeeping, and other functions. See the Concerto F28M35x Technical Reference Manual for additional information on Concerto boot modes, IPC commands, and the underlying boot philosophy. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 175 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.9 Internal Voltage Regulation and Power-On-Reset Functionality

While the analog functions of Concerto draw power from a single dedicated external power source—V DDA, its digital circuits are powered by three separate rails: 3.3-V V DDIO, 1.8-V V DD18, and 1.2-V V DD12. This section describes the sourcing, regulation, and POR functionality for these three digital power rails. Concerto devices can be internally divided into an Analog Subsystem and a Digital Subsystem (having the Cortex-M3-based Master Subsystem and the C28x-based Control Subsystem). The Digital Subsystem uses VDD12 to power the two processors, internal memory, and peripherals. The Analog Subsystem uses V DD18 to power the digital logic associated with the analog functions. Both Digital and Analog Subsystems share a common VDDIO rail to power their 3.3-V I/O buffers through which the Concerto digital signals communicate with the outside world. The Analog and Digital Subsystems each have their own POR circuits that operate independently. With the ARS and XRS reset pins externally tied together, both systems can come out of reset together, and can also be put in reset together by driving both reset pins low. See Figure 8-6 for a snapshot of the voltage regulation and POR functions provided within the Analog and Digital Subsystems of Concerto. 8.9.1 Analog Subsystem: Internal 1.8-V VREG The internal 1.8-V Voltage Regulator (VREG) generates V DD18 power from V DDIO. The 1.8-V VREG is enabled by pulling the VREG18EN pin to a low state. When enabled, the 1.8V VREG provides 1.8 V to digital logic associated with the analog functions of the Analog Subsystem. When the internal 1.8-V VREG function is enabled, the 1.8 V power no longer has to be provided externally; however, a 1.2-µF (10% tolerance) capacitor is required for each V DD18 pin to stabilize the internally generated voltages. These load capacitors are not required if the internal 1.8-V VREG is disabled, and the 1.8 V is provided from an external supply. While removing the need for an external power supply, enabling the internal VREG might affect the V DDIO power consumption. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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‘0’ XRS RESETS POWER-ON-RESET (DIGITAL SUBSYSTEM) NVIC M3 WDOGS (0,1) DIGITAL LOGIC (DIGITAL SUBSYSTEM) 1.2-V VREG (DIGITAL SUBSYSTEM) ‘0’ DEGLITCH DEGLITCH ARS 1.8-V VREG (ANALOG SUBSYSTEM) XRS PIN ARS 1.2-V SUPPLY PINS 3.3-V SUPPLY PINS 1.8-V SUPPLY PINS DIGITAL LOGIC (ANALOG SUBSYSTEM) 1.8 V 1.2 V 3.3 V VREG12EN PIN VREG18EN PIN CONCERTO DEVICE ANALOG SUBSYSTEM GPIOS DIGITAL SUBSYSTEM GPIOS CONNECT THE 2 RESET PINS EXTERNALLY THROUGH A BOARD TRACE 1.8 V 1.2 V 1.8 V 1.2 V I/OI/O 3.3 V 3.3 V TRISTATETRISTATE POR 3.3-V POR 1.8-V POR POWER-ON-RESET (ANALOG SUBSYSTEM) M3WDOGS POR 1.2-V POR 3.3-V POR CRESCNF REG ACIBRST CONTROL SUB- SYSTEM M3RSNIN M3 NMI M3 NMI WDOG M3 CPU RST Figure 8-6. Voltage Regulation and Monitoring 8.9.2 Digital Subsystem: Internal 1.2-V VREG The internal 1.2-V VREG generates V DD12 power from V DDIO. The 1.2-V VREG is enabled by pulling the VREG12EN pin to a low state. When enabled, the 1.2-V VREG internally provides 1.2 V to digital logic associated with the processors, memory, and peripherals of the Digital Subsystem. When the internal 1.2-V VREG function is enabled, the 1.2 V power no longer has to be provided externally; however, the minimum and maximum capacitance required for each V DD12 pin to stabilize the internally generated voltages are 250 nF and 750 nF, respectively. These load capacitors are not required if the internal 1.2-V VREG is disabled and the 1.2 V is provided from an external supply. While removing the need for an external power supply, enabling the internal VREG might affect the V DDIO power consumption.

8.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality

The Analog and Digital Subsystems' each have a POR circuit that creates a clean reset throughout the device enabling glitchless GPIOs during the power-on procedure. The POR function keeps both ARS and XRS driven low during device power up. This functionality is always enabled, even when VREG is disabled. While in most applications, the POR generated reset has a long enough duration to also reset other system ICs, some applications may require a longer lasting pulse. In these cases, the ARS and XRS reset pins (which are open-drain) can also be driven low to match the time the device is held in reset state with the rest of the system. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 177 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

When POR drives the the ARS and XRS pins low, the POR also resets the digital logic associated with both subsystems and puts the GPIO pins in a high impendance state. In addition to the POR reset, the Resets block of the Digital Subsystem also receives reset inputs from the NVIC, the Cortex-M3 Watchdogs (0, 1), and from the Cortex-M3 NMI Watchdog. The resulting reset output signal is then fed back to the XRS pin after being AND-ed with the POR reset (see Figure 8-6). On a related note, only the Master Subsystem comes out of reset state immediately following a device power up. The Control and Analog Subsystems continue to be held in reset until the Master Processor (Cortex-M3) brings them out of reset by writing a "1" to the M3RSNIN and ACIBRST bits of the CRESCNF Register (see Figure 8-6).

8.9.4 Connecting ARS and XRS Pins

In most Concerto applications, TI recommends that the ARS and XRS pins be tied together by external means such as through a signal trace on a PCB board. Tying the ARS and XRS pins together ensures that all reset sources will cause both the Analog and Digital Subsystems to enter the reset state together, regardless of where the reset condition occurs. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.10 Input Clocks and PLLs

Concerto devices have multiple input clock pins from which all internal clocks and the output clock are derived. Figure 8-7 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 and XCLKIN. X1 X2 CONCERTO DEVICE CRYST AL X1 X2 CONCERTO DEVICE X1 X2 CONCERTO DEVICE 3.3V OUTVDD GND CLK R D C L2 C L1 RESONATOR 3.3V OSCILLATOR NC vssosc XCLKIN CONCERTO DEVICE 3.3V OUTVDD GND CLK 3.3V OSCILLATOR vssosc vssosc Figure 8-7. Connecting Input Clocks to a Concerto™ Device www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 179 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.10.1 Internal Oscillator (Zero-Pin)

Each Concerto device contains a zero-pin internal oscillator. This oscillator outputs two fixed-frequency clocks: 10MHZCLK and 32KHZCLK. These clocks are not configurable by the user and should not be used to clock the device during normal operation. They are used inside the Master Subsystem to implement low-power modes. The 10MHZCLK is also used by the Missing Clock Detect circuit.

8.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)

The main oscillator circuit connects to an external crystal through pins X1 and X2. If a resonator is used (version of a crystal with built-in load capacitors), its ground terminal should be connected to the pin V SSOSC (not board ground). The VSSOSC pin should also be used to ground the external load capacitors connected to the two crystal terminals as shown in Figure 8-7.

8.10.3 External Oscillators (Pins X1 and XCLKIN)

Concerto has two pins (X1 and XCLKIN) into which a single-ended clock can be driven from external oscillators or other clock sources. When connecting an external clock source through the X1 terminal, the X2 terminal should be left unconnected. Most internal clocks of this device are derived from the X1 clock input (or X1/X2 crystal) . The XCLKIN clock is only used by the USB PLL and CAN peripherals. Figure 8-7 shows how to connect external oscillators to the X1 and XCLKIN terminals. Locate the external oscillator as close to the MCU as practical. Ideally, the return ground trace should be an isolated trace directly underneath the forward trace or run adjacent to the trace on the same layer. Spacing should be kept minimal, with any other nearby traces double-spaced away, so that the electromagnetic fields created by the two opposite currents cancel each other out as much as possible, thus reducing parasitic inductances that radiate EMI.

8.10.4 Main PLL

The Main PLL uses the reference clock from pins X1 (external oscillator) or X1/X2 (external crystal/resonator). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT register. For example, to achieve PLL multiply of 28.5, the integer multiplier should be set to 28, and the fractional multiplier to 0.5. The output clock from the Main PLL must be between 150 MHz and 300 MHz. The PLL output clock is then divided by 2 before entering a mux that selects between this clock and the PLL input clock – OSCCLK (used in PLL bypass mode). The PLL bypass mode is selected by setting the SPLLIMULT field of the SYSPLLMULT register to 0. The output clock from the mux next enters a divider controlled by the SYSDIVSEL register, after which the output clock becomes the PLLSYSCLK. Figure 8-8 shows the Main PLL function and configuration examples. Table 8-19 to Table 8-22 list the integer multiplier configuration values. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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0000000 : 1/c180 0000001 : 1/c180 0000010 : 2/c180 0000011 : 3/c180 1111101: 125/c180 1111110: 126/c180 1111111: 127/c180 EXAMPLE 1: X1 = 100 MHZ SPLLIMULT = 0000000 ( BYPASS PLL) N/A PL LSYSCLK = 100 MHz EXAMPLE 2: X1 = 10 MHz SPLLIMULT = 0010100 ( 20 ) /c180 SPLLFMULT SPLLFMULT = 00 ( NOT USED) PLLSYSCLK = [ ( 10 20) / 2 ] / 1 = 100 MHz/c180 EXAMPLE 3: X1 = 10 MHz SPLLIMULT = 0010100 ( 20 ) /c180 = 10 ( 0.50) PLLSYSCLK = [ ( 10 20.5) / 2 ] / 1 = 102.5 MHz/c180 /c180 SPLLIMULT SPLLFMULT PLLSYSCLK OUPUT OF MAIN PLL IS ALWAYS DIVIDED BY 2 00: NOT USED 01: 0.25/c180 10: 0.50/c180 11: 0.75/c180 7 2 OSCCLK OSCCLK SYSDIVSEL REG SYSDIVSEL (1:0) = 00 ( /1 ) (1) OUTPUT OF THE MAIN PLL MUST RANGE BETWEEN 150 MHz.–300 SYSPLLCTL REG SPLLEN (2) SPLLCLKEN (2) WHEN SPLLEN BIT = 0, THE MAIN PLL IS POWERED OFF . Figure 8-8. Main PLL Table 8-19. Main PLL Integer Multiplier Configuration (Bypass PLL to × 31) SPLLIMULT(6:0) MULT VALUE 0000000 b Bypass PLL 0000001 b × 1 0000010 b × 2 0000011 b × 3 0000100 b × 4 0000101 b × 5 0000110 b × 6 0000111 b × 7 0001000 b × 8 0001001 b × 9 0001010 b × 10 0001011 b × 11 0001100 b × 12 0001101 b × 13 0001110 b × 14 0001111 b × 15 0010000 b × 16 0010001 b × 17 0010010 b × 18 0010011 b × 19 0010100 b × 20 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 181 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-19. Main PLL Integer Multiplier Configuration (Bypass PLL to × 31) (continued) SPLLIMULT(6:0) MULT VALUE 0010101 b × 21 0010110 b × 22 0010111 b × 23 0011000 b × 24 0011001 b × 25 0011010 b × 26 0011011 b × 27 0011100 b × 28 0011101 b × 29 0011110 b × 30 0011111 b × 31 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-20. Main PLL Integer Multiplier Configuration (× 32 to × 63) SPLLIMULT(6:0) MULT VALUE 0100000 b × 32 0100001 b × 33 0100010 b × 34 0100011 b × 35 0100100 b × 36 0100101 b × 37 0100110 b × 38 0100111 b × 39 0101000 b × 40 0101001 b × 41 0101010 b × 42 0101011 b × 43 0101100 b × 44 0101101 b × 45 0101110 b × 46 0101111 b × 47 0110000 b × 48 0110001 b × 49 0110010 b × 50 0110011 b × 51 0110100 b × 52 0110101 b × 53 0110110 b × 54 0110111 b × 55 0111000 b × 56 0111001 b × 57 0111010 b × 58 0111011 b × 59 0111100 b × 60 0111101 b × 61 0111110 b × 62 0111111 b × 63 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-21. Main PLL Integer Multiplier Configuration (× 64 to × 95) SPLLIMULT(6:0) MULT VALUE 1000000 b × 64 1000001 b × 65 1000010 b × 66 1000011 b × 67 1000100 b × 68 1000101 b × 69 1000110 b × 70 1000111 b × 71 1001000 b × 72 1001001 b × 73 1001010 b × 74 1001011 b × 75 1001100 b × 76 1001101 b × 77 1001110 b × 78 1001111 b × 79 1010000 b × 80 1010001 b × 81 1010010 b × 82 1010011 b × 83 1010100 b × 84 1010101 b × 85 1010110 b × 86 1010111 b × 87 1011000 b × 88 1011001 b × 89 1011010 b × 90 1011011 b × 91 1011100 b × 92 1011101 b × 93 1011110 b × 94 1011111 b × 95 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-22. Main PLL Integer Multiplier Configuration (× 96 to × 127) SPLLIMULT(6:0) MULT VALUE 1100000 b × 96 1100001 b × 97 1100010 b × 98 1100011 b × 99 1100100 b × 100 1100101 b × 101 1100110 b × 102 1100111 b × 103 1101000 b × 104 1101001 b × 105 1101010 b × 106 1101011 b × 107 1101100 b × 108 1101101 b × 109 1101110 b × 110 1101111 b × 111 1110000 b × 112 1110001 b × 113 1110010 b × 114 1110011 b × 115 1110100 b × 116 1110101 b × 117 1110110 b × 118 1110111 b × 119 1111000 b × 120 1111001 b × 121 1111010 b × 122 1111011 b × 123 1111100 b × 124 1111101 b × 125 1111110 b × 126 1111111 b × 127

8.10.5 USB PLL

The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or the internal OSCCLK (originating from the external crystal or oscillator through the X1/X2 pins). An input mux selects the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL Register (see Figure 8-9). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the UPLLIMULT and UPLLFMULT fields of the UPLLMULT register. For example, to achieve PLL multiply of 28.5, the integer multiplier should be set to 28, and the fractional multiplier to 0.5. The output clock from the USB PLL must always be 240 MHz. The PLL output clock is then divided by 4—resulting in 60 MHz that the USB needs—before entering a mux that selects between this clock and the PLL input clock (used in the PLL bypass mode). The PLL bypass mode is selected by setting the UPLLIMULT field of the UPLLMULT register to 0. The output clock from the mux becomes the USBPLLCLK (there is not another clock divider). Figure 8-9 shows the USB PLL function and configuration examples. Table 8-23 and Table 8-24 list the integer multiplier configuration values. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

000000 : 1/c180 000001 : 1/c180 000010 : 2/c180 000011 : 3/c180 111101: 61/c180 111110: 62/c180 111111: 63/c180 EXAMPLE 1: X1 OR XCLKIN = 60 MHZ UPLLIMULT = 000000 ( BYPASS PLL ) N/A PLLSYSCLK = 60 MHz EXAMPLE 2: X1 OR XCLKIN = 10 MHz UPLLIMULT = 011000 ( 24 ) /c180 UPLLFMULT = 00 ( NOT USED) PLLSYSCLK = ( 10 24) / 4 = 60 MHz/c180 EXAMPLE 3: X1 OR XCLKIN = 64 MHz UPLLIMULT = 000011 ( 3) /c180 UPLLFMULT = 11 ( 0.75) PLLSYSCLK = ( 64 3.75 ) / 4 = 60 MHz/c180 /c180 UPLLIMULT UPLLFMULT USBPLLCLK OUPUT OF THE USB PLL IS ALWAYS DIVIDED BY 4 00: NOT USED 01: 0.25/c180 10: 0.50/c180 11: 0.75/c180 6 2 OSCCLK (1) OUPUT OF THE USB PLL MUST BE ALWAYS 240MHz ( SO THAT USBPLLC LK IS 60MHZ ) PIN XCLKIN XCLKIN PLLINP UPLLCLKSRC UPLLCTL REG UPLLCLKENUPLLEN (2) (2) WHEN UPLLEN BIT = 0, THE USB PLL IS POWERED OFF Figure 8-9. USB PLL Table 8-23. USB PLL Integer Multiplier Configuration (Bypass PLL to × 31) SPLLIMULT(5:0) MULT VALUE 000000 b Bypass PLL 000001 b × 1 000010 b × 2 000011 b × 3 000100 b × 4 000101 b × 5 000110 b × 6 000111 b × 7 001000 b × 8 001001 b × 9 001010 b × 10 001011 b × 11 001100 b × 12 001101 b × 13 001110 b × 14 001111 b × 15 010000 b × 16 010001 b × 17 010010 b × 18 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-23. USB PLL Integer Multiplier Configuration (Bypass PLL to × 31) (continued) SPLLIMULT(5:0) MULT VALUE 010011 b × 19 010100 b × 20 010101 b × 21 010110 b × 22 010111 b × 23 011000 b × 24 011001 b × 25 011010 b × 26 011011 b × 27 011100 b × 28 011101 b × 29 011110 b × 30 011111 b × 31 www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 187 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-24. USB PLL Integer Multiplier Configuration (× 32 to × 63) SPLLIMULT(5:0) MULT VALUE 100000 b × 32 100001 b × 33 100010 b × 34 100011 b × 35 100100 b × 36 100101 b × 37 100110 b × 38 100111 b × 39 101000 b × 40 101001 b × 41 101010 b × 42 101011 b × 43 101100 b × 44 101101 b × 45 101110 b × 46 101111 b × 47 110000 b × 48 110001 b × 49 110010 b × 50 110011 b × 51 110100 b × 52 110101 b × 53 110110 b × 54 110111 b × 55 111000 b × 56 111001 b × 57 111010 b × 58 111011 b × 59 111100 b × 60 111101 b × 61 111110 b × 62 111111 b × 63 F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.11 Master Subsystem Clocking

The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divided-down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the SYSPLLCTL register. There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The 10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the 10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control Subsystem where this signal can trip the ePWM peripherals. The 32KHZCLK and 10MHZCLK clocks are also used by the Cortex-M3 Subsystem as possible sources for the Deep Sleep Clock. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register. The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode. Table 8-25 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and peripherals. Figure 8-10 shows the Cortex-M3 clocks and the Master Subsystem low-power modes. Table 8-25. Master Subsystem Low-Power Modes Cortex-M3 LOW-POWER MODE STATE OF Cortex-M3 CPU CLOCK TO Cortex-M3 PERIPHERALS REGISTER USED TO GATE CLOCKS TO Cortex-M3 PERIPHERALS MAIN PLL USB PLL CLOCK TO C28x CLOCK TO SHARED RESOURCES CLOCK TO ANALOG SUBSYSTEM Run Active M3SSCLK(1) RCGC On On PLLSYSCLK(2) PLLSYSCLK(2) ASYSCLK(3) Sleep Stopped M3SSCLK(1) RCGC or SCGC(4) On On PLLSYSCLK(2) PLLSYSCLK(2) ASYSCLK(3) Deep Sleep Stopped M3DSDIVCLK(5) RCGC or DCGC(4) Off Off Off Off Off (1) PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes 10MHZCLK divided-down per the M3SSDIVSEL register. (2) PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK. (3) PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK. (4) Depends on the ACG bit of the RCC register. (5) 32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL register (source determined inside the DSLPCLKCFG register). Figure 8-11 shows the system clock/PLL. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

I C (2) SSI (4) UART (5) USB + PHY (OTG) EMAC GP TIMER (4) uCRC WDOG 0 NMI WDOG WDOG 1 CAN 1,2 USB PLL GPIO_MUX1 /16 uDMA OSCCLK SYSDIVSEL M3SSCLK M3DEEPSLEEP ENABLE CLOCK MODE PERIPHERAL CLOCK ENABLES RCC REG RCGC REG SCGS REG M3RUN M3SLEEP M3DSDIVCLK M3DEEPSLEEP SYSCTRL REG M3SSDIVSEL REG M3SSDIVSEL DCGC REG DSLPCLKCFG REG ACG (Auto Clock Gate) M3SSCLK execution of WFI or WFE instr activates low power modes 10MHZCLK 32KHZCLK OSCCLK DC REG OSCCLK XCLKIN OSCCLK OSCCLK USBPLLCLK MISSING CLK DETECT XCLKIN INTR NVIC 10MHZCLK M3SSCLK M3CLKENBx CONTROL SUBSYSTEM M3 NMI CLOCKFAIL MAIN OSC 10MHZCLK CLOCKFAIL OSCCLK CLOCKFAIL ( GLOBAL PERIPHERAL ENABLES ) ( CLOCK GATING – RUN ) ( CLOCK GATING – SLEEP ) ( CLOCK GATING – DEEP SLEEP ) M3SSCLK REGISTER ACCESS REGISTER ACCESS PERIPH LOGIC M3SSCLK SHARED RESOURCES IPC PERIPH LOGIC CLOCKS CLPMSTAT REG SHARED RAMS MSG RAMS OFF PLLSYSCLK OSCCLK ENTER A LOW POWER MODE SELECTS TYPE OF WAKEUP SELECTS BETWEEN SLEEP AND DEEP SLEEP MODES ASSERT ANY INTERRUPT TO EXIT SLEEP OR DEEP SLEEP SYSPLLCTL REG SYSPLLSTAT REG SYSPLLMULT REG SYSDIVSEL REG MCLKREQUEST REG M3SSCLK SLEEPEXIT Figure 8-10. Cortex-M3 Clocks and Low-Power Modes C28 Read/Write /8* OSCCLK * Default at reset ** Semaphore request write System PLL PLLSYSCLK

150 MHz Max

C28 Read Only** XPLLCLKOUT Pin /4* Master (M3) Subsystem

100 MHz Max

/4* Control (C28) Subsystem on* off

37.5 MHz Max

/8* XTAL XTAL OSC XCLKIN X1/X2 Ext. XTAL 4 – 20 MHz X1 Ext. CLK source up to 30 MHz M3 Read/Write Figure 8-11. System Clock/PLL F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.11.1 Cortex-M3 Run Mode

In Run Mode, the Cortex-M3 processor, memory, and most of the peripherals are clocked by the M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is accomplished through corresponding peripheral configuration registers. Clock gating for individual peripherals is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to peripherals that are enabled in a corresponding DC (Device Configuration) register. Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex-M3 CPU and forces the Cortex-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of the SLEEPDEEP bit of the Cortex-M3 SYSCTRL register. To come out of a low-power mode, any properly configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex-M3 processor/subsystem to Run Mode.

8.11.2 Cortex-M3 Sleep Mode

In Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking, and thus the code is no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clock-gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode. Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently (for the ISR and thereafter). www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 191 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.11.3 Cortex-M3 Deep Sleep Mode

In Deep Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking and thus the code is no longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input clock to the C28x CPU and Shared Resources are turned off. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the DCGS register. RCGS and DCGS clock gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run Mode. One of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected with the DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to DSDIVOVRIDE bits of the DSLPCLKCFG register. The output of this Deep Sleep Divider is further divided-down per the M3SSDIVSEL bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If 32KHXCLK or 10MHZCLK is selected in Deep Sleep mode, the internal oscillator circuit (that generates OSCCLK) is turned off. The Cortex-M3 processor should enter the Deep Sleep mode only after first confirming that the C28x is already in the STANDBY mode. Typically, just before entering the STANDBY mode, the C28x will record in the CLPMSTAT that it is about to do so. The Cortex-M3 processor can read the CLPMSTAT register to check if the C28x is in STANDBY mode, and only then should the Cortex-M3 processor go into Deep Sleep. The reason for the Cortex-M3 processor to confirm that the C28x is in STANDBY mode before the Cortex-M3 processor enters the Deep Sleep mode is that the Deep Sleep mode shuts down the clock to C28x and its peripherals, and if this clock shutdown is not expected by the C28x, unintended consequences could result for some of the C28x control peripherals. Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep Mode depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Deep Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently (for the ISR and thereafter). F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.12 Control Subsystem Clocking

The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1 external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. The Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register. Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is done through the CPCLKCR0,2,3 registers. The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by OSCCLK or 10MHZCLK (see Figure 8-12). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and PIE. The Control Subsystem operates in one of three modes: Normal Mode, IDLE Mode, or STANDBY Mode. Table 8-26 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and peripherals. Figure 8-12 shows the Control Subsystem clocks and low-power modes. Table 8-26. Control Subsystem Low-Power Modes C28x LOW-POWER MODE(1) STATE OF C28x CPU C28CPUCLK(2) C28SYSCLK(3) REGISTERS USED TO GATE CLOCKS TO C28x PERIPHERALS Normal Active On On CPCLKCR0,1,3 IDLE Stopped Off On CPCLKCR0,1,3 STANDBY Stopped Off Off N/A (1) The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem enters the Deep Sleep mode. (2) C28CPUCLK is an output from the C28x CPU. C28CPUCLK clocks the C28x FPU, VCU, and PIE. (3) C28SYSCLK is an output from the C28x CPU. C28SYSCLK clocks C28x peripherals.

8.12.1 C28x Normal Mode

In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK, OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals. Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into IDLE mode or STANDBY Mode.

8.12.2 C28x IDLE Mode

In IDLE Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The C28SYSCLK continues to run. Exit from IDLE Mode is accomplished by any enabled interrupt or the C28NMIINT (C28x nonmaskable interrupt). Upon exit from IDLE Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the IDLE Mode. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 193 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

execution of IDLE instruction activates the IDLES signal ENTER IDLE MODE ENTER ST ANDBY MODE EXIT IDLE MODE EXIT ST ANDBY MODE IDLES LPM(0)LPM(1) Requests To Wake From STANDBY Mode Requests To Wake From IDLE Mode TINT2 TIMER 2 C28 XINT(3) C28x NMI C28 DMA C28CLKENBx LOSPCP REG ECAP (6) I C C28LSPCLK C28x CPU ‘0’ C28CLKIN MASTER SUBSYSTEM ST ANDBY MODE PLLSYSCLK LPMWAKE /32 /14 MTOCIPC(1) IPC LSPCLK CLOCKFAIL TIMER 1 TINT 1 C28x NMI EQEP (3) GPIO_MUX1 SCI SPI McBSP TMR2CLK CPCLKCR3 REG CPCLKCR1 REG CPCLKCR0 REG 10MHZCLK C28x PIE PIEINTRS (1) OSCCLK /16 OSCCLK C28SYSCLK 10MHZCLK CTMR2CLK PRESCALE TMR2CLKSRCSEL CLKCTL REG C28SYSCLK GPIO_MUX1 PULSE STRETCH SOCAOSOCBOSYNCO OFF CCLKCTL REG CLKDIV ASYSCLK ANALOG SUBSYSTEM SRXRST ACIBRST ASYSRST C28x PIE PIEINTRS (12:1) C28 FPU/VCU CLPMST AT REG C28SYSCLK LPM WAKEUP LPMSEL1 REG LPMSEL2 REG SELECT QUALIFICATION SELECT ONE OF 62 GPIs SYSPLLST AT REG SYSPLLMULT REG SYSPLLCTL REG SYSDIVSEL REG CCLKREQUEST REG M3SSCLK CLKOFF REG GPIO_MUX1/4 XCLKOUT PF2_GPIO34 C28SYSCLK C28SYSCLK 0 XPLLCLKCFG REG XPLLCLKOUTDIV OFF/4 OFF CXCLK REG XCLKOUTDIV (NOTE: IN REVISION 0 OF SILICON, XCLKOUT = PLLSYSCLK DIVIDED DOWN BY 1, 2 OR 4)EPWM (9) GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) Figure 8-12. C28x Clocks and Low-Power Modes

8.12.3 C28x STANDBY Mode

In STANDBY Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK, and C28SYSCLK are turned off. Exit from STANDBY Mode is accomplished by 1 of 62 GPIOs from the GPIO_MUX1 block, or MTOCIPCINT2 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the CPCLKCR0 register) before propagating into the wake request logic. Cortex-M3 should use CLPMSTAT register bits to tell the C28x to go into STANDBY mode before going into Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control software is not expecting this clock to shut off. When the device is in Deep Sleep/STANDBY mode, wake-up should happen only from the Master Subsystem, because all C28x clocks are off (C28CLKIN, C28CPUCLK, C28SYSCLK), thus preventing the C28x from waking up first. Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the STANDBY Mode. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Section 6.2.1 are not available).

8.13 Analog Subsystem Clocking

The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the C28x processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog Subsystem resets— ACIBRST and SRXRST. Therefore, while normally the C28x controls the frequency of ASYSCLK, it is possible for the Cortex-M3 software to restore the ASYSCLK to its default value by resetting the Analog Subsystem. The ASYSCLK is shut down when the Cortex-M3 processor enters the Deep Sleep mode.

8.14 Shared Resources Clocking

The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK. The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK. Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is clocked by M3SSCLK.

8.15 Loss of Input Clock (NMI Watchdog Function)

The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of the Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external crystal or just pin X1 when using an external oscillator. The second clock enters the chip through the XCLKIN pin and this second clock can be used to clock the USB PLL and CAN peripherals. Only the main clock has a built-in Missing Clock Detection circuit to recognize when the clock source vanishes and to enable other chip components to take corrective or recovery action from such event (see Figure 8-13). The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator) so that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing source clock, the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex-M3 NMI circuit, the C28x NMI, ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses an active CLOCKFAIL signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK. Simultaneously, the ePWM peripherals can use the CLOCKFAIL signal to stop down driving motor control outputs. The NMI blocks respond to the CLOCKFAIL signal by sending an NMI interrupt to a corresponding CPU, while starting the associated NMI watchdog counter. If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in the device reset. If the software does react to the NMI, the software can prevent the impending reset by disabling the watchdog timers, and then the software can initiate necessary corrective action such as switching over to an alternative clock source (if available) or the software can initiate a shut-down procedure for the system. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 195 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

ADDITIONAL CLOCK CONTROL LOGIC GPIO_MUX1 THE INPUT CLOCK IS DISRUPTED CLOCKFAIL SIGNAL BECOMES ACTIVE PLLSYSCLK SWITCHES TO THE 10MHZCLK CPUS RESPOND TO NMIS AND THE WATCHDOGS ST ART COUNTING SOFTWARE TAKES CORRECTIVE/RECOVERY ACTION IF SOFTWARE DOES NOT STOP THE WATCHDOG COUNTERS, THE WATCHDOGS WILL RESET THE DEVICE AFTER THE COUNT RUNS OUT TYPICAL ACTIVITY FOLLOWING A MISSING CLOCK DETECTION : CLOCK FAIL SIGNAL IS SENT TO M3 NMI BLOCK, C28 NMI BLOCK, EPWM MODULES AND THE PLLSYSCLK MUX M3SSCLK C28CLKIN PIN EPWM_A EPWM_B OTHER NMI SOURCES CLOCKFAIL CLOCKFAIL C28CLKIN M3NMI C28NMI PIN PIN Figure 8-13. Missing Clock Detection

8.16 GPIOs and Other Pins

Most Concerto external pins are shared among many internal peripherals. This sharing of pins is accomplished through several I/O muxes where a specific physical pin can be assigned to selected signals of internal peripherals. Most of the I/O pins of the Concerto MCU can also be configured as programmable GPIOs. Exceptions include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and VREG18EN internal voltage regulator enables; and five JTAG pins. The 74 primary GPIOs are grouped in 2 programmable blocks: GPIO_MUX1 block (66 pins) and GPIO_MUX2 block (8 pins). Additionally, eight secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins). Figure 8-14 shows the GPIOs and other pins.

8.16.1 GPIO_MUX1

Sixty-six pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers to all Cortex-M3 peripherals, to all C28x peripherals, to 66General-Purpose Inputs, to 66 General-Purpose Outputs, or a mixture of all of the above. Sixty-two pins of GPIO_MUX1 (GPIO0–GPIO63 minus GPIO39 and GPIO44) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External Interrupts to the C28x PIE, and the C28x STANDBY Mode Wakeup signal (LMPWAKE). Additionally, each GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex-M3 peripherals (and not to C28x peripherals). Figure 8-15 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two subsystems, based on how the configuration registers are programmed in the blue and green blocks (see Figure 8-16 for the configuration registers). Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or GPIOs to the 66 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to pins, the F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[A:J] IRQ signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem. XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The nine GPIO[A:J] IRQ signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12 GPTRIP[12:1] signals carry trip events from selected external pins to C28x control peripherals—ePWM, eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM GPIO Select block where one of them can be selected to wake up the C28x CPU from Low-Power Mode. Sixty-six (66) GPI signals go to the C28x QUAL block where they can be configured with a qualification sampling period (see Figure 8-16). The configuration registers for the muxing of Master Subsystem peripherals are organized in nine sets (A–J), with each set being responsible for eight pins. These nine sets of registers are programmable by the Cortex-M3 CPU through the AHB bus or the APB bus. The configuration register for the muxing of Control Subsystem peripherals are organized in three sets (A–C), with each set being responsible for up to 32 pins. These registers are programmable by the C28x CPU through the C28x CPU bus. Figure 8-16 shows set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem registers, and the muxing logic for one GPIO pin as driven by these registers. GPIO_MUX2 GPIO_MUX1 MUX GPIO COMPOUT (6:1) ADC ADC 66 66 MUXGPIO XINT (3) EPWM (9) ECAP (6) EQEP (3) McBSP SPI MCLRAMFSRAMDRAMCLXAMFSXAMDXA USB EPI0S (41:0) USB0VBUSUSB0DMUSB0DP USB0ID USB0EPENUSB0OFLT CLOCKS NMI M3EXTNMI XCLKINXCLKOUTLPMWAKE RESETSDEBUG X1 X2 JTAG (7) SCI SCIRXDASCITXDA EPWM (9:1) BEPWM (9:1) AGPTRIP (12:1)GPTRIP (6:4)GPTRIP (12:7)ECAP (6:1) EQEP (3:1) SEQEP (3:1) AEQEP (3:1) I SPISOMISPISIMOSPICLKSPISTE EQEP (3:1) B SDAASCLA I C EMAC MII TX0MII TX1MII TX2MII TX3MII RX0MII RX1MII RX2MII RX3 MII TXENMII MDCMII MDIO MII PHYRSTNMII PHYINTRN MII RXDVMII RXER MII TXCKMII RXCKMII CRSMII COL MII TXER USB PLL XCLKIN MUXGPIO AIO_MUX2 10 MUXGPIO AIO_MUX1 10 VREGS VREG18ENVREG12EN XRSARS NVIC GPIO (H:A) IRQ SSI (4) I C (2) CAN (2) UART (5) SSI (3:0) RXSSI (3:0) TXSSI (3:0) CLKSSI (3:0) FSS I2C (1:0) SCLI2C (1:0) SDACAN (1:0) RXCAN (1:0) TX XCLKINU (4:0) RXU (4:0) TX COMPARATOR + DAC UNITS VDDA (3.3V) VSSA (0V) LPM WAKEUP LPMWAKE C28X CPU M3EXTNMI NMI COMPB2COMPA1 COMPA2 COMPA3 ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 COMPB5COMPA4 COMPA5 COMPA6 EPI GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) Figure 8-14. GPIOs and Other Pins www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 197 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

(3) EPWM (9) ECAP (6) EQEP (3)McBSP SPI USB EPI SCI MCLRAMFSRAMDRAMCLXAMFSXAMDXA SCIRXDASCITXDA EPWM (9:1) BEPWM (9:1) A GPTRIP (12:1) GPTRIP (6:4)GPTRIP (12:7) ECAP (6:1)EQEP (3:1) SEQEP (3:1) AEQEP (3:1) ISPISOMISPISIMOSPICLKSPISTE EQEP (3:1) B SDAASCLA I C EMACUSB PLL MII TX0MII TX1MII TX2MII TX3MII RX0MII RX1MII RX2MII RX3 MII TXENMII MDCMII MDIOMII PHYRSTNMII PHYINTRN MII RXDVMII RXER MII TXCKMII RXCKMII CRSMII COL MII TXEREPI0S (41:0)USB0VBUSUSB0DMUSB0DP USB0ID USB0EPENUSB0OFLT XCLKIN NVIC GPIO (H:A) IRQ SSI (4) I C (2) CAN (2) UART (5) SSI (3:0) RXSSI (3:0) TXSSI (3:0) CLKSSI (3:0) FSS I2C (1:0) SCLI2C (1:0) SDACAN (1:0) RXCAN (1:0) TX XCLKIN M3 PERIPHERAL SIGNAL ROUTING M3 MUX G U (4:0) RXU (4:0) TX C28 MUX B C28 PERIPHERAL SIGNAL ROUTING PIN - LEVEL MUX C28x CPU CPU uDMA XCLKIN BUS BRIDGE C28x DMA C28 MUX A C28 MUX C M3 APB BUS M3 AHB BUS C28 DMA BUS C28 CPU BUS M3 MUX A M3 MUX B M3 MUX D M3 MUX E M3 MUX F M3 MUX H M3 MUX J M3 MUX C NMI EXT NMI INTERRUPTS 8 8 8 8 7 7 8 8 4 32 30 4 GPTRIP (12:1) LPM WAKEUP LPM WAKE GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) (TERMINALS GPIO 39 AND GPIO 44 ARE NOT PINNED OUT ON THIS DEVICE) Figure 8-15. GPIO_MUX1 Block F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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GPIO_MUX1 PINS GPIOICR REG GPIOAFSEL REGGPIODEN REG XRS GPIOCSEL REG GPAMUX1 REG GPAMUX2 REG SEL(1:0) FROM C28 PERIPH 1-3PERIPHERALS 1-3 REPRESENT A SET OF UP TO THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN GPASET REG GPACLEAR REG GPA TOGGLE REG GPIOPUR REG GPIOODR REG C28 REG SET A C28 REG SET A GREY LOGIC IS SPECIFIC TO ONE DEVICE I/O PIN GREEN REGISTER SET A SHOWN REPRESENTS 32 OF 66 GPIOs. THE REMAINING 34 GPIOs ARE CONTROLLED BY SIMILAR REGISTER SETS B AND C OPEN DRAIN LOGIC M3 REG SET A QUAL SYNC C28SYSCLK TO C28x CPU WAKE-UP FROM A LOW POWER MODE GPTRIP (12:1) TO XINT, ECAP, EPWM GPADIR REG C28 REG SET A GPACTRL REG GPIODA TA REG GPIODIR REG GPIOAPSEL REG GPIOPCTL REG GPIOIS REG GPIOIBE REG GPIOIEV REG GPIOIM REG GPIORIS REG GPIOMIS REG GPIOICR REG GPIOAFSEL REGGPIODEN REG GPIO (A) IRQ TO/FROM M3 PERIPH 1 - 11 TO/FROM M3 PERIPH 12 - 15 GPIOCSEL REG PERIPHERALS 1-15 REPRESENT A SET OF UP TO

15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN

‘1’ ‘1’ ‘0’ OUTPUT INPUT OEOE OE OE A-H INTR REQUESTS TO M3 N/C SEL(1:0)

6 SAMPLES

3 SAMPLES

SEL(1:0) GPASEL1 REG GPASEL2 REG C28 REG SET A (C28 GPIO) GPADAT REG N/C AT RESET (M3 GPIO) PULLUP DISABLED ON RESET PRIMARY AT RESET GPIOLOCK REG GPIOCR REG M3 REG SET A GPIOAMSEL REG M3 REG SET A XCLKINGPIO63 ONLY M3 CLOCKS (USB ANALOG SIGNALS) EACH I/O PIN HAS A DEDICATED PAIR OF BITS FOR MUX SELECT EACH I/O PIN HAS A DEDICATED PAIR OF BITS FOR MUX SELECT PULLUP ENB ORANGE LOGIC SHOWS USB ANALOG FUNCTIONS (APPLIES TO 4 PINS ONLY) GPIOAMSEL REG (4 PINS ONLY) ANALOG USB SIGNALS BLUE REGISTER SET A REPRESENTS 8 OF 66 GPIOs. REMAINING 58 GPIOs ARE CONTROLLED BY SIMILAR REGISTER SETS B, C, D, E, F, I, J, H GPTRIP1SEL REG GPTRIP12SEL REG GPI (63:0) MINUS GPI 39 AND GPI 64 Figure 8-16. GPIO_MUX1 Pin Mapping Through Register Set A For each of the 8 pins in set A of the Cortex-M3 GPIO registers, register GPIOPCTL selects between 1 of 11 possible primary Cortex-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The input takes the reverse path. See Table 8-27 and Table 8-28 for the mapping of Cortex-M3 peripheral signals to GPIO_MUX1 pins. Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along the muxing chain towards a given pin. The input takes the reverse path. See Table 8-29 for the mapping of C28x peripheral signals to GPIO_MUX1 pins. In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not available for digital GPIO_MUX1 options as described above. Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is always available at these modules where it can be selected through local registers. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 199 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Section 6.2.1 are not available). Table 8-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes) ANALOG MODE (USB PINS)(1) DEVICE PIN NAME PRIMARY MODE 1 PRIMARY MODE 2 PRIMARY MODE 3 PRIMARY MODE 4 PRIMARY MODE 5 PRIMARY MODE 6 PRIMARY MODE 7 PRIMARY MODE 8 PRIMARY MODE 9 PRIMARY MODE 10 PRIMARY MODE 11 – PA0_GPI – PA1_GPI – PA2_GPI – PA3_GPI – PA4_GPI O4 SSI0RX – MIITXD0 – CAN0RX – – – – – – – PA5_GPI O5 SSI0TX – MIIRXDV – CAN0TX – – – – – – – PA6_GPI O6 I2C1SCL CCP1 MIIRXCK – – CAN0RX – USB0EPE N – – – – PA7_GPI O7 I2C1SDA CCP4 MIIRXER – – CAN0TX CCP3 USB0PFL T – – – – PB0_GPI – PB1_GPI – PB2_GPI O10 I2C0SCL – – CCP3 CCP0 – – USB0EPE N – – – – PB3_GPI O11 I2C0SDA – – – – – – USB0PFL T – – – – PB4_GPI O12 – – – U2RX CAN0RX – U1RX EPI0S23 – – – – PB5_GPI O13 – CCP5 CCP6 CCP0 CAN0TX CCP2 U1TX EPI0S22 – – – – PB6_GPI O14 CCP1 CCP7 – – – CCP5 – EPI0S37 (2) – – – – PB7_GPI O15 – – – EXTNMI – – MIIRXD1 EPI0S36 (2) – – – – PD0_GPI O16 – CAN0RX – U2RX U1RX CCP6 MIIRXDV – – – – – PD1_GPI O17 – CAN0TX – U2TX U1TX CCP7 MIITXER – – CCP2 – – PD2_GPI O18 U1RX CCP6 – CCP5 – – – EPI0S20 – – – – PD3_GPI O19 U1TX CCP7 – CCP0 – – – EPI0S21 – – – – PD4_GPI O20 CCP0 CCP3 – MIITXD3 – – – – – EPI0S19 – – PD5_GPI O21 CCP2 CCP4 – MIITXD2 – – – – U2RX EPI0S28 – – PD6_GPI O22 – – – MIITXD1 – – – – U2TX EPI0S29 – – PD7_GPI O23 – – CCP1 MIITXD0 – – – – – EPI0S30 – – PE0_GPI O24 – SSI1CLK CCP3 – – – – EPI0S8 USB0PFL T – – F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes) (continued) ANALOG MODE (USB PINS)(1) DEVICE PIN NAME PRIMARY MODE 1 PRIMARY MODE 2 PRIMARY MODE 3 PRIMARY MODE 4 PRIMARY MODE 5 PRIMARY MODE 6 PRIMARY MODE 7 PRIMARY MODE 8 PRIMARY MODE 9 PRIMARY MODE 10 PRIMARY MODE 11 – PE1_GPI O25 – SSI1FSS – CCP2 CCP6 – – EPI0S9 – – – – PE2_GPI O26 CCP4 SSI1RX – – CCP2 – – EPI0S24 – – – – PE3_GPI O27 CCP1 SSI1TX – – CCP7 – – EPI0S25 – – – – PE4_GPI O28 CCP3 – – – U2TX CCP2 MIIRXD0 EPI0S34 (2) – – – – PE5_GPI (2) – – – – PE6_GPI – PE7_GPI – PF0_GPI – PF1_GPI – PF2_GPI O34 – – MIIPHYIN TR – – – – EPI0S32(2 ) SSI1CLK – – – PF3_GPI O35 – – MIIMDC – – – – EPI0S33(2 ) SSI1FSS – – – PF4_GPI O36 CCP0 – MIIMDIO – – – – EPI0S12 SSI1RX – – – PF5_GPI O37 CCP2 – MIIRXD3 – – – – EPI0S15 SSI1TX – – USB0VBU S PF6_GPI O38 CCP1 – MIIRXD2 – – – – EPI0S38(2 ) – – – PF7_GPI O39 (no pin) – PG0_GPI O40 U2RX – I2C1SCL – – – USB0EPE N EPI0S13 – – – – PG1_GPI O41 U2TX – I2C1SDA – – – – EPI0S14 – – – USB0DM PG2_GPI O42 – – MIICOL – – – – EPI0S39(2 ) – – – – PG3_GPI PG4_GPI O44 (no pin) USB0DP PG5_GPI O45 CCP5 – MIITXEN – – – – EPI0S40(2 ) – – – USB0ID PG6_GPI O46 – – MIITXCK – – – – EPI0S41(2 ) – – – – PG7_GPI O47 – – MIITXER – – – – CCP5 EPI0S31 – – www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 201 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes) (continued) ANALOG MODE (USB PINS)(1) DEVICE PIN NAME PRIMARY MODE 1 PRIMARY MODE 2 PRIMARY MODE 3 PRIMARY MODE 4 PRIMARY MODE 5 PRIMARY MODE 6 PRIMARY MODE 7 PRIMARY MODE 8 PRIMARY MODE 9 PRIMARY MODE 10 PRIMARY MODE 11 – PH0_GPI O48 CCP6 – MIIPHYRS – PH1_GPI – PH2_GPI – PH3_GPI O51 – – – USB0EPE N – – – EPI0S0 MIITXD2 – – – PH4_GPI O52 – – – USB0PFL T – – – EPI0S10 MIITXD1 – SSI1CLK – PH5_GPI O53 – – – – – – – EPI0S11 MIITXD0 – SSI1FSS – PH6_GPI O54 – – – – – – – EPI0S26 MIIRXDV – SSI1RX – PH7_GPI O55 – – MIIRXCK – – – – EPI0S27 – – SSI1TX – PJ0_GPIO 56 – – MIIRXER – – – – EPI0S16 – – I2C1SCL – PJ1_GPIO T – I2C1SDA – PJ2_GPIO – PJ3_GPIO – PJ4_GPIO – PJ5_GPIO – PJ6_GPIO PJ7_GPIO XCLKIN PC0_GPI O64 (no pin) PC1_GPI O65 (no pin) PC2_GPI O66 (no pin) PC3_GPI O67 (no pin) – PC4_GPI O68 CCP5 – MIITXD3 – CCP2 CCP4 – EPI0S2 CCP1 – – – PC5_GPI O69 CCP1 – – – CCP3 USB0EPE N – EPI0S3 – – – – PC6_GPI O70 CCP3 – – – U1RX CCP0 USB0PFL T EPI0S4 – – – – PC7_GPI O71 CCP4 – – CCP0 U1TX USB0PFL T – EPI0S5 – – – (1) Blank fields represent Reserved functions. (2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes) ANALOG MODE (USB PINS)(1) DEVICE PIN NAME ALTERNATE MODE 12 ALTERNATE MODE 13 ALTERNATE MODE 14 ALTERNATE MODE 15 – PA1_GPIO1 – – – SSI1FSS – PA3_GPIO3 – – – SSI1CLK – PA6_GPIO6 MIITXD3 – – – – PA7_GPIO7 MIIRXD1 – – – – PB0_GPIO8 – SSI2TX CAN1TX U4TX – PB2_GPIO10 – SSI2CLK CAN1RX U4RX – PB3_GPIO11 – SSI2FSS U1RX – – PB4_GPIO12 – – CAN1TX SSI1TX – PB5_GPIO13 – – CAN1RX SSI1RX – PB6_GPIO14 MIICRS I2C0SDA U1TX SSI1CLK – PB7_GPIO15 – I2C0SCL U1RX SSI1FSS – PD0_GPIO16 MIIRXD2 SSI0TX CAN1TX USB0EPEN – PD1_GPIO17 MIICOL SSI0RX CAN1RX USB0PFLT – PD2_GPIO18 – SSI0CLK U1TX CAN0RX – PD3_GPIO19 – SSI0FSS U1RX CAN0TX – PD4_GPIO20 – – U3TX CAN1TX – PD5_GPIO21 – – U3RX CAN1RX – PD6_GPIO22 – – I2C1SDA U1TX – PD7_GPIO23 – – I2C1SCL U1RX – PE0_GPIO24 – SSI3TX CAN0RX SSI1TX – PE1_GPIO25 – SSI3RX CAN0TX SSI1RX – PE2_GPIO26 – SSI3CLK U2RX SSI1CLK – PE3_GPIO27 – SSI3FSS U2TX SSI1FSS – PE4_GPIO28 – U0RX EPI0S38(2) USB0EPEN – PE5_GPIO29 MIITXER U0TX – USB0PFLT – PE6_GPIO30 MIIMDIO CAN0RX – – – PE7_GPIO31 MIIRXD3 CAN0TX – – – PF0_GPIO32 – I2C0SDA TRACED2 – – PF1_GPIO33 – I2C0SCL TRACED3 – – PF2_GPIO34 – – TRACECLK XCLKOUT – PF3_GPIO35 – U0TX TRACED0 – USB0VBUS PF6_GPIO38 – – – – – PF7_GPIO39 (no pin) – – – – www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes) (continued) ANALOG MODE (USB PINS)(1) DEVICE PIN NAME ALTERNATE MODE 12 ALTERNATE MODE 13 ALTERNATE MODE 14 ALTERNATE MODE 15 – PG0_GPIO40 MIIRXD2 U4RX – – – PG1_GPIO41 MIIRXD1 U4TX – – USB0DM PG2_GPIO42 – – – – – PG3_GPIO43 MIIRXDV – TRACED1 – – PG4_GPIO44 (no pin) – – – – USB0DP PG5_GPIO45 – – – – USB0ID PG6_GPIO46 – – – – – PH0_GPIO48 – SSI3TX – – – PH1_GPIO49 MIIRXD0 SSI3RX – – – PH2_GPIO50 – SSI3CLK – – – PH3_GPIO51 – SSI3FSS – – – PH6_GPIO54 MIITXEN SSI0TX – – – PH7_GPIO55 MIITXCK SSI0RX – – – PJ0_GPIO56 – SSI0CLK – – – PJ1_GPIO57 MIIRXDV SSI0FSS – – – PJ2_GPIO58 MIIRXCK SSI0CLK U0TX – – PJ3_GPIO59 MIIMDC SSI0FSS U0RX – – PJ4_GPIO60 MIICOL SSI1CLK – – – PJ5_GPIO61 MIICRS SSI1FSS – – – PJ6_GPIO62 MIIPHYINTR U2RX – – – PJ7_GPIO63/ XCLKIN MIIPHYRST U2TX – – – PC0_GPIO64 (no pin) – – – – – PC1_GPIO65 (no pin) – – – – – PC2_GPIO66 (no pin) – – – – – PC3_GPIO67 (no pin) – – – – (1) Blank fields represent Reserved functions. (2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes) ANALOG MODE (USB PINS)(1) DEVICE PIN NAME C28x PERIPHERAL MODE 0 C28x PERIPHERAL MODE 1 C28x PERIPHERAL MODE 2 C28x PERIPHERAL MODE 3 – PA0_GPIO0 GPIO0 EPWM1A – – – PA1_GPIO1 GPIO1 EPWM1B ECAP6 – – PA2_GPIO2 GPIO2 EPWM2A – – – PA3_GPIO3 GPIO3 EPWM2B ECAP5 – – PA4_GPIO4 GPIO4 EPWM3A – – – PA5_GPIO5 GPIO5 EPWM3B MFSRA ECAP1 – PA6_GPIO6 GPIO6 EPWM4A – EPWMSYNCO – PA7_GPIO7 GPIO7 EPWM4B MCLKRA ECAP2 – PB0_GPIO8 GPIO8 EPWM5A – ADCSOCAO – PB1_GPIO9 GPIO9 EPWM5B – ECAP3 – PB2_GPIO10 GPIO10 EPWM6A – ADCSOCBO – PB3_GPIO11 GPIO11 EPWM6B – ECAP4 – PB4_GPIO12 GPIO12 EPWM7A – – – PB5_GPIO13 GPIO13 EPWM7B – – – PB6_GPIO14 GPIO14 EPWM8A – – – PB7_GPIO15 GPIO15 EPWM8B – – – PD0_GPIO16 GPIO16 SPISIMOA – – – PD1_GPIO17 GPIO17 SPISOMIA – – – PD2_GPIO18 GPIO18 SPICLKA – – – PD3_GPIO19 GPIO19 SPISTEA – – – PD4_GPIO20 GPIO20 EQEP1A MDXA – – PD5_GPIO21 GPIO21 EQEP1B MDRA – – PD6_GPIO22 GPIO22 EQEP1S MCLKXA – – PD7_GPIO23 GPIO23 EQEP1I MFSXA – – PE0_GPIO24 GPIO24 ECAP1 EQEP2A – – PE1_GPIO25 GPIO25 ECAP2 EQEP2B – – PE2_GPIO26 GPIO26 ECAP3 EQEP2I – – PE3_GPIO27 GPIO27 ECAP4 EQEP2S – – PE4_GPIO28 GPIO28 SCIRXDA – – – PE5_GPIO29 GPIO29 SCITXDA – – – PE6_GPIO30 GPIO30 – – EPWM9A – PE7_GPIO31 GPIO31 – – EPWM9B – PF0_GPIO32 GPIO32 I2CASDA SCIRXDA ADCSOCAO – PF1_GPIO33 GPIO33 I2CASCL EPWMSYNCO ADCSOCBO – PF2_GPIO34 GPIO34 ECAP1 SCIRXDA XCLKOUT – PF3_GPIO35 GPIO35 SCITXDA – – – PF4_GPIO36 GPIO36 SCIRXDA – – – PF5_GPIO37 GPIO37 ECAP2 – – USB0VBUS PF6_GPIO38 GPIO38 – – – – PF7_GPIO39 (no pin) – – – – www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

Table 8-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes) (continued) ANALOG MODE (USB PINS)(1) DEVICE PIN NAME C28x PERIPHERAL MODE 0 C28x PERIPHERAL MODE 1 C28x PERIPHERAL MODE 2 C28x PERIPHERAL MODE 3 – PG0_GPIO40 GPIO40 – – – – PG1_GPIO41 GPIO41 – – – USB0DM PG2_GPIO42 GPIO42 – – – – PG3_GPIO43 GPIO43 – – – – PG4_GPIO44 (no pin) – – – – USB0DP PG5_GPIO45 GPIO45 – – – USB0ID PG6_GPIO46 GPIO46 – – – – PG7_GPIO47 GPIO47 – – – – PH0_GPIO48 GPIO48 ECAP5 – – – PH1_GPIO49 GPIO49 ECAP6 – – – PH2_GPIO50 GPIO50 EQEP1A – – – PH3_GPIO51 GPIO51 EQEP1B – – – PH4_GPIO52 GPIO52 EQEP1S – – – PH5_GPIO53 GPIO53 EQEP1I – – – PH6_GPIO54 GPIO54 SPISIMOA – EQEP3A – PH7_GPIO55 GPIO55 SPISOMIA – EQEP3B – PJ0_GPIO56 GPIO56 SPICLKA – EQEP3S – PJ1_GPIO57 GPIO57 SPISTEA – EQEP3I – PJ2_GPIO58 GPIO58 MCLKRA – EPWM7A – PJ3_GPIO59 GPIO59 MFSRA – EPWM7B – PJ4_GPIO60 GPIO60 – – EPWM8A – PJ5_GPIO61 GPIO61 – – EPWM8B – PJ6_GPIO62 GPIO62 – – EPWM9A – PJ7_GPIO63/ XCLKIN GPIO63 – – EPWM9B – PC0_GPIO64 (no pin) – – – – – PC1_GPIO65 (no pin) – – – – – PC2_GPIO66 (no pin) – – – – – PC3_GPIO67 (no pin) – – – – – PC4_GPIO68 GPIO68 – – – – PC5_GPIO69 GPIO69 – – – – PC6_GPIO70 GPIO70 – – – – PC7_GPIO71 GPIO71 – – – (1) Blank fields represent Reserved functions. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.16.2 GPIO_MUX2

The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed through a separate set of registers from those used to program GPIO_MUX1. The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set E. They are accessible by the C28x CPU only. The middle portion of Figure 8-17 shows set G of Control Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPEMUX1 register selects one of six possible digital output signals from analog comparators, or one of eight general-purpose GPIO digital outputs. The GPEPUD register disables pullups for the GPIO_MUX2 pins when a corresponding bit of that register is set to “1”. Other registers of set G allow reading and writing of the eight GPIO bits, as well as setting the direction for each of the bits (read or write). See Table 8-30 for the mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2. Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPEMUX1 register to “00”, “01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPEMUX1 register to “00” (Peripheral Mode 0) assigns pin GPIO130 to internal signal GPIO130 (digital GPIO). Setting bits 5–4 of the GPEMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO130 to internal signal COMP6OUT coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently available. Table 8-30. GPIO_MUX2 Pin Assignments (C28x Peripheral Modes) DEVICE PIN NAME(1) C28x PERIPHERAL MODE 0 C28x PERIPHERAL MODE 1 C28x PERIPHERAL MODE 2 C28x PERIPHERAL MODE 3 GPIO128 GPIO128 – – – GPIO129 GPIO129 – – COMP1OUT GPIO130 GPIO130 – – COMP6OUT GPIO131 GPIO131 – – COMP2OUT GPIO132 GPIO132 – – COMP3OUT GPIO133 GPIO133 – – COMP4OUT GPIO134 GPIO134 – – – GPIO135 GPIO135 – – COMP5OUT (1) Blank fields represent Reserved functions. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 207 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

AIO_MUX2 PINS AIOSET REG AIOCLEAR REG AIOTOGGLE REG AIODIR REG AIO_MUX2 AIODAT REG C28x CPU ADC AIOMUX2 REG C28 CPU BUSANALOG BUS GPIOPUR REGGPGPUD REG ‘1’ PULLUP DISABLED ON RESET PULLUP DIS GPEDIR REG AIODIR REG ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 AIO18 AIO20 AIO22 AIO28 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 ONE OF 8 GPIO_MUX2 PINS GPESET REG GPECLEAR REG GPETOGGLE REG GPEDIR REG GPIO_MUX2 GPEDA T REG COMPARATOR + DAC UNITS GPEMUX1 REG COMPA1 COMPA2 COMPA3 COMPB2 COMPA4 COMPA5 COMPA6 COMPB5 ANALOG COMMON INTERFACE BUS COMPOUT1 COMPOUT2 COMPOUT3 COMPOUT4 COMPOUT5 COMPOUT6 ONE OF 10 AIO_MUX1 PINS AIOSET REG AIOCLEAR REG AIOTOGGLE REG AIODIR REG AIO_MUX1 AIODAT REG ADC AIOMUX1 REG AIODIR REG ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 AIO2 AIO4 AIO6 AIO12 ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 GPIO128 GPIO129 GPIO130 GPIO131 GPIO132 GPIO133 GPIO134 GPIO135 Figure 8-17. Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2

8.16.3 AIO_MUX1

The ten pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. While AIO_MUX1 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1 block is programmed through a separate set of registers from those used to program AIO_MUX2. The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU only. The top portion of Figure 8-17 shows Control Subsystem registers and muxing logic for the associated ten AIO pins. The AIOMUX1 register selects one of ten possible analog input signals or one of four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of the bits (read or write). See Table 8-31 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX1. AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1 register to ‘0’ assigns pin ADC1INA2 to internal signal AIO2 (digital GPIO). Setting bit 5 of the AIOMUX1 register to ‘1’ assigns pin ADC1INA2 to analog inputs ADC1INA2 or COMPA1 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are “don’t cares”. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Table 8-31. AIO_MUX1 Pin Assignments (C28x AIO Modes) DEVICE PIN NAME(1) (2) C28x AIO MODE 0(3) C28x AIO MODE 1(4) ADC1INA0 – ADC1INA0 ADC1INA2 AIO2 ADC1INA2, COMPA1 ADC1INA3 – ADC1INA3 ADC1INA4 AIO4 ADC1INA4, COMPA2 ADC1INA6 AIO6 ADC1INA6, COMPA3 ADC1INA7 – ADC1INA7 ADC1INB0 – ADC1INB0 ADC1INB3 – ADC1INB3 ADC1INB4 AIO12 ADC1INB4, COMPB2 ADC1INB7 – ADC1INB7 (1) Blank fields represent Reserved functions. (2) For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs. (3) AIO Mode 0 represents digital general-purpose inputs or outputs. (4) AIO Mode 1 represents analog inputs for ADC1 or the Comparator module. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.16.4 AIO_MUX2

The ten pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. While AIO_MUX2 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2 block is programmed through a separate set of registers from those used to program AIO_MUX1. The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU only. The bottom portion of Figure 8-17 shows Control Subsystem registers and muxing logic for the associated ten AIO pins. The AIOMUX2 register selects one of ten possible analog input signals or one of four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of the bits (read or write). See Table 8-32 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available. AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2 register to ‘0’ assigns pin ADC2INA4 to internal signal AIO20 (digital GPIO). Setting bit 9 of the AIOMUX2 register to ‘1’ assigns pin ADC2INA4 to analog inputs ADC2INA4 or COMPA5 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are “don’t cares”. Table 8-32. AIO_MUX2 Pin Assignments (C28x AIO Modes) DEVICE PIN NAME(1) (2) C28x AIO MODE 0(3) C28x AIO MODE 1(4) ADC2INA0 – ADC2INA0 ADC2INA2 AIO18 ADC2INA2, COMPA4 ADC2INA3 – ADC2INA3 ADC2INA4 AIO20 ADC2INA4, COMPA5 ADC2INA6 AIO22 ADC2INA6, COMPA6 ADC2INA7 – ADC2INA7 ADC2INB0 – ADC2INB0 ADC2INB3 – ADC2INB3 ADC2INB4 AIO28 ADC2INB4, COMPB5 ADC2INB7 – ADC2INB7 (1) Blank fields represent Reserved functions. (2) For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs. (3) AIO Mode 0 represents digital general-purpose inputs or outputs. (4) AIO Mode 1 represents analog inputs for ADC2 or the Comparator module. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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8.17 Emulation/JTAG

Concerto devices have two types of emulation ports to support debug operations: the 7-pin TI JTAG port and the 5-pin Cortex-M3 Instrumentation Trace Macrocell (ITM) port. The 7-pin TI JTAG port can be used to connect to debug tools through the TI 14-pin JTAG header or the TI 20-pin JTAG header. The 5-pin Cortex-M3 ITM port can only be accessed through the TI 20-pin JTAG header. The JTAG port has seven dedicated pins: TRST, TMS, TDI, TDO, TCK, EMU0, and EMU1. The TRST signal should always be pulled down through a 2.2-kΩ pulldown resistor on the board. EMU0 and EMU1 signals should be pulled up through a pair of pullups ranging from 2.2 k Ω to 4.7 kΩ (depending on the drive strength of the debugger ports). The JTAG port is TI’s standard debug port. The ITM port uses five GPIO pins that can be mapped to internal Cortex-M3 ITM trace signals: TRACE0, TRACE1, TRACE2, TRACE3, and TRACECLK. This port is typically used for advanced software debug. TI JTAG debug probes, and those from other manufacturers, can connect to Concerto devices through TI’s 14-pin JTAG header or 20-pin JTAG header. See Figure 8-18 to see how the 14-pin JTAG header connects to the JTAG port signals in Concerto. The 14-pin header does not support the ITM debug mode. Figure 8-19 shows two possible ways to connect the 20-pin header to the emulation pins in Concerto. The left side of the drawing shows all seven JTAG signals connecting to the 20-pin header similar to the way the 14-pin header was connected. The JTAG EMU0 and EMU1 signals are mapped to the corresponding terminals on the 20-pin header. In this mode, header terminals EMU2, EMU3, and EMU4 are left unconnected and the ITM trace mode is not available. The right side of the drawing shows the same 20-pin header now connected to five ITM signals and five of seven JTAG signals. The EMU0 and EMU1 signals in Concerto are left unconnected in this mode; thus, the emulation functions associated with these two signals are not available when debugging with ITM trace. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

PF3_GPIO35 PG3_GPIO43 PF2_GPIO34 PF0_GPIO32 PF1_GPIO33 JT AG PINS GPIO PINS (A) TMS TDI nTRST PD TDIS KEY TDO GND RTCK GND TCK EMU0 GND EMU1 TI 14-PIN JTAG HEADER 2.2K 4.7K 3.3V 4.7K 104 103 A. The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used. Figure 8-18. Connecting to TI 14-Pin JTAG Debug Probe Header F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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PF3_GPIO35 PG3_GPIO43 PF2_GPIO34 PF0_GPIO32 PF1_GPIO33 JT AG PINS GPIO PINS TMS TDI nTRST PD TDIS KEY TDO GND RTCK GND TCK EMU0 GND RESETn EMU1 GND EMU2 EMU3 EMU4 GND TI 20-PIN JTAG HEADER 2.2K 4.7K 3.3V 4.7K ITM trace from M3 PROCESSOR TMS TRST TDI EMU1 EMU0 TDO TCK CONCERTO F28M35x TRACED0 TRACED1 TRACECLK TRACED2 TRACED3 JT AG PINS GPIO PINS (A) TMS TDI nTRST PD TDIS KEY TDO GND RTCK GND TCK EMU0 GND RESETn EMU1 GND EMU2 EMU3 EMU4 GND TI 20-PIN JTAG HEADER 2.2K 4.7K 104 103 A LOW PULSE FROM THE JT AG DEBUG PROBE CAN BE TIED WITH OTHER RESET SOURCES TO RESET THE BOARD 3.3V 4.7K NC NC NC NC NC OPEN DRAIN OPEN DRAIN A LOW PULSE FROM THE JT AG DEBUG PROBE CAN BE TIED WITH OTHER RESET SOURCES TO RESET THE BOARD 104 103 PF3_GPIO35 PG3_GPIO43 PF2_GPIO34 PF0_GPIO32 PF1_GPIO33 A. The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used. Figure 8-19. Connecting to TI 20-Pin JTAG Debug Probe Header

8.18 Code Security Module

The Code Security Module (CSM) is a security feature incorporated in Concerto devices. The CSM prevents access and visibility to on-chip secure memories by unauthorized persons—that is, the CSM prevents duplication and reverse-engineering of proprietary code. The word "secure" means that access to on-chip secure memories is protected. The word "unsecure" means that access to on-chip secure memory is not protected— that is, the contents of the memory could be read by any means [for example, by using a debugging tool such as Code Composer Studio™ Integrated Development Environment (IDE)]. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

8.18.1 Functional Description

The security module restricts the CPU access to on-chip secure memory without interrupting or stalling CPU execution. When a read occurs to a protected memory location, the read returns a zero value and CPU execution continues with the next instruction. This process, in effect, blocks read and write access to various memories through the JTAG port or external peripherals. Security is defined with respect to the access of on-chip secure memories and prevents unauthorized copying of proprietary code or data. The zone is secure when CPU access to the on-chip secure memories associated with that zone is restricted. When secure, two levels of protection are possible, depending on where the program counter is currently pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked (that is, through the JTAG debug probe). This process allows secure code to access secure data. Conversely, if code is running from unsecure memory, all accesses to secure memories are blocked. User code can dynamically jump in and out of secure memory, thereby allowing secure function calls from unsecure memory. Similarly, interrupt service routines can be placed in secure memory, even if the main program loop is run from unsecure memory. The code security mechanism present in this device offers dual-zone security for the Cortex-M3 code and single- zone security for the C28x code. In case of dual-zone security on the master subsystem, the different secure memories (RAMs and flash sectors) can be assigned to different security zones by configuring the GRABRAM and GRABSECT registers associated with each zone. Flash Sector N and Flash Sector A are dedicated to Zone1 and Zone2, respectively, and cannot be allocated to any other zone by configuration. Similarly, flash sectors get assigned to different zones based on the setting in the GRABSECT registers. Security is provided by a CSM password of 128 bits of data (four 32-bit words) that is used to secure or unsecure the zones. Each zone has its own 128-bit CSM password. The zone can be unsecured by executing the password match flow (PMF). The CSM password for each zone is stored in its dedicated flash sector. The password storage locations in the flash sector store the CSM password. The password is selected by the system designer. If the password locations of a zone have all 128 bits as ones, the zone is considered "unsecure". Because new flash devices have erased flash (all ones), only a read of the password locations is required to bring any zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is considered "secure", regardless of the contents of the CSMKEY registers. The user should not use all zeros as a password or reset the device during an erase of the flash. Resetting the device during an erase routine can result in either an all-zero F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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or unknown password. If a device is reset when the password locations are all zeros, the device cannot be unlocked by the password match flow. Using a password of all zeros will seriously limit the user’s ability to debug secure code or reprogram the flash. Note If a device is reset while the password locations of a zone contain all zeros or an unknown value, that zone will be permanently locked unless a method to run the flash erase routine from secure SARAM is embedded into the flash or OTP. Care must be taken when implementing this procedure to avoid introducing a security hole. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 215 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

8.19 µCRC Module The µCRC module is part of the master subsystem. This module can be used by Cortex-M3 software to compute CRC on data and program, which are stored at memory locations that are addressable by Cortex-M3. On this device, the Cortex-M3 Flash Bank and ROM are mapped to the code space that is only accessed by the ICODE/ DCODE bus of Cortex-M3; and RAMs are mapped on the SRAM space that is accessible by the SYSTEM bus. Hence, the µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program.

8.19.1 Functional Description

The µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program. To allow interrupts execution in between CRC calculations for a block of data and to discard the Cortex-M3 literal pool accesses in between executions of the program (which reads data for CRC calculation), the Cortex-M3 ROM, Flash, and RAMs are mapped to a mirrored memory location. The µCRC module grabs data from the bus to calculate CRC only if the address of the read data belongs to mirrored memory space. After grabbing, the µCRC module performs the CRC calculation on the grabbed data and updates the µCRC Result Register (µCRCRES). This register can be read at any time to get the calculated CRC for all the previous read data. The µCRC module only supports CRC calculation for byte accesses. So, in order to calculate the CRC on a block of data, software must perform byte accesses to all the data. For half-word and word accesses, the µCRC module discards the data and does not update the µCRCRES register. Note If a read to a mirrored address space is thrown from the debugger (Code Composer Studio or any other debug platform), the µCRC module ignores the read data and does not update the CRC result for that particular read.

8.19.2 CRC Polynomials

The following are the CRC polynomials that are supported by the µCRC module:

• CRC8 Polynomial = 0x07
• CRC16 Polynomial-1 = 0x8005
• CRC16 Polynomial-2 = 0x1021
• CRC32 Polynomial = 0x04C11DB7

8.19.3 CRC Calculation Procedure

The software procedure for calculating CRC for a set of data that is stored in Cortex-M3 addressable memory space is as follows: 1. Save the current value of the µCRC Result Register (µCRCRES) into the stack to allow calculation of CRC in nested interrupt 2. Clear the µCRC Result Register (µCRCRES) by setting the CLEAR field of the µCRC Control Register (µCRCCONTROL) to "1" 3. Configure the µCRC polynomials (CRC8, CRC16-P1, CRC16-P2, or CRC32) in the µCRC Configuration Register (µCRCCONFIG) 4. Read the data from memory locations for which CRC needs to be calculated using mirrored address 5. Read the µCRCRES register to get the calculated CRC value. Pop the last saved value of the CRC from the stack and store this value into the µCRC Result Register (uCRCRES)

8.19.4 CRC Calculation for Data Stored In Secure Memory

This device has dual-zone security for the Cortex-M3 subsystem. Because ZoneX (X → 1/2) software does not have access to program/data in ZoneY (Y → 2/1), code running from ZoneX cannot calculate CRC on data stored in ZoneY memory. Similarly, in the case of Exe-Only flash sectors, even though software is running from same secure zone, the software cannot read the data stored in Exe-Only sectors. However, hardware does allow CRC computation on data stored in Exe-Only flash sectors as long as the read access for this data is initiated by code running from same secure zone. These reads are just dummy reads and, in this case, read data only goes to the µCRC module, not to the CPU. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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9 Applications, Implementation, and Layout

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 TI Reference Design

The TI Reference Design Library is a robust reference design library spanning analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all reference designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at the Select TI reference designs page. Single-Phase Energy Meter Solution for Advanced Applications This design features a dual-core microcontroller implementing an integrated electricity metering solution. The meter has been tested to prove 0.5% accuracy across a current dynamic range of 2000:1 by using a precision, low-noise op-amp and a programmable gain amplifier (PGA) to provide four gain stages. The metrology calculations are performed independently of the MCU integrated cores, leaving both MCUs available for other applications, including Power Line Communications (PLC). Developers will benefit from this design by taking advantage of both the Arm ® Cortex®-M3 and C28x MCUs to provide the e-meter host applications and PLC communications. Power Line Communications (PLC) System-on-Module for ARIB Frequency Band The SOMPLC-F28M35 is a single-board System-on-Module (SOM) for PLC in the ARIB frequency band. This single hardware design supports several popular PLC industry standards, including G3 and IEEE-1901.2. TI's certified PLC software is available along with the SOMPLC-F28M35. Engineers can take the SOM design and integrate it into their overall system board or keep the design as an add-on board to their application. The only additional hardware required is the AC mains line coupling circuitry. The included hardware schematics and Gerber files simplify the task for engineers to add PLC to their end system. OEMs will benefit from having the ability to rapidly evaluate and prototype PLC technology in their application. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 217 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

10 Device and Documentation Support

10.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all Concerto MCU devices and support tools. Each Concerto MCU commercial family member has one of three prefixes: x, p, or no prefix (for example, xF28M35H52C1RFPT). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (with prefix x for devices and TMDX for tools) through fully qualified production devices/tools (with no prefix for devices and TMDS, instead of TMDX, for tools). xF28M35... Experimental device that is not necessarily representative of the final device's electrical specifications pF28M35... Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification F28M35... Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product Devices with prefix x or p and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices with prefix of x or p have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RFP) and temperature range (for example, T). For device part numbers and further ordering information of F28M35x devices in the RFP package type, see the TI website (www.ti.com) or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the F28M35x Concerto™ MCUs Silicon Errata. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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Figure 10-1. Device Nomenclature

10.2 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. To view all available tools and software for C2000™ real-time control MCUs, visit the C2000 MCU Tools and Software page. Development Tools H52C1 Concerto Experimenter Kit The C2000 Experimenter Kits from Texas Instruments are ideal products for initial device exploration and testing. The Concerto H52C1 Experimenter Kit has a docking station that features access to all controlCARD signals, breadboard areas and RS-232 and JTAG connectors. Each kit contains a H52C1 controlCARD. The controlCARD is a complete board level module that utilizes and industry-standard DIMM form factor to provide a low-profiles single-board controller solution. Kit is complete with Code Composer StudioTM IDE v4 and USB cable. H52C1 Concerto controlCARD The C2000 controlCARDs from Texas Instruments are ideal products for initial software development and short run builds for system prototypes, test stands, and many other projects that require easy access to high- performance controllers. The controlCARDs are complete board-level modules that utilize an industry-standard DIMM form factor to provide a low-profile single-board controller solution. All of the C2000 controlCARDs use the same 100-pin connector footprint to provide the analog and digital I/Os on-board controller and are completely interchangeable. The host system needs to provide only a single 5V power rail to the controlCARD for it to be fully functional. UniFlash Standalone Flash Tool UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting interface. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 219 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

controlSUITE™ Software Suite: Essential Software and Development Tools for C2000™ Microcontrollers controlSUITE™ for C2000™ microcontrollers is a cohesive set of software infrastructure and software tools designed to minimize software development time. Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers. F021 Flash API The F021 Flash Application Programming Interface (API) provides a software library of functions to program, erase, and verify F021 on-chip Flash memory. Models Various models are available for download from the product Tools & Software pages. These include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all available models, visit the Models section of the Tools & Software page for each device. Training To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance, TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller family. These training resources have been designed to decrease the learning curve, while reducing development time, and accelerating product time to market. For more information on the various training resources, visit the C2000™ real-time control MCUs – Support & training site. Specific F28M35x hands-on training resources can be found at C2000™ MCU Device Workshops.

10.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The current documentation that describes the processor, related peripherals, and other technical collateral is listed below. Errata F28M35x Concerto™ MCUs Silicon Errata describes known advisories on silicon and provides workarounds. Technical Reference Manual Concerto F28M35x Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the F28M35x Microcontroller Processors. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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CPU User's Guides TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference Guide also describes emulation features available on these DSPs. TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and instruction set of the TMU, VCU-II, and FPU accelerators. Peripheral Guides C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x DSPs. Tools Guides TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. Application Reports Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their application in perspective with respect to system-level junction temperature estimation. Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor devices for shipment to end users. Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement. An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/ output structures and future trends. Serial Flash Programming of C2000 ™ Microcontrollers discusses using a flash kernel and ROM loaders for serial programming a device.

10.4 Trademarks

Concerto™, PowerPAD™, TMS320C2000™, controlSUITE™, Texas Instruments™, Code Composer Studio™, C2000™, and TI E2E™ are trademarks of Texas Instruments. Freescale™ is a trademark of Freescale Semiconductor, Inc. Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Bosch® is a registered trademark of Robert Bosch GmbH Corporation. NXP® is a registered trademark of NXP Semiconductors. All trademarks are the property of their respective owners.

10.5 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 221 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 www.ti.com

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11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. For packages with a thermal pad, the MECHANICAL DATA figure shows a generic thermal pad without dimensions. For the actual thermal pad dimensions that are applicable to this device, see the THERMAL PAD MECHANICAL DATA figure. www.ti.com F28M35H52C, F28M35H52C-Q1, F28M35H22C F28M35M52C, F28M35M22C, F28M35E20B SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 223 Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C F28M35E20B

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) F28M35E20B1RFPT Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 F28M35E20B1RFPT F28M35E20B1RFPT.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 F28M35E20B1RFPT F28M35E20B1RFPT.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 105 F28M35H22C1RFPT Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 F28M35H22C1RFPT F28M35H22C1RFPT.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 F28M35H22C1RFPT F28M35H22C1RFPT.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 105 F28M35H52C1RFPQ Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPQ F28M35H52C1RFPQ.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPQ F28M35H52C1RFPQ.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35H52C1RFPS Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPS F28M35H52C1RFPS.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPS F28M35H52C1RFPS.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35H52C1RFPSG4 Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPS F28M35H52C1RFPSG4.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPS F28M35H52C1RFPSG4.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35H52C1RFPT Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 F28M35H52C1RFPT Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) F28M35H52C1RFPT.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPT F28M35H52C1RFPT.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35H52C1RFPTG4 Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPT F28M35H52C1RFPTG4.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35H52C1RFPT F28M35H52C1RFPTG4.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35M22C1RFPS Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35M22C1RFPS F28M35M22C1RFPS.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35M22C1RFPS F28M35M22C1RFPS.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35M22C1RFPT Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 F28M35M22C1RFPT F28M35M22C1RFPT.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35M22C1RFPT F28M35M22C1RFPT.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35M52C1RFPS Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35M52C1RFPS F28M35M52C1RFPS.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35M52C1RFPS F28M35M52C1RFPS.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 F28M35M52C1RFPT Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 F28M35M52C1RFPT F28M35M52C1RFPT.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 125 F28M35M52C1RFPT F28M35M52C1RFPT.B Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (5+1) - Call TI Call TI -40 to 125 Addendum-Page 2

www.ti.com 7-Oct-2025 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF F28M35H52C, F28M35H52C-Q1 :

• Catalog : F28M35H52C
• Automotive : F28M35H52C-Q1 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) F28M35E20B1RFPT RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35H22C1RFPT RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35H52C1RFPQ RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35H52C1RFPS RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35H52C1RFPSG4 RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35H52C1RFPT RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35H52C1RFPTG4 RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35M22C1RFPS RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35M22C1RFPT RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) F28M35M52C1RFPS RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 F28M35M52C1RFPT RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 Pack Materials-Page 2

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