Microcontroller

F28M35H52B1RFPS

Texas Instruments

Concerto Microcontrollers Embedded Memory AUGUST2012

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Technical content

1 F28M35x (Concerto™ )MCUs

1.1 Features

Master Subsystem — ARM ® Cortex™ -M3 • ControlSubsystem — TMS320C28x ™ 32-Bit CPU– 100 MHz – 150 MHz– Embedded Memory – Embedded Memory• Up to512KB Flash(ECC)
Up to512KB Flash(ECC)• Up to32KB RAM (ECC or Parity)
Up to36KB RAM (ECC or Parity)• Up to64KB Shared RAM
Up to64KB Shared RAM• 2KB IPC Message RAM
2KB IPC Message RAM– 5 UniversalAsynchronous Receiver/Transmitters(UARTs) – IEEE-754Single-PrecisionFloating-Point Unit(FPU)– 4 Synchronous SerialInterfaces(SSIs)/ SerialPeripheralInterface(SPI) – Viterbi,Complex Math,CRC Unit(VCU) – 2 Inter-integratedCircuits(I2Cs) – SerialCommunications Interface(SCI) – UniversalSerialBus On-the-Go (USB-OTG) + – SerialPeripheralInterface(SPI) PHY – Inter-integratedCircuit(I2C) – 10/100ENET 1588 MII – 6-ChannelDirectMemory Access (DMA) – 2 ControllerArea Networks (CANs) – 9 Enhanced Pulse Width Modulator(ePWM) – 32-ChannelDirectMemory Access (µDMA) Modules – Dual SecurityZones (128-BitPassword per • 18 Outputs (16High-Resolution) Zone) – 6 32-BitEnhanced Capture (eCAP) Modules – ExternalPeripheralInterface(EPI) – 3 32-BitEnhanced QuadratureEncoder – Micro CyclicRedundancy Check (µCRC) (eQEP) Modules Module – MultichannelBufferedSerialPort(McBSP) – 4 General-PurposeTimers – ExternalPeripheralInterface(EPI) – 2 Watchdog Timer Modules – One SecurityZone (128-BitPassword) – Endianness:LittleEndian – 3 32-BitTimers
Clocking – Endianness:LittleEndian – On-chip CrystalOscillator/ExternalClock Input • Analog Subsystem – Dynamic PLL RatioChanges Supported – Dual 12-BitAnalog-to-DigitalConverters
1.2-VDigital,1.8-VAnalog,3.3-VI/ODesign (ADCs) – Up to2.88MSPS
InterprocessorCommunications (IPC) – Up to20 Channels – 32 Handshaking Channels – 4 Sample-and-Hold (S/H)Circuits – 4 Channels Generate IPC Interrupts – Up to6 Comparators With 10-BitDigital-to- – Can be Used toCoordinateTransferofData Analog Converter(DAC) Through IPC Message RAMs
Package
Up to74 IndividuallyProgrammable, – 144-PinRFP PowerPAD ™ Thermally MultiplexedGPIO Pins Enhanced Thin Quad Flatpack(HTQFP) – Glitch-freeI/Os Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Concerto,TMS320C28x, PowerPAD, C28x,C2000, Piccolo,Delfino,XDS aretrademarksofTexas Instruments. 3Cortexisa trademarkofARM Limited. 4ARM isa registeredtrademarkofARM Ltdoritssubsidiaries. 5Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCT PREVIEW informationconcernsproductsintheformativeordesignphase of Copyright© 2011–2012,Texas InstrumentsIncorporateddevelopment.Characteristicdata and other specificationsare design goals.Texas Instrumentsreservestherighttochange ordiscontinuetheseproductswithoutnotice.

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

1.2 Description

The Concerto™ family is a multi-coresystem-on-chipmicrocontroller(MCU) with independent communicationand real-timecontrolsubsystems.The F28M35x isthefirstseriesintheConcertofamily. The communicationssubsystem isbased on the industry-standard32-bitARM ® Cortex™ -M3 CPU and featuresa wide varietyofcommunicationperipherals,includingEthernet1588,USB OTG withPHY, CAN, UART, SSI,I2C,and an externalinterface. The real-timecontrolsubsystemisbased on TI’s industry-leadingproprietary32-bitC28x™ Floating-Point CPU and featuresthe most flexibleand high-precisioncontrolperipherals,includingePWMs withfault protection,and encoders and captures— allas implementedby TI’s C2000 ™ Piccolo™ and Delfino™ families.In addition,the C28-CPU has been enhanced withthe additionof the Viterbi,Complex Math, CRC Unit(VCU) instructionacceleratorthatimplementsefficientViterbi,Complex Arithmetic,16-bitFFTs and CRC algorithms. A high-speedanalogsubsystem and supplementaryRAM memory isshared,alongwithon-chipvoltage regulationand redundantclockingcircuitry.Safetyconsiderationsalso includeErrorCorrectionCode (ECC),Parity,and Code Secure Memory, as wellas documentationtoassistwithsystem-levelindustrial safetycertification.

2 F28M35x (Concerto™ )MCUs Copyright© 2011–2012,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW RAM 8 KB (parity) RAM 8 KB (parity) BOOT ROM 64 KB GPIO_MUX1 GP TIMER (4) uCRCI2C (2) SSI (4)UART (5) USB+PHY (OTG) EMAC WDOG (2)NMI WDOG 1.2V VREG 1.8V VREG SECURE RAM 8 KB (ECC) SECURE RAM 8 KB (ECC) AHB BUS APB BUS S0-S7 SHARED RAM (parity) 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB MTOC MSG RAM (parity) 2 KB CTOM MSG RAM (parity) 2 KB IPC INTER- PROC COMM M3 SYSTEM BUS uDMA BUS RAM 8 KB (parity) RAM 8 KB (parity) SECURE FLASH 512 KB (ECC) BOOT ROM 64 KB SECURE RAM 8 KB (ECC) SECURE RAM 8 KB (ECC) TIMER (3)XINT (3) EPWM (9)NMI WDOG EQEP (3)ECAP (6) McBSPI2C SCI SPI GPIO_MUX1 RAM 2 KB (ECC) RAM 2 KB (ECC) C28 CPU BUS C28 DMA BUS 16- BIT PF2 32- BIT PF1 32- BIT PF3 C28 CPU C28 FPU C28 VCU C28 DMA M3 CPU NVIC MPUM3 BUS MA TRIX uDMA I-CODE BUS D-CODE BUS

66 PINS

ADC_1 MODULE ADC_2 MODULE GPIO_MUX2

10 PINS

AIO_MUX2 AIO_MUX1

BIT PF0

8 PINS

+ DAC UNITS MEM32 TO AHB BUS BRIDGE ANALOG COMMON INTERFACE BUS 1.2V VMON 1.8V VMON C28 CPU/DMA ACCESS TO EPI EPI INTER- PROC COMM CAN (2) RESETS NMI CLOCKS SECURITY DEBUG FREQ GASKET SECURE FLASH 512 KB (ECC) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

1.3 FunctionalBlock Diagram

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Thisdatasheetrevisionhistoryhighlightsthetechnicalchanges made totheSPRS742C device-specific datasheettomake itan SPRS742D revision. Scope: Added new sections. See tablebelow. LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS Section1.1 Features:

Changed "Up to72 IndividuallyProgrammable,MultiplexedGPIO Pins"to"Up to74 Individually Programmable,MultiplexedGPIO Pins" – Added "Glitch-freeI/Os"feature
ControlSubsystem — TMS320C28x ™ 32-BitCPU: – Added "ExternalPeripheralInterface(EPI)"feature
AnalogSubsystem: – Removed "On-chipTemperatureSensor" Figure1-1 Updated FunctionalBlockDiagram Table2-1 Hardware Features:
12-BitADC 1: – Removed "TemperatureSensor"
Updated "VoltageRegulatorand Monitor"
Updated "Clocking" Table2-3 ControlSubsystem PeripheralFrame 0 (IncludesAnalog):
0000 1780 – 0000 17FF:Added C Hardware LogicBIST Registers Table2-8 ControlSubsystem Flash,ECC, OTP, BootROM:
Added "M Address(Byte-Aligned)"column
Added "µDMA Access"column
0030 0000 – 003F 7FFF: Added EPI0
003F 8000 – 003F FFFF: Added C28x BootROM
Added "The letter"M" referstotheMasterSubsystem"footnote
Added "The ControlSubsystem has no directaccesstoEPI insiliconrevision0 devices"footnote Table2-12 MasterSubsystem Analogand EPI:
Added "C Address(x16Aligned)"column
Added "C DMA Access"column
6000 0000 – DFFF FFFF: Updated theabove two new columns
Added "The letter"C"referstotheControlSubsystem"footnote
Added "The ControlSubsystem has no directaccesstoEPI insiliconrevision0 devices"footnote Section2.3 MasterSubsystem:
Updated "The MasterSubsystem includes..."paragraph Section2.3.1 Cortex™ -M3 CPU:
Removed "MPU isnotavailableon siliconrevision0 devices"NOTE Section2.3.2 Added "Cortex™ -M3 Core Hardware LogicBuilt-InTest(LBIST)"section Figure2-1 Updated "MasterSubsystem"figure Table2-14 InterruptsfromNVIC toCortex™ -M3:
InterruptNumber: Changed 91 to"91–133".Updated "VectorNumber" column.Updated "Vector AddressorOffset"column. Section2.3.6 Cortex™ -M3 LocalPeripherals:
Updated "The Cortex™ -M3 localperipheralsincludetwo Watchdogs ..."paragraph Section2.3.8 Cortex™ -M3 AccessingShared Resourcesand AnalogPeripherals:
Updated "Thereareseveralmemories ..."paragraph
Updated "The Shared Resources..."paragraph
Updated "The AnalogSubsystem has ADC1 ..."paragraph Copyright© 2011–2012,Texas InstrumentsIncorporated Contents 5 SubmitDocumentationFeedback

Updated "The ControlSubsystem includes..."paragraph Figure2-2 Updated "ControlSubsystem"figure Table2-16 PIE PeripheralInterrupts:
INTx.3,INT12:Changed from"C28FLFSM" to"Reserved" Section2.4.5 C28x LocalPeripherals:
Updated "The C28x localperipheralsincludean NMI Watchdog ..."paragraph Section2.4.7 C28x AccessingShared Resourcesand AnalogPeripherals:
Updated "The Shared Resources..."paragraph Section2.5 AnalogSubsystem:
Updated "The AnalogSubsystem has ADC1 ..."paragraph Section2.5.1 ADC1:
Updated "The ADC1 consistsofa 12-bitAnalog-to-Digitalconverter..."paragraph Figure2-3 Updated "AnalogSubsystem"figure Section2.5.4 AnalogCommon InterfaceBus (ACIB):
Updated "The ACIB bus linkstheMasterand ControlSubsystems ..."paragraph Section2.6 MasterSubsystem NMIs:
Updated "The inputstotheCortex™ -M3 NMI blockinclude..."paragraph Section2.7 ControlSubsystem NMIs:
Updated "The inputstotheC28x NMI blockinclude..."paragraph Figure2-4 Updated "Cortex™ -M3 NMI and C28x NMI" figure Section2.8 Resets:
Updated "The XRS pincan receivean externalresetsignal..."paragraph Figure2-5 Updated "Resets"figure Section2.8.3 AnalogSubsystem and Shared ResourcesResets:
Added "EPIisa sharedperipheral..."paragraph Section2.8.4 DeviceBootSequence:
Updated "BootMode 7 ..."paragraph
Updated "BootMode 1 causestheMasterbootprogramtobranch..."paragraph
Updated "BootModes 0,2,3,..."paragraph Table2-17 MasterSubsystem BootMode Selection:
Added BootModes 8–15
Updated and added footnotes Section2.9 Added "InternalVoltageRegulationand Monitoring"section Section2.10 Added "InputClocksand PLLs" section Figure2-10 Updated "Cortex™ -M3 Clocksand Low-Power Modes" figure Section2.12 ControlSubsystem Clocking:
Updated "The C28x processoroutputstwo clocks..."paragraph Figure2-11 Updated "C28x Clocksand Low-Power Modes" figure Section2.12.3 C28x StandbyMode:
Updated "InStandbyMode, theC28x processorstopsexecutinginstructions..."paragraph
Added NOTE aboutGPIO_MUX1 pinsPF6_GPIO38 and PG6_GPIO46 Section2.14 Shared ResourcesClocking:
Updated "...areclockedby PLLSYSCLK." paragraph
Added "EPIisa sharedperipheral..."paragraph Section2.15 Added "LossofInputClock(NMI Watchdog Function)"section Section2.16 GPIOs and OtherPins:
Updated "MostoftheI/OpinsoftheConcerto™ MCU ..."paragraph

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Updated "Pin-LevelMux assignsMasterSubsystem peripheralsignals..."paragraph
Updated "The configurationregistersforthemuxing ofMasterSubsystem peripherals..."paragraph
Updated "Inadditiontopassingmostlydigitalsignals..."paragraph
Added NOTE aboutGPIO_MUX1 pinsPF6_GPIO38 and PG6_GPIO46 Figure2-13 Updated "GPIOs and OtherPins"figure Figure2-14 Updated "GPIO_MUX1 Block"figure Figure2-15 Updated "GPIO_MUX1 PinMapping ThroughRegisterSetA" figure Table2-27 GPIO_MUX1 PinAssignments(M3 PrimaryModes):
PB6_GPIO14: Updated "M3 PrimaryMode 8"column
PB7_GPIO15: Updated "M3 PrimaryMode 8"column
PE4_GPIO28: Updated "M3 PrimaryMode 8"column
PE5_GPIO29: Updated "M3 PrimaryMode 8"column
PF2_GPIO34: Updated "M3 PrimaryMode 8"column
PF3_GPIO35: Updated "M3 PrimaryMode 8"column
PF6_GPIO38: – Updated "M3 PrimaryMode 1"column – Updated "M3 PrimaryMode 3"column – Updated "M3 PrimaryMode 8"column – Updated "M3 PrimaryMode 10"column
PG2_GPIO42: Updated "M3 PrimaryMode 8"column
PG5_GPIO45: Updated "M3 PrimaryMode 8"column
PG6_GPIO46: – Updated "M3 PrimaryMode 3"column – Updated "M3 PrimaryMode 8"column – Updated "M3 PrimaryMode 10"column
Added footnoteaboutmuxing optionavailability Table2-28 GPIO_MUX1 PinAssignments(M3 AlternateModes):
PA6_GPIO6: Updated "M3 AlternateMode 12"column
PE4_GPIO28: Updated "M3 AlternateMode 14"column
Added footnoteaboutmuxing optionavailability Table2-29 GPIO_MUX1 PinAssignments(C28x PeripheralModes):
PF6_GPIO38: Updated "C28x PeripheralMode 0"column
PG6_GPIO46: Updated "C28x PeripheralMode 0"column Section2.16.2 GPIO_MUX2:
Updated "PeripheralModes 0,1,2,and 3 arechosen ..."paragraph Table2-30 Updated "GPIO_MUX2 PinAssignments(C28x PeripheralModes)"table Figure2-16 Updated "PinMuxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2" figure Section2.17 Added "Emulation/JTAG"section Section2.18 Added "Code SecurityModule (CSM)" section Section2.19 Added "µCRC Module"section Figure3-1 144-PinRFP PowerPAD ™ HTQFP (TopView):
Pin109:Changed signalname from"GPIO199/COMP5OUT" to"GPIO135/COMP5OUT"
Pin110:Changed signalname from"GPIO198" to"GPIO134"
Pin111:Changed signalname from"GPIO197/COMP4OUT" to"GPIO133/COMP4OUT"
Pin112:Changed signalname from"GPIO196/COMP3OUT" to"GPIO132/COMP3OUT"
Pin118:Changed signalname from"ADC1V REFLO ,VSSA1 "to"VSSA1 "
Pin135:Changed signalname from"ADC2V REFLO ,VSSA2 "to"VSSA2 "
Pin140:Changed signalname from"GPIO192" to"GPIO128"
Pin141:Changed signalname from"GPIO193/COMP1OUT" to"GPIO129/COMP1OUT"
Pin142:Changed signalname from"GPIO194/COMP6OUT" to"GPIO130/COMP6OUT"
Pin143:Changed signalname from"GPIO195/COMP2OUT" to"GPIO131/COMP2OUT"
Added footnoteaboutGPIO135 Copyright© 2011–2012,Texas InstrumentsIncorporated Contents 7 SubmitDocumentationFeedback

Removed "InputClockConfigurations"figure.Thisfigureisbeingreplacedby thenew "Connecting InputClockstoa ConcertoDevice"figure(Figure2-7). Table3-1 TerminalFunctions:
Made extensiveupdatestoTerminalFunctionstable
Added footnoteaboutpullupand pulldown
Added footnoteaboutGPIO135
Added footnoteaboutmuxing optionavailability Section4.1 AbsoluteMaximum Ratings:
Added Free-Airtemperature,TA Section4.2 Recommended OperatingConditions:
Added Free-Airtemperature,TA
Updated Junctiontemperature,TJ
Removed footnoteaboutambienttemperature Section5 Added "ElectricalSpecifications"section Section5 ElectricalSpecifications:
Moved "CurrentConsumption"sectionfrom"PeripheralInformationand Timings"sectionto"Electrical Specifications"section
Moved "Power Sequencing"sectionfrom"PeripheralInformationand Timings"sectionto"Electrical Specifications"section Table5-1 Changed tabletitlefrom"F28M35Hx CurrentConsumptionat150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" to"CurrentConsumptionat150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" Table5-1 Updated "CurrentConsumptionat150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" tableand footnotes Section5.2 Added "ThermalDesignConsiderations"section Section5.3 Added "TimingParameterSymbology"section Section5.4 Added "ClockFrequencies,Requirements,and Characteristics"section Section5.5 Updated "Power Sequencing"section Section5.5.1 Added "ChangingtheFrequencyoftheMain PLL" section Table5-14 Updated "Power Management and SupervisoryCircuitSolutions"table Section6.1 Updated "Analogand Shared Peripherals"section Figure6-1 Updated "ADC" figure Section6.1.1.3 Updated "AnalogInputs"section Section6.1.2 Updated "Comparator+ DAC Units"section Figure6-2 Updated "Comparator+ DAC Units"figure Section6.1.3 Updated "Inter-ProcessorCommunications(IPC)"section Figure6-3 Updated "InterprocessorCommunications(IPC)"figure Section6.1.4 Updated "ExternalPeripheralInterface(EPI)"section Section6.2 MasterSubsystem Peripherals:
Updated "MasterSubsystem peripheralsarelocatedon theAPB Bus and AHB Bus ..."paragraph Section6.2.1 Added "SynchronousSerialInterface(SSI)"section Section6.2.2 Added "UniversalAsynchronousReceiver/Transmitter(UART)" section Section6.2.3 Added "Cortex™ -M3 Inter-IntegratedCircut(I2C)"section Section6.2.4 Added "Cortex™ -M3 ControllerArea Network(CAN)"section Section6.2.5 Added "Cortex™ -M3 UniversalSerialBus (USB) Controller"section Section6.2.6 Added "Cortex™ -M3 EthernetMedia Access Controller(EMAC)" section Section6.3 ControlSubsystem Peripherals:
Updated "ControlSubsystem peripheralsareaccessiblefromtheC28x CPU ..."paragraph Section6.3.1 Changed sectiontitlefrom"PulseWidthModulator(PWM) and High-ResolutionPWM (HRPWM) Modules" to"High-ResolutionPWM (HRPWM) and Enhanced PWM (ePWM) Modules" Section6.3.1 High-ResolutionPWM (HRPWM) and Enhanced PWM (ePWM) Modules:
Updated "Thereare9 SOCA PWM outputsand 9 SOCB PWM outputs..."paragraph

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS Figure6-15 Changed figurecaptionfrom"ePWM, eQEP, eCAP" to"PWM, eCAP, eQEP" Figure6-15 Updated "PWM, eCAP, eQEP" figure Figure6-16 Changed figurecaptionfrom"ePWM/HRPWM" to"InternalStructureofPWM" Figure6-16 Updated "InternalStructureofPWM" figure Section6.3.2 Added "Enhanced Capture(eCAP) Module"section Section6.3.3 Added "Enhanced QuadratureEncoderPulse(eQEP) Module"section Section6.3.4 Added "C28x Inter-IntegratedCircuitModule (I2C)"section Section6.3.5 Added "C28x SerialCommunicationsInterface(SCI)"section Section6.3.6 Added "C28x SerialPeripheralInterface(SPI)"section Section6.3.7 Added "C28x MultichannelBufferedSerialPort(McBSP)" section Section8.1 Added "ThermalData forPackage"section Copyright© 2011–2012,Texas InstrumentsIncorporated Contents 9 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2 Device Overview

The Concerto™ microcontroller(MCU) comprisesthreesubsystems:theMasterSubsystem,theControl Subsystem,and theAnalog Subsystem.WhiletheMasterand ControlSubsystem each have dedicated localmemories and peripherals,they can alsoshare data and eventsthroughshared memories and peripherals.The Analog Subsystem has two ADC convertersand sixAnalog Comparators.Both the Master and ControlSubsystems access the Analog Subsystem throughthe Analog Common Interface Bus (ACIB).The NMI BlocksforcecommunicationofcriticaleventstotheMasterand ControlSubsystem processorsand theirWatchdog Timers.The Reset Block responds to Watchdog Timer NMI Reset, ExternalReset,and othereventstoinitializesubsystem processorsand therestofthechiptoa known state.The ClockingBlocks supportmultiplelow-power modes where clocksto the processorsand peripheralscan be sloweddown orstoppedinordertomanage power consumption. NOTE Throughoutthisdocument,theMasterSubsystem isdenotedby thecolor"blue";theControl Subsystem isdenoted by the color"green";and the Analog Subsystem isdenoted by the color"orange".

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.1 Device Characteristics

Table2-1liststhefeaturesoftheF28M35Hx devices. Table2-1.Hardware Features FEATURE TYPE (1) H20B1 H20C1 H22B1 H22C1 H32B1 H32C1 H50B1 H50C1 H52B1 H52C1 Master Subsystem — ARM ® Cortex™ -M3 Flash(KB) – 256 256 256 256 256 512 512 512 512 512 RAM ECC (KB) – 16 16 16 16 16 16 16 16 16 16 RAM Parity(KB) – 16 16 16 16 16 16 16 16 16 16 IPC Message RAM Parity(KB) – 2 2 2 2 2 2 2 2 2 2 SecurityZones – 2 2 2 2 2 2 2 2 2 2 10/100ENET 1588 MII 0 No Yes No Yes No Yes No Yes No Yes USB OTG FS 0 No Yes No Yes No Yes No Yes No Yes SynchronousSerialInterface(SSI)/ 0 4 4 4 4 4 4 4 4 4 4SerialPeripheralInterface(SPI) UniversalAsynchronousReceiver/Transmitter(UART) 0 5 5 5 5 5 5 5 5 5 5 Inter-integratedcircuit(I2C) 0 2 2 2 2 2 2 2 2 2 2 ControllerArea Network(CAN) 0 2 2 2 2 2 2 2 2 2 2 DirectMemory Access (µDMA) 0 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch ExternalPeripheralInterface(EPI) 0 1 1 1 1 1 1 1 1 1 1 MicroCyclicRedundancy Check (µCRC) Module 0 1 1 1 1 1 1 1 1 1 1 General-PurposeTimers – 4 4 4 4 4 4 4 4 4 4 Watchdog TimerModules – 2 2 2 2 2 2 2 2 2 2 ControlSubsystem — C28x Floating-PointUnit(FPU)/Viterbi,Complex Math,CRC Unit(VCU) Speed (MHz) 150 150 150 150 150 150 150 150 150 150 Flash(KB) 256 256 256 256 512 256 512 512 512 512 RAM ECC (KB) 20 20 20 20 20 20 20 20 20 20 RAM Parity(KB) 16 16 16 16 16 16 16 16 16 16 IPC Message RAM Parity(KB) 2 2 2 2 2 2 2 2 2 2 SecurityZones 1 1 1 1 1 1 1 1 1 1 Enhanced PulseWidthModulator(ePWM) modules 2 9:18 outputs High-ResolutionPWM outputs 2 16 outputs Enhanced Capture(eCAP) modules/ 0 6 (32-bit)PWM outputs Enhanced QuadratureEncoder(eQEP) modules 0 3 (32-bit) FaultTripZones – 12 on any of64 GPIO pins (1) A typechange representsa majorfunctionalfeaturedifferenceina peripheralmodule.Withina peripheraltype,theremay be minordifferencesbetween devicesthatdo notaffectthe basicfunctionalityofthemodule.These device-specificdifferencesarelistedintheTMS320x28xx, 28xxxDSP PeripheralReferenceGuide (literaturenumber SPRU566 )and inthe peripheralreferenceguides. (2) An integerdivideratiomust be maintainedbetween theC28x and Cortex™ -M3 clockfrequencies;thus,when theC28x isconfiguredtorunatmaximum frequencyof150 MHz, thefastest allowablefrequencyfortheCortex™ -M3 willbe 75 MHz. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-1.Hardware Features(continued) FEATURE TYPE (1) H20B1 H20C1 H22B1 H22C1 H32B1 H32C1 H50B1 H50C1 H52B1 H52C1 MultichannelBufferedSerialPort(McBSP)/ 1 1 1 1 1 1 1 1 1 1 1SerialPeripheralInterface(SPI) SerialCommunicationsInterface(SCI) 0 1 1 1 1 1 1 1 1 1 1 SerialPeripheralInterface(SPI) 0 1 1 1 1 1 1 1 1 1 1 Inter-integratedcircuit(I2C) 0 1 1 1 1 1 1 1 1 1 1 DirectMemory Access (DMA) 0 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 32-BitTimers – 3 3 3 3 3 3 3 3 3 3 Shared SupplementalRAM (KB) 0 0 64 64 64 64 0 0 64 64 ConversionTime 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 12-BitADC 1 3 Channels 10 10 10 10 10 10 10 10 10 10 Sample-and-Hold(S/H) 2 2 2 2 2 2 2 2 2 2 ConversionTime 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 12-BitADC 2 3 Channels 10 10 10 10 10 10 10 10 10 10 Sample-and-Hold(S/H) 2 2 2 2 2 2 2 2 2 2 ComparatorswithIntegratedDACs 0 6 6 6 6 6 6 6 6 6 6 VoltageRegulatorand Monitor Yes – Uses 3.3-VSingleSupply(3.3-V/1.2-Vrecommended for125ºC) Clocking See Section2.10 AdditionalSafety MasterSubsystem 2 Watchdogs,NMI Watchdog:CPU, Memory ControlSubsystem NMI Watchdog:CPU, Memory Shared CriticalRegisterand I/OFunctionLock Protection;RAM FetchProtection Packaging 144-PinRFP PowerPAD ™Package Type AvailableatPrototypeSamplingHTQFP T:–40°C to105°C – Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Temperatureoptions S:–40°C to125°C – No No No No No No No No No No Q: –40°C to125°C (3)(4)(5) – No No No No No No No No No No (3) "Q "referstoQ100 qualificationforautomotiveapplications. (4) The "Q "temperatureoptionisnot availablefortheF28M35 Mxxx1 series. (5) The "Q "temperatureoptionisnot availablefortheF28M35 ExxC1 series,butthistemperatureoptionwillbe availablefortheF28M35 ExxB1 series. Nomenclature,fordescriptionsofdevicestages.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.2 Memory Maps

Memory Map.

2.2.1 ControlSubsystem Memory Map

Table2-2.ControlSubsystem M0, M1 RAM C Address SizeC DMA Access (1) ControlSubsystem M0, M1 RAM(x16Aligned)(1) (Bytes) no 0000 0000 – 0000 03FF M0 RAM (ECC) 2K no 0000 0400 – 0000 07FF M1 RAM (ECC) 2K (1) The letter"C "referstotheControlSubsystem. Table2-3.ControlSubsystem PeripheralFrame 0 (IncludesAnalog) C Address ControlSubsystem PeripheralFrame 0 SizeC DMA Access (1) (x16Aligned)(1) (IncludesAnalog) (Bytes) 0000 0800 – 0000 087F Reserved ControlSubsystem DeviceConfigurationRegisters(Readno 0000 0880 – 0000 0890 34Only) 0000 0891 – 0000 0ADF Reserved no 0000 0AE0 – 0000 0AEF C28x CSM Registers 32 0000 0AF0 – 0000 0AFF Reserved yes 0000 0B00 – 0000 0B0F ADC1 ResultRegisters 32 0000 0B10 – 0000 0B3F Reserved yes 0000 0B40 – 0000 0B4F ADC2 ResultRegisters 32 0000 0B50 – 0000 0BFF Reserved no 0000 0C00 – 0000 0C07 CPU Timer0 16 no 0000 0C08 – 0000 0C0F CPU Timer1 16 no 0000 0C10 – 0000 0C17 CPU Timer2 16 0000 0C18 – 0000 0CDF Reserved no 0000 0CE0 – 0000 0CFF PIE Registers 64 no 0000 0D00 – 0000 0DFF PIE VectorTable 512 no 0000 0E00 – 0000 0EFF PIE VectorTableCopy (Read Only) 512 0000 0F00 – 0000 0FFF Reserved no 0000 1000 – 0000 11FF C28x DMA Registers 1K 0000 1200 – 0000 16FF Reserved no 0000 1700 – 0000 177F AnalogSubsystem ControlRegisters 256 no 0000 1780 – 0000 17FF C Hardware LogicBIST Registers 256 0000 1800 – 0000 3FFF Reserved (1) The letter"C "referstotheControlSubsystem. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-4.ControlSubsystem PeripheralFrame 3 C Address ControlSubsystem Size M Address µDMAC DMA Access (1) (x16Aligned)(1) PeripheralFrame 3 (Bytes) (Byte-Aligned)(2) Access no 0000 4000 – 0000 4181 C28x FlashControlRegisters 772 0000 4182 – 0000 42FF Reserved C28x FlashECC ErrorLogno 0000 4300 – 0000 4323 72Registers 0000 4324 – 0000 43FF Reserved no 0000 4400 – 0000 443F M ClockControlRegisters(2) 128 400F B800 – 400F B87F no 0000 4440 – 0000 48FF Reserved no 0000 4900 – 0000 497F RAM ConfigurationRegisters 256 400F B200 – 400F B2FF no 0000 4980 – 0000 49FF Reserved RAM ECC/Parity/AccessErrorno 0000 4A00 – 0000 4A7F 256 400F B300 – 400F B3FF noLog Registers 0000 4A80 – 0000 4DFF Reserved no 0000 4E00 – 0000 4E3F CtoM and MtoC IPC Registers 128 400F B700 – 400F B77F no 0000 4E40 – 0000 4FFF Reserved yes 0000 5000 – 0000 503F McBSP-A 128 0000 5040 – 0000 50FF Reserved yes 0000 5100 – 0000 517F EPWM1 (Hi-Resolution) 256 yes 0000 5180 – 0000 51FF EPWM2 (Hi-Resolution) 256 yes 0000 5200 – 0000 527F EPWM3 (Hi-Resolution) 256 yes 0000 5280 – 0000 52FF EPWM4 (Hi-Resolution) 256 yes 0000 5300 – 0000 537F EPWM5 (Hi-Resolution) 256 yes 0000 5380 – 0000 53FF EPWM6 (Hi-Resolution) 256 yes 0000 5400 – 0000 547F EPWM7 (Hi-Resolution) 256 yes 0000 5480 – 0000 54FF EPWM8 (Hi-Resolution) 256 yes 0000 5500 – 0000 557F EPWM9 256 0000 5580 – 0000 57FF Reserved (1) The letter"C "referstotheControlSubsystem. (2) The letter"M "referstotheMasterSubsystem.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-5.ControlSubsystem PeripheralFrame 1 C Address SizeC DMA Access (1) ControlSubsystem PeripheralFrame 1(x16Aligned)(1) (Bytes) 0000 5800 – 0000 59FF Reserved no 0000 5A00 – 0000 5A1F ECAP1 64 no 0000 5A20 – 0000 5A3F ECAP2 64 no 0000 5A40 – 0000 5A5F ECAP3 64 no 0000 5A60 – 0000 5A7F ECAP4 64 no 0000 5A80 – 0000 5A9F ECAP5 64 no 0000 5AA0 – 0000 5ABF ECAP6 64 0000 5AC0 – 0000 5AFF Reserved no 0000 5B00 – 0000 5B3F EQEP1 128 no 0000 5B40 – 0000 5B7F EQEP2 128 no 0000 5B80 – 0000 5BBF EQEP3 128 0000 5BC0 – 0000 5F7F Reserved no 0000 5F80 – 0000 5FFF C GPIO Group 1 Registers(1) 256 0000 6000 – 0000 63FF Reserved no 0000 6400 – 0000 641F COMP1 Registers 64 no 0000 6420 – 0000 643F COMP2 Registers 64 no 0000 6440 – 0000 645F COMP3 Registers 64 no 0000 6460 – 0000 647F COMP4 Registers 64 no 0000 6480 – 0000 649F COMP5 Registers 64 no 0000 64A0 – 0000 64BF COMP6 Registers 64 0000 64C0 – 0000 6F7F Reserved no 0000 6F80 – 0000 6FFF C GPIO Group 2 Registersand AIO Mux Registers(1) 256 (1) The letter"C "referstotheControlSubsystem. Table2-6.ControlSubsystem PeripheralFrame 2 C Address SizeC DMA Access (1) ControlSubsystem PeripheralFrame 2(x16Aligned)(1) (Bytes) 0000 7000 – 0000 70FF Reserved no 0000 7010 – 0000 702F C28x System ControlRegisters 64 0000 7030 – 0000 703F Reserved no 0000 7040 – 0000 704F SPI-A 32 no 0000 7050 – 0000 705F SCI-A 32 no 0000 7060 – 0000 706F NMI Watchdog InterruptRegisters 32 no 0000 7070 – 0000 707F ExternalInterruptRegisters 32 0000 7080 – 0000 70FF Reserved ADC1 ConfigurationRegistersno 0000 7100 – 0000 717F 256(Only16-bitread/writeaccesssupported) ADC2 ConfigurationRegistersno 0000 7180 – 0000 71FF 256(Only16-bitread/writeaccesssupported) 0000 7200 – 0000 78FF Reserved no 0000 7900 – 0000 793F I2C-A 128 0000 7940 – 0000 7FFF Reserved (1) The letter"C "referstotheControlSubsystem. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-7.ControlSubsystem RAMs C Address Size M Address µDMAC DMA Access (1) ControlSubsystem RAMs(x16Aligned)(1) (Bytes) (Byte-Aligned)(2) Access no 0000 8000 – 0000 8FFF L0 RAM (ECC, Secure) 8K no 0000 9000 – 0000 9FFF L1 RAM (ECC, Secure) 8K yes 0000 A000 – 0000 AFFF L2 RAM (Parity,Interleaving) 8K yes 0000 B000 – 0000 BFFF L3 RAM (Parity,Interleaving) 8K yes 0000 C000 – 0000 CFFF S0 RAM (Parity,Shared) 8K 2000 8000 – 2000 9FFF yes yes 0000 D000 – 0000 DFFF S1 RAM (Parity,Shared) 8K 2000 A000 – 2000 BFFF yes yes 0000 E000 – 0000 EFFF S2 RAM (Parity,Shared) 8K 2000 C000 – 2000 DFFF yes yes 0000 F000 – 0000 FFFF S3 RAM (Parity,Shared) 8K 2000 E000 – 2000 FFFF yes yes 0001 0000 – 0001 0FFF S4 RAM (Parity,Shared) 8K 2001 0000 – 2001 1FFF yes yes 0001 1000 – 0001 1FFF S5 RAM (Parity,Shared) 8K 2001 2000 – 2001 3FFF yes yes 0001 2000 – 0001 2FFF S6 RAM (Parity,Shared) 8K 2001 4000 – 2001 5FFF yes yes 0001 3000 – 0001 3FFF S7 RAM (Parity,Shared) 8K 2001 6000 – 2001 7FFF yes 0001 4000 – 0003 F7FF Reserved yesyes 0003 F800 – 0003 FBFF CtoM MSG RAM (Parity) 2K 2007 F000 – 2007 F7FF readonly yes 0003 FC00 – 0003 FFFF MtoC MSG RAM (Parity) 2K 2007 F800 – 2007 FFFF yesreadonly 0004 0000 – 0004 7FFF Reserved no 0004 8000 – 0004 8FFF L0 RAM -ECC Bits 8K no 0004 9000 – 0004 9FFF L1 RAM -ECC Bits 8K no 0004 A000 – 0004 AFFF L2 RAM -ParityBits 8K no 0004 B000 – 0004 BFFF L3 RAM -ParityBits 8K no 0004 C000 – 0004 CFFF S0 RAM -ParityBits 8K 2008 8000 – 2008 9FFF no no 0004 D000 – 0004 DFFF S1 RAM -ParityBits 8K 2008 A000 – 2008 BFFF no no 0004 E000 – 0004 EFFF S2 RAM -ParityBits 8K 2008 C000 – 2008 DFFF no no 0004 F000 – 0004 FFFF S3 RAM -ParityBits 8K 2008 E000 – 2008 FFFF no no 0005 0000 – 0005 0FFF S4 RAM -ParityBits 8K 2009 0000 – 2009 1FFF no no 0005 1000 – 0005 1FFF S5 RAM -ParityBits 8K 2009 2000 – 2009 3FFF no no 0005 2000 – 0005 2FFF S6 RAM -ParityBits 8K 2009 4000 – 2009 5FFF no no 0005 3000 – 0005 3FFF S7 RAM -ParityBits 8K 2009 6000 – 2009 7FFF no 0005 4000 – 0007 EFFF Reserved no 0007 F000 – 0007 F3FF M0 RAM -ECC Bits 2K no 0007 F400 – 0007 F7FF M1 RAM -ECC Bits 2K no 0007 F800 – 0007 FBFF CtoM MSG RAM -ParityBits 2K 200F F000 – 200F F7FF no no 0007 FC00 – 0007 FFFF MtoC MSG RAM -ParityBits 2K 200F F800 – 200F FFFF no 0008 0000 – 0009 FFFF Reserved (1) The letter"C "referstotheControlSubsystem. (2) The letter"M "referstotheMasterSubsystem.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-8.ControlSubsystem Flash,ECC, OTP, Boot ROM C Address ControlSubsystem Size M Address µDMAC DMA Access (1) (x16Aligned)(1) Flash,ECC, OTP, Boot ROM (Bytes) (Byte-Aligned)(2) Access SectorN (notavailableforno 0010 0000 – 0010 1FFF 16K256KB Flashconfiguration) SectorM (notavailableforno 0010 2000 – 0010 3FFF 16K256KB Flashconfiguration) SectorL (notavailableforno 0010 4000 – 0010 5FFF 16K256KB Flashconfiguration) SectorK (notavailableforno 0010 6000 – 0010 7FFF 16K256KB Flashconfiguration) SectorJ (notavailableforno 0010 8000 – 0010 FFFF 64K256KB Flashconfiguration) SectorI(notavailableforno 0011 0000 – 0011 7FFF 64K256KB Flashconfiguration) SectorH (notavailableforno 0011 8000 – 0011 FFFF 64K256KB Flashconfiguration) no 0012 0000 – 0012 7FFF SectorG 64K no 0012 8000 – 0012 FFFF SectorF 64K no 0013 0000 – 0013 7FFF SectorE 64K no 0013 8000 – 0013 9FFF SectorD 16K no 0013 A000 – 0013 BFFF SectorC 16K no 0013 C000 – 0013 DFFF SectorB 16K SectorA no 0013 E000 – 0013 FFFF (CSM passwordinthehigh 16K address) 0014 0000 – 001F FFFF Reserved Flash-ECC Bitsno 0020 0000 – 0020 7FFF 64K(1/8ofFlashused = 64 KBytes) 0020 8000 – 0024 01FF Reserved no 0024 0200 – 0024 03FF TIOTP 1K 0024 0400 – 002F FFFF Reserved EPI0 yes 0030 0000 – 003F 7FFF (ExternalPeripheral/Memory 2G 6000 0000 – DFFF FFFF yes Interface)(3) no 003F 8000 – 003F FFFF C28x BootROM (64KBytes) 64K (1) The letter"C "referstotheControlSubsystem. (2) The letter"M "referstotheMasterSubsystem. (3) The ControlSubsystem has no directaccesstoEPI insiliconrevision0 devices. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.2.2 Master Subsystem Memory Map

Table2-9.Master Subsystem Flash,ECC, OTP, Boot ROM M Address SizeµDMA Access Master Subsystem Flash,ECC, OTP, Boot ROM(Byte-Aligned)(1) (Bytes) BootROM -Dual-mapped to0x0100 0000no 0000 0000 – 0000 FFFF 64K(Bothmaps accesssame physicallocation.) 0001 0000 – 001F FFFF Reserved SectorNno 0020 0000 – 0020 3FFF 16K(Zone1 CSM passwordinthelowaddress.) no 0020 4000 – 0020 7FFF SectorM 16K no 0020 8000 – 0020 BFFF SectorL 16K no 0020 C000 – 0020 FFFF SectorK 16K no 0021 0000 – 0021 FFFF SectorJ 64K no 0022 0000 – 0022 FFFF SectorI(notavailablefor256KB Flashconfiguration) 64K no 0023 0000 – 0023 FFFF SectorH (notavailablefor256KB Flashconfiguration) 64K no 0024 0000 – 0024 FFFF SectorG (notavailablefor256KB Flashconfiguration) 64K no 0025 0000 – 0025 FFFF SectorF (notavailablefor256KB Flashconfiguration) 64K no 0026 0000 – 0026 FFFF SectorE 64K no 0027 0000 – 0027 3FFF SectorD 16K no 0027 4000 – 0027 7FFF SectorC 16K no 0027 8000 – 0027 BFFF SectorB 16K SectorAno 0027 C000 – 0027 FFFF 16K(Zone2 CSM passwordinthehighaddress.) 0028 0000 – 005F FFFF Reserved Flash-ECC Bitsno 0060 0000 – 0060 FFFF 64K(1/8ofFlashused = 64 KBytes) 0061 0000 – 0068 047F Reserved no 0068 0480 – 0068 07FF TIOTP 896 no 0068 0800 OTP – SecurityLock 4 0068 0804 Reserved 0068 0808 Reserved no 0068 080C OTP – Zone 2 FlashStartAddress 4 no 0068 0810 OTP – EMAC Address0 4 no 0068 0814 OTP – EMAC Address1 4 0068 0818 – 0070 00FF Reserved OTP – ECC Bits– ApplicationUseno 0070 0100 – 0070 0102 3(1/8ofOTP used = 3 Bytes) 0070 0103 – 00FF FFFF Reserved BootROM – Dual-mapped to0x0000 0000no 0100 0000 – 0100 FFFF 64K(Bothmaps accesssame physicallocation.) 0101 0000 – 03FF FFFF Reserved ROM/Flash/OTP/BootROM – Mirror-mappedforµCRC . Accessingthisareaofmemory by theµCRC peripheral willcause an accessin0000 0000 – 03FF FFFF memory space. MirroredbootROM: 0x0400 0000 – 0x0400 FFFF (Not no 0400 0000 – 07FF FFFF dual-mappedROM address) 64M MirroredFlashbank:0x0420 0000 – 0x042F FFFF MirroredFlashOTP: 0x0468 0000 – 0x0468 1FFF (Read cyclesfromthisspace cause theµCRC peripheral tocontinuouslyupdatedatachecksum insidea register, when readinga blockofdata.) 0800 0000 – 1FFF FFFF Reserved (1) The letter"M "referstotheMasterSubsystem.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-10.Master Subsystem RAMs µDMA M Address Size C AddressMaster Subsystem RAMs C DMA Access (2) Access (Byte-Aligned)(1) (Bytes) (x16Aligned)(2) no 2000 0000 – 2000 1FFF C0 RAM (ECC, Secure) 8K no 2000 2000 – 2000 3FFF C1 RAM (ECC, Secure) 8K yes 2000 4000 – 2000 5FFF C2 RAM (Parity) 8K yes 2000 6000 – 2000 7FFF C3 RAM (Parity) 8K yes 2000 8000 – 2000 9FFF S0 RAM (Parity,Shared) 8K 0000 C000 – 0000 CFFF yes yes 2000 A000 – 2000 BFFF S1 RAM (Parity,Shared) 8K 0000 D000 – 0000 DFFF yes yes 2000 C000 – 2000 DFFF S2 RAM (Parity,Shared) 8K 0000 E000 – 0000 EFFF yes yes 2000 E000 – 2000 FFFF S3 RAM (Parity,Shared) 8K 0000 F000 – 0000 FFFF yes yes 2001 0000 – 2001 1FFF S4 RAM (Parity,Shared) 8K 0001 0000 – 0001 0FFF yes yes 2001 2000 – 2001 3FFF S5 RAM (Parity,Shared) 8K 0001 1000 – 0001 1FFF yes yes 2001 4000 – 2001 5FFF S6 RAM (Parity,Shared) 8K 0001 2000 – 0001 2FFF yes yes 2001 6000 – 2001 7FFF S7 RAM (Parity,Shared) 8K 0001 3000 – 0001 3FFF yes 2001 8000 – 2007 EFFF Reserved yes 2007 F000 – 2007 F7FF CtoM MSG RAM (Parity) 2K 0003 F800 – 0003 FBFF yesreadonly yesyes 2007 F800 – 2007 FFFF MtoC MSG RAM (Parity) 2K 0003 FC00 – 0003 FFFF readonly no 2008 0000 – 2008 1FFF C0 RAM -ECC Bits 8K no 2008 2000 – 2008 3FFF C1 RAM -ECC Bits 8K no 2008 4000 – 2008 5FFF C2 RAM -ParityBits 8K no 2008 6000 – 2008 7FFF C3 RAM -ParityBits 8K no 2008 8000 – 2008 9FFF S0 RAM -ParityBits 8K 0004 C000 – 0004 CFFF no no 2008 A000 – 2008 BFFF S1 RAM -ParityBits 8K 0004 D000 – 0004 DFFF no no 2008 C000 – 2008 DFFF S2 RAM -ParityBits 8K 0004 E000 – 0004 EFFF no no 2008 E000 – 2008 FFFF S3 RAM -ParityBits 8K 0004 F000 – 0004 FFFF no no 2009 0000 – 2009 1FFF S4 RAM -ParityBits 8K 0005 0000 – 0005 0FFF no no 2009 2000 – 2009 3FFF S5 RAM -ParityBits 8K 0005 1000 – 0005 1FFF no no 2009 4000 – 2009 5FFF S6 RAM -ParityBits 8K 0005 2000 – 0005 2FFF no no 2009 6000 – 2009 7FFF S7 RAM -ParityBits 8K 0005 3000 – 0005 3FFF no 2009 8000 – 200F EFFF Reserved no 200F F000 – 200F F7FF CtoM MSG RAM -ParityBits 2K 0007 F800 – 0007 FBFF no no 200F F800 – 200F FFFF MtoC MSG RAM -ParityBits 2K 0007 FC00 – 0007 FFFF no 2010 0000 – 21FF FFFF Reserved BitBanded RAM Zone (Dedicatedaddressforeachyes 2200 0000 – 23FF FFFF 32MRAM bitofCortex™ -M3 RAM blocksabove) AllRAM Spaces – Mirror- Mapped forµCRC . Accessingthismemory by the µCRC peripheralwillcause an accessto 2000 0000 – 23FF FFFFyes 2400 0000 – 27FF FFFF 64Mmemory space. (Read cyclesfromthisspace cause theµCRC peripheralto continuouslyupdatedata checksum insidea register when readinga blockofdata.) 2800 0000 – 3FFF FFFF Reserved (1) The letter"M "referstotheMasterSubsystem. (2) The letter"C "referstotheControlSubsystem. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-11.Master Subsystem Peripherals µDMA M Address Master Subsystem Size C Address C DMA Access (2) Access (Byte-Aligned)(1) Peripherals (Bytes) (x16Aligned)(2) yes 4000 0000 – 4000 0FFF Watchdog Timer0 Registers 4K yes 4000 1000 – 4000 1FFF Watchdog Timer1 Registers 4K 4000 2000 – 4000 3FFF Reserved yes 4000 4000 – 4000 4FFF M GPIO PortA (APB Bus)(1) 4K yes 4000 5000 – 4000 5FFF M GPIO PortB (APB Bus)(1) 4K yes 4000 6000 – 4000 6FFF M GPIO PortC (APB Bus)(1) 4K yes 4000 7000 – 4000 7FFF M GPIO PortD (APB Bus)(1) 4K yes 4000 8000 – 4000 8FFF SSI0 4K yes 4000 9000 – 4000 9FFF SSI1 4K yes 4000 A000 – 4000 AFFF SSI2 4K yes 4000 B000 – 4000 BFFF SSI3 4K yes 4000 C000 – 4000 CFFF UART0 4K yes 4000 D000 – 4000 DFFF UART1 4K yes 4000 E000 – 4000 EFFF UART2 4K yes 4000 F000 – 4000 FFFF UART3 4K yes 4001 0000 – 4001 0FFF UART4 4K 4001 1000 – 4001 FFFF Reserved no 4002 0000 – 4002 07FF I2C0 Master 2K no 4002 0800 – 4002 0FFF I2C0 Slave 2K no 4002 1000 – 4002 17FF I2C1 Master 2K no 4002 1800 – 4002 1FFF I2C1 Slave 2K 4002 2000 – 4002 3FFF Reserved yes 4002 4000 – 4002 4FFF M GPIO PortE (APB Bus)(1) 4K yes 4002 5000 – 4002 5FFF M GPIO PortF (APB Bus)(1) 4K yes 4002 6000 – 4002 6FFF M GPIO PortG (APB Bus)(1) 4K yes 4002 7000 – 4002 7FFF M GPIO PortH (APB Bus)(1) 4K 4002 8000 – 4002 FFFF Reserved yes 4003 0000 – 4003 0FFF GP Timer0 4K yes 4003 1000 – 4003 1FFF GP Timer1 4K yes 4003 2000 – 4003 2FFF GP Timer2 4K yes 4003 3000 – 4003 3FFF GP Timer3 4K 4003 4000 – 4003 CFFF Reserved yes 4003 D000 – 4003 DFFF M GPIO PortJ (APB Bus)(1) 4K

4003 E000 – 4003 FFFF Reserved

yes 4004 8000 – 4004 8FFF ENET MAC0 4K 4004 9000 – 4004 FFFF Reserved yes 4005 0000 – 4005 0FFF USB MAC0 4K 4005 1000 – 4005 7FFF Reserved yes 4005 8000 – 4005 8FFF M GPIO PortA (AHB Bus)(1) 4K yes 4005 9000 – 4005 9FFF M GPIO PortB (AHB Bus)(1) 4K yes 4005 A000 – 4005 AFFF M GPIO PortC (AHB Bus)(1) 4K yes 4005 B000 – 4005 BFFF M GPIO PortD (AHB Bus)(1) 4K yes 4005 C000 – 4005 CFFF M GPIO PortE (AHB Bus)(1) 4K yes 4005 D000 – 4005 DFFF M GPIO PortF (AHB Bus)(1) 4K yes 4005 E000 – 4005 EFFF M GPIO PortG (AHB Bus)(1) 4K (1) The letter"M "referstotheMasterSubsystem. (2) The letter"C "referstotheControlSubsystem.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-11.Master Subsystem Peripherals(continued) µDMA M Address Master Subsystem Size C Address C DMA Access (2) Access (Byte-Aligned)(1) Peripherals (Bytes) (x16Aligned)(2) yes 4005 F000 – 4005 FFFF M GPIO PortH (AHB Bus)(1) 4K yes 4006 0000 – 4006 0FFF M GPIO PortJ (AHB Bus)(1) 4K 4006 1000 – 4006 FFFF Reserved no 4007 0000 – 4007 3FFF CAN0 16K no 4007 4000 – 4007 7FFF CAN1 16K 4007 8000 – 400C FFFF Reserved no 400D 0000 – 400D 0FFF EPI0 (Registersonly) 4K 400D 1000 – 400F 9FFF Reserved no 400F A000 – 400F A303 M FlashControlRegisters(1) 772 400F A304 – 400F A5FF Reserved M FlashECC ErrorLogno 400F A600 – 400F A647 72Registers(1) 400F A648 – 400F B1FF Reserved no 400F B200 – 400F B2FF RAM ConfigurationRegisters 256 0000 4900 – 0000 497F no RAM ECC/Parity/AccessErrorno 400F B300 – 400F B3FF 256 0000 4A00 – 0000 4A7F noLog Registers no 400F B400 – 400F B5FF M CSM Registers(1) 512 no 400F B600 – 400F B67F µCRC 128 400F B680 – 400F B6FF Reserved no 400F B700 – 400F B77F CtoM and MtoC IPC Registers 128 0000 4E00 – 0000 4E3F no 400F B780 – 400F B7FF Reserved no 400F B800 – 400F B87F M ClockControlRegisters(1) 128 0000 4400 – 0000 443F no no 400F B880 – 400F B8BF M LPM ControlRegisters(1) 64 no 400F B8C0 – 400F B8FF M ResetControlRegisters(1) 64 0000 0880 – 0000 0890no 400F B900 – 400F B93F DeviceConfigurationRegisters 64 (Read Only) 400F B940 – 400F B97F Reserved no 400F B980 – 400F B9FF M WriteProtectRegisters(1) 128 no 400F BA00 – 400F BA7F M NMI Registers(1) 128 400F BA80 – 400F EFFF Reserved no 400F F000 – 400F FFFF µDMA Registers 4K 4010 0000 – 41FF FFFF Reserved BitBanded PeripheralZone (Dedicatedaddressforeachyes 4200 0000 – 43FF FFFF 32MregisterbitofCortex™ -M3 peripheralsabove.) 4400 0000 – 4FFF FFFF Reserved Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-12.Master Subsystem Analog and EPI µDMA M Address Master Subsystem Size C Address C DMA Access (2) Access (Byte-Aligned)(1) Analog and EPI (Bytes) (x16Aligned)(2) 5000 0000 – 5000 15FF Reserved yes 5000 1600 – 5000 161F ADC1 ResultRegisters 32 5000 1620 – 5000 167F Reserved yes 5000 1680 – 5000 169F ADC2 ResultRegisters 32 5000 16A0 – 5FFF FFFF Reserved EPI0 yes 6000 0000 – DFFF FFFF (ExternalPeripheral/Memory 2G 0030 0000 – 003F 7FFF (3) yes Interface) (1) The letter"M "referstotheMasterSubsystem. (2) The letter"C "referstotheControlSubsystem. (3) The ControlSubsystem has no directaccesstoEPI insiliconrevision0 devices. Table2-13.Cortex™ -M3 PrivateBus µDMA Cortex™ -M3 Address SizeCortex™ -M3 PrivateBusAccess (Byte-Aligned) (Bytes) no E000 0000 – E000 0FFF ITM (InstrumentationTraceMacrocell) 4K no E000 1000 – E000 1FFF DWT (DataWatchpointand Trace) 4K no E000 2000 – E000 2FFF FPB (FlashPatchand Breakpoint) 4K E000 3000 – E000 E007 Reserved no E000 E008 – E000 E00F System ControlBlock 8 no E000 E010 – E000 E01F System Timer 16 E000 E020 – E000 E0FF Reserved no E000 E100 – E000 E4EF NestedVectoredInterruptController(NVIC) 1008 E000 E4F0 – E000 ECFF Reserved no E000 ED00 – E000 ED3F System ControlBlock 64 E000 ED40 – E000 ED8F Reserved no E000 ED90 – E000 EDB8 Memory ProtectionUnit 41 E000 EDB9 – E000 EEFF Reserved no E000 EF00 – E000 EF03 NestedVectoredInterruptController(NVIC) 4 E000 EF04 – FFFF FFFF Reserved NOTE MPU isnotavailableon siliconrevision0 devices.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.3 Master Subsystem

The Master Subsystem includesthe Cortex™ -M3 CPU, µDMA, Nested VectoredInterruptController (NVIC),Cortex™ -M3 Peripherals,and LocalMemory. Additionally,theCortex™ -M3 CPU and µDMA can access theControlSubsystem throughShared Resources:IPC (CPU only),Message RAM, and Shared RAM; and readADC ResultRegistersviatheAnalogCommon InterfaceBus.The MasterSubsystem can alsoreceiveeventsfromtheNMI blockand send eventstotheResetsblock. Figure2-1shows theMasterSubsystem.

2.3.1 Cortex™ -M3 CPU

The 32-bitCortex™ -M3 processoroffershighperformance,fastinterrupthandling,and accesstoa variety of communication peripherals(includingEthernetand USB). The Cortex™ -M3 featuresa Memory ProtectionUnit(MPU) to providea privilegedmode forprotectedoperatingsystem functionality.A bus bridgeadjacenttotheMPU can routeprogram instructionsand dataon theI-CODE and D-CODE buses thatconnecttotheBoot ROM and Flash.OtherdataistypicallyroutedthroughtheCortex™ -M3 System Bus connectedto the localRAMs. The System Bus alsogoes to the Shared Resources block(also accessibleby the ControlSubsystem) and to the Analog Subsystem throughthe Analog Common InterfaceBus (ACIB).Anotherbus bridgeallowsbus cyclesfrom boththeCortex™ -M3 System Bus and thoseoftheµDMA bus toaccesstheMasterSubsystem peripherals(viatheAPB bus ortheAHP bus). Most of the interruptsto the Cortex™ -M3 CPU come from the Nested VectoredInterruptController (NVIC),whichmanages theinterruptrequestsfromperipheralsand assignshandlingpriorities.There are alsoseveralexceptionsgeneratedby Cortex™ -M3 CPU thatcan returntotheCortex™ -M3 as interrupts afterbeingprioritizedwithotherrequestsinsidetheNVIC. Inadditiontoprogrammablepriorityinterrupts, thereare alsothreelevelsof fixed-priorityinterruptsof which the highestpriority,level-3,isgivento M3PORRST and M3SYSRST resetsfromtheResetsblock.The nexthighestpriority,level-2,isassigned totheM3NMIINT, whichoriginatesfromtheNMI block.The M3HRDFLT (HardFault)interruptisassigned to level-1priority,and thisinterruptis caused by one of the errorconditionexceptions(Memory Management, Bus Fault,Usage Fault)escalatingto Hard Faultbecause they are not enabled or not properlyserviced. The Cortex™ -M3 CPU has two low-powermodes: Sleepand Deep Sleep.

2.3.2 Cortex™ -M3 Core Hardware Logic Built-InTest(LBIST)

The Concerto™ microcontrollerCortex™ -M3 CPU core includesa Logic Built-InSelfTest (LBIST) controllerfortestingtheCPU corelogicforerrors.Testsareinitiatedby softwarewhenever convenient(at start-up,idle,and so on),whichallowsforperiodiclogicteststoensurethattheCPU corelogicisworking correctly.Duringa testcycle,allinterruptsareloggedby theLBIST controllerand re-issuedafterthetest cyclecompletestoensurethatno interruptsaremissed.Intheeventofa logicerror,theLBIST controller generatesan NMI on both coresto signalthatan errorhas been detected.Thisactionallowsforthe softwaretogracefullyhandleany detectedlogicerrors. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback

PRODUCT□PREVIEW BUS MA TRIX EPI I2C (2) SSI (4)UART (5)USB + PHY (OTG) EMAC CAN (2) GP TIMER (4) uCRC WDOG (2)NMI WDOG M3 NMI NVIC (NESTED VECTORED INTERRUPT CONTROLLER) BOOT ROM uDMA RESETS MPU / BRIDGE SECURE FLASH (ECC) FLASHUNCERR BUSFAULTBUS CNTRL/FAULT LOGIC LOCAL MEMORY MEMORY MNGMT FLFSMFLSINGER ANALOG SUBSYSTEM EXCEPTIONS FROM M3 CORE M3NMIINT M3PORRST M3HRDFLT INSTRUCTIONS D-CODE BUS M3 SYSTEM BUS AHB BUS APB BUS I-CODE BUS CPU M3SYSRST UART (5:1) REQ SSI (3:0) REQ USB MAC REQ EPI REQ GPTA/B (3:0) (3:0) REQ EMACRX EMACTX REQ M3DBGRST M3WDRST (1:0) M3NMIRST M3SWRST M3NMI USAGE FAULT SVCALL DBG MONITOR PENDING SV SYS TICK PROGRAM- MABLE PRIORITY INTERRUPTS FIXED PRIORITY INTERRUPTS GPIO_MUX1 DMA INTRS DAT A INTERRUPTS APB BUS (REG ACCESS ONLY) NVIC M3NMIINT ADC INT (8:1) M3NMIINT EOC INTERRUPTS M3 PERIPHERALS UART (1:5) IRQ SSI (0:3) IRQ I2C (1:0) IRQ CAN0/1 (1:0) (1:0) IRQ USB MAC IRQ EPI IRQ GPTA/B (3:0) (3:0) IRQ GPIO (S:A) IRQ WDT (1:0) IRQ EMAC IRQ DMA SW IRQ DMA ERR IRQ PERIPHERAL I/O s RAMUNCERR S0-S7 SHARED RAM (parity) MTOC MSG RAM (parity) CTOM MSG RAM (parity) SHARED RESOURCES CONTROL SUBSYSTEM uDMA BUS CTOM IPC (4:1) IPC REGS FREQ GASKET BUS BRIDGE C2 - C3 RAM (parity) SECURE C0/C1 RAM (ECC) RAMUNCERRRAMACCVIOL RAMSINGERR F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-1.Master Subsystem

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.3.3 Cortex™ -M3 DMA and NVIC

The Cortex™ -M3 directmemory access(µDMA) module providesa hardwaremethod oftransferringdata between peripherals,between memory, and between peripheralsand memory withoutinterventionfrom theCortex™ -M3 CPU. The Nested VectoredInterruptController(NVIC)manages and prioritizesinterrupt handlingfortheCortex™ -M3 CPU. The Cortex™ -M3 peripheralsuse REQ/DONE handshakingtocoordinatedatatransferrequestswiththe µDMA. Ifa DMA channelisenabledfora givenperipheral,REQ/DONE fromtheperipheralwilltriggerthe datatransfer,followingwhichan IRQ requestmay be sentfromtheµDMA totheNVIC toannounce tothe Cortex™ -M3 thatthe transferhas completed.Ifa DMA channelisnot enabledfora givenperipheral, REQ/DONE willdirectlydriveIRQ totheNVIC so thattheCortex™ -M3 CPU can transferthedata.For thoseperipheralsthatarenotsupportedby theµDMA, IRQs aresupplieddirectlytotheNVIC, bypassing theDMA. Thiscase istrueforbothWatchdogs,CANs, I2Cs,and theAnalog-to-DigitalConverterssending ADCINT[8:1]interruptsfromtheAnalogSubsystem.The NMI Watchdog does notsend any eventstothe µDMA ortheNVIC (onlytotheResetsblock).

2.3.4 Cortex™ -M3 Interrupts

Table2-14 shows allinterruptassignmentsfortheCortex™ -M3 processor.Most interrupts(16–107) are associatedwith interruptrequestsfrom Cortex™ -M3 peripherals.The first15 interrupts(1–15) are processorexceptionsgeneratedby theCortex™ -M3 coreitself.These processorexceptionsare detailed inTable2-15. Table2-14.Interruptsfrom NVIC toCortex™ -M3 InterruptNumber VectorNumber VectorAddress or Offset Description(BitinInterruptRegisters) – 0–15 0x0000.0000–0x0000.003C Processorexceptions 0 16 0x0000.0040 GPIO PortA 1 17 0x0000.0044 GPIO PortB 2 18 0x0000.0048 GPIO PortC 3 19 0x0000.004C GPIO PortD 4 20 0x0000.0050 GPIO PortE 5 21 0x0000.0054 UART0 6 22 0x0000.0058 UART1 7 23 0x0000.005C SSI0 8 24 0x0000.0060 I2C0 9–17 25–33 – Reserved 18 34 0x0000.0088 Watchdog Timers0 and 1 19 35 0x0000.008C Timer0A 20 36 0x0000.0090 Timer0B 21 37 0x0000.0094 Timer1A 22 38 0x0000.0098 Timer1B 23 39 0x0000.009C Timer2A 24 40 0x0000.00A0 Timer2B 25–27 41–43 – Reserved 28 44 0x0000.00B0 System Control 29 45 0x0000.00B4 FlashStateMachine 30 46 0x0000.00B8 GPIO PortF 31 47 0x0000.00BC GPIO PortG 32 48 0x0000.00C0 GPIO PortH 33 49 0x0000.00C4 UART2 34 50 0x0000.00C8 SSI1 Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-14.Interruptsfrom NVIC toCortex™ -M3 (continued) InterruptNumber VectorNumber VectorAddress or Offset Description(BitinInterruptRegisters) 35 51 0x0000.00CC Timer3A 36 52 0x0000.00D0 Timer3B 37 53 0x0000.00D4 I2C1 38–41 54–57 – Reserved 42 58 0x0000.00E8 EthernetController 44 60 0x0000.00F0 USB 45 61 – Reserved 46 62 0x0000.00F8 µDMA Software 47 63 0x0000.00FC µDMA Error 48–52 64–68 – Reserved 53 69 0x0000.0114 EPI 54 70 0x0000.0118 GPIO PortJ 55–56 71–72 – Reserved 57 73 0x0000.0124 SSI 2 58 74 0x0000.0128 SSI 3 59 75 0x0000.012C UART3 60 76 0x0000.0130 UART4 61–63 77–79 – Reserved 64 80 0x0000.0140 CAN1 INT0 65 81 0x0000.0144 CAN1 INT1 66 82 0x0000.0148 CAN1 INT0 67 83 0x0000.014C CAN1 INT1 68–71 84–87 – Reserved 72 88 0x0000.0160 ADCINT1 73 89 0x0000.0164 ADCINT2 74 90 0x0000.0168 ADCINT3 75 91 0x0000.016C ADCINT4 76 92 0x0000.0170 ADCINT5 77 93 0x0000.0174 ADCINT6 78 94 0x0000.0178 ADCINT7 79 95 0x0000.017C ADCINT8 80 96 0x0000.0180 CTOMIPC1 81 97 0x0000.0184 CTOMIPC2 82 98 0x0000.0188 CTOMIPC3 83 99 0x0000.018C CTOMIPC4 84–87 100–103 – Reserved 88 104 0x0000.01A0 RAM SingleError 89 105 0x0000.01A4 System /USB PLL Out ofLock 90 106 0x0000.01A8 M3 FlashSingleError 91–133 107–149 – Reserved

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-15.Exceptionsfrom Cortex™ -M3 Core toNVIC VectorAddress orExceptionType Priority(1) VectorNumber ActivationOffset(2) Stacktopisloadedfrom – – 0 0x0000.0000 thefirstentryofthevector tableon reset. Reset –3 (highest) 1 0x0000.0004 Asynchronous Asynchronous On Concertodevices activatedby clockfailNon-MaskableInterrupt –2 2 0x0000.0008 condition,C28 PIE error,(NMI) externalM3GPIO NMI inputsignal,and C28 NMI WD timeoutreset. Hard Fault –1 3 0x0000.000C – Memory Management programmable(3) 4 0x0000.0010 Synchronous Synchronouswhen preciseand asynchronous when imprecise. On ConcertodevicesBus Fault programmable(3) 5 0x0000.0014 activatedby memory accesserrorsand RAM and flashuncorrectable dataerrors. Usage Fault programmable(3) 6 0x0000.0018 Synchronous – – 7–10 – Reserved SVCall programmable(3) 11 0x0000.002C Synchronous Debug Monitor programmable(3) 12 0x0000.0030 Synchronous – – 13 – Reserved PendSV programmable(3) 14 0x0000.0038 Asynchronous SysTick programmable(3) 15 0x0000.003C Asynchronous Interrupts programmable (4) 16 and above 0x0000.0040and above Asynchronous (1) 0 isthedefaultpriorityforalltheprogrammablepriorities (2) See the"VectorTable"subsectionofthe"ExceptionModel"sectionintheCortex-M3ProcessorchapteroftheConcertoF28M35x TechnicalReferenceManual (literaturenumber SPRUH22 ). (3) See SYSPRI1 intheCortex-M3PeripheralschapteroftheConcertoF28M35x TechnicalReferenceManual (literaturenumber SPRUH22 ). (4) See PRIn registersintheCortex-M3PeripheralschapteroftheConcertoF28M35x TechnicalReferenceManual (literaturenumber SPRUH22 ).

2.3.5 Cortex™ -M3 VectorTable

Each peripheralinterruptof Table 2-14 is assignedan address offsetcontainingthe locationof the peripheralinterrupthandler(relativetothevectortablebase)forthatparticularinterrupt(vectornumbers 16–107). Similarly,each exceptioninterruptof Table 2-15 (includingReset)isalsoassignedan address offset containingthe locationof the exceptioninterrupthandler(relativeto the vectortablebase) forthat particularinterrupt(vectornumbers 1–15). In additionto interruptvectors,the vectortablealso containsthe initialstackpointervalue at table location0. Followingsystem reset,the vectortablebase isfixedat address0x0000.0000.Privilegedsoftwarecan writetotheVectorTableOffset(VTABLE) registertorelocatethevectortablestartaddresstoa different memory location,inthe range 0x0000 0200 to 0x3FFF FE00. Note thatwhen configuringthe VTABLE register,theoffsetmust be alignedon a 512-byteboundary. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.3.6 Cortex™ -M3 LocalPeripherals

The Cortex™ -M3 localperipheralsincludetwo Watchdogs, an NMI Watchdog, fourGeneral-Purpose Timers,fourSSI peripherals,two CAN peripherals,fiveUARTs, two I2C peripherals,Ethernet,USB + PHY, EPI,and µCRC (CyclicRedundancy Check).The USB and EPI areaccessiblethroughtheAHB Bus (Advanced High-PerformanceBus).The EPI peripheralisalsoaccessiblefrom the ControlSubsystem. The remainingperipheralsareaccessiblethroughtheAPB Bus (AdvancedPeripheralBus).The APB and AHB bus cyclesoriginatefromtheCPU System Bus ortheµDMA Bus viaa bus bridge. While the Cortex™ -M3 CPU has access to allthe peripherals,the µDMA has access to most,withthe exceptionof the µCRC, Watchdogs, NMI Watchdog, CAN peripherals,and the I2C peripheral.The Cortex™ -M3 peripheralsconnecttotheConcerto™ devicepinsviaGPIO_MUX1. Most oftheperipherals alsogenerateeventsignalsforthe µDMA and the NVIC. The Watchdogs receiveM3SWRST from the NVIC (triggeredby software)and send M3WDRST[1:0] resetrequeststo the Reset block.The NMI Watchdog receivestheM3NMI eventfromtheNMI blockand sends theM3NMIRST requesttotheResets block. See Section6.2formore informationon theCortex™ -M3 peripherals.

2.3.7 Cortex™ -M3 LocalMemory

The LocalMemory includesBoot ROM; Secure FlashwithErrorCorrectionCode (ECC);Secure C0/C1 RAM with ECC; and C2/C3 RAM with ParityErrorChecking.The Boot ROM and Flash are both accessiblethroughthe I-CODE and D-CODE Buses. Flash registerscan also be accessed by the Cortex™ -M3 CPU throughtheAPB Bus.AllLocalMemory isaccessiblefromtheCortex™ -M3 CPU; the C2/C3 RAM isalsoaccessibleby theµDMA. Two typesoferrorcorrectioneventscan be generatedduringaccessoftheLocalMemory: uncorrectable errorsand singleerrors.The uncorrectableerrors(includingone from theShared Memories)generatea Bus FaultExceptiontotheCortex™ -M3 CPU. The lesscriticalsingleerrorsgo totheNVIC where they can resultinmaskableinterruptstotheCortex™ -M3 CPU.

2.3.8 Cortex™ -M3 Accessing Shared Resources and Analog Peripherals

There areseveralmemories,digitalperipherals,and analogperipheralsthatcan be accessedby boththe Masterand ControlSubsystems.They aregroupedintoShared Resourcesand theAnalogSubsystem. The Shared Resources includetheExternalPeripheralInterface(EPI),Inter-ProcessorCommunications (IPC)registers,MTOC Message RAM, CTOM Message RAM, and eightindividuallyconfigurableShared RAM blocks.The RAMs oftheShared Resourcesblockhave ParityErrorChecking. The Message RAMs and theShared RAMs can be accessed by theCortex™ -M3 CPU and µDMA. The MTOC Message RAM isintendedforsendingdatafromtheMasterSubsystem totheControlSubsystem, having r/w access forthe Cortex™ -M3/µDMA and read-onlyaccess forthe C28x/DMA. The CTOM Message RAM isintendedforsendingdatafromtheControlSubsystem totheMasterSubsystem,having r/waccessfortheC28x/DMA and read-onlyaccessfortheCortex™ -M3/µDMA. The IPC registersprovideup to32 handshakingchannelstocoordinatethetransferofdatathroughthe Message RAMs by polling.Four ofthesechannelsare alsobacked up by fourinterruptstoPIE on the ControlSubsystem side,and fourinterruptstotheNVIC on theMasterSubsystem side(toreducedelays associatedwithpolling). The eightShared RAM blocksare similartotheMessage RAMs, inthatthedataflowisonlyone way; however,thedirectionofthedataflowcan be individuallysetforeach blocktobe fromMastertoControl Subsystem orfromControltoMasterSubsystem.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripheralsthatcan be accessed throughthe Analog Common InterfaceBus. The ADC ResultRegistersare accessibleby CPUs and DMAs oftheMasterand ControlSubsystems.AllotherAnalogPeripheralRegistersareaccessibleby the C28x CPU only.The Cortex™ -M3 CPU accesses the ACIB throughthe System Bus, and the µDMA throughthe µDMA Bus. The ACIB arbitratesforaccess to the ADC and Analog Comparator registers between CPU/DMA bus cyclesoftheMasterSubsystem withthoseoftheControlSubsystem.Inaddition to managing bus cycles,the ACIB also transfersEnd-of-ConversionADC interruptsto the Master Subsystem (aswellas totheControlSubsystem).The eightEOC sourcesfromADC1 and theeightEOC sourcesfrom ADC2 are AND-ed togetherby the ACIB, withthe resultingeightADC interruptsgoingto destinationsinboththeMasterSubsystem and theControlSubsystem. See Section6.1formore informationon sharedresourcesand analogperipherals.

2.4 ControlSubsystem

The ControlSubsystem includesthe C28x CPU/FPU/VCU, PeripheralInterruptExpansion(PIE)block, DMA, C28x Peripherals,and LocalMemory. Additionally,theC28x CPU and DMA have accesstoShared Resources:IPC (CPU only),Message RAM, and Shared RAM; and toAnalogPeripheralsviatheAnalog Common InterfaceBus. Figure2-2shows theControlSubsystem.

2.4.1 C28x CPU/FPU/VCU

The F28M35x Concerto™ MCU familyis a member of the TMS320C2000 ™ MCU platform.The Concerto™ C28x CPU/FPU has thesame 32-bitfixed-pointarchitectureas TI'sexistingPiccolo™ MCUs, combined witha single-precision(32-bit)IEEE 754 floating-pointunit(FPU) of TI’s existingDelfino™ MCUs. Each F28M35x deviceisa veryefficientC/C++ engine,enablingusersto developtheirsystem controlsoftwarein a high-levellanguage.Each F28M35x devicealsoenablesmath algorithmsto be developedusingC/C++. The deviceisequallyefficientatDSP math tasksand atsystem controltasks. The 32 x 32-bitMAC 64-bitprocessingcapabilitiesenable the controllerto handle highernumerical resolutionproblemsefficiently.Withtheadditionofthefastinterruptresponsewithautomaticcontextsave of criticalregisters,the deviceiscapableof servicingmany asynchronouseventswithminimallatency. The devicehas an 8-level-deepprotectedpipelinewithpipelinedmemory accesses.This pipelining enables the deviceto execute at high speeds withoutresortingto expensivehigh-speedmemories. Specialbranch-look-aheadhardware minimizes the latencyfor conditionaldiscontinuities.Special conditionalstoreoperationsfurtherimproveperformance.The VCU extendsthecapabilitiesoftheC28x CPU and C28x+FPU processorsby adding additionalinstructionsto accelerateViterbi,Complex Arithmetic,16-bitFFTs, and CRC algorithms.No changes have been made to existinginstructions, pipeline,ormemory bus architecture.Therefore,programswrittenfortheC28x arecompletelycompatible withtheC28x+VCU. There are two eventsgeneratedby the FPU blockthatgo to the C28x PeripheralInterruptExpansion (PIE):LVF and LUV. InsidePIE,theseand othereventsfromC28x peripheralsand memories resultin12 PIE interruptsPIEINTS[12:1]intotheC28x CPU. The C28x CPU alsoreceivesthreeadditionalinterrupts directly(insteadof throughPIE) from Timer 1 (TINT1),from Timer 2 (TINT2),and from the NMI block (C28uNMIINT). The C28x has two low-powermodes: Idleand Standby. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback

PRODUCT□PREVIEW EMUSTOP TIMER (3)XINT (3)EPWM (9) NMIWDOGEQEP (3) ECAP (6)McBSPI2C SCI SPI PIE (PERIPHERAL INTERRUPT EXPANSION) C28x DMA ANALOG SUBSYSTEM GPIO_MUX1 GPIO_MUX1 C28x NMI EQEP ERR SOC TRIGGERS EOC INTERRUPTS ADCINT (8:1) DINTCH (6:1) TINT 0,1,2 ADCINT (4:1) GPTRIP (12:1) GPTRIP (12:7) GPTRIP (6:4) PIENMIERR C28NMIRST C28 CPU BUS C28 DMA BUS C28x CPU C28x FPU C28x VCU PIEINTRS (12:1) C28x LOCAL MEMORY TINT1 TINT2 C28NMIINTC28NMI BOOT ROM L2/L3 RAM (parity) SECURE FLASH (ECC) SECURE L0/L1 RAM (ECC) RAMUNCERR RAMACCVIOL FLASHUNCERR S0-S7 SHARED RAM (parity) MTOC MSG RAM (parity) IPC REGS CTOM MSG RAM (parity) MASTER SUBSYSTEM M0/M1 RAM (ECC) C28x NMI LUFLVFFLFSMFLSINGERR RAMSINGERRMTOCIPC (4:1) SHARED RESOURCES GPIO_MUX1 XINT 1,2,3 MXINTA, MRINTA SOCA (9:1), SOCB(9:1)SOCA (9:1), SOCB(9:1) TINT 0,1,2 XINT 2 ECCDBLERR ECCDBLERR LPMWAKE M3 NMI C28x PERIPHERALS RAMUNCERR M3 CLOCKS CLOCKFAIL LPM WAKEUP RESETS EPWM(9:1)TZINT EPWM(9:1)INT EQEP(3:1)INT ECAP(6:1)INT SPIRXINTA, SPITXINTA SCIRXINTA, SCITXINTA GPIO_MUX1 SOCBOSOCAO SYNCO PERIPHERAL I/O s FREQ GASKET BUS BRIDGE EPI I2CINT1A, I2CINT2A GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-2.ControlSubsystem

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.4.2 C28x ™ Core Hardware Logic Built-InTest(LBIST)

The Concerto™ microcontrollerC28x CPU coreincludesa LogicBuilt-InSelfTest(LBIST)controllerfor testingtheCPU corelogicforerrors.Testsareinitiatedby softwarewhenever convenient(atstart-up,idle, and so on),which allowsforperiodiclogicteststoensurethattheCPU corelogicisworkingcorrectly. Duringa testcycle,allinterruptsare loggedby the LBIST controllerand re-issuedafterthe testcycle completesto ensure thatno interruptsare missed.In the event of a logicerror,the LBIST controller generatesan NMI on both coresto signalthatan errorhas been detected.Thisactionallowsforthe softwaretogracefullyhandleany detectedlogicerrors.

2.4.3 C28x PeripheralInterruptExpansion (PIE)

The PIE blockservestomultiplexnumerous interruptsourcesintoa smallersetofinterruptinputs.The PIE blockcan supportup to96 peripheralinterrupts.On theF28M35x, 66 ofthepossible96 interruptsare used.The 96 interruptsaregroupedintoblocksof8 and each groupisfedinto1 of12 CPU interruptlines (INT1toINT12).Each of12 interruptlinessupportsup to8 simultaneouslyactiveinterrupts.Each ofthe 96 interruptshas itsown vectorstoredina dedicatedRAM blockthatcan be overwrittenby theuser.The vectorisautomaticallyfetchedby theCPU on servicingtheinterrupt.EightCPU clockcyclesareneeded to fetchthe vectorand save criticalCPU registers.Hence, the CPU can quicklyrespond to interrupt events.Prioritizationofinterruptsiscontrolledinhardwareand software.Each individualinterruptcan be enabledordisabledwithinthePIE block.See Table2-16forPIE interruptassignments. Table2-16.PIE PeripheralInterrupts(1) PIE INTERRUPTS CPU INTERRUPTS C28.LPMWAKE TINT0 Reserved XINT2 XINT1 Reserved ADCINT2 ADCINT1 INT1 (C28LPM) (TIMER 0) – – – – (ADC) (ADC) 0x0D4E 0x0D4C 0x0D4A 0x0D48 0x0D46 0x0D44 0x0D42 0x0D40 EPWM8_TZINT EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT INT2 (ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0x0D5E 0x0D5C 0x0D5A 0x0D58 0x0D56 0x0D54 0x0D52 0x0D50 EPWM8_INT EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT INT3 (ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0x0D6E 0x0D6C 0x0D6A 0x0D68 0x0D66 0x0D64 0x0D62 0x0D60 EPWM9_TZINT Reserved ECAP6_INT ECAP5_INT ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT INT4 (ePWM9) – (eCAP6) (eCAP5) (eCAP4) (eCAP3) (eCAP2) (eCAP1) 0x0D7E 0x0D7C 0x0D7A 0x0D78 0x0D76 0x0D74 0x0D72 0x0D70 EPWM9_INT Reserved Reserved Reserved Reserved EQEP3_INT EQEP2_INT EQEP1_INT INT5 (ePWM9) – – – – (eQEP3) (eQEP2) (eQEP1) 0x0D8E 0x0D8C 0x0D8A 0x0D88 0x0D86 0x0D84 0x0D82 0x0D80 Reserved Reserved MXINTA MRINTA Reserved Reserved SPITXINTA SPIRXINTA INT6 – – (McBSPA) (McBSPA) – – (SPIA) (SPIA) 0x0D9E 0x0D9C 0x0D9A 0x0D98 0x0D96 0x0D94 0x0D92 0x0D90 Reserved Reserved DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1 INT7 – – (C28 DMA) (C28 DMA) (C28 DMA) (C28 DMA) (C28 DMA) (C28 DMA) 0x0DAE 0x0DAC 0x0DAA 0x0DA8 0x0DA6 0x0DA4 0x0DA2 0x0DA0 Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A INT8 – – – – – – (I2CA) (I2CA) 0x0DBE 0x0DBC 0x0DBA 0x0DB8 0x0DB6 0x0DB4 0x0DB2 0x0DB0 Reserved Reserved Reserved Reserved Reserved Reserved SCITXINTA SCIRXINTA INT9 – – – – – – (SCIA) (SCIA) 0x0DCE 0x0DCC 0x0DCA 0x0DC8 0x0DC6 0x0DC4 0x0DC2 0x0DC0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 INT10 (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) 0x0DDE 0x0DDC 0x0DDA 0x0DD8 0x0DD6 0x0DD4 0x0DD2 0x0DD0 Reserved Reserved Reserved Reserved MTOCIPCINT4 MTOCIPCINT3 MTOCIPCINT2 MTOCIPCINT1 INT11 – – – – (IPC) (IPC) (IPC) (IPC) 0x0DEE 0x0DEC 0x0DEA 0x0DE8 0x0DE6 0x0DE4 0x0DE2 0x0DE0 LUF LVF EPI_INT C28RAMACCVIOL C28RAMSINGERR Reserved C28FLSINGERR XINT3 INT12 (C28FPU) (C28FPU) (EPI) (Memory) (Memory) – (Memory) (Ext.Int.3) 0x0DFE 0x0DFC 0x0DFA 0x0DF8 0x0DF6 0x0DF4 0x0DF2 0x0DF0 (1) Out ofthe96 possibleinterrupts,66 interruptsarecurrentlyused.The remaininginterruptsarereservedforfuturedevices.These interruptscan be used as softwareinterruptsiftheyareenabledatthePIEIFRxlevel,providednone oftheinterruptswithinthegroupis beingused by a peripheral.Otherwise,interruptscoming infromperipheralsmay be lostby accidentallyclearingtheirflagwhile modifyingthePIEIFR.To summarize,therearetwo safecaseswhen thereservedinterruptscouldbe used as softwareinterrupts: 1)No peripheralwithinthegroupisassertinginterrupts. 2)No peripheralinterruptsareassignedtothegroup(examplePIE group11). Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.4.4 C28x DMA

The C28x directmemory access(DMA) module providesa hardwaremethod oftransferringdatabetween peripherals,between memory, and between peripheralsand memory withoutinterventionfrom theCPU, therebyfreeingup bandwidthforothersystem functions.Additionally,the DMA has the capabilityto orthogonallyrearrangethe data as the data istransferredas wellas “ping-pong” data between buffers. These featuresareusefulforstructuringdataintoblocksforoptimalCPU processing.The interrupttrigger sourceforeach ofthesixDMA channelscan be configuredseparatelyand each channelcontainsitsown independentPIE interrupttonotifytheCPU when a DMA transferhas eitherstartedorcompleted.Fiveof the sixchannelsare exactlythe same, whileChannel 1 has one additionalfeature:the abilityto be configuredata higherprioritythantheothers.

2.4.5 C28x LocalPeripherals

The C28x localperipheralsincludean NMI Watchdog, threeTimers,fourSerialPortPeripherals(SCI, SPI,McBSP, I2C),an ExternalPeripheralInterface(EPI),and threetypesofControlPeripherals(ePWM, eQEP, eCAP). Allperipheralsare accessibleby theC28x CPU viatheC28x Memory Bus. Additionally, theMcBSP and ePWM areaccessibleby theC28x DMA Bus.The EPI peripheralisalsoaccessiblefrom theMasterSubsystem.The SerialPortPeripheralsand theControlPeripheralsconnecttoConcerto’s pins viatheGPIO_MUX1 block.Internally,theC28x peripheralsgenerateeventstothePIE block,C28x DMA, and theAnalog Subsystem.The C28x NMI Watchdog receivesa C28NMI eventfrom theNMI blockand sends a countertimeouteventtotheCortex™ -M3 NMI blockand theResets blocktoflaga potentially criticalcondition. The ePWM peripheralreceivesevents thatcan be used to tripthe ePWM outputsEPWMxA and EPWMxB. These eventsincludeECCDBLERR event from the C28x LocalMemory, PIENMIERR and EMUSTOP eventsfromtheC28x CPU, and up to12 tripsfromGPIO_MUX1. See Section6.3formore informationon C28x peripherals.

2.4.6 C28x LocalMemory

The C28x LocalMemory includesBoot ROM; Secure FlashwithErrorCorrectionCode (ECC); Secure L0/L1RAM withECC; L2/L3RAM withParityErrorChecking;and M0/M1 withECC. Alllocalmemories are accessiblefrom theC28x CPU; theL2/L3RAM isalsoaccessibleby theC28x DMA. Two typesof errorcorrectioneventscan be generatedduringaccess oftheC28x LocalMemory: uncorrectableerrors and singleerrors.The uncorrectableerrorspropagateto the NMI blockwhere they can become the C28NMI totheC28x NMI Watchdog and theC28NMIINT non-maskableinterrupttotheC28x CPU. The lesscriticalsingleerrorsgo to the PIE blockwhere theycan become maskable interruptsto the C28x CPU.

2.4.7 C28x Accessing Shared Resources and Analog Peripherals

There areseveralmemories,digitalperipherals,and analogperipheralsthatcan be accessedby boththe Master and ControlSubsystems. They are grouped intothe Shared Resources and the Analog Subsystem. The Shared Resources includetheExternalPeripheralInterface(EPI),Inter-ProcessorCommunications (IPC)registers,MTOC Message RAM, CTOM Message RAM, and eightindividuallyconfigurableShared RAM blocks. The Message RAMs and theShared RAMs can be accessedby theC28x CPU and DMA and have Parity- ErrorChecking.The MTOC Message RAM isintendedforsendingdatafromtheMasterSubsystem tothe ControlSubsystem, having r/w access for the Cortex™ -M3/µDMA and read-onlyaccess for the C28x/DMA. The CTOM Message RAM isintendedforsendingdata from the ControlSubsystem to the Master Subsystem, having r/w access for the C28x/DMA and read-onlyaccess for the Cortex™ - M3/µDMA.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 The IPC registersprovideup to 32 handshakingchannelsto coordinatetransferof data throughthe Message RAMs by polling.Four ofthesechannelsare alsobacked up by fourinterruptstoPIE on the ControlSubsystem side,and fourinterruptstotheNVIC on theMasterSubsystem side(toreducedelays associatedwithpolling). The eightShared RAM blocksare similartotheMessage RAMs, inthatthedataflowisonlyone way; however,thedirectionofthedataflowcan be individuallysetforeach blocktobe fromMastertoControl Subsystem orfromControltoMasterSubsystem. See Section6.1formore informationon sharedresourcesand analogperipherals.

2.5 Analog Subsystem

The AnalogSubsystem has ADC1, ADC2, and sixAnalogComparator+ DAC unitsthatcan be accessed viatheAnalogCommon InterfaceBus.The ADC ResultRegistersareaccessibleby CPUs and DMAs of the Master and ControlSubsystems.AllotherAnalog PeripheralRegistersare accessibleby the C28x CPU only.The C28x CPU accessestheACIB throughtheC28x Memory Bus,and theC28x DMA through the C28x DMA Bus. The ACIB arbitratesforaccess to ADC and Analog Comparator registersbetween CPU/DMA bus cyclesof the C28x Subsystem withthoseof the Cortex™ -M3 Subsystem.In additionto managing bus cycles,theACIB alsotransfersStart-Of-ConversiontriggerstotheAnalogSubsystem and returnsEnd-Of-ConversionADC interruptstoboththeMasterSubsystem and theControlSubsystem. Thereare22 possibleSOC (Start-Of-Conversion)sourcesfromtheC28x Subsystem thataremapped toa totalof8 possibleSOC triggersinsidetheAnalogSubsystem (toADC1 and ADC2). Going theotherway, eightEOC (End-Of-Conversion)sourcesfrom ADC1 and eightEOC sourcesfrom ADC2 are AND-ed togethertoform eightinterruptsgoingtodestinationsinboththeMasterand Control Subsystems.InsidetheC28x Subsystem,alleightEOC interruptsgo tothePIE,butonlyfourofthesame eightgo totheC28x DMA. The Concerto™ MCU Analog Subsystem has two independentAnalog-to-DigitalConverters(ADC1, ADC2); sixAnalog Comparators+ DAC units;and an Analog Common InterfaceBus (ACIB)tofacilitate analogdatacommunicationswithConcerto’s two digitalsubsystems(Cortex™ -M3 and C28x). Figure2-3shows theAnalogSubsystem.

2.5.1 ADC1

The ADC1 consistsofa 12-bitAnalog-to-Digitalconverterwithup to16 analoginputchannelsofwhich 10 are currentlypinnedout.The analogchannelsare internallypre-assignedto two Sample-and-Hold (S/H)unitsA and B, bothfeedingan AnalogMux whose outputisconvertedtoa 12-bitdigitalvalueand storedinADC1 resultregisters.The two S/H unitsenablesimultaneoussamplingoftwo analogsignalsat a time.Additionalchannels or channel pairsare convertedsequentially.Start-of-Conversion(SOC) triggersfrom the ControlSubsystem initiateanalog-to-digitalconversions.End-of-Conversion(EOC) interruptsfrom ADCs notifytheMasterand ControlSubsystems thattheconversionresultsare readyto be readfromADC1 resultregisters.See Section6.1.1formore informationon ADC peripherals.

2.5.2 ADC2

The ADC2 consistsofa 12-bitAnalog-to-Digitalconverterwithup to16 analoginputchannelsofwhich 10 arecurrentlypinnedout.The analogchannelsareinternallypreassignedtotwo Sample-and-Hold(S/H) unitsA and B, bothfeedingan AnalogMux whose outputisconvertedtoa 12-bitdigitalvalueand stored intheADC2 resultregisters.The two S/H unitsenablesimultaneoussamplingoftwo analogsignalsata time.Additionalchannelsorchannelpairsareconvertedsequentially.Start-of-Conversion(SOC) triggers from the ControlSubsystem initiateanalog-to-digitalconversions.End-of-Conversion(EOC) interrupts from ADCs notifythe Master and ControlSubsystems thatthe conversionresultsare ready to be read fromADC2 resultregisters.See Section6.1.1formore informationon ADC peripherals. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback

PRODUCT□PREVIEW GPIO_MUX2 MUX GPIO COMPOUT (6:1) COMPB2COMPA1 COMPA2 COMPA3 ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 MUXGPIO AIO_MUX2 10 MUXGPIO AIO_MUX1 10 EOC INTER- RUPTS (8:1) ADC ADC ANALOG COMMON INTERFACE BUS ADC1INT (8:1) ADC2INT (8:1) SOC TRIG- GERS (8:1) TRIGS (8:1) TRIGS (8:1) TIMER (3) XINT2 EPWM (9) TINT (2:0) XINT2 SOC (9:1) A SOC (9:1) B C28x CPU C28x DMA CPU uDMA C28 CPU BUS C28 DMA BUS uDMA BUS SYSTEM BUS ADCINT(8:1) ADCINT (4:1) CCIBST ATUS REG MCIBST ATUS REG ANALOG BUS ANALOG BUS COMPB5COMPA4 COMPA5 COMPA6 VDDA (3.3V) VSSA (0V) TRIG8SEL REG TRIG7SEL REG TRIG2SEL REG TRIG1SEL REG . . . COMPARATOR + DAC UNITS F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-3.Analog Subsystem

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.5.3 Analog Comparator + DAC

There are sixComparator blocksenablingsimultaneouscomparisonof multiplepairsof analoginputs, resultinginsixdigitalcomparisonoutputs.The externalanaloginputsthatare beingcompared inthe comparatorscome from AIO_MUX1 and AIO_MUX2 blocks.These analog inputscan be compared againsteach other or the outputsof 10-bitDACs (Digital-to-AnalogConverters)insideindividual Comparator modules. The sixcomparatoroutputsgo to the GPIO_MUX2 blockwhere they can be mapped tosixoutofeightavailablepins. Note thatinordertouse thesecomparatoroutputstotriptheC28x EPWMA/B outputs,theymust be first routedexternallyfrom pinsof the GPIO_MUX2 blockto selectedpinsof the GPIO_MUX1 blockbefore theycan be assignedtoselected12 ePWM TripInputs. See Section6.1.2formore informationon theanalogcomparator+ DAC.

2.5.4 Analog Common InterfaceBus (ACIB)

The ACIB linkstheMasterand ControlSubsystems withtheAnalog Subsystem.The ACIB enablesthe Cortex™ -M3 CPU/ µDMA and C28x CPU/DMA to access Analog Subsystem registers,to send SOC Triggersto the Analog Subsystem, and to receiveEOC Interruptsfrom the Analog Subsystem. The Cortex™ -M3 uses itsSystem Bus and theµDMA Bus toreadfromADC Resultregisters.The C28x uses itsMemory Bus and the DMA bus to access ADC Resultregistersand otherregistersof the Analog Subsystem.The ACIB arbitratesbetween up tofourpossiblysimultaneouslyoccurringbus cycleson the Master/ControlSubsystem sideof ACIB to access the ADC and Analog Comparator registerson the AnalogSubsystem side. Additionally,ACIB maps up to 22 SOC triggersourcesfrom the ControlSubsystem to 8 SOC trigger destinationsinsidetheAnalog Subsystem (sharedbetween ADC1 and ADC2), and up to16 ADC EOC interruptsourcesfromtheAnalogSubsystem to8 destinationsinsidetheMasterand ControlSubsystems. The eightADC interruptsare the resultof AND-ing of eightEOC interruptsfrom ADC1 with8 EOC interruptsfromADC2. The totalof16 possibleADC1 and ADC2 interruptsaresharingthe8 interruptlines because itisunlikelythatany applicationwouldneed all16 interruptsatthesame time. Eightregisters(TRIG1SEL –TRIG8SEL) configureeightcorrespondingSOC triggersto assign1 of 22 possibletriggersourcestoeach SOC trigger. There are two registersthatprovidestatusof ACIB to the Master Subsystem and to the Control Subsystem. The Cortex™ -M3 can read the MCIBSTATUS registerto verifythatthe Analog Subsystem isproperly powered up; the Analog System Clock (ASYSCLK) ispresent;and thatthe bus cycles,triggers,and interruptsarecorrectlypropagatingbetween theMaster,Control,and Analogsubsystems. The C28x can read theCCIBSTATUS registertoverifythattheAnalog Subsystem isproperlypowered up;theAnalogSystem Clock(ASYSCLK) ispresent;and thatthebus cycles,triggers,and interruptsare correctlypropagatingbetween theMaster,Control,and Analogsubsystems. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.6 Master Subsystem NMIs

The Cortex™ -M3 NMI Blockgeneratesan M3NMIINT non-maskableinterruptto the Cortex™ -M3 CPU and an M3NMI eventtotheNMI Watchdog inresponsetopotentiallycriticalconditionsexistinginsideor outsidethe Concerto™ MCU. When ableto respond to the M3NMIINT interrupt,the Cortex™ -M3 CPU may addresstheNMI conditionand disabletheNMI Watchdog.Otherwise,theNMI Watchdog countsout and an M3NMIRST resetsignalissenttotheResetsblock. The inputstotheCortex™ -M3 NMI blockincludetheC28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR, VREGWARN, EXTGPIO, MLBISTERR, and CLBISTERR signals.The C28NMIRST comes fromtheC28x NMI Watchdog; C28NMIRST indicatesthatthe C28x was not ableto preventthe C28x NMI Watchdog counterfrom countingout.PIENMIERR indicatesthatan errorconditionwas generatedduringthe NMI vectorfetchfromtheC28x PeripheralInterruptExpansion(PIE)block.The CLOCKFAIL inputcomes from theMasterClocksBlock,announcinga missingclocksourcetotheMain Oscillator.ACIBERR indicates an abnormalconditioninsidetheAnalogCommon InterfaceBus.The VREGWARN inputcommunicatesa power anomaly. EXTGPIO comes from the GPIO_MUX1 to announce an externalemergency. MLBISTERR isgeneratedby theCortex™ -M3 coretosignalthata BIST time-outor signaturemismatch errorhas been detected.CLBISTERR isgeneratedby the C28x core to signalthata BIST time-outor signaturemismatcherrorhas been detected. The Cortex™ -M3 NMI blockcan be accessedviatheCortex™ -M3 NMI configurationregisters— including the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers— to examine flagbitsforthe NMI sources, cleartheflags,and forcetheflagstoactivestate,respectively. Figure2-4shows theCortex™ -M3 NMI and C28x NMI.

2.7 ControlSubsystem NMIs

The C28x NMI Blockgeneratesa C28NMIINT non-maskableinterrupttotheC28x CPU and a C28NMI event to the C28x NMI Watchdog in response to potentiallycriticalconditionsexistinginsidethe Concerto™ MCU. When abletorespondtotheC28NMIINT interrupt,theC28x CPU may addresstheNMI conditionand disabletheC28x NMI Watchdog. Otherwise,theC28x NMI Watchdog countsoutand the C28NMIRST resetsignalissenttotheResetsblockand theCortex™ -M3 NMI Block,where theCortex™ - M3 NMI Blockcan generatean NMI totheCortex™ -M3 processor. The inputstotheC28x NMI blockincludetheCLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR, PIENMIERR, CLBISTERR, and MLBISTERR signals.The CLOCKFAIL inputcomes from the Clocks Block,announcing a missingclocksource to the Main Oscillator.ACIBERR indicatesan abnormal conditioninsidetheAnalogCommon InterfaceBus.The RAMUCERR and FLASHUNCERR announce the occurrenceof uncorrectableerrorconditionsduringaccess to the Flash or RAM (localor shared). PIENMIERR indicatesthatan errorconditionwas generatedduringNMI vectorfetchfrom the C28x PeripheralInterruptExpansion(PIE)block.MLBISTERR isgeneratedby theCortex™ -M3 coretosignal thata BIST time-outor signaturemismatch errorhas been detected.CLBISTERR isgeneratedby the C28x coretosignalthata BIST time-outorsignaturemismatcherrorhas been detected. The C28x NMI blockcan be accessedviatheC28x NMI configurationregisters— includingtheCNMIFLG, CNMIFLGCLR, and CNMIFLGFRC registers— to examine flagbitsforthe NMI sources,clearthe flags, and forcetheflagstoactivestate,respectively. Figure2-4shows theCortex™ -M3 NMI and C28x NMI.

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PRODUCT□PREVIEW M3 NMI C28x NMI M3 CPU C28x CPU GPIO_MUX ANALOG SUBSYSTEM CLOCKS SHARED RAM C28x LOCAL RAM C28x FLASH 1.2V VREG C28x NMI WDOG RESETS M3 NMI WDOG CLOCKFAIL M3EXTNMI RAMUNCERR C28NMI PIENMIERR M3NMI ACIBERR M3NMIRST VREGWARN M3NMIINT C28NMIINT C28NMIRST NMI C28NMIRSTC28NMI M3NMIRSTM3NMI FLASHUNCERR M3 WDOG (2) M3WDRST (1:0) M3WDRST (1:0) C28NMIRST BIST C28x BIST M3BISTERR C28BISTERR C28BISTERR M3BISTERR M3BISTERR C28BISTERR F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure2-4.Cortex™ -M3 NMI and C28x NMI Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 37 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.8 Resets

The Concerto™ MCU has two externalresetpins:XRS fortheMasterand ControlSubsystems,and ARS forthe Analog Subsystem.TI recommends thatthesetwo pinsbe externallytiedtogetherwitha board signaltrace. The XRS pincan receivean externalresetsignalfromoutsideintothechip,and thepincan drivea reset signalout from insideof the chip.A resetpulsedrivenintotheXRS pinresetsthe Master and Control Subsystems.A resetpulsecan alsobe drivenoutoftheXRS pinby thevoltagemonitoringblockofthe Masterand ControlSubsystems (seeSection2.9).A resetpulsecan be drivenoutoftheXRS pinwhen thetwo Cortex™ -M3 Watchdogs ortheCortex™ -M3 NMI Watchdog timeout. Therearesome requirementson theXRS pin: 1. Duringpower up,theXRS pinmust be heldlowforatleasteightX1 cyclesaftertheinputclockis stable.Thisrequirementistoenabletheentiredevicetostartfroma known condition. 2. Duringpower down, theXRS pinmust be pulledlowatleast8 µs priortoVDDIO reaching1.5V.This requirementistoenhance Flashreliability. 3. TIrecommends thatno voltagelargerthan0.7V be appliedtoany pinpriortopoweringup thedevice. Voltagesappliedtopinson an unpowered devicecan leadtounpredictableresults. The ARS pincan receivean externalresetsignalfromoutsideintothechip,and thepincan drivea reset signaloutfrominsideofthechip.A resetpulsedrivenintotheARS pinresetstheAnalogSubsystem.A resetpulsecan be drivenoutoftheARS pinby thevoltagemonitoringblockoftheAnalogSubsystem. Figure2-5shows theresets.

2.8.1 Cortex™ -M3 Resets

The Cortex™ -M3 CPU and NVIC (Nested VectoredInterruptController)are both resetby the POR (Power-On Reset)ortheM3SYSRST resetsignal.Inbothcases,theCortex™ -M3 CPU restartsprogram executionfrom the address providedby the resetentryin the vectortable.A registercan laterbe referencedtodeterminethesourceofthereset.The M3SYSRST signalalsopropagatestotheCortex™ - M3 peripheralsand therestoftheCortex™ -M3 Subsystem. The M3SYSRST has fourpossiblesources:XRS, M3WDOGS, M3SWRST, and M3DBGRST. The M3WDOGS issetinresponsetotime-outconditionsofthetwo Cortex™ -M3 Watchdogs ortheCortex™ - M3 NMI Watchdog.The M3SWRST isa software-generatedresetoutputby theNVIC. The M3DBGRS is a debugger-generatedresetthatisalsooutputby theNVIC. InadditiontodrivingM3SYSRST, thesetwo resetsalsopropagatetotheC28x Subsystem and theAnalogSubsystem. The M3RSNIN bitcan be setinsidetheCRESCNF registertoselectivelyresettheC28x Subsystem from theCortex™ -M3, and ACIBRST bitofthesame registerselectivelyresetstheAnalog Common Interface Bus. In additionto drivingresetsignalsto otherpartsof the chip,the Cortex™ -M3 can alsodetecta C28SYSRST resetbeing set insidethe C28x Subsystem by readingthe CRES bitof the CRESSTS register. Cortex™ -M3 softwarecan alsosetbitsintheSRCR registertoselectivelyresetindividualCortex™ -M3 peripherals,providedtheyare enabledinsidethe DC (DeviceConfiguration)register.The Reset Cause register(MRESC) can be read to findout ifthe latestreset was caused by ExternalReset, VMON/POR/BOR, Watchdog Timer0,Watchdog Timer1,orSoftwareResetfromNVIC.

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PRODUCT□PREVIEW ARS PIN NMI WDOG SUBSYSTEM CPU NVIC M3 WDOG (0) M3 WDOG (1) M3DBGRST M3SWRST SHARED RESOURCES ANALOG SUBSYSTEM C28x NMI WDOG C28x CPU C28x SUBSYSTEM M3SYSRST ‘0’ DEGLITCH SYNC M3WDOGS XRS PIN M3SSCLK ARS PIN DC REG POR XRS XRS XRS ACIBRST SRXRST M3SYSRST M3PORRST C28RSTIN POR C28SYSRST RESET INPUT SIGNAL ST ATUS XRS( SETS DEFAULT VALUES ) VOLTAGE REGULATION AND MONITORING FLASH PUMP XRS CRESCNF REG DEVICECNF REG CRESSTS REG C28SYSRST C28NMIWD M3WDOGS ACIBRSTM3RSNIN SOFTWARE JT AG CONTROLLER MRESC REG CONTAINS RESET CAUSES PERIPHERAL SOFTWARE RESETS ACIBRST SRCR REG GLOBAL PERIPHERAL ENABLES XRS GPIO_MUX C28x BIST M3 BIST MLBISTRST CLBISTRST F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure2-5.Resets Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 39 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.8.2 C28x Resets

The C28x CPU isresetby theC28RSTIN signal,and theC28x CPU inturnresetstherestoftheC28x Subsystem withthe C28SYSRST signal.When reset,the C28x restartsprogram executionfrom the addressprovidedatthetopoftheBootROM VectorTable. The C28RSTIN has fivepossiblesources:XRS, C28NMIWD, M3SWRST, M3DBGRST, and the M3RSNIN. The C28NMIWD issetinresponseto time-outconditionsof the C28x NMI Watchdog. The M3SWRST isa software-generatedresetoutputby theNVIC. The M3DBGRS isa debugger-generated resetthatis also outputby the NVIC. These two resetsmust be firstenabled by the Cortex™ -M3 processorinorderto propagateto the C28x Subsystem.M3RSNIN resetcomes from the Cortex™ -M3 Subsystem toselectivelyresettheC28x Subsystem fromCortex™ -M3 software. The C28x processorcan learnthestatusoftheinternalACIBRST resetsignaland theexternalXRS pin by readingtheDEVICECNF register.

2.8.3 Analog Subsystem and Shared Resources Resets

Both theAnalog Subsystem and theresourcessharedbetween theC28x and Cortex™ -M3 subsystems (IPC, MSG RAM, Shared RAM) are resetby the SRXRST resetsignal.Additionally,the Analog Subsystem is also resetby the internalACIBRST signalfrom the Cortex™ -M3 Subsystem and the externalARS pin(whichshouldbe externallytiedtotheXRS pin). The SRXRST has threepossiblesources:XRS, M3SWRST, and M3DBGRST. The M3SWRST is a software-generatedresetoutputby theNVIC. The M3DBGRS isa debugger-generatedresetthatisalso outputby the NVIC. These two resetsmust be firstenabledby the Cortex™ -M3 processorinorderto propagatetotheAnalogSubsystem and theShared Resources. AlthoughEPI isa sharedperipheral,itisphysicallylocatedinsidetheCortex™ -M3 Subsystem;therefore, EPI isresetby M3SYSRST.

2.8.4 Device Boot Sequence

Concerto’s boot sequence isused to configurethe Master Subsystem and the ControlSubsystem for executionofapplicationcode.The bootsequence involvesbothinternalresources,and resourcesexternal to the device.These resourcesinclude:Master Subsystem Bootloadercode (M-Bootloader)factory- programmed insidetheMasterSubsystem BootROM (M-BootROM); ControlSubsystem Bootloadercode (C-Bootloader)factory-programmedinsidethe ControlSubsystem Boot ROM (C-Boot ROM); four GPIO_MUX pins forMaster boot mode selection;internalFlash and RAM memories; and selected Cortex™ -M3 and C28x peripheralsfor loadingthe applicationcode intothe Master and Control Subsystems. The boot sequence startswhen the Master Subsystem comes out of reset,which can be caused by device power up, externalreset,debugger reset,softwarereset,Cortex™ -M3 watchdog reset,or Cortex™ -M3 NMI watchdog reset.WhiletheM-Bootloaderstartsexecutingfirst,theC-Bootloaderstarts soon after,and thenbothbootloaderswork intandem toconfigurethedevice,loadapplicationcode for bothprocessors(ifnotalreadyintheFlash),and branchtheexecutionofeach processortoa selected locationintheapplicationcode. Executionof the M-Bootloadercommences when an internalresetsignalgoes from activeto inactive state.At thattime,theControlSubsystem and theAnalog Subsystem continuetobe inresetstateuntil the Master Subsystem takes them out of reset.The M-Bootloaderfirstinitializessome device-level functions,then the M-Bootloaderinitializesthe Master Subsystem. Next,the M-Bootloadertakes the ControlSubsystem and theAnalogSubsystem/ACIBoutofreset.When theControlSubsystem comes out of reset,itsown C-Bootloaderstartsexecutingin parallelwiththe M-Bootloader.Afterinitializingthe ControlSubsystem,the C-Bootloaderentersthe C28x processorintothe idlemode (towaitforthe M- Bootloaderto wake up the C28x processorlaterviathe MTOCIPC1 interrupt).Next,the M-Bootloader reads fourGPIO pins(see Table 2-17) to determinethe boot mode forthe restof the M-Bootloader operation.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-17.Master Subsystem Boot Mode Selection PF2_GPIO34 PF3_GPIO35 PG7_GPIO47 PG3_GPIO43Boot Mode No. Master Subsystem Boot Modes (BOOT_3) (1) (BOOT_2) (1) (BOOT_1) (1) (BOOT_0) (1) 0(2) BootfromParallelGPIO 0 0 0 0 1(2) BoottoMasterSubsystem RAM 0 0 0 1 BootfromMasterSubsystem serial2(2) 0 0 1 0peripherals(UART0/SSI0/I2C0) 3(2) BootfromMasterSubsystem CAN interface 0 0 1 1 BootfromMasterSubsystem Ethernet4(2) 0 1 0 0interface Not supported(DefaultstoBoot-to-Flash),5(2) 0 1 0 1futurebootfromCortex™ -M3 USB 6(2) Not supported(DefaultstoBoot-to-Flash) 0 1 1 0 7(2) BoottoMasterSubsystem Flashmemory 0 1 1 1 8(3) Not supported(DefaultstoBoot-to-Flash) 1 0 0 0 BootfromMasterSubsystem serial9(3) 1 0 0 1peripheral– SSI0 Master BootfromMasterSubsystem serial10(3) 1 0 1 0peripheral– I2C0 Master 11(3) Not supported(DefaultstoBoot-to-Flash) 1 0 1 1 12(3) Not supported(DefaultstoBoot-to-Flash) 1 1 0 0 13(3) Not supported(DefaultstoBoot-to-Flash) 1 1 0 1 14(3) Not supported(DefaultstoBoot-to-Flash) 1 1 1 0 15(3)(4)(5) BoottoMasterSubsystem Flashmemory 1 1 1 1 (1) By default,GPIO terminalsarenotpulledup (theyarefloating). (2) BootModes 0–7 arepin-compatiblewithfuturemembers oftheConcertofamily(theyuse same GPIO terminals). (3) BootModes 8–15 arenotsupportedon siliconrevision0. (4) ThisBootMode uses a fasterFlashpower-upsequence.The maximum supportedOSCCLK frequencyforthismode is30 MHz. (5) ThisBootMode isthesame as BootMode 7,butinFastMode. Boot Mode 7 and Boot Mode 15 cause theMasterprogram tobranchexecutiontotheapplicationinthe MasterFlashmemory. ThisbranchingrequiresthattheMasterFlashbe alreadyprogrammed withvalid code;otherwise,a hard faultexceptionisgeneratedand theCortex™ -M3 goes back totheabove reset sequence.(Therefore,fora factory-freshdevice,theM-Bootloaderwillbe ina continuousresetloopuntil theemulatorisconnectedand a debug sessionstarted.)IftheMasterSubsystem Flashhas alreadybeen programmed, theapplicationcode willstartexecution.Typically,theMasterSubsystem applicationcode willthen establishdata communicationwiththe C28x [throughthe IPC (InterprocessorCommunications peripheral)]tocoordinatetherestofthebootprocesswiththeControlSubsystem.Boot Mode 15 (Fast Boot toFlashMode) supportedon thisdeviceisa specialboottoFlashmode, whichconfiguresFlashfor a fasterpower up,thussavingsome boottime.Boot Mode 7 and othermodes whichdefaulttoFlashdo notconfigureFlashfora fasterpower up likeBoot Mode 15 does.Note thatfollowingreset,theinternal pullupresistorson GPIOs are disabled.Therefore,Boot Mode 15,forexample,willtypicallyrequirefour externalpullups. Boot Mode 1 causes the Master boot program to branch to Cortex™ -M3 RAM, where the Cortex™ -M3 processorstartsexecutingcode thathas been preloadedearlier.Typically,thismode isused during developmentofapplicationcode meant forFlash,butwhichhas tobe firsttestedrunningoutofRAM. In thiscase,theuserwould typicallyloadtheapplicationcode intoRAM usingthedebugger,and thenissue a debugger reset,whilesettingthe fourboot pinsto 0001b. From thatpointon, the restof the boot processon theMasterSubsystem sideiscontrolledby theapplicationcode. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 41 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master applicationcode from an external peripheralbeforebranchingto the applicationcode.Thisprocessisdifferentfrom the processinBoot Modes 1,7,and 15,where theapplicationcode was eitheralreadyprogrammed inFlashor loadedinto RAM by theemulator.Ifthebootmode selectionpinsaresetto0000b,theM-Bootloader(runningoutof M-Boot ROM) willstartuploadingtheMasterapplicationcode frompreselectedParallelGPIO_MUX pins. Ifthebootpinsaresetto0010b,theapplicationcode willbe loadedfromtheMasterSubsystem UART0, SSI0,orI2C0 peripheral.(SSI0and I2C0 areconfiguredtowork inSlavemode inthisBoot Mode.)Ifthe bootpinsaresetto0011b,theapplicationcode willbe loadedfromtheMasterSubsystem CAN interface. Furthermore,ifthe boot pinsare setto 0100b, the applicationcode willbe loadedthroughthe Master Subsystem Ethernetinterface;theIOs used inthisBoot Mode arecompatiblewiththeF28M35x device.If thebootpinsaresetto1001b or1010b,thentheapplicationcode willbe loadedthroughtheSSI0 orI2C0 interface,respectively.SSI0 and I2C0 loaderswork inMasterMode inthisbootmode. Ifthebootpinsare setto1100b,thentheapplicationcode willbe loadedthroughtheMasterSubsystem Ethernetinterface; theIOs used inthisBootMode areF28M35x IOs,whichareavailableonlyina BGA package. Regardlessof the typeof boot mode selected,once the Master applicationcode isresidentinMaster FlashorRAM, thenextstepfortheM-BootloaderistobranchtoMasterFlashorRAM. At thatpoint,the applicationcode takesovercontrolfromtheM-Bootloader,and thebootprocesscontinuesas prescribed by theapplicationcode.At thisstage,theMasterapplicationprogram typicallyestablishescommunication withtheC-Bootloader,whichby now, would have alreadyinitializedtheControlSubsystem and forcedthe C28x to go intoIdlemode. To wake the ControlSubsystem out of Idlemode, the Master application issuesthe Master-to-Control-IPC-interrupt1 (MTOCIPCINT1). Once the data communicationhas been establishedthroughtheIPC,thebootprocesscan now alsocontinueon theControlSubsystem side. The restoftheControlSubsystem bootprocessiscontrolledby theMasterSubsystem applicationissuing IPC instructionsto the ControlSubsystem, withthe C-Bootloaderinterpretingthe IPC commands and actingon them tocontinuethebootprocess.At thisstage,a bootmode fortheControlSubsystem can be established.The ControlSubsystem bootmodes aresimilartotheMasterSubsystem bootmodes, except forthemechanism by which theyare selected.The ControlSubsystem bootmodes are chosen through theIPC commands fromtheMasterapplicationcode totheC-Bootloader,whichinterpretsthem and acts accordingly.The choicesare,as above,tobranchtoalreadyexistingControlapplicationcode inFlash,to branch to preloadedcode inRAM (developmentmode), or to uploadthe Controlapplicationcode from one ofseveralavailableperipherals(seeTable2-18).As before,once theControlapplicationcode isin place (inFlash or RAM), the C-Bootloaderbranches to Flash or RAM, and from thatpointon, the applicationcode takesover. Table2-18.ControlSubsystem Boot Mode Selection ControlSubsystem MTOCIPCBOOTMODE DescriptionBoot Modes RegisterValue Upon receivingthiscommand fromtheMasterSubsystem,C-Boot BOOT_FROM_RAM 0x0000 0001 ROM willbranchtotheControlSubsystem RAM entrypointlocation and startexecutingcode fromthere. Upon receivingthiscommand, C-BootROM willbranchtothe BOOT_FROM_FLASH 0x0000 0002 ControlSubsystem FLASH entrypointand startexecutingcode from there. Upon receivingthiscommand, C-BootROM willbootfromtheBOOT_FROM_SCI 0x0000 0003 ControlSubsystem SCI peripheral. Upon receivingthiscommand, C-BootROM willbootfromtheBOOT_FROM_SPI 0x0000 0004 ControlSubsystem SPI interface. Upon receivingthiscommand, C-BootROM willbootfromtheBOOT_FROM_I2C 0x0000 0005 ControlSubsystem I2C interface. Upon receivingthiscommand, C-BootROM willbootfromtheBOOT_FROM_PARALLEL 0x0000 0006 ControlSubsystem GPIO.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 The bootprocesscan be consideredcompletedonce theCortex™ -M3 and C28x arebothrunningoutof theirrespectiveapplicationprograms.Note thatfollowingthe boot sequence,the C-Bootloaderisstill availabletointerpretand actupon an assortmentofIPC commands thatcan be issuedfrom theMaster Subsystem to performa varietyof configuration,housekeeping,and otherfunctions.See the Concerto F28M35x TechnicalReference Manual (literaturenumber SPRUH22 ) for additionalinformationon Concertobootmodes, IPC commands, and theunderlyingbootphilosophy.

2.9 InternalVoltageRegulationand Monitoring

WhileConcerto’s analogfunctionsdraw power from a singlededicatedexternalpower source— VDDA ,its digitalcircuitsarepowered by threeseparaterails:3.3-VVDDIO ,1.8-VVDD18 ,and 1.2-VVDD12 .Thissection describesthesourcing,regulation,monitoring,and otherconsiderationsforthesethreedigitalpower rails. Concertodevicescan be internallydividedintoan AnalogSubsystem and a DigitalSubsystem (havingthe Cortex™ -M3-based MasterSubsystem and theC28x-based ControlSubsystem).The DigitalSubsystem uses VDD12 topower thetwo processors,internalmemory, and peripherals.The Analog Subsystem uses VDD18 topower thedigitallogicassociatedwiththeanalogfunctions.Both Digitaland AnalogSubsystems share a common VDDIO railto power their3.3-V I/O buffersthroughwhich Concerto’s digitalsignals communicatewiththeoutsideworld. The Analog and DigitalSubsystems each have theirown power regulationand monitoringfunctionsthat operate independently,but which can— when the ARS and XRS reset pins are externallytied together— simultaneouslyresettheentireConcertodevicewhen power lossisimminent.See Figure2-6 fora snapshotofthedigitalpower regulationand monitoringfunctionsprovidedwithinConcerto’s Analog and DigitalSubsystems.

2.9.1 Analog Subsystem VoltageRegulationand Monitoring

The Analog Subsystem internallyprovidesvoltageregulationand monitoringfunctions.Internalvoltage monitoringfeaturesconsistof the Power-On Reset (POR) functionthatholdsthe deviceinresetstate duringpower up,and theBrown-OutReset(BOR) functionsthatresetthedevicejustbeforetheVDDIO and VDD18 power railsdiporVDD18 spikesoutsideofoperationalvoltagerange. 2.9.1.1 Analog Subsystem ’s Internal1.8-VVREG The internal1.8-VVoltageRegulator(VREG) generatesVDD18 power from VDDIO . The 1.8-VVREG is enabledby pullingtheVREG18EN pintoa low state.When enabled,the1.8-VVREG provides1.8V to digitallogicassociatedwiththeanalogfunctionsoftheAnalogSubsystem. When the internal1.8-V VREG functionis enabled,the 1.8 V power no longerhas to be provided externally;however,a 1.2-µF capacitorisrequiredforeach VDD18 pintostabilizetheinternallygenerated voltages.These loadcapacitorsare notrequirediftheinternal1.8-VVREG isdisabled,and the1.8V is providedfroman externalsupply. Note thatthe same VREG18EN pinthatenablesthe internal1.8-VVREG alsoenablesthe 1.8-VBOR functionoftheAnalog Subsystem.Alsonotethatwhileremovingtheneed foran externalpower supply, enablingtheinternalVREG willincreasetheVDDIO power consumption. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 43 SubmitDocumentationFeedback

PRODUCT□PREVIEW PIN ‘0’ DE-GLITCH XRS RESETS VOLTAGE MONITORING (DIGITAL SUBSYSTEM) NVIC M3 WDOGS (0,1) DIGITAL LOGIC (DIGITAL SUBSYSTEM) 1.2V VREG (DIGITAL SUBSYSTEM) ‘0’ DE-GLITCH ARS 1.8V VREG (ANALOG SUBSYSTEM) XRS PIN ARS 1.2V SUPPLY PINS 3.3V SUPPLY PINS 1.8V SUPPLY PINS DIGITAL LOGIC (ANALOG SUBSYSTEM) 1.8V 1.2V 3.3V VREG12EN PIN VREG18EN PIN CONCERTO DEVICE ANALOG SUBSYSTEM GPIOS DIGITAL SUBSYSTEM GPIOS CONNECT THE 2 RESET PINS EXTERNALLY THROUGH A BOARD TRACE 1.8V 1.2V 1.8V 1.2V I/OI/O 3.3V 3.3V TRIST ATETRIST ATE VMON 3.3V POR 3.3V BOR 1.8V BOR VOLTAGE MONITORING (ANALOG SUBSYSTEM) 1.2V BOW M3WDOGS POR VREGWARN NMI 1.2V POR 3.3V POR CHECKS FOR HI/LOW CHECKS FOR LOW CRESCNF REG ACIBRST CONTROL SUB- SYSTEM M3RSNIN CHECKS FOR HI/LOW M3 NMI M3 NMI WDOG M3 CPU RST F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-6.VoltageRegulationand Monitoring

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.9.1.2 Analog Subsystem ’s VoltageMonitoring

The VoltageMonitoringBlockoftheAnalogSubsystem consistsofthePOR functionand BOR functions. POR holdsthedeviceinresetduringpower up,untilpower stabilizesand voltagelevelsreachoperational range.Once thedeviceisproperlypowered up,theBOR functionssearchforpower dipsand spikes,and assertARS when voltagelevelsventureoutsideofoperationalrange. 2.9.1.2.1Analog Subsystem ’s POR POR keeps theARS resetsignalassertedduringdevicepower up,and deassertsthesignalonlywhen the 3.3-Vpower railreachesoperationalvoltagelevel.While inmost applications,the POR-generated resethas a longenough durationtoalsoresetothersystem ICs,some applicationsmay requirea longer- lastingresetpulse.In these cases,the ARS resetpin (whichisopen-drain)can alsobe drivenfrom outsidein,tomatch thetimethedeviceisheldinresetstatewiththerestofthesystem. When POR (orBOR) drivestheARS pinlow,POR (orBOR) alsoresetsthedigitallogicassociatedwith analogfunctions,and putstheGPIO pinsoftheAnalog Subsystem General-PurposeIO blockina high- impedance state. 2.9.1.2.2Analog Subsystem ’s BOR The AnalogSubsystem has two BOR functionsthatassertARS when VDDIO orVDD18 dipsbelow minimum voltagelevels,or when VDD18 surgesabove themaximum operationalvoltage.The internal1.8-VVREG must be enabledtoactivatetheVDD18 BOR function(bypullingtheVREG18EN pinlow). When BOR (orPOR) drivestheARS pinlow,BOR (orPOR) alsoresetsthedigitallogicassociatedwith analogfunctions,and putstheGPIO pinsoftheAnalog Subsystem General-PurposeIO blockina high- impedance state.

2.9.2 DigitalSubsystem VoltageRegulationand Monitoring

The internalvoltagemonitoringfeaturesoftheDigitalSubsystem consistofthePOR functionthatholds thedeviceinresetstateduringpower up,and theBOW (Brown-OutWarning)functionthatissuesa non- maskable interrupt(NMI) to warn the devicebeforeimpendingpower losson the VDD12 rail.The NMI allowssoftwareto safelyshutdown the deviceand forthe resetof the system beforepower fallsinto regionsoutsideofspecification,and potentiallycausingunexpectedorerroneoussystembehavior. 2.9.2.1 DigitalSubsystem ’s Internal1.2-VVREG The internal1.2-VVREG generatesVDD12 power from VDDIO .The 1.2-VVREG isenabledby pullingthe VREG12EN pintoa low state.When enabled,the1.2-VVREG internallyprovides1.2V todigitallogic associatedwiththeprocessors,memory, and peripheralsoftheDigitalSubsystem. When the internal1.2-V VREG functionis enabled,the 1.2 V power no longerhas to be provided externally;however,a 492-nF capacitorisrequiredforeach VDD12 pintostabilizetheinternallygenerated voltages.These loadcapacitorsare notrequirediftheinternal1.2-VVREG isdisabledand the1.2V is providedfroman externalsupply. Note thatwhileremovingtheneed foran externalpower supply,enablingtheinternalVREG willincrease theVDDIO power consumption.

2.9.2.2 DigitalSubsystem ’s VoltageMonitoring

The VoltageMonitoringBlockoftheDigitalSubsystem consistsofPOR functionsand a BOW function. POR functionsholdthedeviceinresetduringpower up,untilpower stabilizesand voltagelevelsreach operationalrange.Once the deviceisproperlypowered up, the BOW functionsearchesfordipsand spikeson the1.2-Vrail,and assertsVREGWARN NMI when voltagelevelsventureoutsideofminimum or maximum values. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 45 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com 2.9.2.2.1DigitalSubsystem ’s POR POR keeps theXRS resetsignalassertedduringdevicepower up,and deassertsthesignalonlywhen the1.2-Vand 3.3-Vpower railsreachoperationalrange.Whileinmost applications,thePOR-generated resethas a longenough durationtoalsoresetothersystem ICs,some applicationsmay requirea longer- lastingsystem resetpulse.In thesecases,theXRS resetpin(whichisopen-drain)can alsobe driven fromoutsidein,tomatch thetimethedeviceisheldinresetstatewiththerestofthesystem. When POR drivestheXRS pinlow,POR alsoresetsalldigitallogicoftheDigitalSubsystem,and putsthe GPIO pinsoftheDigitalSubsystem General-PurposeIO blockina high-impendancestate. InadditiontothePOR reset,theDigitalSubsystem’s ResetsblockalsoreceivesresetinputsfromNVIC, theCortex™ -M3 Watchdogs (0,1),and fromtheCortex™ -M3 NMI Watchdog.The resultingresetoutput signalisthenfedback totheXRS pinafterbeingANDed withthePOR reset(seeFigure2-6). On a relatednote,onlytheMasterSubsystem comes outofresetstateimmediatelyfollowingthedevice power up.The Controland Analog Subsystems continuetobe heldinresetuntiltheMasterProcessor (Cortex™ -M3) bringsthem out of resetby writinga "1" to the M3RSNIN and ACIBRST bitsof the CRESCNF Register(seeFigure2-6). 2.9.2.2.2DigitalSubsystem ’s BOW The DigitalSubsystem has a BOW functionthatcan send a VREGWARN NMI (Non-MaskableInterrupt) to the Cortex™ -M3 NMI blockwhen VDD12 startsdriftingoutsideof operationalrange.The NMI block simultaneouslysends the M3NMIINT to the Cortex™ -M3 NVIC/CPU and startsthe counterinsidethe Cortex™ -M3 NMI Watchdog. While the NMI Watchdog iscountingdown, the Cortex™ -M3 CPU can attemptto safelyshutdown the deviceand the system.When the count reaches "0",the NMI Watchdog assertsa resetinputto the Resets block,forcingthe entireDigitalSubsystem to go intoa resetstate,includingthe CRESCNF register,whichby defaultalsoresetstheAnalogand ControlSubsystems. By default,theBOW functionisdisabledafterreset.

2.9.3 Connecting ARS and XRS Pins

Inmost Concertoapplications,TI recommends thattheARS and XRS pinsbe tiedtogetherby external means — such as througha signaltraceon a PCB board.Tying the ARS and XRS pinsenablesthe internalBOR functionsof the Analog Subsystem to alsoresetthe DigitalSubsystem duringinternally detectedpower brown-outconditions.TyingtheARS and XRS pinsalsoensuresthatotherresetsources willcause boththeAnalog and DigitalSubsystems toentertheresetstatetogether,regardlessofwhere theresetconditionoccurs.

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PRODUCT□PREVIEW X1 X2 CONCERTO DEVICE CRYST AL X1 X2 CONCERTO DEVICE X1 X2 CONCERTO DEVICE 3.3V OUTVDD GND CLK R D C L2 C L1 RESONATOR 3.3V OSCILLATOR NC vssosc XCLKIN CONCERTO DEVICE 3.3V OUTVDD GND CLK 3.3V OSCILLATOR vssosc vssosc NC F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.10 InputClocks and PLLs

Concertodeviceshave multipleinputclockpinsfrom which allinternalclocksand the outputclockare derived.Figure2-7 shows therecommended methods ofconnectingcrystals,resonators,and oscillators topinsX1/X2 and XCLKIN. Figure2-7.Connecting InputClocks toa Concerto Device

2.10.1 InternalOscillator(Zero-Pin)

Each Concertodevicecontainsa zero-pininternaloscillator.Thisoscillatoroutputstwo fixed-frequency clocks:10MHZCLK and 32MHZCLK. These clocksarenotconfigurableby theuser.They areused inside theMasterSubsystem toimplementlow-powermodes. The 10MHZCLK isalsoused by theMissingClock Detectcircuit. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 47 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.10.2 CrystalOscillator/Resonator(PinsX1/X2 and VSSOSC )

The main oscillatorcircuitconnectstoan externalcrystalthroughpinsX1 and X2. Ifa resonatorisused (versionof a crystalwithbuilt-inload capacitors),itsground terminalshouldbe connectedto the pin VSSOSC (notboard ground).The VSSOSC pinshouldalsobe used toground theexternalloadcapacitors connectedtothetwo crystalterminalsas shown inFigure2-7.

2.10.3 ExternalOscillators(PinsX1 and XCLKIN)

Concertohas two pins(X1 and XCLKIN) intowhich a single-endedclockcan be drivenfrom external oscillatorsorotherclocksources.When connectingan externalclocksourcethroughtheX1 terminal,the X2 terminalshouldbe leftunconnected.Most internalclocksofthisdevicearederivedfromtheX1 clock input(orX1/X2 crystal).The XCLKIN clockisonlyused by theUSB PLL and CAN peripherals.Figure2-7 shows how toconnectexternaloscillatorstotheX1 and XCLKIN terminals. When connectingan externaloscillator,use good designpracticestominimizeEMI as wellas clockjitter inducedby externalnoisesources.Minimizetheloopareaformedbetween theforwardcurrentpath(from theoscillatorOUT terminaltotheMCU X1 or XCLKIN terminal)and thereturnpath(fromtheMCU VSS terminaltotheoscillatorGND terminal). Locatetheexternaloscillatoras closetotheMCU as practical.Ideally,thereturngroundtraceshouldbe an isolatedtracedirectlyunderneaththe forwardtraceor run adjacentto the traceon the same layer. Spacing should be kept minimal,with any other nearby tracesdouble-spacedaway, so thatthe electromagneticfieldscreatedby thetwo oppositecurrentscanceleach otheroutas much as possible, thusreducingparasiticinductancesthatradiateEMI.

2.10.4 Main PLL

The Main PLL uses the referenceclock from pins X1 (externaloscillator)or X1/X2 (external crystal/resonator).The inputclockis multipliedby an integermultiplierand a fractionalmultiplieras selectedby theSPLLIMULT and SPLLFMULT fieldsoftheSYSPLLMULT register.The outputclockfrom theMain PLL must be between 110 MHz and 550 MHz. The PLL outputclockisthendividedby 2 before enteringa mux thatselectsbetween thisclockand thePLL inputclock– OSCCLK (usedinPLL bypass mode). The PLL bypass mode isselectedby settingtheSPLLIMULT fieldoftheSYSPLLMULT register to 0. The outputclockfrom the mux nextentersa dividercontrolledby the SYSDIVSEL register,after which the outputclock becomes the PLLSYSCLK. Figure 2-8 shows the Main PLL functionand configurationexamples.Table2-19toTable2-22listtheintegermultiplierconfigurationvalues.

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PRODUCT□PREVIEW MAIN OSC INTEGER MULTIPLIER FRACTIONAL MULTIPLIER PIN SYSPLLMULT REG MAIN PLL 0000000 : x 1 0000001 : x 1 0000010 : x 2 0000011 : x 3 1111101: x 125 1111110: x 126 1111111: x 127 EXAMPLE 1: X1 = 100 MHZ SPLLIMULT = 0000000 ( BYPASS PLL) N/A EXAMPLE 2: X1 = 10 MHz SPLLIMULT = 0010100 ( x 20 ) SPLLFM ULT = 00 ( NOT USED) PLLSYSCLK = [ ( 10 x 20) / 2 ] / 1 = 100 MHz EXAMPLE 3: X1 = 20 MHz SPLLIMULT = 0111100 ( x 60 ) SPLLF MULT = 01 ( x 0.25 ) PLLSYSCLK = [ ( 20 x 60 x 0.25 ) / 2 ] / 1 = 150 MHz SPLLIMULT SPLLFMULT PLLSYSCLK OUPUT OF MAIN PLL IS ALWAYS DIVIDED BY 2 00: NOT USED 01: x 0.25 10: x 0.50 11: x 0.75 7 2 OSCCLK OSCCLK SYSDIVSEL REG SYSDIVSEL (1:0) = 00 ( /1 ) (1) OUPUT OF THE MAIN PLL MUST RANGE BETWEEN 110- 550 MHz PLLOUT (1) SYSPLLCTL REG SPLLEN (2) SPLLCLKEN (2) WHEN SPLLEN BIT = 0, THE MAIN PLL IS POWERED OFF PLLSYSCLK = 100 MHz F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure2-8.Main PLL Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 49 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-19.Main PLL IntegerMultiplierConfiguration (Bypass PLL tox 31) SPLLIMULT(6:0) MULT VALUE 0000000 b Bypass PLL 0000001 b x 1 0000010 b x 2 0000011 b x 3 0000100 b x 4 0000101 b x 5 0000110 b x 6 0000111 b x 7 0001000 b x 8 0001001 b x 9 0001010 b x 10 0001011 b x 11 0001100 b x 12 0001101 b x 13 0001110 b x 14 0001111 b x 15 0010000 b x 16 0010001 b x 17 0010010 b x 18 0010011 b x 19 0010100 b x 20 0010101 b x 21 0010110 b x 22 0010111 b x 23 0011000 b x 24 0011001 b x 25 0011010 b x 26 0011011 b x 27 0011100 b x 28 0011101 b x 29 0011110 b x 30 0011111 b x 31

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-20.Main PLL IntegerMultiplierConfiguration (x32 tox 63) SPLLIMULT(6:0) MULT VALUE 0100000 b x 32 0100001 b x 33 0100010 b x 34 0100011 b x 35 0100100 b x 36 0100101 b x 37 0100110 b x 38 0100111 b x 39 0101000 b x 40 0101001 b x 41 0101010 b x 42 0101011 b x 43 0101100 b x 44 0101101 b x 45 0101110 b x 46 0101111 b x 47 0110000 b x 48 0110001 b x 49 0110010 b x 50 0110011 b x 51 0110100 b x 52 0110101 b x 53 0110110 b x 54 0110111 b x 55 0111000 b x 56 0111001 b x 57 0111010 b x 58 0111011 b x 59 0111100 b x 60 0111101 b x 61 0111110 b x 62 0111111 b x 63 Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 51 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-21.Main PLL IntegerMultiplierConfiguration (x64 tox 95) SPLLIMULT(6:0) MULT VALUE 1000000 b x 64 1000001 b x 65 1000010 b x 66 1000011 b x 67 1000100 b x 68 1000101 b x 69 1000110 b x 70 1000111 b x 71 1001000 b x 72 1001001 b x 73 1001010 b x 74 1001011 b x 75 1001100 b x 76 1001101 b x 77 1001110 b x 78 1001111 b x 79 1010000 b x 80 1010001 b x 81 1010010 b x 82 1010011 b x 83 1010100 b x 84 1010101 b x 85 1010110 b x 86 1010111 b x 87 1011000 b x 88 1011001 b x 89 1011010 b x 90 1011011 b x 91 1011100 b x 92 1011101 b x 93 1011110 b x 94 1011111 b x 95

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-22.Main PLL IntegerMultiplierConfiguration (x96 tox 127) SPLLIMULT(6:0) MULT VALUE 1100000 b x 96 1100001 b x 97 1100010 b x 98 1100011 b x 99 1100100 b x 100 1100101 b x 101 1100110 b x 102 1100111 b x 103 1101000 b x 104 1101001 b x 105 1101010 b x 106 1101011 b x 107 1101100 b x 108 1101101 b x 109 1101110 b x 110 1101111 b x 111 1110000 b x 112 1110001 b x 113 1110010 b x 114 1110011 b x 115 1110100 b x 116 1110101 b x 117 1110110 b x 118 1110111 b x 119 1111000 b x 120 1111001 b x 121 1111010 b x 122 1111011 b x 123 1111100 b x 124 1111101 b x 125 1111110 b x 126 1111111 b x 127

2.10.5 USB PLL

The USB PLL uses thereferenceclockselectablebetween theinputclockarrivingattheXCLKIN pin,or theinternalOSCCLK (originatingfromtheexternalcrystaloroscillatorviatheX1/X2 pins).An inputmux selectsthesourceoftheUSB PLL referencebased on theUPLLCLKSRC bitoftheUPLLCTL Register (seeFigure2-9).The inputclockismultipliedby an integermultiplierand a fractionalmultiplieras selected by the UPLLIMULT and UPLLFMULT fieldsof the UPLLMULT register.The outputclockfrom the USB PLL must alwaysbe 240 MHz. The PLL outputclockisthendividedby 4— resultingin60 MHz thatthe USB needs— beforeenteringa mux thatselectsbetween thisclockand thePLL inputclock(usedinthe PLL bypass mode).The PLL bypass mode isselectedby settingtheUPLLIMULT fieldoftheUPLLMULT registerto0.The outputclockfromthemux becomes theUSBPLLCLK (thereisnotanotherclockdivider). Figure2-9 shows theUSB PLL functionand configurationexamples.Table2-23 and Table2-24 listthe integermultiplierconfigurationvalues. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 53 SubmitDocumentationFeedback

PRODUCT□PREVIEW MAIN OSC INTEGER MULTIPLIER FRACTIONAL MULTIPLIER PIN UPLLMULT REG USB PLL 000000 : x 1 000001 : x 1 000010 : x 2 000011 : x 3 111101: x 61 111110: x 62 111111: x 63 EXAMPLE 1: X1 OR XCLKIN = 60 MHZ UPLLIMULT = 000000 ( BYPASS PLL ) PLLSYSCLK = 60 MHz EXAMPLE 2: X1 OR XCLKIN = 10 MHz UPLLIMULT = 011000 ( x 24 ) UPLLF MULT = 00 ( NOT USED) PLLSYSCLK = ( 10 x 24) / 4 = 60 MHz EXAMPLE 3: X1 OR XCLKIN = 30 MHz UPLLIMULT = 010000 ( x 16 ) UPLLF MULT = 10 ( x 0.50) PLLSYSCLK = ( 30 x 16 x 0.50 ) / 4 = 60 MHz UPLLIMULT UPLLFMULT USBPLLCLK OUPUT OF THE USB PLL IS ALWAYS DIVIDED BY 4 00: NOT USED 01: x 0.25 10: x 0.50 11: x 0.75 6 2 OSCCLK (1) OUPUT OF THE USB PLL MUST BE ALWAYS 240MHz ( SO THAT USBPLLC LK IS 60MHZ ) PLLOUT (1) PIN XCLKIN XCLKIN PLLINP UPLLCLKSRC UPLLCTL REG UPLLCLKENUPLLEN (2) (2) WHEN UPLLEN BIT = 0, THE USB PLL IS POWERED OFF N/A F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-9.USB PLL

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-23.USB PLL IntegerMultiplierConfiguration (Bypass PLL tox 31) SPLLIMULT(5:0) MULT VALUE 000000 b Bypass PLL 000001 b x 1 000010 b x 2 000011 b x 3 000100 b x 4 000101 b x 5 000110 b x 6 000111 b x 7 001000 b x 8 001001 b x 9 001010 b x 10 001011 b x 11 001100 b x 12 001101 b x 13 001110 b x 14 001111 b x 15 010000 b x 16 010001 b x 17 010010 b x 18 010011 b x 19 010100 b x 20 010101 b x 21 010110 b x 22 010111 b x 23 011000 b x 24 011001 b x 25 011010 b x 26 011011 b x 27 011100 b x 28 011101 b x 29 011110 b x 30 011111 b x 31 Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 55 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-24.USB PLL IntegerMultiplierConfiguration (x32 tox 63) SPLLIMULT(5:0) MULT VALUE 100000 b x 32 100001 b x 33 100010 b x 34 100011 b x 35 100100 b x 36 100101 b x 37 100110 b x 38 100111 b x 39 101000 b x 40 101001 b x 41 101010 b x 42 101011 b x 43 101100 b x 44 101101 b x 45 101110 b x 46 101111 b x 47 110000 b x 48 110001 b x 49 110010 b x 50 110011 b x 51 110100 b x 52 110101 b x 53 110110 b x 54 110111 b x 55 111000 b x 56 111001 b x 57 111010 b x 58 111011 b x 59 111100 b x 60 111101 b x 61 111110 b x 62 111111 b x 63

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.11 Master Subsystem Clocking

The internalPLLSYSCLK clock,normallyused as a sourceforallMasterSubsystem clocks,isa divided- down outputof the Main PLL or X1 externalclockinput,as definedby the SPLLCKEN bitof the SYSPLLCTL register. There isalsoa second oscillatorthatinternallygeneratestwo clocks:32KHZCLK and 10MHZCLK. The 10MHZCLK isused by theMissingClockCircuittodetecta possibleabsence ofan externalclocksource totheMain OscillatorthatdrivestheMain PLL. Detectionofa missingclockresultsina substitutionofthe 10MHZCLK forthe PLLSYSCLK. The CLKFAIL signalisalsosent to the NMI Block and the Control Subsystem where thissignalcan triptheePWM peripherals. The 32KHZCLK and 10MMHZCLK clocksare alsoused by the Cortex™ -M3 Subsystem as possible sourcesfortheDeep SleepClock. There are fourregistersassociatedwiththeMain PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically,theCortex™ -M3 processorwritestotheseregisters,whiletheC28x processorhas readaccess.The C28x can requestwriteaccesstotheabove registersthroughtheCLKREQEST register. Cortex™ -M3 can regainwriteownershipoftheseregistersthroughtheMCLKREQUEST register. The MasterSubsystem operatesinone ofthreemodes: Run Mode, Sleep Mode, or Deep Sleep Mode. Table 2-25 shows the Master Subsystem low-powermodes and theireffecton both CPUs, clocks,and peripherals.Figure2-10shows theCortex™ -M3 clocksand theMasterSubsystem low-powermodes. Table2-25.Master Subsystem Low-Power Modes Register Used toCortex™ -M3 Stateof Clock to Clock toGate Clocks Main USB Clock toSharedLow-Power Cortex™ -M3 Cortex™ -M3 Clock toC28x AnalogtoCortex™ - PLL PLL ResourcesMode CPU Peripherals SubsystemM3 Peripherals Run Active M3SSCLK (1) RCGC On On PLLSYSCLK (2) PLLSYSCLK (2) ASYSCLK (3) RCGC orSleep Stopped M3SSCLK (1) On On PLLSYSCLK (2) PLLSYSCLK (2) ASYSCLK (3) SCGC (4) RCGC orDeep Sleep Stopped M3DSDIVCLK (5) Off Off Off Off OffDCGC (4) (1) PLLSYSCLK orOSCCLK divided-downpertheM3SSDIVSEL register.Incase ofa missingsourceclock,M3SSCLK becomes 10MHZCLK divided-downpertheM3SSDIVSEL register. (2) PLLSYSCLK normallyreferstotheoutputoftheMain PLL divided-downpertheSYSDIVSEL register.Incase thePLL isbypassed,the PLLSYSCLK becomes theOSCCLK divided-downpertheSYSDIVSEL register.Incase ofa missingsourceclock,the10MHZCLK is substitutedforthePLLSYSCLK. (3) PLLSYSCLK orOSCCLK divided-downpertheCCLKCTL register.Incase ofa missingsourceclock,ASYSCLK becomes 10MHZCLK. (4) Depends on theACG bitoftheRCC register. (5) 32KHZCLK or10MHZCLK orOSCCLK chosen/divided-downpertheDSLPCLKCFG register,thenagaindividedby theM3SSDIVSEL register(sourcedeterminedinsidetheDSLPCLKCFG register).

2.11.1 Cortex™ -M3 Run Mode

In Run Mode, the Cortex™ -M3 processor,memory, and most of the peripheralsare clockedby the M3SSCLK, whichisa divide-downversionofthePLLSYSCLK (fromMain PLL).The USB isclockedfrom a dedicatedUSB PLL, theCAN peripheralsareclockedby M3SSCLK, OSCCLK, orXCLKIN, and one of two watchdogs (WDOG1) is also clockedby the OSCCLK. Clock selectionforthese peripheralsis accomplishedviacorrespondingperipheralconfigurationregisters.Clockgatingforindividualperipherals is definedinsidethe RCGS register.RCGS, SCGS, and DCGS clock-gatingsettingsonly apply to peripheralsthatareenabledina correspondingDC (DeviceConfiguration)register. ExecutionoftheWFI instruction(Wait-for-Interrupt)shutsdown theHCLK totheCortex™ -M3 CPU and forcestheCortex™ -M3 Subsystem intoSleeporDeep Sleeplow-powermode, dependingon thestateof the SLEEPDEEP bitof the Cortex™ -M3 SYSCTRL register.To come out of a low-powermode, any properlyconfiguredinterrupteventterminatestheSleeporDeep SleepMode and returnstheCortex™ -M3 processor/subsystemtoRun Mode. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 57 SubmitDocumentationFeedback

PRODUCT□PREVIEW M3SSCLK XCLKIN DSDIVOVRIDEDSOSCSRC 32KHZCLK INTERNAL OSC OSCCLK10MHZCLK MAIN PLL /2 M3 CPU HCLKFCLK SLEEPDEEP M3CLKENBx EPI I2C (2) SSI (4) UART (5) USB + PHY (OTG) EMAC GP TIMER (4) uCRC WDOG 0 NMI WDOG WDOG 1 CAN 1,2 USB PLL GPIO_MUX1 /16 uDMA OSCCLK SYSDIVSEL M3SSCLK M3DEEPSLEEP ENABLE CLOCK MODE PERIPHERAL CLOCK ENABLES RCC REG RCGC REG SCGS REG M3RUN M3SLEEP M3DSDIVCLK M3DEEPSLEEP SYSCTRL REG M3SSDIVSEL REG M3SSDIVSEL DCGC REG DSLPCLKCFG REG ACG (Auto Clock Gate) M3SSCLK execution of WFI or WFE instr activates low power modes 10MHZCLK 32KHZCLK OSCCLK DC REG PLL DIS OSCCLK XCLKIN OSCCLK OSCCLK USBPLLCLK MISSING CLK DETECT XCLKIN INTR NVIC 10MHZCLK M3SSCLK M3CLKENBx CONTROL SUBSYSTEM PLL DIS M3 NMI CLOCKFAIL MAIN OSC 10MHZCLK CLOCKFAIL OSCCLK CLOCKFAIL ( GLOBAL PERIPHERAL ENABLES ) ( CLOCK GA TING – RUN ) ( CLOCK GA TING – SLEEP ) ( CLOCK GA TING – DEEP SLEEP ) M3SSCLK REGISTER ACCESS REGISTER ACCESS PERIPH LOGIC M3SSCLK SHARED RESOURCES IPC PERIPH LOGIC CLOCKS CLPMST AT REG SHARED RAMS MSG RAMS OFF PLLSYSCLK OSCCLK ENTER A LOW POWER MODE SELECTS TYPE OF WAKEUP SELECTS BETWEEN SLEEP AND DEEP SLEEP MODES ASSERT ANY INTERRUPT TO EXIT SLEEP OR DEEP SLEEP SYSPLLCTL REG SYSPLLST AT REG SYSPLLMULT REG SYSDIVSEL REG MCLKREQUEST REG M3SSCLK SLEEPONEXITSLEEPONEXIT F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-10.Cortex™ -M3 Clocks and Low-Power Modes

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.11.2 Cortex™ -M3 Sleep Mode

InSleepMode, theCortex™ -M3 processorand memory arepreventedfromclocking,and thusthecode is no longerexecuting.The gatingfortheperipheralclocksmay change based on theACG bitoftheRCC register.When ACG = 0,theperipheralclockgatingisused as definedby theRCGS registers(same as in Run Mode);and when ASC = 1,theclockgatingcomes fromtheSCGS register.RCGS and SCGS clock- gatingsettingsonlyapplytoperipheralsthatareenabledina correspondingDC register.Peripheralclock frequencyfortheenabledperipheralsinSleepMode isthesame as duringtheRun Mode. Sleep Mode is terminatedby any properlyconfiguredinterruptevent.Exitingfrom the Sleep Mode depends on theSleeponexitbitoftheSYSCTRL register.When theSleeponexitbitis1,theprocessorwill temporarilywake up onlyforthedurationoftheISR oftheinterruptcausingthewake-up.Afterthat,the processorgoes back toSleepMode. When theSleeponexitbitis0,theprocessorwakes up permanently (fortheISR and thereafter).

2.11.3 Cortex™ -M3 Deep Sleep Mode

InDeep Sleep Mode, theCortex™ -M3 processorand memory are preventedfrom clockingand thusthe code isno longerexecuting.The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem,and input clocktotheC28x CPU and Shared Resources are turnedoff.The gatingfortheperipheralclocksmay change based on theACG bitoftheRCC register.When ACG = 0,theperipheralclockgatingisused as definedby theRCGS registers(same as inRun Mode);and when ASC = 1,theclockgatingcomes from theDCGS register.RCGS and DCGS clockgatingsettingsonlyapplytoperipheralsthatareenabledina correspondingDC register. Peripheralclockfrequencyforthe enabled peripheralsin Deep Sleep Mode isdifferentfrom the Run Mode. One ofthreesourcesfortheDeep Sleep clocks(32KHZCLK, 10MHZCLK, or OSCLK) isselected with the DSOSCSRC bitsof the DSLPCLKCFG register.This clock is divided-downaccordingto DSDIVOVRIDE bitsof the DSLPCLKCFG register.The outputof thisDeep Sleep Divideris further divided-downpertheM3SSDIVSEL bitsoftheD3SSDIVSEL registertobecome theDeep SleepClock.If 32KHXCLK or 10MHZCLK isselectedinDeep Sleep mode, theinternaloscillatorcircuit(thatgenerates OSCCLK) isturnedoff. The Cortex™ -M3 processorshouldentertheDeep Sleepmode onlyafterfirstconfirmingthattheC28x is alreadyintheStandbymode. Typically,justbeforeenteringtheStandbymode, theC28x willrecordinthe CLPMSTAT thatitisabout to do so.The Cortex™ -M3 processorcan read the CLPMSTAT registerto check ifthe C28x isinStandby mode, and onlythen shouldthe Cortex™ -M3 processorgo intoDeep Sleep.The reasonfortheCortex™ -M3 processortoconfirmthattheC28x isinStandbymode beforethe Cortex™ -M3 processorenterstheDeep Sleepmode isthattheDeep Sleepmode shutsdown theclockto C28x and itsperipherals,and ifthisclock shutdown is not expected by the C28x, unintended consequencescouldresultforsome oftheC28x controlperipherals. Deep Sleep Mode isterminatedby any properlyconfiguredinterruptevent.Exitingfrom theDeep Sleep Mode depends on the Sleeponexitbitof the SYSCTRL register.When the Sleeponexitbitis 1, the processorwilltemporarilywake up onlyforthedurationoftheISR oftheinterruptcausingthewake-up. Afterthat,theprocessorgoes back toDeep Sleep Mode. When theSleeponexitbitis0,theprocessor wakes up permanently(fortheISR and thereafter). Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 59 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.12 ControlSubsystem Clocking

The CLKIN inputclocktotheC28x processorisnormallya divided-downoutputoftheMain PLL or X1 externalclockinput.There arefourregistersassociatedwiththeMain PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically,theCortex™ -M3 processorwritestotheseregisters,whilethe C28x processorhas readaccess.The C28x can requestwriteaccesstotheabove registersthroughthe CLKREQEST register.The Cortex™ -M3 can regainwriteownership of these registersthroughthe MCLKREQUEST register. IndividualC28x peripheralscan be turnedon oroffby gatingC28SYSCLK tothoseperipherals,whichis done viatheCPCLKCR0,2,3 registers. The C28x processoroutputstwo clocks:C28CPUCLK and C28SYSCLK. The C28SYSCLK isused by C28x peripherals,C28x Timer0,C28x Timer1,and C28x Timer2.C28x Timer2 can alsobe clockedby OSCCLK or10MHZCLK (seeFigure2-11).The C28CPUCLK isused by theC28x CPU, FPU, VCU, and PIE. The ControlSubsystem operatesinone of threemodes: Normal Mode, IdleMode, or Standby Mode. Table2-26shows theControlSubsystem low-powermodes and theireffecton theC28x CPU, clocks,and peripherals.Figure2-11shows theControlSubsystem clocksand low-powermodes. Table2-26.ControlSubsystem Low-Power Modes (1) RegistersUsed toGate C28x Low-Power Mode StateofC28x CPU C28CPUCLK (2) C28SYSCLK (3) Clocks toC28x Peripherals Normal Active On On CPCLKCR0,1,3 Idle Stopped Off On CPCLKCR0,1,3 Standby Stopped Off Off N/A (1) The inputclocktotheC28x CPU isPLLSYSCLK fromtheMasterSubsystem.Thisclockisturnedoffwhen theMasterSubsystem enterstheDeep Sleepmode. (2) C28CPUCLK isan outputfromtheC28x CPU. C28CPUCLK clockstheC28x FPU, VCU, and PIE. (3) C28SYSCLK isan outputfromtheC28x CPU. C28SYSCLK clocksC28x peripherals.

2.12.1 C28x Normal Mode

In Normal Mode, the C28x processor,Local Memory, and C28x peripheralsare clocked by the C28SYSCLK, whichisderivedfromtheC28CLKIN inputclocktotheC28x processor.The FPU, VCU, and PIE are clockedby the C28CPUCLK, which isalsoderivedfrom the C28CLKIN. Timer 2 can alsobe clockedby theTMR2CLK, which isa divided-downversionofone ofthreesourceclocks— C28SYSCLK, OSCCLK, and 10MHZCLK — as selectedby theCLKCTL register.Additionally,theLOSPCP registercan be programmed toprovidea dedicatedclock(C28LSPCLK) totheSCI,SPI,and McBSP peripherals;and the HISPCP registercan be programmed to providea dedicatedclock(C28HSPCLK) to stretchthree outputsfromePWM peripherals. Clock gatingforindividualperipheralsisdefinedinsidethe CPCLKCR0,1,3 registers.Executionof the IDLE instructionstopsthe C28x processorfrom clockingand activatesthe IDLES signal.The IDLES signalisgatedwithtwo LPM bitsoftheCPCLKCR0 registertoentertheC28x Subsystem intoIdlemode orStandbyMode.

2.12.2 C28x IdleMode

In IdleMode, the C28x processorstopsexecutinginstructionsand the C28CPUCLK isturnedoff.The C28SYSCLK continuesto run.Exitfrom IdleMode is accomplishedby any enabled interruptor the C28NMIINT (C28x non-maskableinterrupt). Upon exitfromIdleMode, theC28CPUCLK isrestored.IfLPMWAKE interruptisenabled,theLPMWAKE ISR is executed.Next, the C28x processorstartsfetchinginstructionsfrom a locationimmediately followingtheIDLE instructionthatoriginallytriggeredtheIdleMode.

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PRODUCT□PREVIEW CLPMCR0 REG C28CPUCLK C28NMIINT TIMER 0 execution of IDLE instruction activates the IDLES signal ENTER IDLE MODE ENTER ST ANDBY MODE EXIT IDLE MODE EXIT ST ANDBY MODE IDLES LPM(0)LPM(1) Requests To Wake From STANDBY Mode Requests To Wake From IDLE Mode TINT2 TIMER 2 C28 XINT(3) C28x NMI HISPCP REG C28HSPCLK C28 DMA C28CLKENBx LOSPCP REG ECAP (6) I2C C28LSPCLK C28x CPU ‘0’ C28CLKIN MASTER SUBSYSTEM ST ANDBY MODE PLLSYSCLK LPMWAKE /14 /14 MTOCIPC(1) IPC HSPCLK LSPCLK CLOCKFAIL TIMER 1 TINT 1 C28x NMI EQEP (3) GPIO_MUX1 SCI SPI McBSP TMR2CLK CPCLKCR3 REG CPCLKCR1 REG CPCLKCR0 REG 10MHZCLK C28x PIE PIEINTRS (1) OSCCLK /16 OSCCLK C28SYSCLK 10MHZCLK CTMR2CLK PRESCALE TMR2CLKSRCSEL CLKCTL REG C28SYSCLK GPIO_MUX1 PULSE STRETCH SOCAOSOCBOSYNCO OFF CCLKCTL REG CLKDIV ASYSCLK ANALOG SUBSYSTEM SRXRST ACIBRST ASYSRST C28x PIE PIEINTRS (12:1) C28 FPU/VCU CLPMST AT REG C28SYSCLK LPM WAKEUP LPMSEL1 REG LPMSEL2 REG SELECT QUALIFICATION SELECT ONE OF 62 GPIs SYSPLLST AT REG SYSPLLMULT REG SYSPLLCTL REG SYSDIVSEL REG CCLKREQUEST REG M3SSCLK CLKOFF REG GPIO_MUX1/4 XCLKOUT PF2_GPIO34 C28SYSCLK C28SYSCLK 0 XPLLCLKCFG REG XPLLCLKOUTDIV OFF/4 OFF CXCLK REG XCLKOUTDIV (NOTE: IN REVISION 0 OF SILICON, XCLKOUT = PLLSYSCLK DIVIDED DOWN BY 1, 2 OR 4) EPWM (9) GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure2-11.C28x Clocks and Low-Power Modes Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 61 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.12.3 C28x Standby Mode

InStandbyMode, theC28x processorstopsexecutinginstructionsand theC28CLKIN, C28CPUCLK, and C28SYSCLK are turnedoff.Exitfrom Standby Mode is accomplishedby 1 of 62 GPIOs from the GPIO_MUX1 block,orMTOCIPCINT1 (interruptfromMTOC IPC peripheral).The wakeup GPIO selected insidethe GPIO_MUX block enters the QualificationBlock as the LPMWAKE signal.Insidethe QualificationBlock,the LPMWAKE signalis sampled per the QUALSTDBY bits(bits[7:2]of the CPCLKCR0 register)beforepropagatingintothewake requestlogic. Cortex™ -M3 shoulduse CLPMSTAT registerbitstotelltheC28x togo intoStandby mode beforegoing intoDeep Sleep mode. Otherwise,the clockto the C28x willbe turnedoffsuddenlywhen the control softwareisnotexpectingthisclocktoshutoff.When thedeviceisinDeep Sleep/Standbymode, wake-up shouldhappen onlyfromtheMasterSubsystem,sinceallC28x clocksareoff(C28CLKIN, C28CPUCLK, C28SYSCLK), thuspreventingtheC28x fromwakingup first. Upon exitfrom STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored.Ifthe LPMWAKE interruptisenabled,theLPMWAKE ISR isexecuted.Next,theC28x processorstartsfetching instructionsfroma locationimmediatelyfollowingtheIDLE instructionthatoriginallytriggeredtheStandby Mode. NOTE ForGPIO_MUX1 pinsPF6_GPIO38 and PG6_GPIO46, onlythecorrespondingUSB function isavailableon siliconrevision0 devices(GPIO and otherfunctionslistedinTable3-1arenot available).

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.13 Analog Subsystem Clocking

The Analog Subsystem isclockedby ASYSCLK, which isa divided-downversionofthePLLSYSCLK as definedby CLKDIV bitsoftheCCLKCTL register.The CCLKCTL registerisexclusivelyaccessibleby the C28x processor.The CCLKCTL registeris resetby ASYSRST, which is derivedfrom two Analog Subsystem resets— ACIBRST and SRXRST. Therefore,whilenormallytheC28x controlsthefrequencyof ASYSCLK, itispossibleforthe Cortex™ -M3 softwareto restorethe ASYSCLK to itsdefaultvalueby resettingtheAnalogSubsystem. The ASYSCLK isshutdown when theCortex™ -M3 processorenterstheDeep Sleepmode.

2.14 Shared Resources Clocking

The IPC,Shared RAMs, and Message RAMs areclockedby PLLSYSCLK. EPI isclockedby M3SSCLK. The PLLSYSCLK normallyreferstotheoutputoftheMain PLL divided-downpertheSYSDIVSEL register. Incase thePLL isbypassed,thePLLSYSCLK becomes theOSCCLK divided-downpertheSYSDIVSEL register.Incase ofa missingsourceclock,the10MHZCLK issubstitutedforthePLLSYSCLK. AlthoughEPI isa sharedperipheral,itisphysicallylocatedinsidetheCortex™ -M3 Subsystem;therefore, EPI isclockedby M3SSCLK.

2.15 Loss ofInputClock (NMI Watchdog Function)

The Concertodevicesuse two typeofinputclocks.The main clock,forclockingmost ofthedigitallogicof theMaster,Control,and Analogsubsystems,entersthechipthroughpinsX1 and X2 when usingexternal crystalor justpinX1 when usingan externaloscillator.The second clockentersthe chipthroughthe XCLKIN pinand thissecond clockcan be used toclocktheUSB PLL and CAN peripherals.Onlythemain clockhas a built-inMissingClockDetectioncircuittorecognizewhen theclocksourcevanishesand to enableotherchipcomponents totakecorrectiveorrecoveryactionfromsuch event(seeFigure2-12). The MissingClockDetectioncircuititselfisclockedby the10MHZCLK (froman internalzero-pinoscillator) so that,ifthe main clockdisappears,the circuitisstillworking.Immediatelyafterdetectinga missing sourceclock,theMissingClockDetectioncircuitoutputstheCLOCKFAIL signaltotheCortex™ -M3 NMI circuit,theC28x NMI, ePWM peripherals,and thePLLSYSCLK mux. When thePLLSYSCLK mux senses an activeCLOCKFAIL signal,the PLLSYSCLK mux revivesthe PLLSYSCLK using the 10MHZCLK. Simultaneously,theePWM peripheralscan use theCLOCKFAIL signaltostopdown drivingmotorcontrol outputs.The NMI blocks respond to the CLOCKFAIL signalby sending an NMI interruptto a correspondingCPU, whilestartingtheassociatedNMI watchdogcounter. Ifthesoftwaredoes notrespondtotheclock-failcondition,thewatchdog timerswilloverflow,resultingin thedevicereset.Ifthesoftwaredoes reacttotheNMI, thesoftwarecan preventtheimpendingresetby disablingthe watchdog timers,and then the softwarecan initiatenecessarycorrectiveactionsuch as switchingover to an alternativeclocksource (ifavailable)or the softwarecan initiatea shut-down procedureforthesystem. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 63 SubmitDocumentationFeedback

PRODUCT□PREVIEW INTERNAL OSC MAIN PLL PIN MISSING CLK DETECT CLOCKFAIL MAIN OSC 10MHZCLK PLLSYSCLK OSCCLK EPWM M3 NMI C28x NMI CPU C28x CPU M3 NMI WDOG C28x NMI WDOG RESETS ADDITIONAL CLOCK CONTROL LOGIC GPIO_MUX1 THE INPUT CLOCK IS DISRUPTED CLOCKFAIL SIGNAL BECOMES ACTIVE PLLSYSCLK SWITCHES TO THE 10MHZCLK CPUS RESPOND TO NMIS AND THE WATCHDOGS ST ART COUNTING SOFTWARE TAKES CORRECTIVE/RECOVERY ACTION IF SOFTWARE DOES NOT STOP THE WATCHDOG COUNTERS, THE WATCHDOGS WILL RESET THE DEVICE AFTER THE COUNT RUNS OUT TYPICAL ACTIVITY FOLLOWING A MISSING CLOCK DETECTION : CLOCK FAIL SIGNAL IS SENT TO M3 NMI BLOCK, C28 NMI BLOCK, EPWM MODULES AND THE PLLSYSCLK MUX M3SSCLK C28CLKIN PIN EPWM_A EPWM_B OTHER NMI SOURCES CLOCKFAIL CLOCKFAIL C28CLKIN M3NMI C28NMI PIN PIN F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-12.MissingClock Detection

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.16 GPIOs and Other Pins

Most Concerto externalpins are shared among many internalperipherals.This sharingof pins is accomplishedthroughseveralI/O muxes where a specificphysicalpin can be assignedto selected signalsofinternalperipherals. Most oftheI/OpinsoftheConcerto™ MCU can alsobe configuredas programmableGPIOs. Exceptions includetheX1 and X2 oscillatorinputs;theXRS digitalresetand ARS analogreset;theVREG12EN and VREG18EN internalvoltageregulatorenables;and fiveJTAG pins.The 74 primaryGPIOs aregroupedin 2 programmableblocks:GPIO_MUX1 block(66pins)and GPIO_MUX2 block(8pins).Additionally,eight secondaryGPIOs areavailablethroughtheAIO_MUX1 block(fourpins)and AIO_MUX2 block(fourpins). Figure2-13shows theGPIOs and otherpins.

2.16.1 GPIO_MUX1

Sixty-sixpinsoftheGPIO_MUX1 blockcan be selectivelymapped throughcorrespondingsetsofregisters to allCortex™ -M3 peripherals,to allC28x peripherals,to 66 General-PurposeInputs,to 66 General- Purpose Outputs,ora mixtureofalloftheabove.Sixty-twopinsofGPIO_MUX1 (GPIO0–GPIO63 minus GPIO39 and GPIO44) can alsobe mapped to12 ePWM TripInputs,6 eCAP inputs,3 ExternalInterrupts to the C28x PIE, and the C28x Standby Mode Wakeup signal(LMPWAKE). Additionally,each GPIO_MUX1 pincan have a pullupenabledor disabled.By default,allpullupsand outputsare disabled on reset,and allpinsoftheGPIO_MUX1 blockaremapped toCortex™ -M3 peripherals(andnottoC28x peripherals). Figure 2-14 shows the internalstructureof GPIO_MUX1. The blue blocks representthe Master Subsystem sideofGPIO_MUX1, and thegreenblocksaretheControlSubsystem side.The greyblockin the center,Pin-LevelMux, iswhere the GPIO_MUX1 pinsare individuallyassignedbetween the two subsystems,based on how theconfigurationregistersareprogrammed intheblueand greenblocks(see Figure2-15fortheconfigurationregisters). Pin-LevelMux assignsMaster Subsystem peripheralsignals,ControlSubsystem peripheralsignals,or GPIOs to the 66 GPIO_MUX1 pins.In additionto connectingperipheralI/Osof the two subsystems to pins,the Pin-LevelMux also providesothersignalsto the subsystems:XCLKIN and GPIO[A:J]IRQ signalsto the Master Subsystem,plusGPTRIP[12:1]and GPI[63:0]signalsto the ControlSubsystem. XCLKIN carriesa clockfrom an externalpinto USB PLL and CAN modules.The nineGPIO[A:J]IRQ signalsare interruptrequestsfrom selectedexternalpins to the NVIC interruptcontroller.The 12 GPTRIP[12:1]signalscarrytripeventsfrom selectedexternalpinstoC28x controlperipherals— ePWM, eCAP, and eQEP. Sixty-fourGPI signalsgo totheC28x LPM GPIO Selectblockwhere one ofthem can be selectedtowake up theC28x CPU from Low-Power Mode. Sixty-six(66)GPI signalsgo totheC28x QUAL blockwhere theycan be configuredwitha qualificationsamplingperiod(seeFigure2-15). The configurationregistersforthe muxing of Master Subsystem peripheralsare organizedinninesets (A–J),witheach setbeingresponsibleforeightpins.These ninesetsofregistersare programmable by the Cortex™ -M3 CPU viathe AHB bus or the APB bus. The configurationregisterforthe muxing of ControlSubsystem peripheralsare organizedinthreesets(A–C),witheach setbeingresponsibleforup to 32 pins.These registersare programmable by the C28x CPU viathe C28x CPU bus.Figure2-15 shows set A of the Master Subsystem GPIO configurationregisters,set A of the ControlSubsystem registers,and themuxing logicforone GPIO pinas drivenby theseregisters. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 65 SubmitDocumentationFeedback

PRODUCT□PREVIEW GPIO_MUX2 GPIO_MUX1 MUX GPIO COMPOUT (6:1) ADC ADC 66 66 MUXGPIO XINT (3) EPWM (9) ECAP (6) EQEP (3) McBSP SPI MCLRAMFSRAMDRAMCLXAMFSXAMDXA USB EPI0S (41:0) USB0VBUSUSB0DMUSB0DP USB0ID USB0EPENUSB0OFLT CLOCKS NMI M3EXTNMI XCLKINXCLKOUTLPMWAKE RESETSDEBUG X1 X2 JTAG (7) SCI SCIRXDASCITXDA EPWM (9:1) BEPWM (9:1) AGPTRIP (12:1)GPTRIP (6:4)GPTRIP (12:7)ECAP (6:1) EQEP (3:1) SEQEP (3:1) AEQEP (3:1) I SPISOMISPISIMOSPICLKSPISTE EQEP (3:1) B SDAASCLA I2C EMAC MII TX0MII TX1MII TX2MII TX3MII RX0MII RX1MII RX2MII RX3 MII TXENMII MDCMII MDIO MII PHYRSTNMII PHYINTRN MII RXDVMII RXER MII TXCKMII RXCKMII CRSMII COL MII TXER USB PLL XCLKIN MUXGPIO AIO_MUX2 10 MUXGPIO AIO_MUX1 10 VREGS VREG18ENVREG12EN XRSARS NVIC GPIO (H:A) IRQ SSI (4) I2C (2) CAN (2) UART (5) SSI (3:0) RXSSI (3:0) TXSSI (3:0) CLKSSI (3:0) FSS I2C (1:0) SCLI2C (1:0) SDACAN (1:0) RXCAN (1:0) TX XCLKINU1CTSU1DCD U (4:0) RXU (4:0) TXU1DTR U1DSRU1RTSU1RI COMPARATOR + DAC UNITS VDDA (3.3V) VSSA (0V) LPM WAKEUP LPMWAKE C28X CPU M3EXTNMI NMI COMPB2COMPA1 COMPA2 COMPA3 ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 COMPB5COMPA4 COMPA5 COMPA6 EPI GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-13.GPIOs and Other Pins

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PRODUCT□PREVIEW XINT (3) EPWM (9) ECAP (6) EQEP (3)McBSP SPI USB EPI SCI MCLRAMFSRAMDRAMCLXAMFSXAMDXA SCIRXDASCITXDA EPWM (9:1) BEPWM (9:1) A GPTRIP (12:1) GPTRIP (6:4)GPTRIP (12:7) ECAP (6:1)EQEP (3:1) SEQEP (3:1) AEQEP (3:1) ISPISOMISPISIMOSPICLKSPISTE EQEP (3:1) B SDAASCLA I2C EMACUSB PLL MII TX0MII TX1MII TX2MII TX3MII RX0MII RX1MII RX2MII RX3 MII TXENMII MDCMII MDIOMII PHYRSTNMII PHYINTRN MII RXDVMII RXER MII TXCKMII RXCKMII CRSMII COL MII TXEREPI0S (41:0)USB0VBUSUSB0DMUSB0DP USB0ID USB0EPENUSB0OFLT XCLKIN NVIC GPIO (H:A) IRQ SSI (4) I2C (2) CAN (2) UART (5) SSI (3:0) RXSSI (3:0) TXSSI (3:0) CLKSSI (3:0) FSS I2C (1:0) SCLI2C (1:0) SDACAN (1:0) RXCAN (1:0) TX XCLKIN U1CTSU1DCD U (4:0) RXU (4:0) TXU1DTR U1DSRU1RTSU1RI M3 PERIPHERAL SIGNAL ROUTING M3 MUX G C28 MUX B C28 PERIPHERAL SIGNAL ROUTING PIN - LEVEL MUX C28x CPU CPU uDMA XCLKIN BUS BRIDGE C28x DMA C28 MUX A C28 MUX C M3 APB BUS M3 AHB BUS C28 DMA BUS C28 CPU BUS M3 MUX A M3 MUX B M3 MUX D M3 MUX E M3 MUX F M3 MUX H M3 MUX J M3 MUX C NMI EXT NMI INTERRUPTS 8 8 8 8 7 7 8 8 4 32 30 4 GPTRIP (12:1) LPM WAKEUP LPM WAKE GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) (TERMINALS GPIO 39 AND GPIO 44 ARE NOT PINNED OUT ON THIS DEVICE) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure2-14.GPIO_MUX1 Block Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 67 SubmitDocumentationFeedback

PRODUCT□PREVIEW ONE OF 66 GPIO_MUX1 PINS GPIOICR REG GPIOAFSEL REGGPIODEN REG XRS GPIOCSEL REG GPAMUX1 REG GPAMUX2 REG SEL(1:0) FROM C28 PERIPH 1-3PERIPHERALS 1-3 REPRESENT A SET OF UP TO THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN GPASET REG GPACLEAR REG GPA TOGGLE REG GPIOPUR REG GPIOODR REG C28 REG SET A C28 REG SET A GREY LOGIC IS SPECIFIC TO ONE DEVICE I/O PIN GREEN REGISTER SET A SHOWN REPRESENTS 32 OF 66 GPIOs. THE REMAINING 34 GPIOs ARE CONTROLLED BY SIMILAR REGISTER SETS B AND C OPEN DRAIN LOGIC M3 REG SET A QUAL SYNC C28SYSCLK TO C28x CPU WAKE-UP FROM A LOW POWER MODE GPTRIP (12:1) TO XINT, ECAP, EPWM GPADIR REG C28 REG SET A GPACTRL REG GPIODA TA REG GPIODIR REG GPIOAPSEL REG GPIOPCTL REG GPIOIS REG GPIOIBE REG GPIOIEV REG GPIOIM REG GPIORIS REG GPIOMIS REG GPIOICR REG GPIOAFSEL REGGPIODEN REG GPIO (A) IRQ TO/FROM M3 PERIPH 1 - 11 TO/FROM M3 PERIPH 12 - 15 GPIOCSEL REG PERIPHERALS 1-15 REPRESENT A SET OF UP TO

15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN

‘1’ ‘1’ ‘0’ OUTPUT INPUT OEOE OE OE A-H INTR REQUESTS TO M3 N/C SEL(1:0)

6 SAMPLES

3 SAMPLES

SEL(1:0) GPASEL1 REG GPASEL2 REG C28 REG SET A (C28 GPIO) GPADAT REG N/C AT RESET (M3 GPIO) PULL-UP DISABLED ON RESET PRIMARY AT RESETGPIOLOCK REG GPIOCR REG M3 REG SET A GPIOAMSEL REG M3 REG SET A XCLKINGPIO63 ONLY M3 CLOCKS (USB ANALOG SIGNALS) EACH I/O PIN HAS A DEDICATED PAIR OF BITS FOR MUX SELECT EACH I/O PIN HAS A DEDICATED PAIR OF BITS FOR MUX SELECT PULL UP ENB ORANGE LOGIC SHOWS USB ANALOG FUNCTIONS (APPLIES TO 4 PINS ONLY) GPIOAMSEL REG (4 PINS ONLY) ANALOG USB SIGNALS BLUE REGISTER SET A REPRESENTS 8 OF 66 GPIOs. REMAINING 58 GPIOs ARE CONTROLLED BY SIMILAR REGISTER SETS B, C, D, E, F, I, J, H GPTRIP1SEL REG GPTRIP12SEL REG GPI (63:0) MINUS GPI 39 AND GPI 64 F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-15.GPIO_MUX1 Pin Mapping Through RegisterSet A

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 For each ofthe8 pinsinsetA oftheCortex™ -M3 GPIO registers,registerGPIOPCTL selectsbetween 1 of11 possibleprimaryCortex™ -M3 peripheralsignals,or 1 of4 possiblealternateperipheralsignals. RegisterGPIOAPSEL thenpicksone outputtopropagatefurtheralongthemuxing chaintowardsa given pin.The inputtakesthe reversepath.See Table 2-27 and Table 2-28 forthe mapping of Cortex™ -M3 peripheralsignalstoGPIO_MUX1 pins. Similarly,on theC28x side,GPAMUX1 and GPAMUX2 registersselect1 of4 possibleC28x peripheral signalsforeach of32 pinsofsetA. The selectedC28x peripheraloutputthenpropagatesfurtheralong themuxing chaintowardsa givenpin.The inputtakesthereversepath.See Table2-29forthemapping ofC28x peripheralsignalstoGPIO_MUX1 pins. In additionto passingmostlydigitalsignals,fourGPIO_MUX1 pins can also be assignedto analog signals.The GPIO AnalogMode Select(GPIOAMSEL) Registerisused toassignfourpinstoanalogUSB signals.PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes USB0DP, and PG6_GPIO46 becomes USB0ID. When analogmode isselected,thesefourpinsare not availablefordigitalGPIO_MUX1 optionsas describedabove. Anotherspecialcase isthe ExternalOscillatorInputsignal(XCLKIN).Thissignal,availablethroughpin PJ7_GPIO63, isdirectlytiedtoUSBPLLCLK (clockinputtoUSB PLL) and two CAN modules.XCLKIN is alwaysavailableatthesemodules where itcan be selectedthroughlocalregisters. NOTE ForGPIO_MUX1 pinsPF6_GPIO38 and PG6_GPIO46, onlythecorrespondingUSB function isavailableon siliconrevision0 devices(GPIO and otherfunctionslistedinTable3-1arenot available). Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 69 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-27.GPIO_MUX1 Pin Assignments (M3 PrimaryModes) (1) Analog M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 M3DeviceMode Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary PrimaryPin Name(USB Pins) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 – PA6_GPIO6 I2C1SCL CCP1 MMI_RXCK – – CAN0RX – USB0EPEN U1CTS – – – PA7_GPIO7 I2C1SDA CCP4 MMI_RXER – – CAN0TX CCP3 USB0PFLT U1DCD – – – PB2_GPIO10 I2C0SCL – – CCP3 CCP0 – – USB0EPEN – – – – PB4_GPIO12 – – – U2RX CAN0RX – U1RX EPI0S23 – – – – PB5_GPIO13 – CCP5 CCP6 CCP0 CAN0TX CCP2 U1TX EPI0S22 – – – – PB6_GPIO14 CCP1 CCP7 – – – CCP5 – EPI0S37 (2) – – – – PD0_GPIO16 PWM0 CAN0RX – U2RX U1RX CCP6 MII_RXDV – U1CTS – – – PD1_GPIO17 PWM1 CAN0TX – U2TX U1TX CCP7 MII_TXER – U1DCD CCP2 – – PD2_GPIO18 U1RX CCP6 – CCP5 – – – EPI0S20 – – – – PD3_GPIO19 U1TX CCP7 – CCP0 – – – EPI0S21 – – – – PD4_GPIO20 CCP0 CCP3 – MII_TXD3 – – – – U1RI EPI0S19 – – PD5_GPIO21 CCP2 CCP4 – MII_TXD2 – – – – U2RX EPI0S28 – – PD6_GPIO22 Fault0 – – MII_TXD1 – – – – U2TX EPI0S29 – – PD7_GPIO23 IDX0 – CCP1 MII_TXD0 – – – – U1DTR EPI0S30 – – PE0_GPIO24 PWM4 SSI1CLK CCP3 – – – – EPI0S8 USB0PFLT – – – PE1_GPIO25 PWM5 SSI1FSS – CCP2 CCP6 – – EPI0S9 – – – – PE2_GPIO26 CCP4 SSI1RX – – CCP2 – – EPI0S24 – – – – PE3_GPIO27 CCP1 SSI1TX – – CCP7 – – EPI0S25 – – – – PE4_GPIO28 CCP3 – – – U2TX CCP2 MII_RXD0 EPI0S34(2) – – – (1) BlankfieldsrepresentReservedfunctions. (2) Thismuxing optionisonlyavailableon siliconRevisionA devices;thismuxing optionisnotavailableon siliconRevision0 devices.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-27.GPIO_MUX1 Pin Assignments (M3 PrimaryModes) (1)(continued) Analog M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 M3DeviceMode Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary PrimaryPin Name(USB Pins) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 – PF1_GPIO33 CAN1TX – – MII_RXER – – – – U1RTS CCP3 – – PF2_GPIO34 – – MII_PHYINTR – – – – SSI1CLK – –EPI0S32(2) – PF4_GPIO36 CCP0 – MII_MDIO – – – – EPI0S12 SSI1RX – – – PF5_GPIO37 CCP2 – MII_RXD3 – – – – EPI0S15 SSI1TX – – USB0VBUS PF6_GPIO38 CCP1 – MII_RXD2 – – – – – U1RTS –EPI0S38(2) – PG0_GPIO40 U2RX – I2C1SCL – – – USB0EPEN EPI0S13 – – – USB0DP PG5_GPIO45 CCP5 – MII_TXEN – – – – – U1DTR –EPI0S40(2) USB0ID PG6_GPIO46 – – MII_TXCK – – – – – U1RI –EPI0S41(2) – PH4_GPIO52 – – – USB0PFLT – – – EPI0S10 MII_TXD1 – SSI1CLK – PJ1_GPIO57 – – – – – – – EPI0S17 USB0PFLT – I2C1SDA Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 71 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-27.GPIO_MUX1 Pin Assignments (M3 PrimaryModes) (1)(continued) Analog M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 M3DeviceMode Primary Primary Primary Primary Primary Primary Primary Primary Primary Primary PrimaryPin Name(USB Pins) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 – PC4_GPIO68 CCP5 – MII_TXD3 – CCP2 CCP4 – EPI0S2 CCP1 – – – PC5_GPIO69 CCP1 – – – CCP3 USB0EPEN – EPI0S3 – – – – PC6_GPIO70 CCP3 – – – U1RX CCP0 USB0PFLT EPI0S4 – – – – PC7_GPIO71 CCP4 – – CCP0 U1TX USB0PFLT – EPI0S5 – – –

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-28.GPIO_MUX1 Pin Assignments (M3 AlternateModes) (1) M3 M3 M3 M3Analog Mode Device Pin Name Alternate Alternate Alternate Alternate(USB Pins) Mode 12 Mode 13 Mode 14 Mode 15 – PA1_GPIO1 – – – SSI1FSS – PA3_GPIO3 – – U1DCD SSI1CLK – PA6_GPIO6 MII_TXD3 – U1DTR – – PA7_GPIO7 MII_RXD1 – U1RI – – PB0_GPIO8 – SSI2TX CAN1TX U4TX – PB2_GPIO10 – SSI2CLK CAN1RX U4RX – PB3_GPIO11 – SSI2FSS U1RX – – PB4_GPIO12 – – CAN1TX SSI1TX – PB5_GPIO13 – – CAN1RX SSI1RX – PB6_GPIO14 MII_CRS I2C0SDA U1TX SSI1CLK – PB7_GPIO15 – I2C0SCL U1RX SSI1FSS – PD0_GPIO16 MII_RXD2 SSI0TX CAN1TX USB0EPEN – PD1_GPIO17 MII_COL SSI0RX CAN1RX USB0PFLT – PD2_GPIO18 – SSI0CLK U1TX CAN0RX – PD3_GPIO19 – SSI0FSS U1RX CAN0TX – PD4_GPIO20 – – U3TX CAN1TX – PD5_GPIO21 – – U3RX CAN1RX – PD6_GPIO22 – – I2C1SDA U1TX – PD7_GPIO23 – – I2C1SCL U1RX – PE0_GPIO24 – SSI3TX CAN0RX SSI1TX – PE1_GPIO25 – SSI3RX CAN0TX SSI1RX – PE2_GPIO26 – SSI3CLK U2RX SSI1CLK – PE3_GPIO27 – SSI3FSS U2TX SSI1FSS – PE4_GPIO28 – U0RX EPI0S38 (2) USB0EPEN – PE5_GPIO29 MII_TXER U0TX – USB0PFLT – PE6_GPIO30 MII_MDIO CAN0RX – – – PE7_GPIO31 MII_RXD3 CAN0TX – – – PF0_GPIO32 – I2C0SDA TRACED2 – – PF1_GPIO33 – I2C0SCL TRACED3 – – PF2_GPIO34 – – TRACECLK XCLKOUT – PF3_GPIO35 – U0TX TRACED0 – USB0VBUS PF6_GPIO38 – – – – (1) BlankfieldsrepresentReservedfunctions. (2) Thismuxing optionisonlyavailableon siliconRevisionA devices;thismuxing optionisnotavailableon siliconRevision0 devices. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 73 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-28.GPIO_MUX1 Pin Assignments (M3 AlternateModes) (1)(continued) M3 M3 M3 M3Analog Mode Device Pin Name Alternate Alternate Alternate Alternate(USB Pins) Mode 12 Mode 13 Mode 14 Mode 15 – PG0_GPIO40 MII_RXD2 U4RX – MII_TXCK – PG1_GPIO41 MII_RXD1 U4TX – MII_TXER USB0DM PG2_GPIO42 – – – – – PG3_GPIO43 MII_RXDV – TRACED1 – USB0DP PG5_GPIO45 – – – – USB0ID PG6_GPIO46 – – – – – PH0_GPIO48 – SSI3TX – MII_TXD3 – PH1_GPIO49 MII_RXD0 SSI3RX – MII_TXD2 – PH2_GPIO50 – SSI3CLK – MII_TXD1 – PH3_GPIO51 – SSI3FSS – MII_TXD0 – PH4_GPIO52 – U3TX – MII_COL – PH5_GPIO53 – U3RX – MII_PHYRST – PH6_GPIO54 MII_TXEN SSI0TX – MII_PHYINTR – PH7_GPIO55 MII_TXCK SSI0RX – MII_MDC – PJ0_GPIO56 – SSI0CLK – MII_MDIO – PJ1_GPIO57 MII_RXDV SSI0FSS – MII_RXD3 – PJ2_GPIO58 MII_RXCK SSI0CLK U0TX MII_RXD2 – PJ3_GPIO59 MII_MDC SSI0FSS U0RX MII_RXD1 – PJ4_GPIO60 MII_COL SSI1CLK – MII_RXD0 – PJ5_GPIO61 MII_CRS SSI1FSS – MII_RXDV – PJ6_GPIO62 MII_PHYINTR U2RX – MII_RXER PJ7_GPIO63/– MII_PHYRST U2TX – MII_RXCKXCLKIN

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table2-29.GPIO_MUX1 Pin Assignments (C28x PeripheralModes) (1) C28x C28x C28x C28xAnalog Mode Device Pin Name Peripheral Peripheral Peripheral Peripheral(USB Pins) Mode 0 Mode 1 Mode 2 Mode 3 – PA0_GPIO0 GPIO0 EPWM1A – – – PA1_GPIO1 GPIO1 EPWM1B ECAP6 – – PA2_GPIO2 GPIO2 EPWM2A – – – PA3_GPIO3 GPIO3 EPWM2B ECAP5 – – PA4_GPIO4 GPIO4 EPWM3A – – – PA5_GPIO5 GPIO5 EPWM3B MFSRA ECAP1 – PA6_GPIO6 GPIO6 EPWM4A – EPWMSYNCO – PA7_GPIO7 GPIO7 EPWM4B MCLKRA ECAP2 – PB0_GPIO8 GPIO8 EPWM5A – ADCSOCAO – PB1_GPIO9 GPIO9 EPWM5B – ECAP3 – PB2_GPIO10 GPIO10 EPWM6A – ADCSOCBO – PB3_GPIO11 GPIO11 EPWM6B – ECAP4 – PB4_GPIO12 GPIO12 EPWM7A – – – PB5_GPIO13 GPIO13 EPWM7B – – – PB6_GPIO14 GPIO14 EPWM8A – – – PB7_GPIO15 GPIO15 EPWM8B – – – PD0_GPIO16 GPIO16 SPISIMOA – – – PD1_GPIO17 GPIO17 SPISOMIA – – – PD2_GPIO18 GPIO18 SPICLKA – – – PD3_GPIO19 GPIO19 SPISTEA – – – PD4_GPIO20 GPIO20 EQEP1A MDXA – – PD5_GPIO21 GPIO21 EQEP1B MDRA – – PD6_GPIO22 GPIO22 EQEP1S MCLKXA – – PD7_GPIO23 GPIO23 EQEP1I MFSXA – – PE0_GPIO24 GPIO24 ECAP1 EQEP2A – – PE1_GPIO25 GPIO25 ECAP2 EQEP2B – – PE2_GPIO26 GPIO26 ECAP3 EQEP2I – – PE3_GPIO27 GPIO27 ECAP4 EQEP2S – – PE4_GPIO28 GPIO28 SCIRXDA – – – PE5_GPIO29 GPIO29 SCITXDA – – – PE6_GPIO30 GPIO30 – – EPWM9A – PE7_GPIO31 GPIO31 – – EPWM9B – PF0_GPIO32 GPIO32 I2CASDA SCIRXDA ADCSOCAO – PF1_GPIO33 GPIO33 I2CASCL EPWMSYNCO ADCSOCBO – PF2_GPIO34 GPIO34 ECAP1 SCIRXDA XCLKOUT – PF3_GPIO35 GPIO35 SCITXDA – – – PF4_GPIO36 GPIO36 SCIRXDA – – – PF5_GPIO37 GPIO37 ECAP2 – – USB0VBUS PF6_GPIO38 GPIO38 – – – (1) BlankfieldsrepresentReservedfunctions. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 75 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table2-29.GPIO_MUX1 Pin Assignments (C28x PeripheralModes) (1)(continued) C28x C28x C28x C28xAnalog Mode Device Pin Name Peripheral Peripheral Peripheral Peripheral(USB Pins) Mode 0 Mode 1 Mode 2 Mode 3 – PG0_GPIO40 GPIO40 – – – – PG1_GPIO41 GPIO41 – – – USB0DM PG2_GPIO42 GPIO42 – – – – PG3_GPIO43 GPIO43 – – – USB0DP PG5_GPIO45 GPIO45 – – – USB0ID PG6_GPIO46 GPIO46 – – – – PG7_GPIO47 GPIO47 – – – – PH0_GPIO48 GPIO48 ECAP5 – – – PH1_GPIO49 GPIO49 ECAP6 – – – PH2_GPIO50 GPIO50 EQEP1A – – – PH3_GPIO51 GPIO51 EQEP1B – – – PH4_GPIO52 GPIO52 EQEP1S – – – PH5_GPIO53 GPIO53 EQEP1I – – – PH6_GPIO54 GPIO54 SPISIMOA – EQEP3A – PH7_GPIO55 GPIO55 SPISOMIA – EQEP3B – PJ0_GPIO56 GPIO56 SPICLKA – EQEP3S – PJ1_GPIO57 GPIO57 SPISTEA – EQEP3I – PJ2_GPIO58 GPIO58 MCLKRA – EPWM7A – PJ3_GPIO59 GPIO59 MFSRA – EPWM7B – PJ4_GPIO60 GPIO60 – – EPWM8A – PJ5_GPIO61 GPIO61 – – EPWM8B – PJ6_GPIO62 GPIO62 – – EPWM9A PJ7_GPIO63/– GPIO63 – – EPWM9BXCLKIN – PC4_GPIO68 GPIO68 – – – – PC5_GPIO69 GPIO69 – – – – PC6_GPIO70 GPIO70 – – – – PC7_GPIO71 GPIO71 – – –

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.16.2 GPIO_MUX2

The eightpinsoftheGPIO_MUX2 blockcan be selectivelymapped toeightGeneral-PurposeInputs,eight General-PurposeOutputs,or six COMPOUT outputsfrom the Analog Comparator peripheral.Each GPIO_MUX2 pincan have a pullupenabledordisabled.On reset,allpinsoftheGPIO_MUX2 blockare configuredas analoginputs,and theGPIO functionisdisabled.The GPIO_MUX2 blockisprogrammed througha separatesetofregistersfromthoseused toprogramGPIO_MUX1. The multipleregistersresponsibleforconfiguringtheGPIO_MUX2 pinsare organizedinregistersetG. They are accessibleby the C28x CPU only.The middleportionof Figure2-16 shows setG of Control Subsystem registers,plus muxing logicforthe associatedeightGPIO pins.The GPGMUX1 register selectsone ofsixpossibledigitaloutputsignalsfromanalogcomparators,orone ofeightgeneral-purpose GPIO digitaloutputs.The GPGPUD registerdisablespullupsfor the GPIO_MUX2 pins when a correspondingbitof thatregisterissetto“1”. Other registersof setG allowreadingand writingof the eightGPIO bits,as wellas settingthedirectionforeach ofthebits(readorwrite).See Table2-30forthe mapping ofcomparatoroutputsand GPIO totheeightpinsofGPIO_MUX2. PeripheralModes 0,1,2,and 3 are chosen by settingselectedbitpairsofGPGMUX1 registerto“00”, “01”, “10”, and “11”, respectively.For example, settingbits5–4 of the GPGMUX1 registerto “00” (PeripheralMode 0) assignspinGPIO130 tointernalsignalGPIO130 (digitalGPIO). Settingbits5–4 of theGPGMUX1 registerto“11” (PeripheralMode 3) assignspinGPIO130 tointernalsignalCOMP6OUT coming from Analog Comparator 6. PeripheralModes 1 and 2 are reservedand are not currently available. Table2-30.GPIO_MUX2 Pin Assignments (C28x PeripheralModes) (1) C28x C28x C28x C28x Device Pin Name Peripheral Peripheral Peripheral Peripheral Mode 0 Mode 1 Mode 2 Mode 3 GPIO128 GPIO128 – – – GPIO129 GPIO129 – – COMP1OUT GPIO130 GPIO130 – – COMP6OUT GPIO131 GPIO131 – – COMP2OUT GPIO132 GPIO132 – – COMP3OUT GPIO133 GPIO133 – – COMP4OUT GPIO134 GPIO134 – – – GPIO135 GPIO135 – – COMP5OUT (1) BlankfieldsrepresentReservedfunctions. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 77 SubmitDocumentationFeedback

PRODUCT□PREVIEW ONE OF 10 AIO_MUX2 PINS AIOSET REG AIOCLEAR REG AIOTOGGLE REG AIODIR REG AIO_MUX2 AIODAT REG ANALOG COMMON INTERFACE BUS C28x CPU ADC AIOMUX2 REG C28 CPU BUSANALOG BUS GPIOPUR REGGPGPUD REG ‘1’ PULL-UP DISABLED ON RESET PULL UP DIS GPGDIR REG AIODIR REG ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 AIO18 AIO20 AIO22 AIO28 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 ONE OF 8 GPIO_MUX2 PINS GPGSET REG GPGCLEAR REG GPGTOGGLE REG GPGDIR REG GPIO_MUX2 GPGDA T REG COMPARATOR + DAC UNITS GPGMUX1 REG COMPA1 COMPA2 COMPA3 COMPB2 COMPA4 COMPA5 COMPA6 COMPB5 COMPOUT1 COMPOUT2 COMPOUT3 COMPOUT4 COMPOUT5 COMPOUT6 ONE OF 10 AIO_MUX1 PINS AIOSET REG AIOCLEAR REG AIOTOGGLE REG AIODIR REG AIO_MUX1 AIODAT REG ADC AIOMUX1 REG AIODIR REG ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 AIO2 AIO4 AIO6 AIO12 ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 GPIO128 GPIO129 GPIO130 GPIO131 GPIO132 GPIO133 GPIO134 GPIO135 F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure2-16.Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.16.3 AIO_MUX1

The tenpinsofAIO_MUX1 can be selectivelymapped througha dedicatedsetofregistersto12 analog inputsforADC1 peripheral,sixanaloginputsforComparatorperipherals,fourGeneral-PurposeInputs,or fourGeneral-PurposeOutputs.Note thatwhileAIO_MUX1 has been named afterthe analog signals passingthroughit,theGPIOs (herecalledAIOs)arestilldigital,althoughwithfewerfeaturesthanthosein theGPIO_MUX1 and GPIO_MUX2 blocks— forexample,theydo notofferpullups.On reset,allpinsofthe AIO_MUX1 blockare configuredas analoginputsand the GPIO functionisdisabled.The AIO_MUX1 blockisprogrammed througha separatesetofregistersfromthoseused toprogramAIO_MUX2. The multipleregistersresponsibleforconfiguringthe AIO_MUX1 pinsare accessibleby the C28x CPU only.The top portionof Figure2-16 shows ControlSubsystem registersand muxing logicforthe associatedtenAIO pins.The AIOMUX1 registerselectsone oftenpossibleanaloginputsignalsorone of fourgeneral-purposeAIO inputs.Otherregistersallowreadingand writingofthefourAIO bits,as wellas settingthedirectionforeach ofthebits(reador write).See Table2-31 forthemapping ofanaloginputs and AIOs tothetenpinsofAIO_MUX1. AIO Mode 0 ischosen by settingselectedodd bitsoftheAIOMUX1 registerto‘0’.AIO Mode 1 ischosen by settingselectedodd bitsoftheAIOMUX1 registerto‘1’.For example,settingbit5 oftheAIOMUX1 registerto‘0’assignspinADC1INA2 tointernalsignalAIO2 (digitalGPIO).Settingbit5 oftheAIOMUX1 registerto ‘1’ assignspin ADC1INA2 to analog inputsADC1INA2 or COMPA1 (onlyone should be enabledata timeintherespectiveanalogmodule).Currently,alleven bitsoftheAIOMUX1 registerare “don’tcares”. Table2-31.AIO_MUX1 Pin Assignments (C28x AIO Modes) (1)(2) Device Pin Name C28x AIO Mode 0(3) C28x AIO Mode 1(4) ADC1INA0 – ADC1INA0 ADC1INA2 AIO2 ADC1INA2, COMPA1 ADC1INA3 – ADC1INA3 ADC1INA4 AIO4 ADC1INA4, COMPA2 ADC1INA6 AIO6 ADC1INA6, COMPA3 ADC1INA7 – ADC1INA7 ADC1INB0 – ADC1INB0 ADC1INB3 – ADC1INB3 ADC1INB4 AIO12 ADC1INB4, COMPB2 ADC1INB7 – ADC1INB7 (1) BlankfieldsrepresentReservedfunctions. (2) Foreach fieldwithtwo pins(forexample,ADC1INA2, COMPA1), onlyone pinshouldbe enabledata time;theotherpinshouldbe disabled.Use registersinsidetherespectivedestinationanalogperipheralstoenableordisabletheseinputs. (3) AIO Mode 0 representsdigitalgeneral-purposeinputsoroutputs. (4) AIO Mode 1 representsanaloginputsforADC1 ortheComparatormodule. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 79 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.16.4 AIO_MUX2

The tenpinsofAIO_MUX2 can be selectivelymapped througha dedicatedsetofregistersto12 analog inputsforADC2 peripheral,sixanaloginputsforComparatorperipherals,fourGeneral-PurposeInputs,or fourGeneral-PurposeOutputs.Note thatwhileAIO_MUX2 has been named afterthe analog signals passingthroughit,theGPIOs (herecalledAIOs)arestilldigital,althoughwithfewerfeaturesthanthosein theGPIO_MUX1 and GPIO_MUX2 blocks— forexample,theydo notofferpullups.On reset,allpinsofthe AIO_MUX2 blockare configuredas analoginputsand the GPIO functionisdisabled.The AIO_MUX2 blockisprogrammed througha separatesetofregistersfromthoseused toprogramAIO_MUX1. The multipleregistersresponsibleforconfiguringthe AIO_MUX2 pinsare accessibleby the C28x CPU only.The bottom portionof Figure2-16 shows ControlSubsystem registersand muxing logicforthe associatedtenAIO pins.The AIOMUX2 registerselectsone oftenpossibleanaloginputsignalsorone of fourgeneral-purposeAIO inputs.Otherregistersallowreadingand writingofthefourAIO bits,as wellas settingthedirectionforeach ofthebits(reador write).See Table2-32 forthemapping ofanaloginputs and AIOs tothetenpinsofAIO_MUX2. PeripheralModes 1 and 2 arecurrentlynotavailable. AIO Mode 0 ischosen by settingselectedodd bitsoftheAIOMUX2 registerto‘0’.AIO Mode 1 ischosen by settingselectedodd bitsoftheAIOMUX2 registerto‘1’.For example,settingbit9 oftheAIOMUX2 registerto‘0’assignspinADC2INA4 tointernalsignalAIO20 (digitalGPIO).Settingbit9 oftheAIOMUX2 registerto ‘1’ assignspin ADC2INA4 to analog inputsADC2INA4 or COMPA5 (onlyone should be enabledata timeintherespectiveanalogmodule).Currently,alleven bitsoftheAIOMUX2 registerare “don’tcares”. Table2-32.AIO_MUX2 Pin Assignments (C28x AIO Modes) (1)(2) Device Pin Name C28x AIO Mode 0(3) C28x AIO Mode 1(4) ADC2INA0 – ADC2INA0 ADC2INA2 AIO18 ADC2INA2, COMPA4 ADC2INA3 – ADC2INA3 ADC2INA4 AIO20 ADC2INA4, COMPA5 ADC2INA6 AIO22 ADC2INA6, COMPA6 ADC2INA7 – ADC2INA7 ADC2INB0 – ADC2INB0 ADC2INB3 – ADC2INB3 ADC2INB4 AIO28 ADC2INB4, COMPB5 ADC2INB7 – ADC2INB7 (1) BlankfieldsrepresentReservedfunctions. (2) Foreach fieldwithtwo pins(forexample,ADC2INA6, COMPA6), onlyone pinshouldbe enabledata time;theotherpinshouldbe disabled.Use registersinsidetherespectivedestinationanalogperipheralstoenableordisabletheseinputs. (3) AIO Mode 0 representsdigitalgeneral-purposeinputsoroutputs. (4) AIO Mode 1 representsanaloginputsforADC2 ortheComparatormodule.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

2.17 Emulation/JTAG

Concertodeviceshave two typesofemulationportstosupportdebug operations:the7-pinTIJTAG port and the 5-pinCortex™ -M3 InstrumentationTrace Macrocell(ITM)port.The 7-pinTI JTAG portcan be used toconnecttodebug toolsviatheTI 14-pinJTAG header or theTI 20-pinJTAG header.The 5-pin Cortex™ -M3 ITM portcan onlybe accessedthroughtheTI20-pinJTAG header. The JTAG porthas seven dedicatedpins:TRST, TMS, TDI,TDO, TCK, EMU0, and EMU1. The TRST signalshouldalways be pulleddown viaa 2.2-kΩ pulldownresistoron the board.EMU0 and EMU1 signalsshouldbe pulledup througha pairofpullupsrangingfrom 2.2kΩ to4.7kΩ (dependingon the drivestrengthofthedebuggerports).The JTAG portisTI’s standarddebug port. The ITM portuses fiveGPIO pins thatcan be mapped to internalCortex™ -M3 ITM tracesignals: TRACE0, TRACE1, TRACE2, TRACE3, and TRACECLK. This portis typicallyused foradvanced softwaredebug. TIemulators,and thosefromothermanufacturers,can connecttoConcertodevicesviaTI’s 14-pinJTAG header or 20-pinJTAG header.See Figure2-17 to see how the 14-pinJTAG header connectsto Concerto’s JTAG portsignals.Note thatthe14-pinheaderdoes notsupporttheITM debug mode. Figure2-18shows two possibleways toconnectthe20-pinheadertoConcerto’s emulationpins.The left sideofthedrawingshows allseven JTAG signalsconnectingtothe20-pinheadersimilartotheway the 14-pinheader was connected.Note thatthe JTAG EMU0 and EMU1 signalsare mapped to the correspondingterminalson the20-pinheader.Inthismode, header terminalsEMU2, EMU3, and EMU4 areleftunconnectedand theITM tracemode isnotavailable. The rightsideofthedrawingshows thesame 20-pinheadernow connectedtofiveITM signalsand fiveof seven JTAG signals.Note thatConcerto’s EMU0 and EMU1 signalsare leftunconnectedinthismode; thus,the emulationfunctionsassociatedwiththesetwo signalsare not availablewhen debuggingwith ITM trace. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 81 SubmitDocumentationFeedback

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PRODUCT□PREVIEW ITM trace from M3 PROCESSOR TMS TRST TDI EMU1 EMU0 TDO TCK CONCERTO F28M35x TRACED0 TRACED1 TRACECLK TRACED2 TRACED3 PF3_GPIO35 PG3_GPIO43 PF2_GPIO34 PF0_GPIO32 PF1_GPIO33 JT AG PINS GPIO PINS TMS TDI nTRST PD TDIS KEY TDO GND RTCK GND TCK EMU0 GND RESETn EMU1 GND EMU2 EMU3 EMU4 GND TI 20-PIN JTAG HEADER 2.2K 4.7K 3.3V 4.7K ITM trace from M3 PROCESSOR TMS TRST TDI EMU1 EMU0 TDO TCK CONCERTO F28M35x TRACED0 TRACED1 TRACECLK TRACED2 TRACED3 JT AG PINS GPIO PINS TMS TDI nTRST PD TDIS KEY TDO GND RTCK GND TCK EMU0 GND RESETn EMU1 GND EMU2 EMU3 EMU4 GND TI 20-PIN JTAG HEADER 2.2K 4.7K 104 103 A LOW PULSE FROM THE EMULATOR CAN BE TIED WITH OTHER RESET SOURCES TO RESET THE BOARD 3.3V 4.7K NC NC NC NC NC OPEN DRAIN OPEN DRAIN A LOW PULSE FROM THE EMULATOR CAN BE TIED WITH OTHER RESET SOURCES TO RESET THE BOARD NC NC NC NC NC 104 103 PF3_GPIO35 PG3_GPIO43 PF2_GPIO34 PF0_GPIO32 PF1_GPIO33 F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure2-18.Connecting toTI20-PinJTAG Emulator Header Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 83 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.18 Code SecurityModule (CSM)

The Code SecurityModule (CSM) isa securityfeatureincorporatedinConcerto™ devices.The CSM preventsaccess and visibilityto on-chipsecurememories by unauthorizedpersons— thatis,the CSM preventsduplicationand reverse-engineeringofproprietarycode.The word "secure"means thataccessto on-chipsecurememories isprotected.The word "unsecure"means thataccesstoon-chipsecurememory isnotprotected— thatis,thecontentsofthememory couldbe readby any means (forexample,by usinga debuggingtoolsuch as Code Composer Studio™ ).

2.18.1 FunctionalDescription

The securitymodule restrictsthe CPU access to on-chipsecurememory withoutinterruptingor stalling CPU execution.When a read occurstoa protectedmemory location,theread returnsa zerovalueand CPU executioncontinueswiththenextinstruction.Thisprocess,ineffect,blocksreadand writeaccessto variousmemories throughtheJTAG portor externalperipherals.Securityisdefinedwithrespecttothe accessofon-chipsecurememories and preventsunauthorizedcopyingofproprietarycode ordata. The zone issecure when CPU access to the on-chipsecure memories associatedwiththatzone is restricted.When secure,two levelsofprotectionarepossible,dependingon where theprogram counteris currentlypointing.Ifcode iscurrentlyrunningfrominsidesecurememory, onlyan accessthroughJTAG is blocked (thatis,through the emulator).This process allowssecure code to access secure data. Conversely,ifcode isrunningfromunsecurememory, allaccessestosecurememories areblocked.User code can dynamicallyjump in and out of secure memory, therebyallowingsecure functioncallsfrom unsecurememory. Similarly,interruptserviceroutinescan be placedinsecurememory, even ifthemain programloopisrunfromunsecurememory. The code securitymechanism presentinthisdeviceoffersdual-zonesecurityfortheCortex™ -M3 code and single-zonesecurityfortheC28x code.Incase ofdual-zonesecurityon themastersubsystem,the differentsecure memories (RAMs and flashsectors)can be assignedto differentsecurityzones by configuringthe GRABRAM and GRABSECT registersassociatedwitheach zone.FlashSectorN and FlashSectorA are dedicatedto Zone1 and Zone2, respectively,and cannotbe allocatedto any other zone by configuration.Similarly,flashsectorsgetassignedtodifferentzones based on thesettinginthe GRABSECT registers. Securityisprovidedby a CSM password of128 bitsofdata(four32-bitwords)thatisused tosecureor unsecure the zones.Each zone has itsown 128-bitCSM password.The zone can be unsecured by executingthepasswordmatch flow(PMF). The CSM password foreach zone isstoredinitsdedicatedflashsector.The password storagelocations inthe flashsectorstorethe CSM password.The password isselectedby the system designer.Ifthe password locationsofa zone have all128 bitsas ones,thezone isconsidered"unsecure".Sincenew flashdeviceshave erasedflash(allones),onlya readofthepassword locationsisrequiredtobringany zone intounsecuremode. Ifthe password locationsof a zone have all128 bitsas zeros,the zone is considered"secure",regardlessof the contentsof the CSMKEY registers.The user shouldnot use all zerosas a passwordorresetthedeviceduringan eraseoftheflash.Resettingthedeviceduringan erase routinecan resultin eitheran all-zeroor unknown password.Ifa deviceisresetwhen the password locationsareallzeros,thedevicecannotbe unlockedby thepassword match flow.Usinga password of allzeroswillseriouslylimittheuser’s abilitytodebug securecode orreprogramtheflash. NOTE Ifa deviceisresetwhilethepassword locationsofa zone containallzerosor an unknown value,thatzone willbe permanentlylockedunlessa method torun theflasheraseroutine from secure SARAM is embedded intothe flashor OTP. Care must be taken when implementingthisproceduretoavoidintroducinga securityhole.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 2.19 µCRC Module The µCRC module ispartofthemastersubsystem.Thismodule can be used by Cortex™ -M3 softwareto compute CRC on data and program,which are storedat memory locationsthatare addressableby Cortex™ -M3.On thisdevice,theCortex™ -M3 FlashBank and ROM aremapped tothecode space thatis onlyaccessed by theICODE/DCODE bus ofCortex™ -M3; and RAMs are mapped on theSRAM space thatisaccessibleby theSYSTEM bus.Hence, theµCRC module snoops boththeDCODE and SYSTEM buses tosupportCRC calculationfordataand program.

2.19.1 FunctionalDescription

The µCRC module snoops boththeDCODE and SYSTEM buses tosupportCRC calculationfordataand program.To allowinterruptsexecutioninbetween CRC calculationsfora blockofdataand todiscardthe Cortex™ -M3 literalpool accesses in between executionsof the program (whichreads data forCRC calculation),the Cortex™ -M3 ROM, Flash,and RAMs are mapped to a mirroredmemory location.The µCRC module grabsdatafrom thebus tocalculateCRC onlyiftheaddressoftheread databelongsto mirroredmemory space.Aftergrabbing,theµCRC module performstheCRC calculationon thegrabbed dataand updatestheµCRC ResultRegister(µCRCRES). Thisregistercan be readatany timetogetthe calculatedCRC forallthepreviousreaddata.The µCRC module onlysupportsCRC calculationforbyte accesses.So, inordertocalculatetheCRC on a blockofdata,softwaremust performbyteaccessesto allthedata.For half-wordand word accesses,theµCRC module discardsthedataand does notupdate theµCRCRES register. NOTE Ifa read toa mirroredaddressspace isthrownfrom thedebugger (Code Composer Studio orany otherdebug platform),theµCRC module ignoresthereaddataand does notupdate theCRC resultforthatparticularread.

2.19.2 CRC Polynomials

The followingaretheCRC polynomialsthataresupportedby theµCRC module:

CRC8 Polynomial= 0x07
CRC16 Polynomial-1= 0x8005
CRC16 Polynomial-2= 0x1021
CRC32 Polynomial= 0x04C11DB7

2.19.3 CRC CalculationProcedure

The softwareprocedureforcalculatingCRC fora setofdatathatisstoredinCortex™ -M3 addressable memory space isas follows: 1. Save thecurrentvalueoftheµCRC ResultRegister(µCRCRES) intothestacktoallowcalculationof CRC innestedinterrupt 2. CleartheµCRC ResultRegister(µCRCRES) by settingtheCLEAR fieldoftheµCRC ControlRegister (µCRCCONTROL) to"1" 3. ConfiguretheµCRC polynomials(CRC8, CRC16-P1, CRC16-P2, orCRC32) intheµCRC ConfigurationRegister(µCRCCONFIG) 4. Read thedatafrommemory locationsforwhichCRC needs tobe calculatedusingmirroredaddress 5. Read theµCRCRES registertogetthecalculatedCRC value.Pop thelastsaved valueoftheCRC fromthestackand storethisvalueintotheµCRC ResultRegister(uCRCRES) Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOverview 85 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

2.19.4 CRC CalculationforData StoredInSecure Memory

Thisdevicehas dual-zonesecurityfortheCortex™ -M3 subsystem.SinceZoneX (X → 1/2)softwaredoes nothave accesstoprogram/datainZoneY (Y → 2/1),code runningfromZoneX cannotcalculateCRC on datastoredinZoneY memory. Similarly,inthecase ofExe-Onlyflashsectors,even thoughsoftwareis runningfromsame securezone,thesoftwarecannotreadthedatastoredinExe-Onlysectors.However, hardware does allowCRC computationon data storedin Exe-Only flashsectorsas long as the read access forthisdata isinitiatedby code runningfrom same securezone.These reads are justdummy readsand,inthiscase,readdataonlygoes totheµCRC module,nottotheCPU.

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PRODUCT□PREVIEW 108 2 3 4 5 P A0_GPIO0 GPIO135/COMP5OUT (A) 109 144 1 10 1 1 1 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 120 121 PG5_GPIO45 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 6 7 8 9 10 1 112 13 14 15 16 17 18 19 20 21 22 23 23 24 25 26 27 27 28 29 30 31 32 33 34 35 36 10710610510410310210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 V DD18V DDIO V DDIOXRS P A1_GPIO1P A2_GPIO2P A3_GPIO3P A4_GPIO4 V DDIO V DD12 P A5_GPIO5P A6_GPIO6P A7_GPIO7PB0_GPIO8 FL T1V DDIO PB1_GPIO9PB2_GPIO10PB3_GPIO1 1 FL T2 PE6_GPIO30PE7_GPIO31 V DD12 V DDIO PB6_GPIO14PB7_GPIO15PD2_GPIO18 PD3_GPIO19PB4_GPIO12PB5_GPIO13PE2_GPIO26PE3_GPIO27 V DDIO PH3_GPIO51PH2_GPIO50 PC4_GPIO68 PC5_GPIO69 PC6_GPIO70 PC7_GPIO71 PH0_GPIO48 PH1_GPIO49 PE0_GPIO24 VDDIO PE1_GPIO25 PH4_GPIO52 PH5_GPIO53 PF4_GPIO36 PG0_GPIO40 PG1_GPIO41 PF5_GPIO37 PG7_GPIO47 PJ6_GPIO62 VDDIO VDD12 PJ5_GPIO61 PJ4_GPIO60 VDD12 VDDIO PJ3_GPIO59 PJ2_GPIO58 PJ1_GPIO57 PJ0_GPIO56 PD5_GPIO21 PD4_GPIO20 VDD12 VDDIO PD7_GPIO23 PF6_GPIO38 PG6_GPIO46 PG2_GPIO42 PD6_GPIO22V DDIO V DD12 PE5_GPIO29PE4_GPIO28PG3_GPIO43PH6_GPIO54PH7_GPIO55PF3_GPIO35PF2_GPIO34EMU0TDOTRSTEMU1TMSTDITCKV DD12 NCV DDIO X1V SSOSC X2V DDIO PJ7_GPIO63PD1_GPIO17V DD12 V DDIO VREG12ENPD0_GPIO16PF1_GPIO33PF0_GPIO32V DDIO V DDIO V DDIO V DD18 GPIO134 GPIO133/COMP4OUT GPIO132/COMP3OUT VREG18EN ADC1INB7 ADC1INB4 ADC1INB3 ADC1INB0 VSSA1 VDDA1 ADC1VREFHI ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ADC2INA7 ADC2INA6 ADC2INA4 ADC2INA3 ADC2INA2 ADC2INA0 ADC2VREFHI VDDA2 VSSA2 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 GPIO128 GPIO129/COMP1OUT GPIO130/COMP6OUT GPIO131/COMP2OUT ARS F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

3 Device Pins

3.1 Pin Assignments

Figure3-1 shows the144-pinRFP PowerPAD ™ ThermallyEnhanced ThinQuad Flatpack(HTQFP) pin assignments. A. AllI/Os,exceptforGPIO135, areglitch-freeduringpower up and power down. See Section2.11. B. See Table3-1,TerminalFunctions,forthecompletemultiplexedsignalnames. Figure3-1.144-PinRFP PowerPAD ™ HTQFP (Top View) Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 87 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

3.2 TerminalFunctions

Table3-1describesthesignals. Table3-1.TerminalFunctions(1) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. ADC 1 ReferenceInputs,Analog Comparator Inputs,DAC Inputs,AIO Group 1 ADC1 ExternalHighReference– used onlywhenADC1V REFHI 120 I inADC externalreferencemode. ADC1 ExternalLow Reference– used onlywhenADC1V REFLO see VSSA1 I inADC externalreferencemode. ADC1INA0 121 I ADC1 Group A,Channel0 input ADC1INA2 I ADC1 Group A,Channel2 input COMPA1 122 I ComparatorInputA1 4 mA AIO2 I/O DigitalAIO2 ADC1INA3 123 I ADC1 Group A,Channel3 input ADC1INA4 I ADC1 Group A,Channel4 input COMPA2 124 I ComparatorInputA2 4 mA AIO4 I/O DigitalAIO4 ADC1INA6 I ADC1 Group A,Channel6 input COMPA3 125 I ComparatorInputA3 4 mA AIO6 I/O DigitalAIO6 ADC1INA7 126 I ADC1 Group A,Channel7 input ADC1INB0 117 I ADC1 Group B,Channel0 input ADC1INB3 116 I ADC1 Group B,Channel3 input ADC1INB4 I ADC1 Group B,Channel4 input COMPB2 115 I ComparatorInputB2 4 mA AIO12 I/O DigitalAIO12 ADC1INB7 114 I ADC1 Group B,Channel7 input ADC 2 ReferenceInputs,Analog Comparator Inputs,DAC Inputs,AIO Group 2 ADC2 ExternalHighReference– used onlywhenADC2V REFHI 133 I inADC externalreferencemode. ADC2 ExternalLow Reference– used onlywhenADC2V REFLO see VSSA2 I inADC externalreferencemode. ADC2INA0 132 I ADC2 Group A,Channel0 input ADC2INA2 I ADC2 Group A,Channel2 input COMPA4 131 I ComparatorInputA4 4 mA AIO18 I/O DigitalAIO18 ADC2INA3 130 I ADC2 Group A,Channel3 input ADC2INA4 I ADC2 Group A,Channel4 input COMPA5 129 I ComparatorInputA5 4 mA AIO20 I/O DigitalAIO20 ADC2INA6 I ADC2 Group A,Channel6 input COMPA6 128 I ComparatorInputA6 4 mA AIO22 I/O DigitalAIO22 ADC2INA7 127 I ADC2 Group A,Channel7 input ADC2INB0 136 I ADC2 Group B,Channel0 input ADC2INB3 137 I ADC2 Group B,Channel3 input

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. ADC2INB4 I ADC2 Group B,Channel4 input COMPB5 138 I ComparatorInputB5 4 mA AIO28 I/O DigitalAIO28 ADC2INB7 139 I ADC2 Group B,Channel7 input ADC Modules Analog Power and Ground 3.3-VAnalogModule 1 Power Pin.TiewithVDDA1 119 a 2.2-µF capacitor(typical)closetothepin. 3.3-VAnalogModule 2 Power Pin.TiewithVDDA2 134 a 2.2-µF capacitor(typical)closetothepin. AnaloggroundforADC1, ADC1V REFLO ,VSSA1 118 COMP1 –3,and DAC1 –3 AnaloggroundforADC2, ADC2V REFLO ,VSSA2 135 COMP4 –6,and DAC4 –6 Analog Comparator Results(Digital)and GPIO Group 2 (C28x Access Only) GPIO128 140 I/O General-purposeinput/output128 PU 4 mA GPIO129 I/O General-purposeinput/output129

141 PU 4 mA

COMP1OUT O Compare resultfromAnalogComparator1 GPIO130 I/O General-purposeinput/output130

142 PU 4 mA

COMP6OUT O Compare resultfromAnalogComparator6 GPIO131 I/O General-purposeinput/output131

143 PU 4 mA

COMP2OUT O Compare resultfromAnalogComparator2 GPIO132 I/O General-purposeinput/output132

112 PU 8 mA

COMP3OUT O Compare resultfromAnalogComparator3 GPIO133 I/O General-purposeinput/output133

111 PU 4 mA

COMP4OUT O Compare resultfromAnalogComparator4 GPIO134 110 I/O General-purposeinput/output134 PU 4 mA GPIO135 (4) I/O General-purposeinput/output135

109 PU 8 mA

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. GPIO Group 1 and PeripheralSignals PA0_GPIO0 I/O/Z General-purposeinput/output0 M_U0RX I UART-0 receivedata M_I2C1SCL 5 I/OD I2C-1clockopen-drainbidirectionalport PU 4 mA M_U1RX I UART-1 receivedata C_EPWM1A O Enhanced PWM-1 outputA PA1_GPIO1 I/O/Z General-purposeinput/output1 M_U0TX O UART-0 transmitdata M_I2C1SDA I/OD I2C-1dataopen-drainbidirectionalport M_U1TX 6 O UART-1 datatransmit PU 4 mA M_SSI1FSS I/O SSI-1frame C_EPWM1B O Enhanced PWM-1 outputB C_ECAP6 I/O Enhanced Capture-6input/output PA2_GPIO2 I/O/Z General-purposeinput/output2 M_SSI0CLK I/O SSI-0clock M_MIITXD2 7 O EMAC MIItransmitdatabit2 PU 4 mA M_U1CTS I UART-1 clear-to-sendmodem status C_EPWM2A O Enhanced PWM-2 outputA PA3_GPIO3 I/O/Z General-purposeinput/output3 M_SSI0FSS I/O SSI-0frame M_MIITXD1 O EMAC MIItransmitdatabit1 M_U1DCD 8 I UART-1 datacarrierdetect PU 4 mA M_SSI1CLK I/O SSI-1clock C_EPWM2B O Enhanced PWM-2 outputB C_ECAP5 I/O Enhanced Capture-5input/output PA4_GPIO4 I/O/Z General-purposeinput/output4 M_SSI0RX I SSI-0receivedata M_MIITXD0 O EMAC MIItransmitdatabit0

9 PU 4 mA

M_CAN0RX I CAN-0 receivedata M_U1DSR I UART-1 datasetready C_EPWM3A O Enhanced PWM-3 outputA PA5_GPIO5 I/O/Z General-purposeinput/output5 M_SSI0TX O SSI-0transmitdata M_MIIRXDV I EMAC MIIreceivedatavalid M_CAN0TX O CAN-0 transmitdata

12 PU 4 mA

M_U1RTS O UART-1 request-to-send C_EPWM3B O Enhanced PWM-3 outputB C_MFSRA I McBSP-A receiveframesync C_ECAP1 I/O Enhanced Capture-1input/output

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PA6_GPIO6 I/O/Z General-purposeinput/output6 M_I2C1SCL I/OD I2C-1clockopen-drainbidirectionalport Capture/Compare/PWM-1M_CCP1 I/O (General-purposeTimer) M_MIIRXCK I EMAC MIIreceiveclock M_CAN0RX I CAN-0 receivedata

13 PU 4 mA

USB-0 externalpower enableM_USB0EPEN O (optionallyused inhostmode) M_U1CTS I UART-1 clear-to-sendmodem status M_U1DTR O UART-1 dataterminalready C_EPWM4A O Enhanced PWM-4 outputA C_EPWMSYNCO O Enhanced PWM-4 externalsyncpulse PA7_GPIO7 I/O/Z General-purposeinput/output7 M_I2C1SDA I/OD I2C-1dataopen-drainbidirectionalport Capture/Compare/PWM-4M_CCP4 I/O (General-purposeTimer) M_MIIRXER I EMAC MIIreceiveerror M_CAN0TX O CAN-0 transmitdata Capture/Compare/PWM-3M_CCP3 I/O (General-purposeTimer)

14 PU 4 mAUSB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode)

M_U1DCD I UART-1 datacarrierdetect M_MIIRXD1 I EMAC MIIreceivedata1 M_U1RI I UART-1 ringindicatormodem status C_EPWM4B O Enhanced PWM-4 outputB C_MCLKRA I McBSP-A receiveclock C_ECAP2 I/O Enhanced Capture-1input/output PB0_GPIO8 I/O/Z General-purposeinput/output8 Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer) M_U1RX I UART-1 datareceivedata M_SSI2TX O SSI-2transmitdata15 PU 4 mA M_CAN1TX O CAN-1 transmitdata M_U4TX O UART-4 transmitdata C_EPWM5A O Enhanced PWM-5 outputA C_ADCSOCAO O ADC start-of-conversionA PB1_GPIO9 I/O/Z General-purposeinput/output9 Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer) Capture/Compare/PWM-1M_CCP1 I/O (General-purposeTimer)18 PU 4 mA M_U1TX O UART-1 transmitdata M_SSI2RX I SSI-2receivedata C_EPWM5B O Enhanced PWM-5 outputB C_ECAP3 I/O Enhanced Capture-3input/output Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 91 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PB2_GPIO10 I/O/Z General-purposeinput/output10 M_I2C0SCL I/OD I2C-0clockopen-drainbidirectionalport Capture/Compare/PWM-3M_CCP3 I/O (General-purposeTimer) Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer) USB-0 externalpower enable19 PU 4 mAM_USB0EPEN O (optionallyused inthehostmode) M_SSI2CLK I/O SSI-2clock M_CAN1RX I CAN-1 receivedata M_U4RX I UART-4 receivedata C_EPWM6A O Enhanced PWM-6 outputA C_ADCSOCBO O ADC start-of-conversionB PB3_GPIO11 I/O/Z General-purposeinput/output11 M_I2C0SDA I/OD I2C-0dataopen-drainbidirectionalport USB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode)

20 PU 4 mAM_SSI2FSS I/O SSI-2frame

M_U1RX I UART-1 receivedata C_EPWM6B O Enhanced PWM-6 outputB C_ECAP4 I/O Enhanced Capture-4input/output PB4_GPIO12 I/O/Z General-purposeinput/output12 M_U2RX I UART-2 receivedata M_CAN0RX I CAN-0 receivedata M_U1RX I UART-1 receivedata

30 PU 4 mA

M_EPI0S23 I/O EPI-0signal23 M_CAN1TX O CAN-1 transmitdata M_SSI1TX O SSI-1transmitdata C_EPWM7A O Enhanced PWM-7 outputA PB5_GPIO13 I/O/Z General-purposeinput/output13 Capture/Compare/PWM-5M_CCP5 I/O (General-purposeTimer) Capture/Compare/PWM-6M_CCP6 I/O (General-purposeTimer) Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer) M_CAN0TX O CAN-0 transmitdata31 PU 4 mA Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer) M_U1TX O UART-1 transmitdata M_EPI0S22 I/O EPI-0signal22 M_CAN1RX I CAN-1 receivedata M_SSI1RX I SSI-1receivedata C_EPWM7B O Enhanced PWM-7 outputB

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PB6_GPIO14 I/O/Z General-purposeinput/output14 Capture/Compare/PWM-1M_CCP1 I/O (General-purposeTimer) Capture/Compare/PWM-7M_CCP7 I/O (General-purposeTimer) Capture/Compare/PWM-5M_CCP5 I/O (General-purposeTimer)26 PU 4 mA M_EPI0S37 (5) I/O EPI-0signal37 M_MIICRS I EMAC MIIcarriersense M_I2C0SDA I/OD I2C-0dataopen-drainbidirectionalport M_U1TX O UART-1 transmitdata M_SSI1CLK I/O SSI-1clock C_EPWM8A O Enhanced PWM-8 outputA PB7_GPIO15 I/O/Z General-purposeinput/output15 M_EXTNMI I Cortex™ -M3 externalnon-maskableinterrupt M_MIIRXD1 I EMAC MIIreceivedata1 M_EPI0S36 (5) I/O EPI-0signal36

27 PU 4 mA

M_I2C0SCL I/OD I2C-0clockopen-drainbidirectionalport M_U1RX I UART-1 receivedata M_SSI1FSS I/O SSI-1frame C_EPWM8B O Enhanced PWM-8 outputB PD0_GPIO16 I/O/Z General-purposeinput/output16 M_CAN0RX I CAN-0 receivedata M_U2RX I UART-2 receivedata M_U1RX I UART-1 receivedata Capture/Compare/PWM-6M_CCP6 I/O (General-purposeTimer) M_MIIRXDV I EMAC MIIreceivedatavalid

102 PU 4 mA

M_U1CTS I UART-1 clear-to-sendmodem status M_MIIRXD2 I EMAC MIIreceivedata2 M_SSI0TX O SSI-0transmitdata M_CAN1TX O CAN-1 transmitdata USB-0 externalpower enableM_USB0EPEN O (optionallyused inthehostmode) C_SPISIMOA I/O SPI-Aslavein,masterout Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 93 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PD1_GPIO17 I/O/Z General-purposeinput/output17 M_CAN0TX O CAN-0 transmitdata M_U2TX O UART-2 transmitdata M_U1TX O UART-1 transmitdata Capture/Compare/PWM-7M_CCP7 I/O (General-purposeTimer) M_MIITXER O EMAC MIItransmiterror M_U1DCD I UART-1 datacarrierdetect98 PU 4 mA Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer) M_MIICOL I EMAC MIIcollisiondetect M_SSI0RX I SSI-0receivedata M_CAN1RX I CAN-1 receivedata USB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode) C_SPISOMIA I/O SPI-Amasterin,slaveout PD2_GPIO18 I/O/Z General-purposeinput/output18 M_U1RX I UART-1 receivedata Capture/Compare/PWM-6M_CCP6 I/O (General-purposeTimer) Capture/Compare/PWM-5M_CCP5 I/O (General-purposeTimer)28 PU 4 mA M_EPI0S20 I/O EPI-0signal20 M_SSI0CLK I/O SSI-0clock M_U1TX O UART-1 transmitdata M_CAN0RX I CAN-0 receivedata C_SPICLKA I/O SPI-Aclock PD3_GPIO19 I/O/Z General-purposeinput/output19 M_U1TX O UART-1 transmitdata Capture/Compare/PWM-7M_CCP7 I/O (General-purposeTimer) Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer)29 PU 4 mA M_EPI0S21 I/O EPI-0signal21 M_SSI0FSS I/O SSI-0frame M_U1RX I UART-1 receivedata M_CAN0TX O CAN-0 transmitdata C_SPISTEA I/O SPI-Aslavetransmitenable

94 DevicePins Copyright© 2011–2012,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PD4_GPIO20 I/O/Z General-purposeinput/output20 Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer) Capture/Compare/PWM-3M_CCP3 I/O (General-purposeTimer) M_MIITXD3 O EMAC MIItransmitdata3

65 PU 4 mAM_U1RI I UART-1 ringindicatormodem status

M_EPI0S19 I/O EPI-0signal19 M_U3TX O UART-3 transmitdata M_CAN1TX O CAN-1 transmitdata C_EQEP1A I Enhanced QEP-1 inputA C_MDXA O McBSP-A transmitdata PD5_GPIO21 I/O/Z General-purposeinput/output21 Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer) Capture/Compare/PWM-4M_CCP4 I/O (General-purposeTimer) M_MIITXD2 O EMAC MIItransmitdata2

64 PU 6 mAM_U2RX I UART-2 receivedata

M_EPI0S28 I/O EPI-0signal28 M_U3RX I UART-3 receivedata M_CAN1RX I CAN-1 receivedata C_EQEP1B I Enhanced QEP-1 inputB C_MDRA I McBSP-A receivedata PD6_GPIO22 I/O/Z General-purposeinput/output22 M_MIITXD1 O EMAC MIItransmitdata1 M_U2TX O UART-2 transmitdata M_EPI0S29 I/O EPI-0signal29

73 PU 6 mA

M_I2C1SDA I/OD I2C-0dataopen-drainbidirectionalport M_U1TX O UART-1 transmitdata C_EQEP1S I/O Enhanced QEP-1 strobe C_MCLKXA O McBSP-A transmitclock PD7_GPIO23 I/O/Z General-purposeinput/output23 Capture/Compare/PWM-1M_CCP1 I/O (General-purposeTimer) M_MIITXD0 O EMAC MIItransmitdata0 M_U1DTR O UART-1 dataterminalready

68 PU 6 mAM_EPI0S30 I/O EPI-0signal30

M_I2C1SCL I/OD I2C-1clockopen-drainbidirectionalport M_U1RX I UART-1 receivedata C_EQEP1I I/O Enhanced QEP-1 index C_MFSXA O McBSP-A transmitframesync Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 95 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PE0_GPIO24 I/O/Z General-purposeinput/output24 M_SSI1CLK I/O SSI-1clock Capture/Compare/PWM-3M_CCP3 I/O (General-purposeTimer) M_EPI0S8 I/O EPI-0signal8 USB-0 externalpower errorstateM_USB0PFLT I43 PU 4 mA(optionallyused inthehostmode) M_SSI3TX O SSI-3transmitdata M_CAN0RX I CAN-1 receivedata M_SSI1TX O SSI-1transmitdata C_ECAP1 I/O Enhanced Capture-1input/output C_EQEP2A I Enhanced QEP-2 inputA PE1_GPIO25 I/O/Z General-purposeinput/output25 M_SSI1FSS I/O SSI-1frame Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer) Capture/Compare/PWM-6M_CCP6 I/O (General-purposeTimer)

45 PU 4 mAM_EPI0S9 I/O EPI-0signal9

M_SSI3RX I SSI-3receivedata M_CAN0TX O CAN-1 transmitdata M_SSI1RX O SSI-1receivedata C_ECAP2 I/O Enhanced Capture-2input/output C_EQEP2B I Enhanced QEP-2 inputB PE2_GPIO26 I/O/Z General-purposeinput/output26 Capture/Compare/PWM-4M_CCP4 I/O (General-purposeTimer) M_SSI1RX I SSI-1receivedata Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer)

32 PU 4 mAM_EPI0S24 I/O EPI-0signal24

M_SSI3CLK I/O SSI-3clock M_U2RX I UART-2 receivedata M_SSI1CLK I/O SSI-1clock C_ECAP3 I/O Enhanced Capture-3input/output C_EQEP2I I/O Enhanced QEP-2 index PE3_GPIO27 I/O/Z General-purposeinput/output27 Capture/Compare/PWM-1M_CCP1 I/O (General-purposeTimer) M_SSI1TX O SSI-1transmitdata Capture/Compare/PWM-7M_CCP7 I/O (General-purposeTimer)

33 PU 4 mAM_EPI0S25 I/O EPI-0signal25

M_SSI3FSS I/O SSI-3frame M_U2TX O UART-2 transmitdata M_SSI1FSS I/O SSI-1frame C_ECAP4 I/O Enhanced Capture-4input/output C_EQEP2S I/O Enhanced QEP-2 strobe

96 DevicePins Copyright© 2011–2012,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PE4_GPIO28 I/O/Z General-purposeinput/output28 Capture/Compare/PWM-3M_CCP3 I/O (General-purposeTimer) M_U2TX O UART-2 transmitdata Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer) M_MIIRXD0 I EMAC MIIreceivedata077 PU 4 mA M_EPI0S34 (5) I/O EPI-0signal34 M_U0RX I UART-0 receivedata M_EPI0S38 (5) I/O EPI-0signal38 USB-0 externalpower enableM_USB0EPEN O (optionallyused inthehostmode) C_SCIRXDA I SCI-A receivedata PE5_GPIO29 I/O/Z General-purposeinput/output29 Capture/Compare/PWM-5M_CCP5 I/O (General-purposeTimer) M_EPI0S35 (5) I/O EPI-0signal35 M_MIITXER 76 O EMAC MIItransmiterror PU 4 mA M_U0TX O UART-0 transmitdata USB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode) C_SCITXDA O SCI-A transmitdata PE6_GPIO30 I/O/Z General-purposeinput/output30 M_U1CTS I UART-1 clear-to-sendmodem status M_MDIOD 22 I/O EMAC management datainput/output PU 4 mA M_CAN0RX I CAN-0 receivedata C_EPWM9A O Enhanced PWM-9 outputA PE7_GPIO31 I/O/Z General-purposeinput/output31 M_U1DCD I UART-1 datacarrierdetect M_MIIRXD3 23 I EMAC MIIreceivedata3 PU 4 mA M_CAN0TX O CAN-0 transmitdata C_EPWM9B O Enhanced PWM-9 outputB PF0_GPIO32 I/O/Z General-purposeinput/output32 M_CAN1RX I CAN-1 receivedata M_MIIRXCK I EMAC MIIreceiveclock M_U1DSR I UART-1 datasetready M_I2C0SDA 104 I/OD I2C-0dataopen-drainbidirectionalport PU 4 mA M_TRACED2 O Tracedata2 C_I2CASDA I/OD I2C-Adataopen-drainbidirectionalport C_SCIRXDA I SCI-A receivedata C_ADCSOCAO O ADC start-of-conversionA(6) Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 97 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PF1_GPIO33 I/O/Z General-purposeinput/output33 M_CAN1TX O CAN-1 transmitdata M_MIIRXER I EMAC MIIreceiveerror M_U1RTS O UART-1 request-to-send Capture/Compare/PWM-3M_CCP3 I/O (General-purposeTimer)103 PU 4 mA M_I2C0SCL I/OD I2C-0clockopen-drainbidirectionalport M_TRACED3 O Tracedata3 C_I2CASCL I/OD I2C-Aclockopen-drainbidirectionalport C_EPWMSYNCO O Enhanced PWM syncout C_ADCSOCBO O ADC start-of-conversionB(6) PF2_GPIO34 I/O/Z General-purposeinput/output34 M_MIIPHYINTR I EMAC PHY MIIinterrupt M_EPI0S32 (5) I/O EPI-0signal32 M_SSI1CLK I/O SSI-1clock M_TRACECLK O Traceclock

82 PU 4 mA

M_XCLKOUT O Externaloutputclock C_ECAP1 I/O Enhanced Capture-1input/output C_SCIRXDA I SCI-A receivedata C_XCLKOUT O Externaloutputclock BOOT_3 I Bootpin3 PF3_GPIO35 I/O/Z General-purposeinput/output35 M_MDIOCK I EMAC management dataclock M_EPI0S33 (5) I/O EPI-0signal33 M_SSI1FSS I/O SSI-1frame

81 PU 4 mA

M_U0TX O UART-0 transmitdata M_TRACED0 O Tracedata0 C_SCITXDA O SCI-A transmitdata BOOT_2 I Bootpin2 PF4_GPIO36 I/O/Z General-purposeinput/output36 Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer) M_MDIOD I/O EMAC management datainput/output

48 PU 4 mAM_EPI0S12 I/O EPI-0signal12

M_SSI1RX I SSI-1receivedata M_U0RX I UART-0 receivedata C_SCIRXDA I SCI-A receivedata PF5_GPIO37 I/O/Z General-purposeinput/output37 Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer) M_MIIRXD3 I EMAC MIIreceivedata3

51 PU 4 mAM_EPI0S15 I/O EPI-0signal15

M_SSI1TX O SSI-1transmitdata M_MIITXEN O EMAC MIItransmitenable C_ECAP2 I/O Enhanced Capture-2input/output

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. General-purposeinput/output38. NOTE: Forthispin,onlytheUSB0VBUS function PF6_GPIO38 I/O/Z isavailableon siliconrevision0 devices(GPIO and thefourotherfunctionslistedarenot available). M_USB0VBUS Analog USB0 VBUS power (5-Vtolerant)69 PU 4 mA Capture/Compare/PWM-1M_CCP1 I/O (General-purposeTimer) M_MIIRXD2 I EMAC MIIreceivedata2 M_EPI0S38 (5) I/O EPI-0signal38 M_U1RTS O UART-1 request-to-send PF7_GPIO39 No Pin No Pin General-purposeinput/output39 isnotpinnedout. PG0_GPIO40 I/O/Z General-purposeinput/output40 M_U2RX I UART-2 receivedata M_I2C1SCL I/OD I2C-1clockopen-drainbidirectionalport USB-0 externalpower enableM_USB0EPEN O (optionallyused inthehostmode)49 PU 4 mA M_EPI0S13 I/O EPI-0signal13 M_MIIRXD2 I EMAC MIIreceivedata2 M_U4RX I UART-4 receivedata M_MIITXCK I EMAC MIItransmitclock PG1_GPIO41 I/O/Z General-purposeinput/output41 M_U2TX O UART-2 transmitdata M_I2C1SDA I/OD I2C-1dataopen-drainbidirectionalport M_EPI0S14 50 I/O EPI-0signal14 PU 4 mA M_MIIRXD1 I EMAC MIIreceivedata1 M_U4TX O UART-4 transmitdata M_MIITXER O EMAC MIItransmiterror PG2_GPIO42 I/O/Z General-purposeinput/output42 M_USB0DM Analog USB0 dataminus

71 PU 4 mA

M_MIICOL I EMAC MIIcollisiondetect M_EPI0S39 (5) I/O EPI-0signal39 PG3_GPIO43 I/O/Z General-purposeinput/output43 M_MIICRS I EMAC MIIcarriersense M_MIIRXDV 78 I EMAC MIIreceivedatavalid PU 4 mA M_TRACED1 O Tracedata1 BOOT_0 I Bootpin0 PG4_GPIO44 No Pin No Pin General-purposeinput/output44 isnotpinnedout. PG5_GPIO45 I/O/Z General-purposeinput/output45 M_USB0DP Analog USB0 dataplus Capture/Compare/PWM-5M_CCP5 I/O (General-purposeTimer)72 PU 4 mA M_MIITXEN O EMAC MIItransmitenable M_EPI0S40 (5) I/O EPI-0signal40 M_U1DTR O UART-1 dataterminalready Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 99 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. General-purposeinput/output46. NOTE: Forthispin,onlytheUSB0ID functionisPG6_GPIO46 I/O/Z availableon siliconrevision0 devices(GPIO and thethreeotherfunctionslistedarenotavailable).

70 PU 4 mAM_USB0ID Analog USB0 ID (5-Vtolerant)

M_MIITCK I EMAC MIItransmitclock M_EPI0S41 (5) I/O EPI-0signal41 M_U1RI I UART-1 receivedata PG7_GPIO47 I/O/Z General-purposeinput/output47 M_MIITXER O EMAC MIItransmiterror Capture/Compare/PWM-5M_CCP5 I/O (General-purposeTimer)52 PU 6 mA M_EPI0S31 I/O EPI-0signal31 M_MIICRS I EMAC MIIcarriersense BOOT_1 I Bootpin1 PH0_GPIO48 I/O/Z General-purposeinput/output48 Capture/Compare/PWM-6M_CCP6 I/O (General-purposeTimer) M_MIIPHYRST O EMAC PHY MIIreset

41 PU 4 mAM_EPI0S6 I/O EPI-0signal6

M_SSI3TX O SSI-3transmitdata M_MIITXD3 O EMAC MIItransmitdata3 C_ECAP5 I/O Enhanced Capture-5input/output PH1_GPIO49 I/O/Z General-purposeinput/output49 Capture/Compare/PWM-7M_CCP7 I/O (General-purposeTimer) M_EPI0S7 I/O EPI-0signal7

42 PU 4 mAM_MIIRXD0 I EMAC MIIreceivedata0

M_SSI3RX I SSI-3receivedata M_MIITXD2 O EMAC MIItransmitdata2 C_ECAP6 I/O Enhanced Capture-6input/output PH2_GPIO50 I/O/Z General-purposeinput/output50 M_EPI0S1 I/O EPI-0signal1 M_MIITXD3 O EMAC MIItransmitdata3

36 PU 4 mA

M_SSI3CLK I/O SSI-3clock M_MIITXD1 O EMAC MIItransmitdata1 C_EQEP1A I Enhanced QEP-1 inputA PH3_GPIO51 I/O/Z General-purposeinput/output51 USB-0 externalpower enableM_USB0EPEN O (optionallyused inthehostmode) M_EPI0S0 I/O EPI-0signal0

35 PU 4 mAM_MIITXD2 O EMAC MIItransmitdata2

M_SSI3FSS I/O SSI-3frame M_MIITXD0 O EMAC MIItransmitdata0 C_EQEP1B I Enhanced QEP-1 inputB

100 DevicePins Copyright© 2011–2012,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PH4_GPIO52 I/O/Z General-purposeinput/output52 USB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode) M_EPI0S10 I/O EPI-0signal10 M_MIITXD1 O EMAC MIItransmitdata146 PU 4 mA M_SSI1CLK I/O SSI-1clock M_U3TX O UART-3 transmitdata M_MIICOL I EMAC MIIcollisiondetect C_EQEP1S I/O Enhanced QEP-1 strobe PH5_GPIO53 I/O/Z General-purposeinput/output53 M_EPI0S11 I/O EPI-0signal11 M_MIITXD0 O EMAC MIItransmitdata0 M_SSI1FSS 47 I/O SSI-1frame PU 4 mA M_U3RX I UART-3 receivedata M_MIIPHYRST O EMAC PHY MIIreset C_EQEP1I I/O Enhanced QEP-1 index PH6_GPIO54 I/O/Z General-purposeinput/output54 M_EPI0S26 I/O EPI-0signal26 M_MIIRXDV I EMAC MIIreceivedatavalid M_SSI1RX I SSI-1receivedata M_MIITXEN 79 O EMAC MIItransmitenable PU 4 mA M_SSI0TX O SSI-0transmitdata M_MIIPHYINTR I EMAC PHY MIIinterrupt C_SPISIMOA I/O SPI-Aslavein,masterout C_EQEP3A I Enhanced QEP-1 inputA PH7_GPIO55 I/O/Z General-purposeinput/output55 M_MIIRXCK I EMAC MIIreceiveclock M_EPI0S27 I/O EPI-0signal27 M_SSI1TX O SSI-1transmitdata M_MIITXCK 80 I EMAC MIItransmitclock PU 4 mA M_SSI0RX I SSI-0receivedata M_MDIOCK O EMAC management dataclock C_SPISOMIA I/O SPI-Amasterin,slaveout C_EQEP3B I Enhanced QEP-3 inputB PJ0_GPIO56 I/O/Z General-purposeinput/output56 M_MIIRXER I EMAC MIIreceiveerror M_EPI016 I/O EPI-0signal16 M_I2C1SCL I/OD I2C-1clockopen-drainbidirectionalport

63 PU 4 mA

M_SSI0CLK I/O SSI-0clock M_MDIOD I/O EMAC management datainput/output C_SPICLKA I/O SPI-Aclock C_EQEP3S I/O Enhanced QEP-3 strobe Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 101 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PJ1_GPIO57 I/O/Z General-purposeinput/output57 M_EPI0S17 I/O EPI-0signal17 USB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode) M_I2C1SDA I/OD I2C-1dataopen-drainbidirectionalport

62 PU 4 mAM_MIIRXDV I EMAC MIIreceivedatavalid

M_SSI0FSS I/O SSI-0frame M_MIIRXD3 I EMAC MIIreceivedata3 C_SPISTEA I/O SPI-Aslavetransmitenable C_EQEP3I I/O Enhanced QEP-3 index PJ2_GPIO58 I/O/Z General-purposeinput/output58 M_EPI0S18 I/O EPI-0signal18 Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer) M_MIIRXCK I EMAC MIIreceiveclock

61 PU 4 mAM_SSI0CLK I/O SSI-0clock

M_U0TX O UART-0 transmitdata M_MIIRXD2 I EMAC MIIreceivedata2 C_MCLKRA I McBSP-A receiveclock C_EPWM7A O Enhanced PWM-7 outputA PJ3_GPIO59 I/O/Z General-purposeinput/output59 M_EPI0S19 I/O EPI-0signal19 M_U1CTS I UART-1 clear-to-send Capture/Compare/PWM-6M_CCP6 I/O (General-purposeTimer) M_MDIOCK O EMAC management dataclock60 PU 4 mA M_SSI0FSS I/O SSI-0frame M_U0RX I UART-0 receivedata M_MIIRXD1 I EMAC MIIreceivedata1 C_MFSRA I McBSP-A receiveframesync C_EPWM7B O Enhanced PWM-7 outputB PJ4_GPIO60 I/O/Z General-purposeinput/output60 M_EPI0S28 I/O EPI-0signal28 M_U1DCD I UART-1 datacarrierdetect Capture/Compare/PWM-4M_CCP4 I/O (General-purposeTimer)57 PU 6 mA M_MIICOL I EMAC MIIcollisiondetect M_SSI1CLK I/O SSI-1clock M_MIIRXD0 I EMAC MIIreceivedata0 C_EPWM8A O Enhanced PWM-8 outputA

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PJ5_GPIO61 I/O/Z General-purposeinput/output61 M_EPI0S29 I/O EPI-0signal29 M_U1DSR I UART-1 datasetready Capture/Compare/PWM-2M_CCP2 I/O (General-purposeTimer)56 PU 6 mA M_MIICRS I EMAC MIIcarriersense M_SSI1FSS I/O SSI-1frame M_MIIRXDV I EMAC MIIreceivedatavalid C_EPWM8B O Enhanced PWM-8 outputB PJ6_GPIO62 I/O/Z General-purposeinput/output62 M_EPI0S30 I/O EPI-0signal30 M_U1RTS O UART-1 request-to-send Capture/Compare/PWM-1M_CCP1 I/O (General-purposeTimer)53 PU 6 mA M_MIIPHYINTR I EMAC PHY MIIinterrupt M_U2RX I UART-2 receivedata M_MIIRXER I EMAC MIIreceiveerror C_EPWM9A O Enhanced PWM-9 outputA PJ7_GPIO63 I/O/Z General-purposeinput/output63 M_U1DTR O UART-1 dataterminalready Capture/Compare/PWM-0M_CCP0 I/O (General-purposeTimer) M_MIIPHYRST O EMAC PHY MIIreset

97 PU 4 mA

M_U2TX O UART-2 transmitdata M_MIIRXCK I EMAC MIIreceiveclock ExternaloscillatorinputforUSB PLL and CANM_XCLKIN I (alwaysavailable,see Figure2-15) C_EPWM9B O Enhanced PWM-9 outputB PC0_GPIO64 No Pin No Pin General-purposeinput/output64 isnotpinnedout. PC1_GPIO65 No Pin No Pin General-purposeinput/output65 isnotpinnedout. PC2_GPIO66 No Pin No Pin General-purposeinput/output66 isnotpinnedout. PC3_GPIO67 No Pin No Pin General-purposeinput/output67 isnotpinnedout. PC4_GPIO68 I/O/Z General-purposeinput/output68 Capture/Compare/PWM-5M_CCP5 I (General-purposeTimer) M_MIITXD3 O EMAC MIItransmitdata3 Capture/Compare/PWM-2M_CCP2 I37 (General-purposeTimer) PU 4 mA Capture/Compare/PWM-4M_CCP4 I (General-purposeTimer) M_EPI0S2 I/O EPI-0signal2 Capture/Compare/PWM-1M_CCP1 I (General-purposeTimer) Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 103 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. PC5_GPIO69 I/O/Z General-purposeinput/output69 Capture/Compare/PWM-1M_CCP1 I (General-purposeTimer) Capture/Compare/PWM-3M_CCP3 38 I PU 4 mA(General-purposeTimer) USB-0 externalpower enableM_USB0EPEN O (optionallyused inthehostmode) M_EPI0S3 I/O EPI-0signal3 PC6_GPIO70 I/O/Z General-purposeinput/output70 Capture/Compare/PWM-3M_CCP3 I (General-purposeTimer) M_U1RX I UART-1 receivedata

39 PU 4 mACapture/Compare/PWM-0M_CCP0 I (General-purposeTimer)

USB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode) M_EPI0S4 I/O EPI-0signal4 PC7_GPIO71 I/O/Z General-purposeinput/output71 Capture/Compare/PWM-4M_CCP4 I (General-purposeTimer) Capture/Compare/PWM-0M_CCP0 I (General-purposeTimer)40 PU 4 mA M_U1TX O UART-1 transmitdata USB-0 externalpower errorstateM_USB0PFLT I (optionallyused inthehostmode) M_EPI0S5 I/O EPI-0signal5

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. Resets DigitalSubsystem Reset(in)and Watchdog/Brown-outReset(out).Inmost applications,TIrecommends thattheXRS pinbe tiedwiththeARS pin.The DigitalSubsystem has a built-inpower-on-reset(POR) and brown-out- reset(BOR) circuitry.As such,no externalcircuitry isneeded togeneratea resetpulse.Duringa power-onorbrown-outcondition,thispinisdriven lowby theDigitalSubsystem.Thispinisalso drivenlowby theDigitalSubsystem when a watchdogresetoccurs.Duringwatchdogreset, theXRS pinisdrivenlowforthewatchdogreset durationof512 OSCCLK cycles.Ifneed be,an XRS 4 I/OD externalcircuitrymay alsodrivethispintoassert PU 4 mA devicereset.Inthiscase,TIrecommends thatthis pinbe drivenby an open-draindevice.An R-C circuitmust be connectedtothispinfornoise immunityreasons.Regardlessofthesource,a deviceresetcausestheDigitalSubsystem to terminateexecution.The Cortex™ -M3 program counterpointstotheaddresscontainedatthe location0x00000004.The C28 programcounter pointstotheaddresscontainedatthelocation 0x3FFFC0. When resetisdeactivated,execution beginsatthelocationdesignatedby theprogram counter.The outputbufferofthispinisan open- drainwithan internalpullup. AnalogSubsystem Reset(in)and Brown-out Reset(out).Inmost applications,TIrecommends thattheARS pinbe tiedwiththeXRS pin.The DigitalSubsystem has a built-inbrown-out-reset (BOR) circuitry.As such,no externalcircuitryis needed togeneratea resetpulse.Duringa power- on orbrown-outcondition,thispinisdrivenlowby theAnalogSubsystem.Ifneed be,an external ARS 144 I/OD circuitrymay alsodrivethispintoasserta device PU 4 mA reset.Inthiscase,TIrecommends thatthispinbe drivenby an open-draindevice.An R-C circuit must be connectedtothispinfornoiseimmunity reasons.Regardlessofthesource,theAnalog Subsystem resetcausesthedigitallogic associatedwiththeAnalogSubsystem,toenter resetstate.The outputbufferofthispinisan open-drainwithan internalpullup. Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 105 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. Clocks Externaloscillatorinputoron-chipcrystal- oscillatorinput.To use theon-chiposcillator,aX1 93 I quartzcrystalora ceramicresonatormust be connectedacrossX1 and X2.See Figure2-7. On-chipcrystal-oscillatoroutput.A quartzcrystal ora ceramicresonatormust be connectedacrossX2 95 O X1 and X2.IfX2 isnotused,itmust be left unconnected.See Figure2-7. ClockOscillatorGround Pin.Use thispinto connecttheGND ofexternalcrystalload VSSOSC 94 capacitorsorthegroundpinof3-terminalceramic resonatorswithbuilt-incapacitors.Do not connect toboardground.See Figure2-7. Externaloscillatorinput.Thispinfeedsa clockseeXCLKIN I froman external3.3-VoscillatortointernalUSBPJ7_GPIO63 PLL module and totheCAN peripherals. Externaloscillatoroutput.Thispinoutputsa clock see divided-downfromtheinternalPLL System Clock.XCLKOUT O/ZPF2_GPIO34 The divideratioisdefinedintheXCLKCFG register. Boot Pins One offourbootmode pins.BOOT_0 selectsaseeBOOT_0 I specificconfigurationsourcefromwhichthe PUPG3_GPIO43 Concertodevicebootson start-up. One offourbootmode pins.BOOT_1 selectsaseeBOOT_1 I specificconfigurationsourcefromwhichthe PUPG7_GPIO47 Concertodevicebootson start-up. One offourbootmode pins.BOOT_2 selectsaseeBOOT_2 I specificconfigurationsourcefromwhichthe PUPF3_GPIO35 Concertodevicebootson start-up. One offourbootmode pins.BOOT_3 selectsaseeBOOT_3 I specificconfigurationsourcefromwhichthe PUPF2_GPIO34 Concertodevicebootson start-up. JTAG JTAG testresetwithinternalpulldown.TRST, when drivenhigh,givesthescan systemcontrolof theoperationsofthedevice.Ifthissignalisnot connectedordrivenlow,thedeviceoperatesinits functionalmode, and thetestresetsignalsare ignored.NOTE: TRST isan active-lowtestpin and must be maintainedlowduringnormaldevice operation.An externalpulldownresistorisTRST 85 I PDrequiredon thispin.The valueofthisresistor shouldbe based on drivestrengthofthedebugger pods applicabletothedesign.A 2.2-kΩ resistor generallyoffersadequateprotection.Sincethe valueoftheresistorisapplication-specific,TI recommends thateach targetboardbe validated forproperoperationofthedebuggerand the application. TCK 89 I JTAG testclock JTAG test-modeselect(TMS) withinternalpullup. TMS 87 I ThisserialcontrolinputisclockedintotheTAP PU controlleron therisingedge ofTCK. JTAG testdatainput(TDI)withinternalpullup. TDI 88 I TDI isclockedintotheselectedregister PU (instructionordata)on a risingedge ofTCK.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. JTAG scan out,testdataoutput(TDO).The contentsoftheselectedregister(instructionorTDO 84 O 4 mAdata)areshiftedoutofTDO on thefallingedge of TCK. Emulatorpin0.When TRST isdrivenhigh,this pinisused as an interrupttoorfromtheemulator systemand isdefinedas input/outputthroughthe JTAG scan.Thispinisalsoused toputthedevice intoboundary-scanmode. WiththeEMU0 pinata logic-highstateand theEMU1 pinata logic-low state,a risingedge on theTRST pinwouldlatch thedeviceintoboundary-scanmode. NOTE: An externalpullupresistorisrequiredon thispin.The valueofthisresistorshouldbe based EMU0 83 I/O/Z on thedrivestrengthofthedebuggerpods PU 4 mA applicabletothedesign.A 2.2-kΩ to4.7-kΩ resistorisgenerallyadequate.Sincethevalueof theresistorisapplication-specific,TIrecommends thateach targetboardbe validatedforproper operationofthedebuggerand theapplication. NOTE: IfEMU0 is0 and EMU1 is1 when coming outofreset,thedeviceentersWait-in-Reset mode. WIR suspendsbootloaderexecution, allowingtheEmulatortoconnecttothedeviceand tomodifyFLASH contents. Emulatorpin1.When TRST isdrivenhigh,this pinisused as an interrupttoorfromtheemulator systemand isdefinedas input/outputthroughthe JTAG scan.Thispinisalsoused toputthedevice intoboundary-scanmode. WiththeEMU0 pinata logic-highstateand theEMU1 pinata logic-low state,a risingedge on theTRST pinwouldlatch thedeviceintoboundary-scanmode. NOTE: An externalpullupresistorisrequiredon thispin.The valueofthisresistorshouldbe based EMU1 86 I/O/Z on thedrivestrengthofthedebuggerpods PU 4 mA applicabletothedesign.A 2.2-kΩ to4.7-kΩ resistorisgenerallyadequate.Sincethevalueof theresistorisapplication-specific,TIrecommends thateach targetboardbe validatedforproper operationofthedebuggerand theapplication. NOTE: IfEMU0 is0 and EMU1 is1 when coming outofreset,thedeviceentersWait-in-Reset mode. WIR suspendsbootloaderexecution, allowingtheEmulatortoconnecttothedeviceand tomodifyFLASH contents. ITM Trace (ARM ® InstrumentationTrace Macrocell) seeTRACED0 O ITM Tracedata0 4 mAPF3_GPIO35 seeTRACED1 O ITM Tracedata1 4 mAPG3_GPIO43 seeTRACED2 O ITM Tracedata2 4 mAPF0_GPIO32 seeTRACED3 O ITM Tracedata3 4 mAPF1_GPIO33 seeTRACECLK O ITM Traceclock 4 mAPF2_GPIO34 Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 107 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. TestPins FLASH TestPin1.ReservedforTI.Must be leftFLT1 16 I/O unconnected. FLASH TestPin2.ReservedforTI.Must be leftFLT2 21 I/O unconnected. InternalVoltageRegulatorControl Internal1.8-VVREG Enable/DisableforVDD18 . VREG18EN 113 Pulllowtoenabletheinternal1.8-Vvoltage PD regulator(VREG18), pullhightodisableVREG18. Internal1.2-VVREG Enable/DisableforVDD12 . VREG12EN 101 Pulllowtoenabletheinternal1.2-Vvoltage PD regulator(VREG12), pullhightodisableVREG12. DigitalLogic Power Pins forI/Os,Flash,USB, and InternalOscillators 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 107 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 10 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 25 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 34 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 44 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 54 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 59 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 105 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 3 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 67 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 74 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 92 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 100 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 96 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 17 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 2 0.1-µF capacitor(typical)closetothepin. 3.3-VDigitalI/Oand FLASH Power Pin.TiewithaVDDIO 106 0.1-µF capacitor(typical)closetothepin.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. DigitalLogic Power Pins (AnalogSubsystem) 1.8-VDigitalLogicPower Pins(associatedwith theAnalogSubsystem)-no supplyneeded when usinginternalVREG18. Tiewith2.2-µF (minimum)VDD18 1 ceramiccapacitor(10% tolerance)togroundwhen usinginternalVREG. Highervaluecapacitorsmay be used butcouldimpactsupply-railramp-uptime. 1.8-VDigitalLogicPower Pins(associatedwith theAnalogSubsystem)-no supplyneeded when usinginternalVREG18. Tiewith2.2-µF (minimum)VDD18 108 ceramiccapacitor(10% tolerance)togroundwhen usinginternalVREG. Highervaluecapacitorsmay be used butcouldimpactsupply-railramp-uptime. DigitalLogic Power Pins (Masterand ControlSubsystems) 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 24 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 55 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 66 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 99 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 75 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 58 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 11 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. Copyright© 2011–2012,Texas InstrumentsIncorporated DevicePins 109 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table3-1.TerminalFunctions(1) (continued) TERMINAL PU OUTPUT I/O/Z(2) DESCRIPTION or BUFFERRFPNAME PD (3) STRENGTHPIN NO. 1.2-VDigitalLogicPower Pins-no supplyneeded when usinginternalVREG12. Tiewith470-nF (minimum)ceramiccapacitor(10% tolerance)toVDD12 90 groundwhen usinginternalVREG. Highervalue capacitorsmay be used butcouldimpactsupply- railramp-uptime. DigitalLogic Ground (Analog,Master,and ControlSubsystems) DigitalGround Power Pad (locatedon thebottomVSS PWR PAD ofthechip) No Connect Pins NC 91 No connect (1) Throughoutthistable,MasterSubsystem signalsaredenotedby thecolor"blue";ControlSubsystem signalsaredenotedby thecolor "green";and AnalogSubsystem signalsaredenotedby thecolor"orange". (2) I= Input,O = Output,Z = HighImpedance,OD = Open Drain (3) PU = Pullup,PD = Pulldown – GPIO_MUX1 pullupscan be enabledordisabledby Cortex™ -M3 software(disabledon reset). – GPIO_MUX2 pullupscan be enabledordisabledby C28x software(disabledon reset). – AIO_MUX1 and AIO_MUX2 terminalsdo nothave pullupsorpulldowns. – Allotherpullupsarealwaysenabled(XRS, ARS, TMS, TDI,EMU0, EMU1). – Allpulldownsarealwaysenabled(VREG18EN, VREG12EN, TRST). (4) AllI/Os,exceptforGPIO135, areglitch-freeduringpower up and power down. See Section2.11. (5) Thismuxing optionisonlyavailableon siliconRevisionA devices;thismuxing optionisnotavailableon siliconRevision0 devices. (6) OutputfromtheConcertoePWM ismeant fortheexternalADC (ifpresent).

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

4 Device OperatingConditions

4.1 AbsoluteMaximum Ratings(1)(2)

Supplyvoltagerange,VDDIO (I/Oand Flash) withrespecttoVSS –0.3V to4.6V Supplyvoltagerange,VDD18 withrespecttoVSS –0.3V to2.5V Supplyvoltagerange,VDD12 withrespecttoVSS –0.3V to1.5V Analogvoltagerange,VDDA withrespecttoVSSA –0.3V to4.6V Inputvoltagerange,VIN (3.3V) –0.3V to4.6V Outputvoltagerange,VO –0.3V to4.6V Inputclamp current,IIK (VIN < 0 orVIN > VDDIO )(3) ±20 mA Outputclamp current,IOK (VO < 0 orVO > VDDIO ) ±20 mA Free-Airtemperature,TA –40°C to125°C Junctiontemperaturerange,TJ (4) –40°C to150°C Storagetemperaturerange,Tstg (4) –65°C to150°C (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderSection4.2isnotimplied. Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagevaluesarewithrespecttoVSS ,unlessotherwisenoted. (3) Continuousclamp currentperpinis± 2 mA. (4) Long-termhigh-temperaturestorageorextendeduse atmaximum temperatureconditionsmay resultina reductionofoveralldevicelife. Foradditionalinformation,see IC Package ThermalMetricsApplicationReport(literaturenumber SPRA953 )and ReliabilityData for TMS320LF24xx and TMS320F28xx DevicesApplicationReport(literaturenumber SPRA963 ).

4.2 Recommended OperatingConditions

Devicesupplyvoltage,I/O,VDDIO Devicesupplyvoltage,AnalogSubsystem,VDD18 1.71 1.8 1.995 (when internalVREG isdisabledand 1.8V is V suppliedexternally) Devicesupplyvoltage,Masterand Control 1.14 1.2 1.26 Subsystems,VDD12 V(when internalVREG isdisabledand 1.2V is suppliedexternally) Supplyground,VSS 0 V Analogsupplyvoltage,VDDA Analogground,VSSA 0 V Deviceclockfrequency(systemclock) 2 60 MHz High-levelinputvoltage,VIH (3.3V) VDDIO *0.7 VDDIO + 0.3 V Low-levelinputvoltage,VIL(3.3V) VSS – 0.3 VDDIO *0.3 V High-leveloutputsourcecurrent,VOH = VOH(MIN) ,IOH AllGPIO/AIO pins –4 mA Group 2(2) –8 mA Low-leveloutputsinkcurrent,VOL = VOL(MAX) ,IOL AllGPIO/AIO pins 4 mA Group 2(2) 8 mA Free-Airtemperature,TA T version –40 105 S version –40 125 °C Q version(Q100 qualification) –40 125 Junctiontemperature,TJ T version –40 125 S version –40 150 °C Q version(Q100 qualification) –40 150 (1) VDDIO and VDDA shouldbe maintainedwithinapproximately0.3V ofeach other. (2) Group 2 pinsareas follows:PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1, PD0_GPIO16, AIO7,AIO4. Copyright© 2011–2012,Texas InstrumentsIncorporated DeviceOperatingConditions 111 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

4.3 ElectricalCharacteristics(1)

overrecommended operatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH = IOH MAX VDDIO *0.8 VOH High-leveloutputvoltage V IOH = 50 μA VDDIO – 0.2 VOL Low-leveloutputvoltage IOL = IOL MAX VDDIO *0.2 V AllGPIO/AIO –140Pinwithpullup VDDIO = 3.3V,VIN = 0 VenabledInputcurrent XRS pinand ARS pin –300IIL μA(lowlevel) Pinwithpulldown VDDIO = 3.3V,VIN = 0 V ±2enabled Pinwithpullup VDDIO = 3.3V,VIN = VDDIO ±2enabledInputcurrentIIH μA(highlevel) Pinwithpulldown VDDIO = 3.3V,VIN = VDDIO 50enabled Outputcurrent,pulluporIOZ VO = VDDIO or0 V ±2 μApulldowndisabled C I Inputcapacitance 2 pF VDDIO BOR trippoint FallingVDDIO 2.78 V VDDIO BOR hysteresis 35 mV Supervisorresetrelease Time afterBOR/POR/OVR eventisremoved to 600 μsdelaytime XRS release VREG VDD18 output InternalVREG18 on 1.8 V VREG VDD12 output InternalVREG12 on 1.2 V (1) When theon-chipVREGs areused,theiroutputismonitoredby thePOR/BOR circuits,whichwillresetthedeviceshouldthecore voltages(VDD18 ,VDD12 )go outofrange.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

5 ElectricalSpecifications

5.1 CurrentConsumption

Table5-1.CurrentConsumption at150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK (1)(2) VREG ENABLED VREG DISABLED MODE TEST CONDITIONS (3) IDDIO (4) IDDA IDD18 IDD12 IDDIO (4) IDDA TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX The followingCortex™ -M3 peripheralsareexercised:

I2C1
SSI1,SSI2
UART0, UART1, UART2
CAN0
USB
µDMA
Timer0,Timer1
µCRC
WDOG0, WDOG1
Flash
InternalOscillator1, InternalOscillator2 The followingC28x peripheralsare exercised:
McBSP Operational 445 mA TBD 32 mA TBD 20 mA TBD 367 mA TBD 33 mA TBD 32 mA TBD• eQEP1, eQEP2(RAM)
eCAP1, eCAP2, eCAP3, eCAP4
SCI-A
SPI-A
I2C
DMA
VCU
FPU
Flash The followingAnalogperipherals areexercised:
ADC1, ADC2
Comparator1, Comparator2, Comparator3, Comparator4, Comparator5, Comparator6 (1) Currentlyonlytypicalcurrentconsumptiondataisavailable,maximum numbers willcome inanotherreleaseofthisdatasheet. (2) The numbers inTable5-1arenotassuredatthistime,and aresubjecttochange. (3) The followingisdone ina loop:
Code isrunningoutofRAM.
AllI/Opinsareleftunconnected.
Allthecommunicationperipheralsareexercisedinloop-backmode.
USB – Onlylogicisexercisedby loadingand unloadingFIFO.
µDMA does memory-to-memorytransfer.
DMA does memory-to-memorytransfer.
VCU – CRC calculatedand checked.
FPU – Floatoperationsperformed.
ePWM – 6 enabledand generates150-kHzPWM outputon 12 pins,HRPWM clockenabled.
Timersand Watchdog serviced.
eCAP inAPWM mode generates36.6-kHzoutputon 4 pins.
ADC performscontinuousconversion.
FLASH iscontinuouslyreadand inactivestate.
XCLKOUT isturnedoff. (4) IDDIO currentisdependenton theelectricalloadingon theI/Opins. (5) The TYP numbers areapplicableoverroom temperatureand nominalvoltage. Copyright© 2011–2012,Texas InstrumentsIncorporated ElectricalSpecifications 113 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table5-1.CurrentConsumption at150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK (1)(2)(continued) VREG ENABLED VREG DISABLED MODE TEST CONDITIONS (3) IDDIO (4) IDDA IDD18 IDD12 IDDIO (4) IDDA TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX

PLL ison.
Cortex™ -M3 CPU isnot executing.
M3SSCLK ison.SLEEP IDLE 80 mA – 315 µA – 14 mA – 51 mA – 15 mA – 315 µA –• C28CLKIN ison.
C28x™ CPU isnotexecuting.
C28CPUCLK isoff.
C28SYSCLK ison.
PLL ison.
Cortex™ -M3 CPU isnot executing.
M3SSCLK ison.SLEEP 71 mA – 210 µA – 15 mA – 42 mA – 14 mA – 205 µA –STANDBY • C28CLKIN isoff.
C28x™ CPU isnotexecuting.
C28CPUCLK isoff.
C28SYSCLK isoff.
PLL isoff.
Cortex™ -M3 CPU isnot executing.
M3SSCLK is32 kHz.DEEP SLEEP 24 mA – 200 µA – 2 mA – 19 mA – 3 mA – 195 µA –STANDBY • C28CLKIN isoff.
C28x™ CPU isnotexecuting.
C28CPUCLK isoff.
C28SYSCLK isoff. NOTE The peripheral-I/Omultiplexingimplementedinthedevicepreventsallavailableperipherals frombeingused atthesame timebecause more thanone peripheralfunctionmay sharean I/Opin.Itis,however,possibletoturnon theclockstoalltheperipheralsatthesame time, althoughsuch a configurationisnotuseful.Iftheclockstoalltheperipheralsare turnedon atthesame time,thecurrentdrawn by thedevicewillbe more thanthenumbers specifiedin thecurrentconsumptiontable.

5.2 Thermal Design Considerations

Based on theend-applicationdesignand operationalprofile,theIDD12 ,IDD18 ,and IDDIO currentscouldvary. Systems thatexceed the recommended maximum power dissipationin the end productmay require additionalthermalenhancements.Ambient temperature(TA) varieswiththeend applicationand product design.The criticalfactorthataffectsreliabilityand functionalityisTJ, the junctiontemperature,not the ambienttemperature.Hence, careshouldbe takentokeep TJ withinthespecifiedlimits.Tcase shouldbe measured toestimatetheoperatingjunctiontemperatureTJ.Tcase isnormallymeasured atthecenterof the package top-sidesurface.For more detailsabout thermal metricsand definitions,see the Semiconductorand IC Package ThermalMetricsApplicationReport(literaturenumber SPRA953 )and the ReliabilityData forTMS320LF24xx and TMS320F28xx Devices ApplicationReport (literaturenumber SPRA963 ).

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PRODUCT□PREVIEW Z0 = 50 /c87 (A) TD = 6 ns OUTPUT UNDER TEST 20 pF 15 /c8725 /c87 DEVICE PIN (B) DATA SHEET TIMING REFERENCE POINT TESTER PIN ELECTRONICS CONCERTO DEVICE TRANSMISSION LINE 20 pF F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

5.3 Timing Parameter Symbology

Timingparametersymbols used are createdinaccordancewithJEDEC Standard100. To shortenthe symbols,some ofthepinnames and otherrelatedterminologyhave been abbreviatedas follows: Lowercase subscriptsand their Lettersand symbols and their meanings: meanings: a accesstime H High c cycletime(period) L Low d delaytime V Valid Unknown, changing,ordon'tcaref falltime X level h holdtime Z Highimpedance r risetime su setuptime t transitiontime v validtime w pulseduration(width)

5.3.1 GeneralNotes on Timing Parameters

Alloutputsignalsfromthe28x devices(includingXCLKOUT) arederivedfroman internalclocksuch that alloutputtransitionsfora givenhalf-cycleoccurwitha minimum ofskewingrelativetoeach other. The signalcombinationsshown in the followingtimingdiagrams may not necessarilyrepresentactual cycles.Foractualcycleexamples,see theappropriatecycledescriptionsectionofthisdocument.

5.3.2 TestLoad Circuit

Thistestloadcircuitisused tomeasure allswitchingcharacteristicsprovidedinthisdocument. A. Inputrequirementsinthisdatasheetare testedwithan inputslewrateof< 4 Voltsper nanosecond (4 V/ns)atthe devicepin. B. The data sheet providestimingat the devicepin.For outputtiminganalysis,the testerpin electronicsand its transmissionlineeffectsmust be takenintoaccount.A transmissionlinewitha delayof2 ns orlongercan be used to producethedesiredtransmissionlineeffect.The transmissionlineisintendedas a loadonly.Itisnotnecessaryto add orsubtractthetransmissionlinedelay(2ns orlonger)fromthedatasheettiming. Figure5-1.3.3-VTestLoad Circuit Copyright© 2011–2012,Texas InstrumentsIncorporated ElectricalSpecifications 115 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

5.4 Clock Frequencies,Requirements,and Characteristics

This sectionprovidesthe frequenciesand timingrequirementsof the inputclocks;PLL locktimes; frequenciesoftheinternalclocks;and thefrequencyand switchingcharacteristicsoftheoutputclock.

5.4.1 InputClock Frequency and Timing Requirements,PLL Lock Times

Table 5-2 shows the frequencyrequirementsforthe inputclocksto the F28M35x devices.Table 5-3 shows the inputclockcycletime.Table 5-4, Table 5-5, Table 5-6, and Table 5-7 show the timing requirementsforthe inputclocksto the F28M35x devices.Table 5-8 shows the PLL locktimesforthe Main PLL and theUSB PLL. The Main PLL operatesfromtheX1 orX1/X2 inputclockpins,and theUSB PLL operatesfromtheXCLKIN inputclockpin. Table5-2.InputClock Frequency MIN MAX UNIT f(OSC) Frequency,X1/X2,fromexternalcrystalorresonator 2 20 MHz f(OCI) Frequency,X1,fromexternaloscillator(PLL enabled) 2 30 MHz f(OCI) Frequency,X1,fromexternaloscillator(PLL disabled) 2 100 MHz f(XCI) Frequency,XCLKIN, fromexternaloscillator 2 60 MHz Table5-3.InputClock Cycle Time NO. MAX MIN UNIT C1 tc(OSC) Cycletime,X1/X2,fromexternalcrystalorresonator 500 50 ns C2 tc(OCI) Cycletime,X1,fromexternaloscillator(PLL enabled) 500 33.3 ns C2 tc(OCI) Cycletime,X1,fromexternaloscillator(PLL disabled) 500 10 ns C3 tc(XCI) Cycletime,XCLKIN, fromexternaloscillator 500 16.6 ns Table5-4.X1 Timing Requirements -PLL Enabled(1) NO. MIN MAX UNIT C4 tf(OCI) Falltime,X1 6 ns C5 tr(OCI) Risetime,X1 6 ns C6 tw(OCL) Pulseduration,X1 lowas a percentageoftc(OCI) 45 55 % C7 tw(OCH) Pulseduration,X1 highas a percentageoftc(OCI) 45 55 % (1) The possibleMain PLL configurationmodes areshown inTable2-19toTable2-22. Table5-5.X1 Timing Requirements -PLL Disabled NO. MIN MAX UNIT C4 tf(OCI) Falltime,X1 Up to20 MHz 6 ns

20 MHz to100 MHz 2

C5 tr(OCI) Risetime,X1 Up to20 MHz 6 ns C6 tw(OCL) Pulseduration,X1 lowas a percentageoftc(OCI) 45 55 % C7 tw(OCH) Pulseduration,X1 highas a percentageoftc(OCI) 45 55 %

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table5-6.XCLKIN Timing Requirements -PLL Enabled(1) NO. MIN MAX UNIT C8 tf(XCI) Falltime,XCLKIN 6 ns C9 tr(XCI) Risetime,XCLKIN 6 ns C10 tw(XCL) Pulseduration,XCLKIN lowas a percentageoftc(XCI) 45 55 % C11 tw(XCH) Pulseduration,XCLKIN highas a percentageoftc(XCI) 45 55 % (1) The possibleUSB PLL configurationmodes areshown inTable2-23and Table2-24. Table5-7.XCLKIN Timing Requirements -PLL Disabled NO. MIN MAX UNIT C8 tf(XCI) Falltime,XCLKIN Up to20 MHz 6 ns C9 tr(XCI) Risetime,XCLKIN Up to20 MHz 6 ns C10 tw(XCL) Pulseduration,XCLKIN lowas a percentageoftc(XCI) 45 55 % C11 tw(XCH) Pulseduration,XCLKIN highas a percentageoftc(XCI) 45 55 % Table5-8.PLL Lock Times MIN NOM MAX UNIT inputclockt(PLL) Lock time,Main PLL (X1,fromexternaloscillator) 2000(1) cycles inputclockt(USB) Lock time,USB PLL (XCLKIN,fromexternaloscillator) 2000(1) cycles (1) Forexample,iftheinputclocktothePLL is10 MHz, thenthePLL locktimeis100 ns x 2000 = 200 µs.

5.4.2 InternalClock Frequencies

Table5-9providestheclockfrequenciesfortheinternalclocksoftheF28M35x devices. Table5-9.InternalClock Frequencies(150-MHz Devices) MIN NOM MAX UNIT f(USB) Frequency,USBPLLCLK 60 MHz f(PLL) Frequency,PLLSYSCLK 2 150 MHz f(OCK) Frequency,OSCCLK 2 100 MHz f(M3C) Frequency,M3SSCLK 2 100(1) MHz f(ADC) Frequency,ASYSCLK 2 37.5 MHz f(SYS) Frequency,C28SYSCLK 2 150(1) MHz f(HSP) Frequency,C28HSPCLK 2 150(1) MHz f(LSP) Frequency,C28LSPCLK (2) 2 37.5(3) 150(1) MHz f(10M) Frequency,10MHzCLK 10 MHz f(32K) Frequency,32KHzCLK 32 kHz (1) An integerdivideratiomust be maintainedbetween theC28x and Cortex™ -M3 clockfrequencies.Forexample,when theC28x is configuredtorunata maximum frequencyof150 MHz, thefastestallowablefrequencyfortheCortex™ -M3 willbe 75 MHz. See Figure2-10and Figure2-11tosee theinternalclocksand clockdivideroptions. (2) Lower LSPCLK willreducedevicepower consumption. (3) ThisisthedefaultresetvalueifC28SYSCLK = 150 MHz. Copyright© 2011–2012,Texas InstrumentsIncorporated ElectricalSpecifications 117 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

5.4.3 Output Clock Frequency and SwitchingCharacteristics

Table5-10 providesthefrequencyoftheoutputclockfrom theF28M35x devices.Table5-11 shows the switchingcharacteristicsoftheoutputclockfromtheF28M35x devices,XCLKOUT. Table5-10.Output Clock Frequency NO. MIN MAX UNIT C14 f(XCO) Frequency,XCLKOUT 2 37.5 MHz Table5-11.XCLKOUT SwitchingCharacteristics(PLL Bypassed or Enabled)(1)(2) overrecommended operatingconditions(unlessotherwisenoted) NO. PARAMETER MIN TYP MAX UNIT C15 tf(XCO) Falltime,XCLKOUT 5 ns C16 tr(XCO) Risetime,XCLKOUT 5 ns C17 tw(XCOL) Pulseduration,XCLKOUT low H – 2 H + 2 ns C18 tw(XCOH) Pulseduration,XCLKOUT high H – 2 H + 2 ns (1) A loadof40 pF isassumed fortheseparameters. (2) H = 0.5tc(XCO)

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PRODUCT□PREVIEW V V (3.3 V) DDIO DDA, VDD12, VDD18 tw(RSL1) th(boot-mode)(C) X1/X2 XRS (D) Boot-Mode Pins XCLKOUT I/O Pins User-code dependent User-code dependent Boot-ROM execution starts Peripheral/GPIO function Based on boot code GPIO pins as input GPIO pins as input (state depends on internal PU/PD) (E) tOSCST User-code dependent Address/Data/ Control (Internal) Address/data valid, internal boot-ROM code execution phase User-code execution phasetd(EX) (A) (B) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

5.5 Power Sequencing

There isno power sequencingrequirementneeded toensurethedeviceisintheproperstateafterreset ortopreventtheI/Osfromglitchingduringpower up and power down. (AllI/Os,exceptforGPIO135, are glitch-freeduringpower up and power down.)No voltagelargerthana diodedrop (0.7V) above VDDIO shouldbe appliedtoany digitalpin(foranalogpins,thisvalueis0.7V above VDDA )priortopoweringup thedevice.Voltagesappliedtopinson an unpowered devicecan biasinternalp-njunctionsinunintended ways and produceunpredictableresults. A. Upon power up,PLLSYSCLK isOSCCLK/8. SincetheXCLKOUTDIV bitsintheXCLK registercome up witha reset stateof0,PLLSYSCLK isfurtherdividedby 4 beforePLLSYSCLK appearsatXCLKOUT. XCLKOUT = OSCCLK/32 duringthisphase. B. Boot ROM configuresthe SYSDIVSEL bitsfor/1 operation.XCLKOUT = OSCCLK/4 duringthisphase.Note that XCLKOUT willnotbe visibleatthepinuntilexplicitlyconfiguredby usercode. C. Afterreset,thebootROM code samples Boot Mode pins.Based on thestatusoftheBoot Mode pin,thebootcode branchesto destinationmemory or boot code function.Ifboot ROM code executesafterpower-on conditions(in debugger environment),thebootcode executiontimeisbased on thecurrentM3SSCLK speed.The M3SSCLK will be based on userenvironmentand couldbe withorwithoutPLL enabled. D. UsingtheXRS pinisoptionaldue totheon-chippower-onreset(POR) circuitry. E. The internalpulluporpulldownwilltakeeffectwhen BOR isdrivenhigh. Figure5-2.Power-On Reset Copyright© 2011–2012,Texas InstrumentsIncorporated ElectricalSpecifications 119 SubmitDocumentationFeedback

PRODUCT□PREVIEW th(boot-mode)(A) tw(RSL2) X1/X2 XRS Boot-Mode Pins XCLKOUT I/O Pins Address/Data/ Control (Internal) Boot-ROM Execution Starts User-Code Execution Starts User-Code Dependent User-Code Execution Phase User-Code Dependent User-Code Execution Peripheral/GPIO Function User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) GPIO Pins as Input Peripheral/GPIO Function td(EX) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table5-12.Reset (XRS )Timing Requirements MIN MAX UNIT th(boot-mode)(1) Holdtimeforboot-modepins 14000tc(M3C) cycles tw(RSL2) Pulseduration,XRS lowon warm reset 32tc(OCK) cycles (1) The minimum holdtimeforbootmode pinsis23 timeslongerforsiliconrevision0 devices. Table5-13.Reset (XRS )SwitchingCharacteristics overrecommended operatingconditions(unlessotherwisenoted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulseduration,XRS drivenby device 600 μs tw(WDRS) Pulseduration,resetpulsegeneratedby watchdog 512tc(OCK) cycles td(EX) Delaytime,address/datavalidafterXRS high 32tc(OCK) cycles tINTOSCST Startup time,internalzero-pinoscillator 3 μs tOSCST (1) On-chipcrystal-oscillatorstart-uptime 1 10 ms (1) Dependent on crystal/resonatorand boarddesign. A. Afterreset,theBoot ROM code samples BOOT Mode pins.Based on thestatusoftheBoot Mode pin,thebootcode branchesto destinationmemory or boot code function.IfBoot ROM code executesafterpower-on conditions(in debugger environment),theBoot code executiontimeisbased on thecurrentM3SSCLK speed.The M3SSCLK will be based on userenvironmentand couldbe withorwithoutPLL enabled. Figure5-3.Warm Reset

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PRODUCT□PREVIEW PLLSYSCLK BEFORE THE CHANGE WRITE TO SYSPLLCTL REGISTER TO PUT PLL IN BYPASS MODE WRITE TO SYSPLLCTL REGISTER TO TAKE PLL OUT OF BYPASS MODE (MINIMUM 2000 OSCCLK CYCLES) WRITE TO SYSPLLMULT REGISTGER TO CHANGE PLL MULTIPLIER CONFIGURA TION STEP 1 STEP 2 STEP 3

10 MHz x 40 =

400 MHz / 2 =

200 MHz / 2 =

100 MHz / 1 =

100 MHz

10 MHz

150 MHz

SPLLIMULT = 40 SPLLFMULT = 2 PLL OUTPUT / 2 SYSDIVSEL = 0

10 MHz x 60 =

600MHz / 2 =

300 MHz / 2 =

150 MHz / 1 =

SPLLIMULT = 60 SPLLFMULT = 2 PLL OUTPUT / 2 SYSDIVSEL = 0 PLLSYSCLK F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

5.5.1 Changing theFrequency oftheMain PLL

Figure5-4shows how tochange thefrequencyoftheMain PLL.The threestepsaredescribedbelow: 1. The PLL must firstbe placedinbypassmode (bywritingtotheSYSPLLCTL register)beforeany changes aremade totheSPLLIMULT and SPLLFMULT fieldsoftheSYSPLLMULT Register.Figure5- 4 shows thatbeforebeingplacedinbypassmode, theinternalPLLSYSCLK clockwas operatingat 100 MHz. Afterenteringthebypassmode, thePLLSYSCLK becomes 10 MHz, whichisthefrequency ofOSCCLK, theinputclocktothePLL 2. Once thePLL isplacedinbypassmode, theSYSPLLMULT registercan be modifiedtoincreasethe PLLSYSCLK frequencyto150 MHz. See Figure5-4forthesettingsoftheSPLLIMULT (integer)and SPLLFMULT (fractional)multiplyfieldsoftheSYSPLLMULT registerforthisstep,and see Figure2-8 forthefunctionaldescriptionoftheMain PLL.The PLL bypassmode must be maintainedforatleast 2000 OSCCLK cyclesinorderforthePLL toproperlylocktothenew frequency. 3. Finally,theSYSPLLCTL registeriswrittentoagain,thistimetotakethePLL outofthebypassmode. Followingthisstep,thePLLSYSCLK switchesoverfrom10 MHz tothenew frequencyof150 MHz. Figure5-4.Changing theFrequency oftheMain PLL Copyright© 2011–2012,Texas InstrumentsIncorporated ElectricalSpecifications 121 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

5.5.2 Power Management and SupervisoryCircuitSolutions

Table 5-14 liststhe power management and supervisorycircuitsolutionsforF28M35x devices.LDO selectiondepends on the totalpower consumed inthe end application.Go to www.ti.comand clickon Power Management fora completelistofTIpower ICs orselectthePower Management SelectionGuide linkforspecificpower referencedesigns. Table5-14.Power Management and SupervisoryCircuitSolutions SUPPLIER TYPE PART DESCRIPTION Texas Instruments DC/DC TPS62160/170 1/0.5-A,3–17-V input,step-downconverterin2x2 QFN package Texas Instruments DC/DC TPS62140/150 2/1-A,3–17-V input,step-downconverterin3x3 QFN package Texas Instruments LDO TPS7A8001 Low-noise,high-bandwidthPSRR, 1A low-dropoutlinearregulator Texas Instruments LDO TPS7A7001 2A,single-output,very-lowinput,adjustablelow-dropoutlinearregulator Texas Instruments LDO/SVS TPS75005 Dual,500-mA, low-dropoutregulatorsand triple-voltagerailmonitor Texas Instruments DC/DC LM22672/1 1/0.5-A,4.5–42-V inputSIMPLE SWITCHER ® ,step-downvoltageregulator withfeatures Texas Instruments DC/DC TPS54160/060 3.5-Vto60-V input,1.5/0.5-Astep-downconverterwithEco-Mode Texas Instruments Module LMZ10501 1A SIMPLE SWITCHER ® Nano Module with5.5-Vmaximum inputvoltage Texas Instruments SVS TPS386000/040 Quad supplyvoltagesupervisorswithprogrammabledelayand watchdog timer Texas Instruments LDO TPS73719 Single-outputLDO, 1-A,fixed(1.9-V),reverse-currentprotection Texas Instruments LDO TPS73534 Single-outputLDO, 500-mA, fixed(3.4-V),low-quiescentcurrent,low-noise, highPSRR

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6 PeripheralInformationand Timings

6.1 Analog and Shared Peripherals

ConcertoShared PeripheralsareaccessiblefromboththeMasterSubsystem and theControlSubsystem. The Analog Shared Peripheralsincludetwo 12-bitADCs (Analog-to-DigitalConverters),and six Comparator+ DAC (10-bit)modules.The ADC ResultRegistersareaccessibleby CPUs and DMAs ofthe Master and ControlSubsystems. Allother analog registers,such as the ADC Configurationand ComparatorRegisters,areaccessibleby theC28x CPU only.The DigitalShared Peripheralsincludethe Inter-ProcessorCommunications (IPC)peripheraland the ExternalPeripheralInterface(EPI).IPC is accessibleby bothCPUs; EPI isaccessibleby bothCPUs and bothDMAs. IPC isused forsendingand receivingsynchronizationeventsbetween Masterand Controlsubsystemsto coordinateexecutionof softwarerunningon both processors,or exchangingof data between the two processors.EPI isused by thisdevicetocommunicatewithexternalmemory and otherdevices.

6.1.1 Analog-to-DigitalConverter(ADC)

Figure6-1shows theinternalstructureofeach ofthetwo ADC peripheralsthatarepresenton Concerto. Each ADC has 16 channelsthatcan be programmed to selectanaloginputs,selectstart-of-conversion trigger,setthesamplingwindow,and selectend-of-conversioninterrupttoprompta CPU orDMA toread 16 resultregisters.The 16 ADC channels can be used independentlyor in pairs,based on the assignmentsinsidetheSAMPLEMODE register.Pairingup thechannelsallowstwo analoginputstobe sampled simultaneously— thereby,increasingtheoverallconversionperformance.

6.1.1.1 Sample Mode

Each ADC has 16 programmable channelsthatcan be independentlyprogrammed foranalog-to-digital conversionwhen correspondingbitsin the SAMPLEMODE registerare set to SequentialMode. For example,ifbit2 intheSAMPLEMODE registerissetto0,ADC channels4 and 5 are settosequential mode. Both theSOC4CTL and SOC5CTL registerscan thenbe programmed toconfigurechannels4 and 5 to independentlyperformanalog-to-digitalconversionswithresultsbeingstoredinthe RESULT4 and RESULT5 registers."Independently"means thatchannel4 may use a differentStart-Of-Conversion(SOC) trigger,differentanaloginput,and differentsamplingwindow thanthetrigger,input,and window assigned tochannel5. The 16 programmable channels for each ADC may also be grouped in 8 channel pairswhen correspondingbitsintheSAMPLEMODE registerare settoSimultaneousMode. For example,ifbit2 in the SAMPLEMODE registerisset to 1, ADC channels4 and 5 are set to SimultaneousMode. The SOC4CTL registernow containsconfigurationparametersforboth channel4 and channel5, and the SOC5CTL registerisignored.Whilechannel4 and channel5 arestillusingdedicatedanaloginputs(now selectedas pairsintheCHSEL fieldofSOC4CTL), theybothsharethesame SOC triggerand Sampling Window, withtheresultsbeingstoredintheRESULT4 and RESULT5 registers. The Simultaneousmode ismade possibleby two sample-and-holdunitspresentin each ADC. Each sample-and-holdunithas itsown mux forselectinganaloginputs(seeFigure6-1).By programming the SAMPLEMODE register,the 16 availablechannelscan be configuredas 16 independentchannels, 8 channelpairs,or any combinationthereof(forexample,10 sequentialchannelsand 3 simultaneous pairs). Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 123 SubmitDocumentationFeedback

PRODUCT□PREVIEW VREFLO 1 N/C AIO_MUX MUX GPIO SOC0CTL REG SOC1CTL REG SOC2CTL REG SOC3CTL REG SOC4CTL REG SOC5CTL REG SOC6CTL REG SOC7CTL REG SOC8CTL REG SOC9CTL REG SOC10CTL REG SOC11CTL REG SOC12CTL REG SOC13CTL REG SOC14CTL REG SOC15CTL REGADC CONTROL ADC INTERUPT CONTROL TRIGS(8:1) EOC(15:0) SOCx TRIGGER CONTROL ADC_INT(8:1) SOC(15:0) STORE RESULT ASEL INTSOCSEL1 REG INTSOCSEL2 REG INTSEL1N2 REG INTSEL3N4 REG INTSEL5N6 REG INTSEL7N8 REG SOCPRICTL REG SAMPLEMODE REG ADCCTL1 REG 12-BIT ADC CONVERTER REV REG OFFTRIM REG REFTRIM REG S / H A S / H B INTFLG REG INTFLGCLR REG INTOVF REG INTOVFCLR REG SOCFLG REG SOCFRC REG SOCOVF REG SOCOVFCLR REG SOCSHSEL REGSEL ADCINT1 ADCINT2 BSEL ANALOG BUS ADC_INA0 ADC_INA2 ADC_INA3 ADC_INA4 ADC_INA6 ADC_INA7 ADC_INB0 ADC_INB3 ADC_INB4 ADC_INB7 ACIB RESULT0 REG RESULT1 REG RESULT2 REG RESULT3 REG RESULT4 REG RESULT5 REG RESULT6 REG RESULT7 REG RESULT8 REG RESULT9 REG RESULT10 REG RESULT11 REG RESULT12 REG RESULT13 REG RESULT14 REG RESULT15 REG N/C A B ACIB (ANALOG COMMON INTERFACE BUS) ADCCTL1 REG VREFLOCONV N/C N/C N/C (1) CURRENTLY DEFAULT IS “NO CONNECT”, CHANGE ADDCCTL1 REGI STER TO CONNECT TO VREFLO F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-1.ADC

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.1.1.2 Start-of-Conversion(SOC) Triggers

There are eightexternalSOC triggersthatgo to each of the two ADC modules (fromthe Control Subsystem).In additionto the eightexternalSOC triggers,thereare alsotwo internalSOC triggers derivedfrom End-Of-Conversion(EOC) interruptsinsideeach ADC module (ADCINT1 and ADCINT2). RegistersINTSOCSEL1 and 2 areused toconfigureeach ofthe16 ADC channelsforinternalorexternal SOC sources.IfinternalSOC ischosen fora givenchannel,theINTSOCSEL1 and 2 registersalsoselect whethertheinternalsourceisADCINT1 orADCINT2. IfexternalSOC ischosen fora givenADC channel, theTRIGSEL fieldofthecorrespondingSOCxCTL registerselectswhich oftheeightexternaltriggersis used forSOC inthatchannel.One analog-to-digitalconversioncan be performedata timeby the12-bit ADC. The analog-to-digitalconversionpriorityismanaged accordingtothestateofthePRICTL register.

6.1.1.3 Analog Inputs

Analog inputstoeach ofthetwo ADC modules are organizedintwo groups— A and B, witheach group havinga dedicatedmux and sample-and-holdunit(see Figure6-1).Mux A selectsone of sixpossible analoginputsviaAIO MUX. Mux B selectsone offivepossibleanaloginputs— fourexternalinputsviaAIO MUX, and one fromtheinternalVREFLO signal,whichiscurrentlytiedtotheAnalogGround.The Mux A and Mux B inputscan be simultaneouslyor sequentiallysampled by the two sample-and-holdunits accordingtothesamplingwindow chosen intheSOCxCTL registerforthecorrespondingchannel.

6.1.1.4 ADC ResultRegistersand EOC Interrupts

Concertoanalog-to-digitalconversionresultsare storedin32 ResultsRegisters(16 forADC1 and 16 for ADC2). The 16 ADCx channelscan be programmed viathe INTSELxNy registersto triggerup to eight ADCINT interruptsperADC module,when theirresultsarereadytobe read.The eightADCINT interrupts fromADC1 and theeightADCINT interruptsfromADC2 areAND-ed togetherbeforepropagatingtoboth theMasterSubsystem and theControlSubsystem,announcingthattheResultRegistersarereadytobe readby a CPU orDMA (seeFigure2-3).

6.1.2 Comparator + DAC Units

Figure6-2 shows the internalstructureof the sixanalogComparator + DAC unitspresentinConcerto devices.Each unitcompares two analoginputs(A and B) and assignsa valueof‘1’when thevoltageof theA inputisgreaterthanthatoftheB input,ora valueof‘0’when theoppositeistrue.The sixA inputs and two B inputscome fromAIO_MUX1 and AIO_MUX2. AllsixB inputscan alsobe providedby the10- bitdigital-to-analogunitsthatarepresentineach comparatorDAC. The 10-bitvalueforeach DAC unitis programmed in the respectiveDACVAL register.Another comparator register,COMPCTL, can be programmed to selectthe sourceof the B input,to enableor disablethe comparatorcircuit,to invert comparatoroutput,to synchronizecomparatoroutputto C28x SYSCLK, and to selectthe qualification period(number ofclockcycles).Allsixoutputsignalsfrom thesixcomparatorscan be routedouttothe devicepinsviaGPIO_MUX2 pinmux. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 125 SubmitDocumentationFeedback

PRODUCT□PREVIEW GPIO_MUX2 MUX GPIO AIO_MUX1 MUX GPIO AIO_MUX2 COMPCTL REG SYNC / QUAL C28SYSCLK QUALSEL COMPSTS SYNCSELCOMPINVCOMPDACE COMPSTS REG COMP2 COMPA(1) COMPA(2) COMPB(2) COMPA(3) COMPA(4) COMPA(5) COMPB(5) COMPA(6) COMPOUT(1) COMPOUT(2) COMPOUT(3) COMPOUT(4) COMPOUT(5) COMPOUT(6) COMP1 MUX GPIO 10-BIT DAC2 DACVAL REG DACVAL(8:0) VDDA VSSA COMPSOURCE COMP2 0 0 V V = ( DACVAL * ( VDDA -VSSA ) ) / 1023 COMP = 0 WHEN VOLTAGE A < VOLTAGE B COMP = 1 WHEN VOLTAGE A > VOLTAGE B DAC1 COMP3 DAC3 COMP4 DAC4 COMP5 DAC5 COMP6 DAC6 N/C N/C N/C N/C F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-2.Comparator + DAC Units

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.1.3 Inter-ProcessorCommunications (IPC)

Figure6-3shows theinternalstructureoftheIPC peripheralused tosynchronizeprogram executionand exchange of data between the Cortex™ -M3 and the C28x CPU. IPC can be used by itselfwhen synchronizingprogram executionoritcan be used inconjunctionwithMessage RAMs when coordinating datatransfersbetween processors.Ineithercase,theoperationoftheIPC isthesame. There are two independentsidestotheIPC peripheral— MTOC (MastertoControl)and CTOM (ControltoMaster). The MTOC IPC isused by theMasterSubsystem tosend eventstotheControlSubsystem.The MTOC IPC typicallysends eventsto the ControlSubsystem by usingthe followingregisters:MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS (1),and MTOCIPCACK. Each ofthe32 bitsoftheseregistersrepresents32 independentchannelsthroughwhich theCortex™ -M3 CPU can send up to32 eventstotheC28x CPU viasoftwarehandshaking.Additionally,thefirst4 bitsoftheMTOCIPC registersare supplementedwith interrupts.To send an eventviachannel2 fromCortex™ -M3 toC28x, forexample,theCortex™ -M3 and C28x CPUs use bit2 oftheMTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers.The handshake startswiththeCortex™ -M3 pollingbit2 oftheMTOCIPCFLG registertomake surebit2 is‘0’. Next,theCortex™ -M3 writesa ‘1’intobit2 oftheMTOCIPCSET registertostartthehandshake.Inthe mean time,theC28x iscontinuallypollingtheMTOCIPCSTS registerwhilewaitingforthemessage. As soon as the Cortex™ -M3 writes ‘1’ to bit 2 of the MTOCIPCSET register,bit 2 of MTOCIPCFLG/MTOCIPCSTS alsoturns‘1’,thusannouncingtheeventtotheC28x. As soon as theC28x CPU readsa ‘1’fromtheMTOCIPCSTS register,theC28x CPU shouldacknowledgeby writinga ‘1’tobit 2 oftheMTOCIPCACK register,which inturn,clearsbit2 oftheMTOCIPCFLG/MTOCIPCSTS register, enablingthe Cortex™ -M3 to send anothermessage. Since the firstfourchannels(bits0, 1, 2, 3) are backed up by interrupts,bothprocessorsintheabove example can use IPC interrupt2 insteadofpolling toincreaseperformance. A similarhandshake isalsoused when sendingdata(notjustevent)from theMasterSubsystem tothe ControlSubsystem,butwithtwo additionalsteps.Beforesettinga bitintheMTOCIPCSET register,the Cortex™ -M3 shouldfirstloadtheMTOC Message RAM witha blockofdatathatistobe made available to the C28x. In the second additionalstep,the C28x shouldread the data beforesettinga bitinthe MTOCIPCACK register.Thisway, no datagetslostduringmultipledatatransfersthrougha givenblockof themessage RAM. The CTOM IPC isused by theControlSubsystem tosend eventstotheMasterSubsystem.The CTOM IPC typicallysends eventstotheMasterSubsystem by usingthefollowingthreeregisters:CTOMIPCSET, CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The processisexactlythesame as thatfortheMTOC IPC communicationabove. (1) Note thatphysicallyMTOCIPCFLG/MTOCIPCSTS isone register,butitisreferredtoas theMTOCIPCFLG registerwhen theCortex™ - M3 CPU readsit,and as theMTOCIPCSTS registerwhen theC28x CPU readsit. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 127 SubmitDocumentationFeedback

PRODUCT□PREVIEW M3 SYSTEM BUS C28 CPU BUS MTOC MTOC MTOCIPCACK REG MTOCIPCFLG REG MTOCIPCSTS REG MTOCIPCSET REG WRDATA RDDATA (31:0) ACK(31:0) STS(31:0) MTOC MSG RAM MTOC IPC CTOMCTOM CTOMIPCSET REG CTOMIPCSACK REG CTOMIPCSTS REG CTOMIPCSFLG REG STS(31:0) ACK(31:0) RDDATA (31:0) FLG(31:0) SET(31:0) WRDATA (31:0) CTOM MSG RAMCTOM IPC C28x CPUPIE INTRSSTS(3:0) CPU NVIC CTOM IPC INT (3:0) STS(3:0)INTRS ACK REG STS REG SET REG 0 031 CTOM_CH31 CTOM_CH30 CTOM_CH29CTOM_CH2 CTOM_CH1 CTOM_CH0 . . . . . . . . . FLG REG

32 CTOM IPC CHANNELS

(3:0) MTOC_CH0MTOC_CH1MTOC_CH2MTOC_CH29MTOC_CH30MTOC_CH31 SET REG FLG REG ACK REG0 031 . . . . . . . . . STS REG

32 MTOC IPC CHANNELS

PHYSICALLY THIS IS ONE REGISTER WITH TWO DIFFERENT NAMES – FLG FOR THE M3 AND STS FOR THE C28 PHYSICALLY THIS IS ONE REGISTER WITH TWO DIFFERENT NAMES – FLG FOR THE C28 AND STS FOR THE M3 F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-3.InterprocessorCommunications (IPC)

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.1.4 ExternalPeripheralInterface(EPI)

The ExternalPeripheralInterface(EPI) providesa high-speedparallelbus for interfacingexternal peripheralsand memory. EPI isaccessiblefromboththeMasterSubsystem and theControlSubsystem. EPI has severalmodes of operationto enablegluelessconnectivityto most typesof externaldevices. Some EPI modes of operationconform to standardmicroprocessoraddress/databus protocols,while othersaretailoredtosupporta varietyoffastcustom interfaces,such as thosecommunicatingwithfield- programmablegatearrays(FPGAs) and complexprogrammablelogicdevices(CPLDs). The EPI peripheralcan be accessedby theCortex™ -M3 CPU, theCortex™ -M3 DMA, theC28x CPU, and theC28x DMA overthehigh-performanceAHB bus.The Cortex™ -M3 CPU and theµDMA driveAHB bus cyclesdirectlythroughthe Cortex™ -M3 Bus Matrix.The C28x CPU and DMA also connect to the Cortex™ -M3 Bus Matrix,but not directly.Beforeenteringthe Cortex™ -M3 Bus Matrix,the nativeC28x CPU and DMA bus cyclesarefirstconvertedtoAHB protocolinsidetheMEM32-to-AHB Bus Bridge.After that,theypass throughtheFrequencyGasket toreducethebus frequencyby a factorof2 or4.Insidethe Cortex™ -M3 Bus Matrix,the Cortex™ -M3 bus cyclesmay have to compete withC28x bus cyclesfor accesstotheAHB bus on theway totheEPI peripheral.See Figure6-4tosee how EPI interfacestothe ConcertoMasterSubsystem,theConcertoControlSubsystem,Resets,Clocks,and Interrupts. NOTE The ControlSubsystem has no directaccesstoEPI insiliconrevision0 devices. Depending on how theReal-TimeWindow registersare configuredinsidetheBus Matrix,thearbitration between the Cortex™ -M3 and C28x bus cyclesisfixed-prioritywithCortex™ -M3 havinghigherpriority than C28x, or the C28x having the optionto own the Bus Matrixfor a fixedperiod of time (window)— effectivelystallingallCortex™ -M3 accessesduringthattime.AnotherEPI registerinsidethe Cortex™ -M3 Bus Matrixisthe Memory ProtectionRegister,which enablesassignmentsof chip-select spaces toCortex™ -M3 orC28x EPI accesses(orboth).The assignmentsofchip-selectspaces preventa bus cycle(fromany processor)thatdoes notown a givenchip-selectspace,fromgettingthroughtoEPI. The Real-timeWindow registersaretheonlyEPI-relatedregistersthatareconfigurableby theC28x. The Memory ProtectionRegisteris configurableonly by the Cortex™ -M3 CPU, as are allconfiguration registersinsidetheEPI peripheral.Figure6-4 shows theEPI registersand how theyrelatetoindividual blockswithintheEPI. Once a bus cyclearrivesattheAHB bus interfaceinsidetheEPI peripheral,thebus cycleisroutedtothe General-PurposeBlock,SDRAM Block,or the Host Bus Module, depending on the operatingmode chosen throughtheEPI ConfigurationRegister.Writecyclesare bufferedina 4-word-deepWriteFIFO; therefore,inmost cases,thewritecyclesdo notstalltheCPU or DMA unlesstheWriteFIFO becomes full.Read cyclescan be handledintwo differentways:blockingreadcyclesand non-blockingreadcycles. Blockingreadcyclesareimplementedwhen thecontentofa Read Data Registeris0.Blockingreadsstall theCPU orDMA untilthebus transactioncompletes.Non-blockingreadcyclesaretriggeredwhen a non- zerovalueiswrittenintoa Read Data Register.A non-zerovaluebeingwrittenintoa Read Data register triggersEPI to autonomouslyperformmultipledata reads inthe background(withoutinvolvingCPU or DMA) accordingto valuesstoredinsidethe Read Address Registerand the Read Size Register.The incomingdataisthentemporarilystoredintheNon-BlockingRead (NBR) FIFO untilan EPI interruptis generatedto prompt the CPU or DMA to read the FIFO withoutriskof stalling.Furthermore,EPI has actuallytwo setsofData/Address/Sizeregisters(set0 and set1) toenableping-pongoperationofnon- blockingreads.Ina ping-pongoperation,whilethepreviouslyfetcheddataisbeingread by theCPU or DMA fromone end oftheNBR FIFO,thenextsetofdatawords issimultaneouslybeingdepositedintothe otherend oftheNBR FIFO. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 129 SubmitDocumentationFeedback

PRODUCT□PREVIEW GPIO_MUX1 EPI AHB BUS M3 BUS MA TRIX uDMA HOST BUS INTERFACESDRAM INTERFACEGENERAL PURPOSE INTERFACE BAUD RATE CONTROL AHB BUS INTERFACE EPI MUX

42 PINS

GPIOCSEL REGSDRAM CFG REG GPIOCSEL REGHB-8 CONFIG2 REGGPIOCSEL REGGP CONFIG2 REG GPIOCSEL REGHB-8 CONFIG REG 8-BIT MODE GPIOCSEL REG GPIOCSEL REG 16-BIT MODE HB-16 CONFIG2 REG HB-16 CONFIG REGGPIOCSEL REGGP CONFIG REG GPIOCSEL REGEPI ADDR MAP REG EPI BAUD REG READ FIFO CNT REG FIFO LEVEL SEL REG EPI CONFIG REG EPI ST ATUS REG READ FIFO REG 8X32 NBR FIFO4X32 WR FIFO READ FIFO ALIAS 1 READ FIFO ALIAS 2 READ FIFO ALIAS 3 READ FIFO ALIAS 4 READ FIFO ALIAS 5 READ FIFO ALIAS 6 READ FIFO ALIAS 7 C28 CPU C28 DMA CPU APB BUS RTWEPIREG REG RTWEPICNTR REG RTWEPIWD REG CEPIST ATUS REG MEMPROT REG MEM32 TO AHB BUS BRIDGE CONVERTS C28 CPU/DMA BUS CYCLES TO M3 AHB BUS CYCLES MEM32 TO AHB BUS BRIDGE FREQ GASKET REAL-TIME WINDOW MODE ALLOWS UN-INTERRUPTED ACCESS TO EPI FROM C28 CPU/DMA, WHILE STALLING M3 CPU/DMA CYCLES THE M3 FREQUENCY GASKET REDUCES AHB BUS ACCESS FREQUENCY FOR C28 CPU/DMA CYCLES BY FACTOR OF 2 OR FACTOR OF 4 MEMORY PROTECTION LOGIC ASSIGNS CS SPACES TO C28 ONLY, M3 ONLY, OR BOTH NVIC PIE WR FIFO CNT REG EPI REQ EPI EPI CHAN 20 CHAN 22 VECT# 69 INT12/INTx.6 MASK INT ST AT REG ERR INT ST AT /CLR INT MASK REG RAW INT ST AT REG EPI INTERRUPT INTERRUPT SOURCES EPI RD DATA0 REG EPI RD ADDR0 REG EPI RD SIZE0 REG EPI RD DATA1 REG EPI NON-BLOCKING ACCESS REGISTERS M3SSCLK EPI RD ADDR0 REG EPI RD SIZE0 REG WRITE FIFO READ (NON-BLOCKING) NON-FIFO READ (BLOCKING) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-4.ExternalPeripheralInterface(EPI)

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 EPI can directlyinterrupttheCortex™ -M3 CPU, theCortex™ -M3 uDMA, and theC28x CPU (butnotthe C28x DMA) viatheEPI interrupt.Typically,EPI interruptsare used toprompt theCPU or DMA tomove data to and from EPI. There are fourEPI Interruptregistersthatcontrolvariousfacetsof interrupt generation,clearing,and masking.The EPI Interruptcan triggerµDMA to performreads and writes throughDMA Channels20 and 22.Ifa CPU istheintendedrecipient,theCortex™ -M3 CPU isinterrupted by Nested VectoredInterruptController(NVIC)vector69,and theC28x CPU isinterruptedthroughthe INT12/INTx6vectortothePIE. DuringEPI bus cycles,addressesenteringtheEPI module can propagateunchanged tothepins,or be remapped to differentaddresses accordingto values storedin the EPI Address Map Registerin conjunctionwiththemost significantbitoftheincomingaddress. The EPI'sthreeprimaryoperatingmodes are:the General-PurposeMode, the SDRAM Mode, and the HostBus Mode (including8-bitand 16-bitversions).

6.1.4.1 EPI General-PurposeMode

The EPI General-PurposeMode is designed for high-speed clocked interfacessuch as ones communicatingwithFPGAs and CPLDs. The high-speedclockedinterfacesare differentfrom theslower Host Bus interfaces,which have more relaxedtimingsthatare compatiblewithestablishedprotocolslike ones used to communicate with8051 devices.Supportof bus cycleframingand preciselycontrolled clockingare theadditionalfeaturesoftheGeneral-PurposeMode thatdifferentiatetheGeneral-Purpose Mode fromthe8-bitand 16-bitHostBus Modes. Framingallowsmultiplebus transactionstobe groupedtogetherwithan outputsignalcalledFRAME. The slavedevicerespondingtothebus cyclesmay use thissignaltorecognizerelatedwords ofdataand to speed up theirtransfers.The frame lengthsare programmable and may vary from 1 to 30 clocks, dependingon theclockingmode used. Preciseclockingisaccomplishedwitha dedicatedclockoutputpin(CLK).Devicesrespondingthe bus cyclescan synchronizeto CLK forfastertransfers.The clockfrequencycan be preciselycontrolled throughtheBaud Rate Controlblock.Thisoutputclockcan be gatedor free-running.A gatedapproach uses a setup-timemodel inwhichtheEPI clockcontrolswhen bus transactionsarestartingand stopping. A free-runningEPI clockrequiresanothermethod fordeterminingwhen dataislive,such as theframepin orRD/WR strobes. These and numerous otheraspectsof the General-PurposeMode are controlledthroughthe General- Purpose ConfigurationRegisterand the General-PurposeConfiguration2Register.The clockingforthe General-PurposeMode isconfiguredthroughtheEPI Baud RegisteroftheEPI Baud Rate Controlblock. See Figure6-5 fora snapshotof the General-PurposeMode registers,modes, and features.For more detailedmaps oftheGeneral-PurposeMode, see Table6-1. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 131 SubmitDocumentationFeedback

PRODUCT□PREVIEW EPI CONFIG REG MODE = GEN PURP READY SIGNAL ADDRESS RANGE DATA SIZE ASIZE = 3 ASIZE = 0 A0 – A18 A0 – A10 A0 – A2 N/A YES YES YES NO GP CONFIG REG DSIZE = 0 DSIZE = 3 RDYEN = 1 A0 – A2 YES 24 A0 – A10 YES 16 A0 – A18 YES 8 FRMPIN = 1 RDYEN = 0 FRAME SIGNAL YES NO A0 – A19 NO 8 A0 – A19 NO 8 YES NO ASIZE = 2 DSIZE = 1 ASIZE = 1 DSIZE = 2 RDYEN = X FRMPIN = X A0 – A3 NO 24 A0 – A3 NO 24 A0 – A11 NO 16 A0 – A11 NO 16 YES NO YES NO YES NO YES NO NO RDYEN = 1 FRMPIN = 1 RDYEN = 0 RDYEN = 1 FRMPIN = 1 RDYEN = 0 RDYEN = 1 FRMPIN = 1 RDYEN = 0 RDYEN = 1 FRMPIN = 1 RDYEN = 0 RDYEN = 1 FRMPIN = 1 RDYEN = 0 F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-5.EPI General-PurposeModes

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table6-1.EPI MODES – General-PurposeMode (EPICFG/MODE = 0x0) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN General-Purpose General-Purpose General-Purpose General-PurposeAccessibleby Accessibleby (AvailableGPIOMUX_1Signal Signal Signal SignalCortex™ -M3 C28x Muxing Choices forEPI)(D8,A20) (D16,A12) (D24,A4) (D30,No Addr) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 D8 D8 D8 PE0_GPIO24 EPI0S9 A1 D9 D9 D9 PE1_GPIO25 EPI0S10 A2 D10 D10 D10 PH4_GPIO52 EPI0S11 A3 D11 D11 D11 PH5_GPIO53 EPI0S12 A4 D12 D12 D12 PF4_GPIO36 EPI0S13 A5 D13 D13 D13 PG0_GPIO40 EPI0S14 A6 D14 D14 D14 PG1_GPIO41 EPI0S15 A7 D15 D15 D15 PF5_GPIO37 EPI0S16 A8 A0 D16 D16 PJ0_GPIO56 EPI0S17 A9 A1 D17 D17 PJ1_GPIO57 EPI0S18 A10 A2 D18 D18 PJ2_GPIO58 EPI0S19 A11 A3 D19 D19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A12 A4 D29 D29 PD2_GPIO18 EPI0S21 A13 A5 D21 D21 PD3_GPIO19 EPI0S22 A14 A6 D22 D22 PB5_GPIO13 EPI0S23 A15 A7 D23 D23 PB4_GPIO12 EPI0S24 A16 A8 A0 D24 PE2_GPIO26 EPI0S25 A17 A9 A1 D25 PE3_GPIO27 EPI0S26 A18 A10 A2 D26 PH6_GPIO54 EPI0S27 A19/RDY A11/RDY A3/RDY D27 PH7_GPIO55 EPI0S28 WR WR WR D28 PD5_GPIO21 PJ4_GPIO60 EPI0S29 RD RD RD D29 PD6_GPIO22 PJ5_GPIO61 EPI0S30 FRAME FRAME FRAME D30 PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK CLK CLK D31 PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 133 SubmitDocumentationFeedback

PRODUCT□PREVIEW EPI CONFIG REG MODE = SDRAM SDRAM CFG REG SDRAM SIZE DATA SIZE SIZE = 0 SIZE = 1 SIZE = 2 SIZE = 3

16 MBit

128 MBit

256 MBit

512 MBit

F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.1.4.2 EPI SDRAM Mode

The EPI SDRAM Mode combines high performance,low cost,and low pin utilizationto access up to 512 megabits(Mb)ofexternalmemory. Main featuresoftheEPI SDRAM interfaceare:

Supportsx16 (singledatarate)SDRAM
Supportslow-costSDRAMs up to64 megabytes (MB) [or512Mb]
Includesautomaticrefreshand accesstoallbanks,rows
IncludesSleep/StandbyMode tokeep contentsactivewithminimalpower drain
Multiplexedaddress/datainterfaceforreducedpincount See Figure6-6 fora snapshotof the SDRAM Mode registersand supportedmemory sizes.For more detailedmaps oftheSDRAM Mode, see Table6-2. Figure6-6.EPI SDRAM Mode

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table6-2.EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN Accessibleby (AvailableGPIOMUX_1Accessibleby C28x Column/Row Address DataCortex™ -M3 Muxing Choices forEPI) EPI0S0 A0 D0 PH3_GPIO51 EPI0S1 A1 D1 PH2_GPIO50 EPI0S2 A2 D2 PC4_GPIO68 EPI0S3 A3 D3 PC5_GPIO69 EPI0S4 A4 D4 PC6_GPIO70 EPI0S5 A5 D5 PC7_GPIO71 EPI0S6 A6 D6 PH0_GPIO48 EPI0S7 A7 D7 PH1_GPIO49 EPI0S8 A8 D8 PE0_GPIO24 EPI0S9 A9 D9 PE1_GPIO25 EPI0S10 A10 D10 PH4_GPIO52 EPI0S11 A11 D11 PH5_GPIO53 EPI0S12 A12 D12 PF4_GPIO36 EPI0S13 BA0 D13 PG0_GPIO40 EPI0S14 BA1 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S16 DQML PJ0_GPIO56 EPI0S17 DQMH PJ1_GPIO57 EPI0S18 CAS PJ2_GPIO58 EPI0S19 RAS PD4_GPIO20 PJ3_GPIO59 EPI0S28 WE PD5_GPIO21 PJ4_GPIO60 EPI0S29 CS PD6_GPIO22 PJ5_GPIO61 EPI0S30 CKE PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK PG7_GPIO47 EPI0S20 x PD2_GPIO18 EPI0S21 x PD3_GPIO19 EPI0S22 x PB5_GPIO13 EPI0S23 x PB4_GPIO12 EPI0S24 x PE2_GPIO26 EPI0S25 x PE3_GPIO27 EPI0S26 x PH6_GPIO54 EPI0S27 x PH7_GPIO55 EPI0S32 x PF2_GPIO34 PC0_GPIO64 EPI0S33 x PF3_GPIO35 PC1_GPIO65 EPI0S34 x PE4_GPIO28 EPI0S35 x PE5_GPIO29 EPI0S36 x PB7_GPIO15 PC3_GPIO67 EPI0S37 x PB6_GPIO14 PC2_GPIO66 EPI0S38 x PF6_GPIO38 PE4_GPIO28 EPI0S39 x PG2_GPIO42 EPI0S40 x PG5_GPIO45 EPI0S41 x PG6_GPIO46 Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 135 SubmitDocumentationFeedback

PRODUCT□PREVIEW HB8 CONFIG2 REGEPI CONFIG REG MODE = HB-8 HP8 CONFIG REG MODE = NOMUX MODE = MUXED MODE = FIFO CSCFG = 2 CS CSCFG = ALE + 2 CS N/A N/A NO NO READY SIGNAL ADDRESS RANGE DATA SIZE CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A19 A0 – A19 A0 – A18 A0 – A17 NO NO NO NO CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A27 A0 – A27 A0 – A26 A0 – A25 NO NO NO NO F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.1.4.3 EPI Host Bus Mode

There are two versionsoftheEPI Host Bus Mode: an 8-bitversion(HB-8)and a 16-bitversion(HB-16). Bus Mode. 6.1.4.3.1EPI 8-BitHost Bus (HB-8)Mode The 8-BitHost Bus (HB-8)Mode uses fewerdatapinsthanthe16-BitHost Bus (HB-16)Mode; hence, more pinsare availableforaddress.The HB-8 Mode isalsoslowerthan the General-PurposeMode in ordertoaccommodate olderlogic.The HB-8 Mode isselectedwiththeMODE fieldofEPI Configuration Register.Withinthe HB-8 Mode, two additionalregistersare used to selectaddress/datamuxing,chip selects,and other options.These registersare the HB-8 ConfigurationRegisterand the HB-8 Configuration2Register.See Figure6-7fora snapshotofHB-8 registers,modes, and features. Figure6-7.EPI 8-BitHost Bus Mode The HB-8 Muxed Mode multiplexesaddress signalswithlow-orderdata signals.For thisreason,the Muxed Mode allowsfora largeraddressspace as compared totheNon-Muxed Mode. The HB-8 Muxed Mode isselectedwiththeMODE fieldoftheHB-8 ConfigurationRegister.Inadditiontodataand address signals,the HB-8 Muxed Mode alsofeaturesthe ALE signal(indicatingto an externallatchto capture addressand holdtheaddressuntilthedataphase);RD and WR datastrobes;and 1–4 Chip Select(CS) signalstoenableone offourexternalperipherals.The ALE and CS optionsarechosen withtheCSCFG fieldoftheHB-8 Configuration2Register.For more detailedmaps oftheHB-8 Muxed Mode, see Table6-

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table6-3.EPI MODES – 8-BitHost-Bus Mode (EPICFG/MODE = 0x2), Muxed (EPIHB16CFG/MODE = 0x0) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1 Cortex™ -M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 A8 A8 A8 A8 PE0_GPIO24 EPI0S9 A9 A9 A9 A9 PE1_GPIO25 EPI0S10 A10 A10 A10 A10 PH4_GPIO52 EPI0S11 A11 A11 A11 A11 PH5_GPIO53 EPI0S12 A12 A12 A12 A12 PF4_GPIO36 EPI0S13 A13 A13 A13 A13 PG0_GPIO40 EPI0S14 A14 A14 A14 A14 PG1_GPIO41 EPI0S15 A15 A15 A15 A15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 137 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com The HB-8 Non-Muxed Mode uses dedicatedpinsforaddressand datasignals.For thisreason,theNon- Muxed Mode has reducedaddressreachas compared totheMuxed Mode. The HB-8 Non-Muxed Mode isselectedwiththe MODE fieldof the HB-8 ConfigurationRegister.In additionto data and address signals,theHB-8 Non-Muxed Mode alsofeaturestheALE signal(indicatingtoan externallatchtocapture addressand holdtheaddressuntilthedataphase);RD and WR datastrobes;and 1–4 Chip Select(CS) signalstoenableone offourexternalperipherals.The ALE and CS optionsarechosen withtheCSCFG fieldof the HB-8 Configuration2Register.For more detailedmaps of the HB-8 Non-Muxed Mode, see Table6-4. Table6-4.EPI MODES – 8-BitHost-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1 Cortex™ -M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 A0 A0 A0 PE0_GPIO24 EPI0S9 A1 A1 A1 A1 PE1_GPIO25 EPI0S10 A2 A2 A2 A2 PH4_GPIO52 EPI0S11 A3 A3 A3 A3 PH5_GPIO53 EPI0S12 A4 A4 A4 A4 PF4_GPIO36 EPI0S13 A5 A5 A5 A5 PG0_GPIO40 EPI0S14 A6 A6 A6 A6 PG1_GPIO41 EPI0S15 A7 A7 A7 A7 PF5_GPIO37 EPI0S16 A8 A8 A8 A8 PJ0_GPIO56 EPI0S17 A9 A9 A9 A9 PJ1_GPIO57 EPI0S18 A10 A10 A10 A10 PJ2_GPIO58 EPI0S19 A11 A11 A11 A11 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A12 A12 A12 A12 PD2_GPIO18 EPI0S21 A13 A13 A13 A13 PD3_GPIO19 EPI0S22 A14 A14 A14 A14 PB5_GPIO13 EPI0S23 A15 A15 A15 A15 PB4_GPIO12 EPI0S24 A16 A16 A16 A16 PE2_GPIO26 EPI0S25 A17 A17 A17 A17 PE3_GPIO27 EPI0S26 A18 A18 A18 CS0 PH6_GPIO54 EPI0S27 A19 A19 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table6-4.EPI MODES – 8-BitHost-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1)(continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1 Cortex™ -M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 The HB-8 FIFO Mode uses 8 bitsofdata,removes ALE and addresspins,and optionallyadds external FIFO Full/Emptyflaginputs.This scheme is used by many devices,such as radios,communication devices(includingUSB2 devices),and some FPGA configuration(FIFO throughblockRAM). ThisFIFO Mode presentsthedatasideofthenormalHost-Businterface,butispaced by FIFO controlsignals.Itis importantto considerthatthe FIFO Full/Emptycontrolinputsmay stallthe EPI interfaceand can potentiallyblockotherCPU or DMA accesses.For more detailedmaps of the HB-8 FIFO Mode, see Table6-5. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 139 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table6-5.EPI MODES – 8-BitHost-Bus Mode (EPICFG/MODE = 0x2), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With One With TwoAccessibleby (AvailableGPIOMUX_1Accessibleby C28x Chip Select Chip SelectsCortex™ -M3 Muxing Choices forEPI)(CSCFG = 0x1) (CSCFG = 0x2) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S8 x x PE0_GPIO24 EPI0S9 x x PE1_GPIO25 EPI0S10 x x PH4_GPIO52 EPI0S11 x x PH5_GPIO53 EPI0S12 x x PF4_GPIO36 EPI0S13 x x PG0_GPIO40 EPI0S14 x x PG1_GPIO41 EPI0S15 x x PF5_GPIO37 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 PJ3_GPIO59 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 EPI0S32 x x PF2_GPIO34 PC0_GPIO64 EPI0S31 x x PG7_GPIO47 EPI0S33 x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x PE4_GPIO28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46

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PRODUCT□PREVIEW HB16 CONFIG2 REGEPI CONFIG REG MODE = HB-16 HP16 CONFIG REG MODE = NOMUX MODE = MUXED MODE = FIFO BSEL = DON’T CARE CSCFG = 2 CS CSCFG = ALE + 2 CS N/A N/A NO NO BSEL = NO CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS CSCFG = 3 CS CSCFG = 4 CS READY SIGNAL A0 – A11 ADDRESS RANGE A0 – A11 A0 – A10 A0 – A9 A0 – A18 A0 – A16 NO YES YES YES YES YES DATA SIZE BSEL = YES CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS CSCFG = 3 CS CSCFG = 4 CS A0 – A9 A0 – A9 A0 – A8 A0 – A7 A0 – A16 A0 – A14 NO YES YES YES YES YES BSEL = NO CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A27 A0 – A27 A0 – A26 A0 – A25 NO NO NO NO BSEL = YES CSCFG = ALE CSCFG = 1 CS CSCFG = 2 CS CSCFG = ALE + 2 CS A0 – A25 A0 – A25 A0 – A24 A0 – A23 NO NO NO NO F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 6.1.4.3.2EPI 16-BitHost Bus (HB-16)Mode The 16-BitHost Bus (HB-16)Mode uses feweraddresspinsthanthe8-BitHost Bus (HB-8)Mode; hence, more pinsareavailablefordata.The HB-16 Mode isalsoslowerthantheGeneral-PurposeMode inorder to accommodate olderlogic.The HB-16 Mode isselectedwiththe MODE fieldof EPI Configuration Register.WithintheHB-16 Mode, two additionalregistersare used toselectaddress/datamuxing,byte selects,chipselects,and otheroptions.These registersaretheHB-16 ConfigurationRegisterand theHB- 16 Configuration2Register.See Figure6-8fora snapshotofHB-16 registers,modes, and features. Figure6-8.EPI 16-BitHost Bus Mode Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 141 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com The HB-16 Muxed Mode multiplexesaddresssignalswithlow-orderdata signals.For thisreason,the Muxed Mode allowsfora largeraddressspace as compared totheNon-Muxed Mode. The HB-16 Muxed Mode isselectedwiththeMODE fieldoftheHB-16 ConfigurationRegister.Inadditiontodataand address signals,theHB-16 Muxed Mode alsofeaturestheALE signal(indicatingtoan externallatchtocapture addressand holdthe addressuntilthe data phase);RD and WR data strobes;1–4 Chip Select(CS) signalstoenableone offourexternalperipherals;and two Byte Select(BSEL) signalstoaccommodate byteaccessestolowerorupperhalfof16-bitdata.The ByteSelectsarechosen withtheBSEL fieldofthe HB-16 ConfigurationRegister.The ALE and CS optionsare chosen withtheCSCFG fieldoftheHB-16 Configuration2Register.For more detailedmaps of the HB-16 Muxed Mode withoutByte Selects,see Table6-6.Formore detailedmaps oftheHB-16 Muxed Mode withByteSelects,see Table6-7. Table6-6.EPI MODES – 16-BitHost-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0),WithoutByte Selects(EPIHB16CFG/BSEL = 0x1), and With Chip Selects(EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1 Cortex™ -M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table6-6.EPI MODES – 16-BitHost-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0),WithoutByte Selects(EPIHB16CFG/BSEL = 0x1), and With Chip Selects(EPIHB16CFG2/CSCFG = 0x0,1,2,3)(continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1 Cortex™ -M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Table6-7.EPI MODES – 16-BitHost-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0),With Byte Selects(EPIHB16CFG/BSEL = 0x0), and With Chip Selects(EPIHB16CFG2/CSCFG=0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1 Cortex™ -M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 BSEL0 PE2_GPIO26 EPI0S25 A25 A25 BSEL0 BSEL1 PE3_GPIO27 Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 143 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table6-7.EPI MODES – 16-BitHost-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0),With Byte Selects(EPIHB16CFG/BSEL = 0x0), and With Chip Selects(EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1 Cortex™ -M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 The HB-16 Non-Muxed Mode uses dedicatedpinsforaddressand datasignals.For thisreason,theNon- Muxed Mode has reducedaddressreachas compared totheMuxed Mode. The HB-16 Non-Muxed Mode isselectedwiththe MODE fieldof the HB-16 ConfigurationRegister.In additionto data and address signals,the HB-16 Non-Muxed Mode alsofeaturesthe ALE signal(indicatingto an externallatchto captureaddressand holdtheaddressuntilthedataphase);RD and WR datastrobes;1–4 Chip Select (CS) signalsto enable one of four externalperipherals;and two Byte Select(BSEL) signalsto accommodate byteaccessestoloweror upper halfof16-bitdata.The Byte Selectsare chosen withthe BSEL fieldof the HB-16 ConfigurationRegister.The ALE and CS optionsare chosen withthe CSCFG fieldoftheHB-16 Configuration2Register.For Non-Muxed bus cycles,most oftheCSCFG modes also supporta RDY signal.The RDY inputtoEPI isused by an externalperipheraltoextendbus cycleswhen theperipheralneeds more timetocompletereadingor writingofdata.Whilemost EPI modes use up to 32 pins,theNon-Muxed CSCFG modes with3 and 4 Chip Selectsuse 10 additionalpinstoextendthe addressreach and the number of CS signals.For detailedmaps of HB-16 Non-Muxed Modes without Byte Selects,see Table 6-8 and Table 6-9. For detailedmaps of HB-16 Non-Muxed Modes with Byte Selects,see Table6-10and Table6-11.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table6-8.EPI MODES – 16-BitHost-Bus Mode (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1),WithoutByte Selects(EPIHB16CFG/BSEL = 0x1), and With Chip Selects(EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1Accessibleby C28xCortex™ -M3 Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 A8 PE2_GPIO26 EPI0S25 A9 A9 A9 A9 PE3_GPIO27 EPI0S26 A10 A10 A10 CS0 PH6_GPIO54 EPI0S27 A11 A11 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 145 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table6-9.EPI MODES – 16-BitHost-Bus Mode (EPICFG/MODE=0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1),WithoutByte Selects(EPIHB16CFG/BSEL = 0x1), and With AdditionalChip Selects(EPIHB16CFG2/CSCFG = 0x5,7) EPI SIGNAL EPI SIGNALEPI PORT NAME DEVICE PIN EPI PORT NAME DEVICE PINFUNCTION FUNCTION With WithAccessible Accessible Accessible AccessibleThree (AvailableGPIOMUX_1 Four (AvailableGPIOMUX_1by by by byChip Selects Muxing Choices forEPI) Chip Selects Muxing Choices forEPI)Cortex™ -M3 C28x Cortex™ -M3 C28x(CSCFG = 0x7) (CSCFG = 0x5) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S25 A9 PE3_GPIO27 EPI0S25 A9 PE3_GPIO27 EPI0S26 A10 PH6_GPIO54 EPI0S26 A10 PH6_GPIO54 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S40 A15 PG5_GPIO45 EPI0S35 A16 PE5_GPIO29 EPI0S41 A16 PG6_GPIO46 EPI0S40 A17 PG5_GPIO45 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S41 A18 PG6_GPIO46 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIO28 EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Table6-10.EPI MODES – 16-BitHost-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1),With Byte Selects(EPIHB16CFG/BSEL = 0x0), and With Chip Selects(EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With With With With Accessibleby Address Latch One Two ALE and Two (AvailableGPIOMUX_1Accessibleby C28xCortex™ -M3 Enable Chip Select Chip Selects Chip Selects Muxing Choices forEPI) (CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 BSEL0 PE2_GPIO26 EPI0S25 A9 A9 BSEL0 BSEL1 PE3_GPIO27 EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 147 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table6-11.EPI MODES – 16-BitHost-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1),With Byte Selects(EPIHB16CFG/BSEL = 0x0), and With AdditionalChip Selects(EPIHB16CFG2/CSCFG = 0x5,7) EPI SIGNAL EPI SIGNALEPI PORT NAME DEVICE PIN EPI PORT NAME DEVICE PINFUNCTION FUNCTION With WithAccessible Accessible Accessible AccessibleThree (AvailableGPIOMUX_1 Four (AvailableGPIOMUX_1by by by byChip Selects Muxing Choices forEPI) Chip Selects Muxing Choices forEPI)Cortex™ -M3 C28x Cortex™ -M3 C28x(CSCFG = 0x7) (CSCFG = 0x5) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S40 A9 PG5_GPIO45 EPI0S40 A9 PG5_GPIO45 EPI0S41 A10 PG6_GPIO46 EPI0S41 A10 PG6_GPIO46 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S25 BSEL0 PE3_GPIO27 EPI0S35 A16 PE5_GPIO29 EPI0S26 BSEL1 PH6_GPIO54 EPI0S25 BSEL0 PE3_GPIO27 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S26 BSEL1 PH6_GPIO54 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIO28 EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 The HB-16 FIFO Mode uses 16 bitsofdata,removes ALE and addresspins,and optionallyadds external FIFO Full/Emptyflaginputs.This scheme is used by many devices,such as radios,communication devices(includingUSB2 devices),and some FPGA configuration(FIFO throughblockRAM). ThisFIFO Mode presentsthedatasideofthenormalHost-Businterface,butispaced by FIFO controlsignals.Itis importantto considerthatthe FIFO Full/Emptycontrolinputsmay stallthe EPI interfaceand can potentiallyblockotherCPU orDMA accesses.For detailedmaps oftheHB-16 FIFO Mode, see Table6- 12. Table6-12.EPI MODES – 16-BitHost-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With One With TwoAccessibleby (AvailableGPIOMUX_1Accessibleby C28x Chip Select Chip SelectsCortex™ -M3 Muxing Choices forEPI)(CSCFG = 0x1) (CSCFG = 0x2) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 PF5_GPIO37 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x x PF2_GPIO34 PC0_GPIO64 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 PJ3_GPIO59 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 EPI0S31 x x PG7_GPIO47 Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 149 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Table6-12.EPI MODES – 16-BitHost-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3)(continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With One With TwoAccessibleby (AvailableGPIOMUX_1Accessibleby C28x Chip Select Chip SelectsCortex™ -M3 Muxing Choices forEPI)(CSCFG = 0x1) (CSCFG = 0x2) EPI0S33 x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x PE4_GPIO28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.2 Master Subsystem Peripherals

MasterSubsystem peripheralsare locatedon theAPB Bus and AHB Bus, and are accessiblefrom the Cortex™ -M3 CPU/ µDMA. The AHB peripheralsincludeEPI, USB, and two CAN modules. The APB peripheralsincludeEMAC, two I2Cs,fiveUARTs, fourSSIs,fourGPTIMERs, two WDOGs, NMI WDOG, and a µCRC module (CyclicRedundancy Check).The Cortex™ -M3 CPU/ µDMA alsohave access to Analog(ResultRegistersonly)and Shared peripherals(seeSection6.1).

6.2.1 Synchronous SerialInterface(SSI)

This devicehas fourSynchronous SerialInterface(SSI)modules. Each SSI has a Master or Slave interfaceforsynchronousserialcommunicationwithperipheraldevicesthathave Texas Instruments™ SynchronousSerialinterfaces,SPI,MICROWIRE ® ,orFreescale™ serialformat. The SSI peripheralperformsserial-to-parallelconversionon datareceivedfrom a peripheraldevice.The CPU accesses data,control,and statusinformation.The transmitand receivepathsare bufferedwith internalFIFO memories,allowingup toeight16-bitvaluestobe storedindependentlyinbothtransmitand receivemodes. The SSI also supportsµDMA transfers.The transmitand receiveFIFOs can be programmed as destination/sourceaddressesinthe µDMA module.An µDMA operationisenabledby settingtheappropriatebitorbitsintheSSIDMACTL register. Figure6-9shows theSSI peripheral.

6.2.1.1 BitRate Generation

The SSI includesa programmablebit-rateclockdividerand prescalertogeneratetheserialoutputclock. Bitratesare supportedto 2 MHz and higher,althoughmaximum bitrateisdeterminedby peripheral devices.The serialbitrateisderivedby dividing-downtheinputclock(SysClk).The clockisfirstdivided by an even prescalevalueCPSDVSR from 2 to 254, which isprogrammed inthe SSI Clock Prescale (SSICPSR) register.The clockisfurtherdividedby a valuefrom1 to256,whichis1 + SCR, where SCR isthevalueprogrammed intheSSI Control0 (SSICR0) register.The frequencyoftheoutputclockSSIClk isdefinedby: SSIClk= SysClk/[CPSDVSR *(1+ SCR)] NOTE For mastermode, thesystem clockmust be atleastfourtimesfasterthanSSIClk,withthe restrictionthatSSIClkcannotbe fasterthan25 MHz. For slavemode, thesystem clockmust be atleast12 timesfasterthanSSIClk.

6.2.1.2 TransmitFIFO

The transmitFIFO isa 16-bit-wide,8-location-deep,first-in,first-outmemory buffer.The CPU writesdata totheFIFO throughtheSSI Data (SSIDR) register,and dataisstoredintheFIFO untilthedataisread out by the transmissionlogic.When configuredas a master or a slave,paralleldata iswrittenintothe transmitFIFO priorto serialconversionand transmissionto the attachedslaveor master,respectively, throughtheSSITx pin. Inslavemode, theSSI transmitsdataeach timethemasterinitiatesa transaction.IfthetransmitFIFO is empty and themasterinitiatesa transaction,theslavetransmitsthe8thmost recentvalueinthetransmit FIFO. Iflessthaneightvalueshave been writtentothetransmitFIFO sincetheSSI module clockwas enabledusingtheSSI bitintheRGCG1 register,then"0"istransmitted.Care shouldbe takentoensure thatvaliddataisintheFIFO as needed.The SSI can be configuredtogeneratean interruptoran µDMA requestwhen theFIFO isempty. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 151 SubmitDocumentationFeedback

PRODUCT□PREVIEW TRANSMIT / RECEIVE LOGIC PIN SSIFSS SSICLK SSIRX SSITX PIN PIN PIN GPIO_MUX1 CONTROL / ST ATUS INTR CONTROL SSICR0 REG SSICR1 REG SSISR REG SSIRIS REG SSIICR REG SSIIM REG SSIPERIPHLD4 REG CPU REGISTER ACCESS M3SSCLK SSI M3CLKENBx M3 CLOCKS uDMA M3 NVICSSIxIRQ SSIPERIPHLD5 REG SSIPERIPHLD6 REG SSIPCELLID0 REG SSIPCELLID1 REG SSIPCELLID2 REG SSIPCELLID3 REG SSIPERIPHLD0 REG SSIPERIPHLD1REG SSIPERIPHLD2 REG SSIPERIPHLD3 REG SSIPERIPHLD7 REG SSIMIS REG SSIDMACTL REG DMA CONTROL SSICPSR REG CLOCK PRESCALER SSIxCLK INTxREQ DMAxREQ TX FIFO ST AT RX FIFO ST AT IDENTIFICA TION REGISTERS INTR TX/RX FIFO ACCESS TX FIFO ( 8 x 16 ) RX FIFO ( 8 x 16 ) SSIDR REG F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-9.SSI

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.2.1.3 Receive FIFO

The receiveFIFO isa 16-bit-wide,8-location-deep,first-in,first-outmemory buffer.Receiveddatafromthe serialinterfaceisstoredinthebufferuntilreadoutby theCPU, whichaccessesthereadFIFO by reading theSSIDR register.When configuredas a masterorslave,serialdatareceivedthroughtheSSIRx pinis registeredpriortoparallelloadingintotheattachedslaveormasterreceiveFIFO,respectively.

6.2.1.4 Interrupts

The SSI can generateinterruptswhen thefollowingconditionsareobserved:

TransmitFIFO service(when thetransmitFIFO ishalffullorless)
ReceiveFIFO service(when thereceiveFIFO ishalffullormore)
ReceiveFIFO time-out
ReceiveFIFO overrun
End oftransmission Allof the interrupteventsare ORed togetherbeforebeing sent to the interruptcontroller,so the SSI generatesa singleinterruptrequesttothecontrollerregardlessofthenumber ofactiveinterrupts.Each of thefourindividualmaskable interruptscan be masked by clearingtheappropriatebitintheSSI Interrupt Mask (SSIIM)register.Settingtheappropriatemask bitenablestheinterrupt. The individualoutputs,alongwitha combined interruptoutput,allowtheuse ofeithera globalinterrupt serviceroutineormodulardevicedriverstohandleinterrupts.The transmitand receivedynamic data-flow interruptshave been separatedfromthestatusinterruptsso thatdatacan be readorwritteninresponse totheFIFO triggerlevels.The statusoftheindividualinterruptsourcescan be read from theSSI Raw InterruptStatus(SSIRIS)and SSI Masked InterruptStatus(SSIMIS)registers. The receiveFIFO has a time-outperiodthatis32 periodsattherateofSSIClk(whetherornotSSIClkis currentlyactive)and isstartedwhen theRX FIFO goes from EMPTY tonot-EMPTY. IftheRX FIFO is emptiedbefore32 clockshave passed,thetime-outperiodisreset.As a result,theISR shouldclearthe ReceiveFIFO Time-outInterruptjustafterreadingouttheRX FIFO by writinga "1"totheRTIC bitinthe SSI InterruptClear(SSIICR)register.The interruptshouldnot be clearedso latethatthe ISR returns beforetheinterruptisactuallycleared,ortheISR may be reactivatedunnecessarily. The End-of-Transmission(EOT) interruptindicatesthatthe data has been transmittedcompletely.This interruptcan be used toindicatewhen itissafetoturnofftheSSI module clockorentersleepmode. In addition,because transmitteddataand receiveddatacompleteatexactlythesame time,theinterruptcan alsoindicatethatread dataisreadyimmediately,withoutwaitingforthereceiveFIFO time-outperiodto complete.

6.2.1.5 Frame Formats

Each dataframe isbetween 4 bitsand 16 bitslong,dependingon thesizeofdataprogrammed, and is transmittedstartingwiththeMSB. Threebasicframetypescan be selected:

Texas Instruments™ SynchronousSerial
Freescale™ SPI
MICROWIRE ® For allthreeformats,theserialclock(SSIClk)isheldinactivewhiletheSSI isidle,and SSIClktransitions attheprogrammed frequencyonlyduringactivetransmissionorreceptionofdata.The idlestateofSSIClk isutilizedto providea receivetime-outindicationthatoccurswhen the receiveFIFO stillcontainsdata aftera time-outperiod. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 153 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.2.2 UniversalAsynchronous Receiver/Transmitter(UART)

Thisdevicehas fiveUniversalAsynchronousReceiver/Transmitter(UART) modules.The CPU accesses data,control,and statusinformation.The UART alsosupportsµDMA transfers.Each UART performs functionsofparallel-to-serialand serial-to-parallelconversions.Each ofthefiveUART modules issimilar infunctionalitytoa 16C550 UART, butisnotregister-compatible. The UART isconfiguredfortransmitand receiveviathe TXE bitand the RXE bit,respectively,of the UART Control(UARTCTL) register.Transmitand receivearebothenabledoutofreset.Beforeany control registersare programmed, theUART must be disabledby clearingtheUARTEN bitinUARTCTL. Ifthe UART isdisabledduringa TX or RX operation,the currenttransactioniscompletedpriorto the UART stopping. The UART module alsoincludesa serialIR (SIR)encoder/decoderblockthatcan be connectedto an infraredtransceivertoimplementan IrDA SIR physicallayer.The SIR functionisprogrammed usingthe UARTCTL register. Figure6-10shows theUART peripheral.

6.2.2.1 Baud-Rate Generation

The baud-ratedivisorisa 22-bitnumber consistingof a 16-bitintegerand a 6-bitfractionalpart.The number formedby thesetwo valuesisused by thebaud-rategeneratortodeterminethebitperiod.Having a fractionalbaud-ratedividerallowstheUART togenerateallthestandardbaud rates. The 16-bitintegerisloadedthroughtheUART IntegerBaud-RateDivisor(UARTIBRD) register,and the6- bitfractionalpartisloadedwiththeUART FractionalBaud-RateDivisor(UARTFBRD) register.The baud ratedivisor(BRD) has thefollowingrelationshiptothesystem clock(whereBRDI istheintegerpartofthe BRD, and BRDF isthefractionalpart,separatedby a decimalplace). BRD = BRDI + BRDF = UARTSysClk /(ClkDiv*Baud Rate) where UARTSysClk isthe system clockconnectedto the UART, and ClkDiviseither16 (ifHSE in UARTCTL isclear)or8 (ifHSE isset). The 6-bitfractionalnumber (thatistobe loadedintotheDIVFRAC bitfieldintheUARTFBRD register)can be calculatedby takingthefractionalpartofthebaud-ratedivisor,multiplyingthisfractionalpartby 64, and adding0.5toaccountforroundingerrors: UARTFBRD[DIVFRAC] = integer(BRDF*64 + 0.5) The UART generatesan internalbaud-ratereferenceclockat 8x or 16x the baud rate[referredto as Baud8 and Baud16, dependingon thesettingoftheHSE bit(bit5 inUARTCTL)]. Thisreferenceclockis dividedby 8 or16 togeneratethetransmitclock,and isused forerrordetectionduringreceiveoperations. Along withthe UART LineControl,High Byte (UARTLCRH) register,the UARTIBRD and UARTFBRD registersform an internal30-bitregister.Thisinternalregisterisonlyupdatedwhen a writeoperationto UARTLCRH isperformed,so any changes to the baud-ratedivisormust be followedby a writeto the UARTLCRH registerforthechanges totakeeffect.

6.2.2.2 Transmitand Receive Logic

The transmitlogicperformsparallel-to-serialconversionon the data read from the transmitFIFO. The controllogicoutputstheserialbitstreambeginningwitha startbitand followedby thedatabits(LSB first), paritybit,and thestopbitsaccordingtotheprogrammed configurationinthecontrolregisters. The receivelogicperformsserial-to-parallelconversionon thereceivedbitstreamaftera validstartpulse has been detected.Overrun,parity,frame errorchecking,and line-breakdetectionare alsoperformed, and theirstatusaccompaniesthedatathatiswrittentothereceiveFIFO.

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PRODUCT□PREVIEW TX FIFO ( 8 x 16 ) TRANSMITTER UxRX UxTX PIN PIN GPIO_MUX1 RX FIFO ( 8 x 16 ) CONTROL / ST ATUS UARTDR REG INTR CONTROL UARTCR0 REG UARTCR1 REG UARTSR REG UARTRIS REG UARTICR REG UARTIM REG UARTPERIPHLD4 CPU REGISTER ACCESS M3SSCLK UART UARTCLKENBx M3 CLOCKSM3 NVICUARTxIRQ UARTPERIPHLD5 UARTPERIPHLD6 UARTPCELLID0 UARTPCELLID1 UARTPCELLID2 UARTPCELLID3 UARTPERIPHLD0 UARTPERIPHLD1 UARTPERIPHLD2 UARTPERIPHLD3 UARTPERIPHLD7 UARTMIS REG UARTDMACTL REG DMA CONTROL UARTIBRD REG BAUDE RATE GENERATOR INTxREQ TX FIFO ST AT RX FIFO ST AT IDENTIFICA TION REGISTERS INTR UARTIFLS REG UARTFBRD REG XCLK UARTxCLK uDMA DMAxREQ TX/RX FIFO ACCESS RECEIVER (WITH SIR RECEIVE DECODER) (WITH SIR TRANSMIT ENCODER) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure6-10.UART Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 155 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.2.2.3 Data Transmissionand Reception

Data receivedor transmittedisstoredintwo 16-byteFIFOs,thoughthereceiveFIFO has an extrafour bitsper characterforstatusinformation.For transmission,data iswrittenintothe transmitFIFO. Ifthe UART is enabled,a data frame startstransmittingwiththe parametersindicatedin the UARTLCRH register.Data continuestobe transmitteduntilthereisno dataleftinthetransmitFIFO.The BUSY bitin theUART Flag(UARTFR) registerisassertedas soon as dataiswrittentothetransmitFIFO (thatis,if theFIFO isnon-empty)and remainsassertedwhiledataisbeingtransmitted.The BUSY bitisnegated onlywhen thetransmitFIFO isempty,and thelastcharacterhas been transmittedfromtheshiftregister, includingthestopbits.The UART can indicatethatitisbusy even thoughtheUART may no longerbe enabled. When thereceiverisidle(theUnRx signaliscontinuously"1"),and thedatainputgoes Low (a startbit has been received),the receivecounterbegins runningand data is sampled on the eighthcycleof Baud16 orthefourthcycleofBaud8,dependingon thesettingoftheHSE bit(bit5 inUARTCTL). The startbitisvalidand recognizedifthe UnRx signalisstilllow on the eighthcycleof Baud16 (HSE clear)or thefourthcycleofBaud 8 (HSE set),otherwisethestartbitisignored.Aftera validstartbitis detected,successivedatabitsaresampled on every16thcycleofBaud16 or8thcycleofBaud8 (thatis, one bitperiodlater),accordingtotheprogrammed lengthofthedatacharactersand valueoftheHSE bit inUARTCTL. The paritybitisthenchecked ifparitymode isenabled.Data lengthand parityaredefined intheUARTLCRH register. Lastly,a validstopbitisconfirmedifthe UnRx signalisHigh,otherwisea framingerrorhas occurred. When a fullword isreceived,thedataisstoredinthereceiveFIFO alongwithany errorbitsassociated withthatword.

6.2.2.4 Interrupts

The UART can generateinterruptswhen thefollowingconditionsareobserved:

OverrunError
BreakError
ParityError
FramingError
ReceiveTime-out
Transmit(when theconditiondefinedintheTXIFLSEL bitintheUARTIFLS registerismet,or ifthe EOT bitinUARTCTL isset,when thelastbitofalltransmitteddataleavestheserializer)
Receive(when theconditiondefinedintheRXIFLSEL bitintheUARTIFLS registerismet) AlloftheinterrupteventsareORed togetherbeforebeingsenttotheinterruptcontroller,so theUART can onlygeneratea singleinterruptrequesttothecontrolleratany giventime.Softwarecan servicemultiple interruptevents in a singleinterruptserviceroutineby readingthe UART Masked InterruptStatus (UARTMIS) register. The interrupteventsthatcan triggera controller-levelinterruptare definedinthe UART InterruptMask (UARTIM) registerby settingthecorrespondingIM bits.Ifinterruptsarenotused,theraw interruptstatus isalwaysvisibleviatheUART Raw InterruptStatus(UARTRIS) register. Interruptsare always cleared(forboth the UARTMIS and UARTRIS registers)by writinga "1"to the correspondingbitintheUART InterruptClear(UARTICR) register. The receivetime-outinterruptisassertedwhen the receiveFIFO isnot empty,and no furtherdata is receivedover a 32-bitperiod.The receivetime-outinterruptisclearedeitherwhen the FIFO becomes empty throughreadingallthe data (orby readingthe holdingregister),or when a "1"iswrittento the correspondingbitintheUARTICR register.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.2.3 Cortex™ -M3 Inter-IntegratedCircut(I2C)

This devicehas two Cortex™ -M3 I2C peripherals.The Cortex™ -M3 Inter-IntegratedCircuit(I2C)bus providesbidirectionaldatatransferthrougha two-wiredesign(a serialdatalineSDA and a serialclock lineSCL), and interfacestoexternalI2C devicessuch as serialmemory (RAMs and ROMs), networking devices,LCDs, tone generators,and so on. The I2C bus may alsobe used forsystem testingand diagnosticpurposes in productdevelopment and manufacture.The microcontrollerincludestwo I2C modules,providingtheabilitytointeract(bothtransmitand receive)withotherI2C deviceson thebus. The two Cortex™ -M3 I2C modules includethefollowingfeatures:

Deviceson theI2C bus can be designatedas eithera masterora slave – Supportsbothtransmittingand receivingdataas eithera masterora slave – Supportssimultaneousmasterand slaveoperation
FourI2C modes – Mastertransmit – Masterreceive – Slavetransmit – Slavereceive
Two transmissionspeeds:Standard(100Kbps)and Fast(400Kbps)
Masterand slaveinterruptgeneration – Mastergeneratesinterruptswhen a transmitor receiveoperationcompletes(orabortsdue toan error) – Slave generatesinterruptswhen data has been transferredor requestedby a master or when a START orSTOP conditionisdetected
Masterwitharbitrationand clocksynchronization,multimastersupport,and 7-bitaddressingmode Figure6-11shows theCortex™ -M3 I2C peripheral.

6.2.3.1 FunctionalOverview

Each I2C module comprisesboth master and slavefunctions.For properoperation,the SDA and SCL pinsmust be configuredas open-drainsignals. The I2C bus uses onlytwo signals:SDA and SCL, named I2CSDA and I2CSCL. SDA isthebidirectional serialdatalineand SCL isthebidirectionalserialclockline.The bus isconsideredidlewhen bothlines arehigh. Everytransactionon theI2C bus isninebitslong,consistingofeightdatabitsand a singleacknowledge bit.The number ofbytespertransfer(definedas thetimebetween a validSTART and STOP condition)is unrestricted,buteach bytehas tobe followedby an acknowledgebit,and datamust be transferredMSB first.When a receivercannotreceiveanothercompletebyte,thereceivercan holdtheclocklineSCL Low and forcethe transmitterintoa waitstate.The data transfercontinueswhen the receiverreleasesthe clockSCL.

6.2.3.2 AvailableSpeed Modes

The I2C bus can run ineitherstandardmode (100 Kbps) or fastmode (400 Kbps).The selectedmode shouldmatch thespeed oftheotherI2C deviceson thebus. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 157 SubmitDocumentationFeedback

PRODUCT□PREVIEW I2C MASTER CORE I2C I/O SELECT PIN I2CxSDA I2CxSCL PIN GPIO_MUX1 I2C SLAVE CORE CPU REGISTER ACCESS M3SSCLK I2C (M3) M3CLKENBx M3 CLOCKSM3 NVICI2CxIRQ I2CxCLK INTR I2CSCL_M I2CSDA_M I2CSCL_S I2CSDA_S I2C CONTROLI2CMSA REG I2CMCS REG I2CMDR REG I2CMTPR REG I2CMIMR REG I2CMRISREG I2CMMIS REG I2CMICR REG I2CMCR REG I2CSIMR REG I2CSDR REG I2CSMIS REG I2CSICR REG I2CSRISREG I2CSOAR REG I2CSCSR REG F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-11.I2C (Cortex™ -M3)

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.2.4 Cortex™ -M3 ControllerArea Network (CAN)

This device has two Cortex™ -M3 ControllerArea Network (CAN) peripherals.CAN is a serial communicationsprotocolthatefficientlysupportsdistributedreal-timecontrolwitha highlevelofsecurity. The CAN module supportsbitratesup to 1 Mbit/sand is compliantwith the CAN 2.0B protocol specification. CAN implementsthefollowingfeatures:

CAN protocolversion2.0partA,B
Bitratesup to1 Mbit/s
Multipleclocksources
32 message objects
Individualidentifiermask foreach message object
Programmable FIFO mode formessage objects
Programmable loop-backmodes forself-testoperation
Suspend mode fordebug support
Softwaremodule reset
Automaticbus on afterBus-Offstateby a programmable32-bittimer
Message RAM paritycheckmechanism
Two interruptlines
Globalpower down and wakeup support Figure6-12shows theCortex™ -M3 CAN peripheral.

6.2.4.1 FunctionalOverview

CAN performsCAN protocolcommunicationaccordingtoISO 11898-1(identicaltoBosch® CAN protocol specification2.0A, B).The bitratecan be programmed tovaluesup to1 Mbit/s.Additionaltransceiver hardwareisrequiredfortheconnectiontothephysicallayer(CAN bus). For communicationon a CAN network,individualmessage objectscan be configured.The message objectsand identifiermasks are storedinthe Message RAM. Allfunctionsconcerningthe handlingof messages areimplementedinthemessage handler.Those functionsare:acceptancefiltering,thetransfer ofmessages between theCAN Core and theMessage RAM, and thehandlingoftransmissionrequests. The registersetoftheCAN isaccessibledirectlyby theCPU viathemodule interface.These registersare used tocontrol/configuretheCAN Core and themessage handler,and toaccessthemessage RAM. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 159 SubmitDocumentationFeedback

PRODUCT□PREVIEW CAN CORE PIN CANxRX CANxTX PIN GPIO_MUX1 CPU REGISTER ACCESS M3SSCLK CAN (M3) M3CLKENBx M3 CLOCKSM3 NVICCANxIRQ CANxCLK INTR

32 MESSAGE

OBJECT ACCESS (IFX) MODULE INTERFACE F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-12.CAN (Cortex™ -M3)

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.2.5 Cortex™ -M3 UniversalSerialBus (USB) Controller

Thisdevicehas one Cortex™ -M3 USB controller.The USB controlleroperatesas a full-speedor low- speed functioncontrollerduringpoint-to-pointcommunicationswith the USB Host, Device,or OTG functions.The controllercomplieswiththe USB 2.0 standard,which includesSUSPEND and RESUME signaling.Thirty-twoendpoints,which comprised of 2 hardwiredendpointsforcontroltransfers(one endpointforIN and one endpointforOUT) and 30 endpointsdefinedby firmware,alongwitha dynamic sizableFIFO,supportmultiplepacketqueuing.DMA accesstotheFIFO allowsminimalinterferencefrom system software.Software-controlledconnectand disconnectallowflexibilityduringUSB devicestart-up. The controllercomplieswiththeOTG standard'sSessionRequest Protocol(SRP) and Host Negotiation Protocol(HNP). The USB controllerincludesthefollowingfeatures:

ComplieswithUSB-IF certificationstandards
USB 2.0full-speed(12-Mbps)and low-speed(1.5-Mbps)operation
IntegratedPHY
Fourtransfertypes:Control,Interrupt,Bulk,and Isochronous
32 endpoints: – One dedicatedcontrolIN endpointand one dedicatedcontrolOUT endpoint – 15 configurableIN endpointsand 15 configurableOUT endpoints
4KB dedicatedendpointmemory: one endpointmay be definedfor double-buffered1023-byte isochronouspacketsize
VBUS droopand validID detectionand interrupt
Efficienttransfersusingdirectmemory accesscontroller(DMA): – Separatechannelsfortransmitand receiveforup tothreeIN endpointsand threeOUT endpoints – Channelrequestsassertedwhen FIFO containsrequiredamount ofdata Figure6-13shows theUSB peripheral.

6.2.5.1 FunctionalDescription

The USB controllerprovidesfullOTG negotiationby supportingboththeSessionRequest Protocol(SRP) and theHost NegotiationProtocol(HNP).The SRP allowsdeviceson theB sideofa cabletorequestthe A-sidedevices'turnon VBUS. The HNP isused aftertheinitialsessionrequestprotocolhas powered the bus and providesa method todeterminewhichend ofthecablewillactas theHost controller.When the deviceisconnectedto non-OTG peripheralsor devices,the controllercan detectwhich cableend was used and providesa registertoindicateifthecontrollershouldactas theHost controlleror theDevice controller.Thisindicationand themode ofoperationarehandledautomaticallyby theUSB controller.This autodetectionallowsthesystem touse a singleA/B connectorinsteadofhavingbothA and B connectors inthesystem,and supportsfullOTG negotiationswithotherOTG devices. Inaddition,theUSB controllerprovidessupportforconnectingtonon-OTG peripheralsorHostcontrollers. The USB controllercan be configuredto actas eithera dedicatedHost or Device,inwhich case,the USB0VBUS and USB0ID signalscan be used as GPIOs. However,when theUSB controllerisactingas a self-poweredDevice,a GPIO inputmust be connectedtoVBUS and configuredtogeneratean interrupt when theVBUS leveldrops.Thisinterruptisused todisablethepullupresistoron theUSB0DP signal. NOTE When theUSB isused inthesystem,theminimum systemfrequencyis20 MHz. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 161 SubmitDocumentationFeedback

PRODUCT□PREVIEW CPU REGISTER ACCESS M3SSCLK USBCLKENB M3 CLOCKSM3 NVIC USBMAC_IRQ INTR USB uDMA DMAxREQ TX/RX FIFO ACCESS USBMAC REQ PIN USB0DM PIN PIN PIN GPIO_MUX1 PACKET ENCODE PACKET DECODE CRC GEN/CHECK PACKET ENCODE / DECODE CYCLE CONTROL RX BUFF RX BUFF TX BUFF TX BUFF FIFO RAM CONTROLLER TRANSMIT RECEIVE EP 0-31 CONTROL COMBINE ENDPOINTS HOST TRANSACTION SCHEDULER ENDPOINT CONTROLCPU INTERFACE INTERRUPT CONTROL EP REGISTER DECODER COMMON REGS CYCLE CONTROL FIFO DECODER DAT A SYNC HNP / SRP TIMERS UTM SYNCHRONIZATION PIN PIN USB0DP USB0VBUS USB0ID USB0EPEN USB0PFLT PHY USBPLLCLK (5V TOLERANT) (5V TOLERANT) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-13.USB

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.2.6 Cortex™ -M3 EthernetMedia Access Controller(EMAC)

The Cortex™ -M3 EthernetMedia Access Controller(EMAC) conformstoIEEE 802.3specificationsand fullysupports10BASE-T and 100BASE-TX standards.This devicehas one EthernetMedia Access Controller. The EMAC module has thefollowingfeatures:

Conforms totheIEEE 802.3-2002specification – 10BASE-T/100BASE-TX IEEE-802.3compliant
Multipleoperationalmodes – Full-and half-duplex100-Mbps – Full-and half-duplex10-Mbps – Power-savingand power-down modes
Highlyconfigurable: – Programmable MAC address – Promiscuousmode support – CRC error-rejectioncontrol – User-configurableinterrupts
IEEE 1588 PrecisionTime Protocol:Provideshighlyaccuratetimestamps forindividualpackets
EfficienttransfersusingtheMicroDirectMemory Access Controller(µDMA) – Separatechannelsfortransmitand receive – Receivechannelrequestassertedon packetreceipt – Transmitchannelrequestassertedon empty transmitFIFO Figure6-14shows theEMAC peripheral.

6.2.6.1 FunctionalOverview

The EthernetControllerisfunctionallydividedintotwo layers:theMedia Access Controller(MAC) layer and theNetwork Physical(PHY) layer.The MAC residesinsidethedevice,and thePHY outsideofthe device.These layerscorrespondtotheOSI model layers2 and 1,respectively.The CPU accessesthe EthernetControllervia the MAC layer.The MAC layerprovidestransmitand receiveprocessingfor Ethernetframes.The MAC layeralsoprovidesthe interfaceto the externalPHY layerviaan internal Media IndependentInterface(MII).The PHY layercommunicateswiththeEthernetbus. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 163 SubmitDocumentationFeedback

PRODUCT□PREVIEW MII_CRS PIN GPIO_MUX1 INTR CONTROL MACIACK REG CPU REGISTER ACCESS M3SSCLK EMAC EMACCLKENB M3 CLOCKSM3 NVICEMAC_IRQ MACIM REG EMACTX_REQ INTR MACRIS REG uDMA DMAxREQ TX/RX FIFO ACCESS TIMER SUPPORT MACTS REG INDIVIDUAL ADDRESS MACIA0 REG MACIA1 REG RECEIVE CONTROL MACRCTL REG MACNP REG DATA ACCESS MACDDATA REG TRANSMIT CONTROL MACTHR REG MACTR REG MACTCTL REG MII CONTROL MACMDV REG MACMTXD REG MACMCTL REG MACMRXD REG MADIX REG TRANSMIT FIFO RECEIVE FIFO MDIO EMACRX_REQ MII_TXCLK MII_TXD(3:0) MII_TXEN PIN PIN MII_COL PIN PIN PIN MII_RXCLK MII_RXD(3:0) MII_RXER PIN PIN MII_RXDV PIN MDIO_CK MDIO_D PIN PIN MACMAR REG F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-14.EMAC

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.2.6.2 MIISignals

The individualEMAC and MDIO signalsfortheMIIinterfacearesummarized inTable6-13. Table6-13.EMAC and MDIO SignalsforMIIInterface SIGNAL TYPE (1) DESCRIPTION Transmitclock.The transmitclockisa continuousclockthatprovidesthetimingreference fortransmitoperations.The MII_TXD and MII_TXEN signalsaretiedtothisclock.The clockMII_TXCK I isgeneratedby thePHY and is2.5MHz at10-Mbps operationand 25 MHz at100-Mbps operation. Transmitdata.The transmitdatapinsarea collectionoffourdatasignalscomprising4 bits MII_TXD[3-0] O ofdata.MTDX0 istheleast-significantbit(LSB).The signalsaresynchronizedby MII_TXCLK and arevalidonlywhen MII_TXEN isasserted. Transmitenable.The transmitenablesignalindicatesthattheMII_TXD pinsaregeneratingMII_TXEN O nibbledataforuse by thePHY. MII_TXEN isdrivensynchronouslytoMII_TXCLK. Collisiondetected.Inhalf-duplexoperation,theMII_COL pinisassertedby thePHY when thePHY detectsa collisionon thenetwork.The MII_COL pinremainsassertedwhilethe collisionconditionpersists.ThissignalisnotnecessarilysynchronoustoMII_TXCLK or MII_COL I MII_RXCLK. Infull-duplexoperation,theMII_COL pinisused forhardwaretransmitflow control.AssertingtheMII_COL pinwillstoppackettransmissions;packetsintheprocessof beingtransmittedwhen MII_COL isassertedwillcompletetransmission.The MII_COL pin shouldbe heldlowifhardwaretransmitflowcontrolisnotused. Carriersense.Inhalf-duplexoperation,theMII_CRS pinisassertedby thePHY when the networkisnotidleineithertransmitorreceive.The pinisdeassertedwhen bothtransmitMII_CRS I and receiveareidle.ThissignalisnotnecessarilysynchronoustoMII_TXCLK or MII_RXCLK. Infull-duplexoperation,theMII_CRS pinshouldbe heldlow. Receiveclock.The receiveclockisa continuousclockthatprovidesthetimingreferencefor receiveoperations.The MII_RXD, MII_RXDV, and MII_RXER signalsaretiedtothisclock.MII_RXCK I The clockisgeneratedby thePHY and is2.5MHz at10-Mbps operationand 25 MHz at 100-Mbps operation. Receivedata.The receivedatapinsarea collectionoffourdatasignalscomprising4 bitsof MII_RXD[3-0] I data.MRDX0 istheleast-significantbit(LSB).The signalsaresynchronizedby MII_RXCLK and arevalidonlywhen MII_RXDV isasserted. Receivedatavalid.The receivedatavalidsignalindicatesthattheMII_RXD pinsare MII_RXDV I generatingnibbledataforuse by theEMAC. MII_RXDV isdrivensynchronouslyto MII_RXCLK. Receiveerror.The receiveerrorsignalisassertedforone ormore MII_RXCLK periodsto MII_RXER I indicatethatan errorwas detectedinthereceivedframe.The MII_RXER signalbeing assertedismeaningfulonlyduringdatareceptionwhen MII_RXDV isactive. Management dataclock.The MDIO dataclockissourcedby theMDIO module on the system.MDIO_CK isused tosynchronizeMDIO dataaccessoperationsdone on theMDIOMDIO_CK O pin.The frequencyofthisclockiscontrolledby theCLKDIV bitsintheMDIO Control Register(CONTROL). Management datainputoutput.The MDIO datapindrivesPHY management dataintoand outofthePHY by way ofan accessframethatconsistsofstart-of-frame,read/writeMDIO_D I/O indication,PHY address,registeraddress,and databitcycles.The MDIO_D pinactsas an outputforallbutthedatabitcycles,atwhichtimethepinisan inputforreadoperations. (1) I= Input,O = Output,I/O= Input/Output Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 165 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.3 ControlSubsystem Peripherals

ControlSubsystem peripheralsare accessiblefrom theC28x CPU viatheC28x Memory Bus, and from theC28x DMA viatheC28x DMA Bus. They includeone NMI Watchdog, threeTimers,fourSerialPort Peripherals(SCI,SPI, McBSP, I2C),and threetypes of ControlPeripherals(ePWM, eQEP, eCAP). Additionally,the C28x CPU/DMA alsohave access to the ExternalPeripheralInterface(EPI),and to Analogand Shared peripherals(seeSection6.1).

6.3.1 High-ResolutionPWM (HRPWM) and Enhanced PWM (ePWM) Modules

There are ninePWM modules inthe Concertodevice.Eightof theseare of the High-ResolutionPWM (HRPWM) typewithhigh-resolutioncontrolon bothA and B signaloutputs,and one isoftheEnhanced PWM (ePWM) type.The HRPWM modules have allthefeaturesoftheePWM plustheyoffersignificantly higherPWM resolution(timegranularityon the orderof 150 ps).Figure6-15 shows the eightHRPWM modules (PWM 1–8)and one ePWM module (PWM 9). The synchronizationinputstothePWM modules includetheSYNCI signalfrom theGPTRIP1 outputof GPIO_MUX1, and the TBCLKSYNC signalfrom the CPCLKCR0 register.Synchronizationoutput SYNCO1 comes from the ePWM1 module and is stretchedby 8 HSPCLK cyclesbeforeentering GPIO_MUX1. There are two groupsoftripsignalinputstoPWM modules.TRIP1–15 inputscome from GPTRIP1 –12 (fromGPIO_MUX1), ECCDBLERR signal(fromC28x Localand Shared RAM), and PIEERR signalfrom the C28x CPU. TZ1–6 (TripZone) inputscome from GPTRIP 1–3 (fromGPIO_MUX1), EQEPERR (fromtheeQEP peripheral),CLOCKFAIL (fromM3 CLOCKS), and EMUSTOP (fromtheC28x CPU). There are 9 SOCA PWM outputsand 9 SOCB PWM outputs— a pairfrom each PWM module. The

9 SOCA outputsareOR-ed togetherand stretchedby 32 HSPCLK cyclesbeforeenteringGPIO_MUX1 as

a singleSOCAO signal.The 9 SOCB outputsare OR-ed togetherand stretchedby 32 HSPCLK cycles beforeenteringGPIO_MUX1 as a singleSOCBO signal.The 18 SOCA/B outputsfrom PWM1 –PWM9 alsogo to the Analog Subsystem,where theycan be selectedto become conversiontriggersto ADC modules. The ninePWM modules alsodrivetwo othersetsofoutputswhich can interrupttheC28x CPU viathe C28x PIE block.These are nineEPWMINT interruptsand nineEPWMTZINT trip-zoneinterrupts.See Figure6-16 fortheinternalstructureoftheHRPWM and ePWM modules.The green-coloredblocksare common tobothePWM and HRPWM modules,butonlytheHRPWMs have thegrey-coloredhi-resolution blocks.

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PRODUCT□PREVIEW C28x DMA ANALOGSUBSYSTEM GPIO_MUX1 PULSE STRETCH

32 HSPCLK CYCLES

ECCDBLERR EMUSTOP CLOCKFAILGPTRIP(1-12) GPTRIP7 GPTRIP8 GPTRIP9 GPTRIP10 GPTRIP11 GPTRIP12 ECAP1INP ECAP2INP ECAP3INP ECAP4INP ECAP5INP ECAP6INP PULSE STRETCH

8 HSPCLK CYCLES

LEGEND: ECAP ECAP ECAP ECAP ECAP ECAP EPWM (9:1) B EPWM (9:1) A ECAP(6:1) EQEP 1 EQEP 2 EQEP3 EQEP(3:1)INT ECAP(6:1)INT EPWM (9:1) TZINT EPWM (9:1) INT EQEP1A EQEP1B EQEP1S EQEP1I EQEP2A EQEP2B EQEP2S EQEP2I EQEP3A EQEP3B EQEP3S EQEP3I SOCA (9:1) SOCB(9:1) CPCLKCR0 REG TRIPIN1 TRIPIN2 TRIPIN3 TRIPIN4 TRIPIN5 TRIPIN6 TRIPIN7 TRIPIN8 TRIPIN9 TRIPIN10 TRIPIN11 TRIPIN12 TRIPIN13 TRIPIN14 TRIPIN15 GPTRIP1 GPTRIP2 GPTRIP3 GPTRIP4 GPTRIP5 GPTRIP6 GPTRIP7 GPTRIP8 GPTRIP9 GPTRIP10 GPTRIP11 GPTRIP12 ECCDBLERR PIEERR GPTRIP6 SYNCI TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 GPTRIP1 GPTRIP2 GPTRIP3 EQEPERR CLOCKFAIL EMUSTOP PIEERR SHARED RAMC28x LOCAL RAM SYNCO ‘0’ SYNCI GPIO_MUX1 PWM PWM PWM PWM PWM PWM PWM PWM PWM SYNCO EPWM ECAP EQEP F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure6-15.PWM, eCAP, eQEP Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 167 SubmitDocumentationFeedback

PRODUCT□PREVIEW TIME BASE (TB) COUNTER COMPARE (CC) ACTION QUALIFIER (AQ) DEAD BAND (DB) PWM CHOPPER (PC) DIGITAL COMPARE (DC) TRIP ZONE (TZ) EVENT TRIGGER (ET) CTR=PRD CTR_DIR CTR=ZER DCAEVT1.SYNC DCBEVT1.SYNC CTR=CMPA CTR=CMPB SYNCI SYNCO (1) SWFSYNC SYNCI DCBEVT1.SOC DCAEVT1.SOC CTR=PRDCTR=ZER EPWM_A EPWM_INT EPWM_B TRIPIN(15:1) SOCA SOCB TBCLK C28SYSCLK HiRES CONTROL CMPB CMPA PHS FEDREDDCAEVT1.SYNC DCBEVT1.SYNC CNTRL CAL TBCTR (15:0) TBCLK CTR=ZER CTR=PRD TBCTR (15:0) TZ (6:1) EPWM_TZINT TBCLKSYNC PRD DCBEVT1.SOC DCAEVT1.SOC C28SYSCLK HiRES PWM (HRPWM) EPWM_INT SYNCI CTR=CMPA CTR=CMPB CTR=CMPC CTR=CMPD CTR= CMPB CTR=ZER CTR=PRD CTR_DIR DCAEVT1.FORCE DCAEVT2.FORCE DCAEVT1.INTER DCAEVT2.INTER DCBEVT1.FORCE DCBEVT2.FORCE DCBEVT1.INTER DCBEVT2.INTER (1) NOTE THAT SYNCO OUTPUTS FROM PWM MODULES 3,6 AND 9 ARE NOT C ONNECTED, THUS THEY ARE NOT USEABLE F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-16.InternalStructureofPWM

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.3.2 Enhanced Capture (eCAP) Module

There aresixidenticaleCAP modules inConcertodevices:eCAP1, 2,3,4,5,and 6.Each eCAP module representsone completecapturechannel.Itsmain functionistoaccuratelycapturethetimingsofexternal events.One can alsouse eCAP modules forPWM, when theyarenotbeingused forinputcaptures.This secondaryfunctionisselectedby flippingtheCAP/APWM bitoftheECCTL2 Register.For PWM function, the counteroperatesin count-upmode, providinga time base forasymmetricalpulse width(PWM) waveforms.The CAP1 and CAP2 registersbecome theperiodand compare registers,respectively;while the CAP3 and CAP4 registersbecome the shadow registersof the main periodand captureregisters, respectively. The leftsideofFigure6-17 shows internalcomponents associatedwiththecaptureblock,and theright sidedepictsthePWM block.The two blockssharea setoffourregistersthatare used inbothCapture and PWM modes. Other components includethe Counterblockthatuses the SYNCIN and SYNCOUT portsto synchronizewithothermodules;and the InterruptTriggerand Flag Controlblockthatsends Capture,PWM, and Counter eventsto the C28x PIE blockviathe ECAPxINT output.There are six ECAPxINT interrupts— one foreach eCAP module. The eCAP peripheralsare clockedby C28SYSCLK, and itsregistersare accessibleby the C28x CPU. Thisperipheralclockcan be enabledordisabledby flippinga bitinone ofthesystemcontrolregisters. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 169 SubmitDocumentationFeedback

PRODUCT□PREVIEW CAP1/PERIOD REGPOLARITY SELECT POLARITY SELECT POLARITY SELECT POLARITY SELECT CAPTURE MODE CAPTURE EVENT QUALIFIER PWM COMPARE LOGIC CAP2/COMP REG CAP3/PER SHDW CAP4/CMP SHDW EVENT PRE-SCALE PIN GPIO_MUX1 PWM MODE MODE SELECT CAPTURE CONTROL INTERRUPT TRIGGER AND FLAG CONTROL CEVT (4:1) (CAPTURE EVENTS) 4 4 C28x PIE LD1 LD2 LD3 LD4 CTR_OVF CTRPHS REG CTR=PER CTR=CMP PRD(31:0) CMP(31:0) CTR(31:0) RST DELTA MODE TSCTR REGCOUNTER SYNC IN EPWM1 OR OTHER ECAP PERIPHERALS SYNC OUT OTHER ECAP PERIPHERALS C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK ECAPxENCLK MASTER SUBSYSTEM CTR_OVF ECAPx ECCTL2 REG ECAPxINT SYNCIN SYNCOUT ECAPx F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-17.eCAP

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.3.3 Enhanced QuadratureEncoder Pulse (eQEP) Module

The Enhanced Quadrature Encoder Pulse (eQEP) module interfacesdirectlywith linearor rotary incrementalencoderstoobtainposition,direction,and speed informationfrom rotatingmachines used in high-performancemotionand position-controlsystems.There are threeType 0 eQEP modules ineach Concertodevice. Each eQEP peripheralcomprisesfivemajorfunctionalblocks:QuadratureCaptureUnit(QCAP), Position Counter/ControlUnit(PCCU), QuadratureDecoder (QDU), UnitTime Base forspeed and frequency measurement (UTIME),and Watchdog timerfordetectingstalls(QWDOG). The C28x CPU controlsand communicates withthesemodules througha setof associatedregisters(see Figure6-18).The eQEP peripheralsare clockedby C28SYSCLK, and itsregistersare accessibleby the C28x CPU. This peripheralclockcan be enabledordisabledby flippinga bitinone ofthesystemcontrolregisters. Each eQEP peripheralconnectsthroughtheGPIO_MUX1 blocktofourdevicepins.Two ofthefourpins are alwaysinputs,whiletheothertwo can be inputsor outputs,dependingon theoperatingmode. The PCCU blockofeach eQEP alsodrivesone interrupttotheC28x PIE.There isa totalofthreeEQEPxINT interrupts— one fromeach ofthethreeeQEP modules. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 171 SubmitDocumentationFeedback

PRODUCT□PREVIEW QCPRD REG QCTMR REG QWDTMR REG QWDPRD REG QUTMR REG QUPRD REG QFLG REG QEPCTL REG QEPSTS REG REGISTERS USED BY MULTIPLE UNITS OCTMRLAT REG QCPRDLAT REG QPOSILAT REG QPOSLAT REG QPOSSLAT REG QPOSMAX REG QPOSCNT REG QPOSINIT REG QCLR REG QEINT REG QFRC REG QPOSCTL REG QPOSCMP REG QDECCTL REG UTIME QWDOG 1632 1632 32 QCAPCTL REG POSITION COUNTER/CONTROL UNIT ( PCCU ) QUADRATURE CAPTURE UNIT ( QCAP ) QUADRATURE DECODER ( QDU ) EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE QCLK WDTOUT UTOUT QDIR QI QS PHE PCSOUT PIN EQEPxS EQEPxI EQEPxB /XDIR EQEPxA /XCLK PIN PIN PIN GPIO_MUX1 C28x PIE EQEPxINT C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK EQEPxENCLK MASTER SUBSYSTEM EQEPx F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-18.eQEP

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.3.4 C28x Inter-IntegratedCircuitModule (I2C)

Thisdevicehas one C28x inter-integratedcircuit(I2C)peripheral.The I2C providesan interfacebetween a Concerto device and devicescompliantwith the Philips® I2C-Bus SpecificationVersion2.1 and connectedby way ofan I2C Bus® .Externalcomponents attachedtothis2-wireserialbus can transmit 1-bitto8-bitdatatoand receive1-bitto8-bitdatafromthedevicethroughtheI2C module . NOTE A unitof data transmittedor receivedby the I2C module can have fewer than 8 bits; however,forconvenience,a unitofdataiscalleda data byte inthissection.The number of bitsina databyteisselectableviatheBC bitsofthemode register,I2CMDR. The I2C module has thefollowingfeatures:

CompliancewiththePhilips® I2C-Bus SpecificationVersion2.1: – Supportfor1-bitto8-bitformattransfers – 7-bitand 10-bitaddressingmodes – Generalcall – START bytemode – Supportformultiplemaster-transmittersand slave-receivers – Supportformultipleslave-transmittersand master-receivers – Combined mastertransmit-and-receiveand receive-and-transmitmode – Data transferrateoffrom10 Kbps up to400 Kbps (I2CFast-moderate)
One 4-wordreceiveFIFO and one 4-wordtransmitFIFO
One interruptthatcan be used by theCPU. Thisinterruptcan be generatedas a resultofone ofthe followingconditions: – Transmit-dataready – Receive-dataready – Register-accessready – No-acknowledgmentreceived – Arbitrationlost – Stopconditiondetected – Addressedas slave
An additionalinterruptthatcan be used by theCPU when inFIFO mode
Module enableordisablecapability
Freedataformatmode The I2C module does notsupport:
High-speedmode (Hs-mode)

PRODUCT□PREVIEW PIN I2CASDA I2CASCL PIN GPIO_MUX1 I2C (C28) I2CINT1A INTR TX FIFO RX FIFO I2CXSR REG I2CDRR REG I2CRXR REG I2CDXR REG I2CIER REG C28x PIE I2CINT2A C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK I2CA_ENCLK MASTER SUBSYSTEM SLAVE CLOCK SYNCHRONIZER INTERRUPT CONTROL AND ARBITRATION CLOCK PRESCALER I2CCLK I2COAR REG I2CCLKL REG I2CCLKH REG I2CCNT REG I2CSAR REG I2CMDR REG I2CISRC REG I2CPSC REG I2CFFTX REG I2CFFRX REG MASTER CLOCK DIVIDER MODE AND STATUS REGISTERS I2CSTR REG I2CCLK REGISTER ACCESS CLK TX/RX LOGIC F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-19.I2C (C28x)

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.3.4.1 FunctionalOverview

Each deviceconnectedto an I2C Bus isrecognizedby a uniqueaddress.Each devicecan operateas eithera transmitterora receiver,dependingon thefunctionofthedevice.A deviceconnectedtotheI2C Bus can alsobe consideredas themasterortheslavewhen performingdatatransfers.A masterdeviceis thedevicethatinitiatesa datatransferon thebus and generatestheclocksignalstopermitthattransfer. Duringthistransfer,any deviceaddressedby thismasterisconsidereda slave.The I2C module supports themulti-mastermode, inwhichone ormore devicescapableofcontrollingan I2C Bus can be connected tothesame I2C Bus. For datacommunication,theI2C module has a serialdatapin(SDA) and a serialclockpin(SCL).These two pinscarryinformationbetween theC28x deviceand otherdevicesconnectedtotheI2C Bus.The SDA and SCL pinsbothare bidirectional.They each must be connectedtoa positivesupplyvoltageusinga pullupresistor.When thebus isfree,bothpinsare high.The driverofthesetwo pinshas an open-drain configurationtoperformtherequiredwired-ANDfunction.Therearetwo majortransfertechniques: 1. StandardMode: Send exactlyn datavalues,where n isa valueyou programinan I2C module register. 2. Repeat Mode: Keep sendingdatavaluesuntilyou use softwaretoinitiatea STOP conditionora new START condition. The I2C module consistsofthefollowingprimaryblocks:

A serialinterface:one datapin(SDA) and one clockpin(SCL)
Data registersand FIFOs to temporarilyholdreceivedata and transmitdata travelingbetween the SDA pinand theCPU
Controland statusregisters
A peripheralbus interfacetoenabletheCPU toaccesstheI2C module registersand FIFOs.

6.3.4.2 Clock Generation

The deviceclockgeneratorreceivesa signalfrom an externalclocksourceand producesan I2C input clockwitha programmed frequency.The I2C inputclockisequivalentto the CPU clockand isthen dividedtwicemore insidetheI2C module toproducethemodule clockand themasterclock. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 175 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.3.5 C28x SerialCommunications Interface(SCI)

This devicehas one serialcommunicationinterface(SCI)peripheral.SCI isa two-wireasynchronous serialport,commonly known as a UART. The SCI module supportsdigitalcommunicationsbetween the CPU and otherasynchronousperipheralsthatuse thestandardnon-return-to-zero(NRZ) format The SCI receiverand transmittereach have a 16-level-deepFIFO forreducingservicingoverhead,and each has itsown separateenableand interruptbits.Both can be operatedindependentlyforhalf-duplex communication,orsimultaneouslyforfull-duplexcommunication.To specifydataintegrity,theSCI checks receiveddata forbreak detection,parity,overrun,and framingerrors.The bitrateisprogrammable to differentspeeds througha 16-bitbaud-selectregister. FeaturesoftheSCI module include:

Two externalpins: – SCITXD: SCI transmit-outputpin – SCIRXD: SCI receive-inputpin NOTE: Bothpinscan be used as GPIO ifnotused forSCI. – Baud rateprogrammableto64K differentrates
Data-wordformat – One startbit – Data-wordlengthprogrammablefromone toeightbits – Optionaleven/odd/noparitybit – One ortwo stopbits
Fourerror-detectionflags:parity,overrun,framing,and breakdetection
Two wake-up multiprocessormodes: idle-lineand addressbit
Half-orfull-duplexoperation
Double-bufferedreceiveand transmitfunctions
Transmitterand receiveroperationscan be accomplishedthroughinterrupt-drivenorpolledalgorithms withstatusflags. – Transmitter:TXRDY flag(transmitter-bufferregisterisreadytoreceiveanothercharacter)and TX EMPTY flag(transmitter-shiftregisterisempty) – Receiver:RXRDY flag(receiver-bufferregisterisreadytoreceiveanothercharacter),BRKDT flag (breakconditionoccurred),and RX ERROR flag(monitoringfourinterruptconditions)
Separateenablebitsfortransmitterand receiverinterrupts(exceptBRKDT)
NRZ (non-return-to-zero)format NOTE Allregistersin thismodule are 8-bitregistersthatare connectedto PeripheralFrame 2. When a registerisaccessed,theregisterdataisinthelowerbyte(bits7–0),and theupper byte(bits15–8)isreadas zeros.Writingtotheupperbytehas no effect.
Autobaud-detecthardwarelogic
4-leveltransmitand receiveFIFO Figure6-20shows theC28x SCI peripheral.

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PRODUCT□PREVIEW PIN SCIRXDA SCITXDA PIN GPIO_MUX1 SCI (C28) SCIRXINA INTR C28x PIE C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK SCIA_ENCLK MASTER SUBSYSTEM C28LSPCLK /14 TXSHF REG RXSHF REG SCITXINA REGISTER ACCESS TX FIFO RX FIFO RX INTERRUPT LOGIC TX INTERRUPT LOGIC SCIRXBUF REG SCITXBUF REG SCIPRI REG SCIFFTXA REG SCIFFRXA REG SCICCRA REG SCRXST REG SCICTL2 REG SCIRXEMUA REG SCICTL1A REG BAUD-RATE GEN SCIHBAUD REG SCILBAUD REG TX DELAY SCEFFCT REG AUTO-BAUD DETECT LOGIC TX/RX LOGIC F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012 Figure6-20.SCI (C28x) Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 177 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.3.5.1 Architecture

The majorelementsused infull-duplexoperationinclude:

A transmitter(TX)and itsmajorregisters: – SCITXBUF register– TransmitterData Bufferregister.Containsdata (loadedby the CPU) to be transmitted – TXSHF register– TransmitterShiftregister.Acceptsdatafrom theSCITXBUF registerand shifts dataontotheSCITXD pin,one bitata time
A receiver(RX)and itsmajorregisters: – RXSHF register– ReceiverShiftregister.ShiftsdatainfromtheSCIRXD pin,one bitata time – SCIRXBUF register– ReceiverData Bufferregister.Containsdata to be read by the CPU. Data from a remote processorisloaded intothe RXSHF registerand then intothe SCIRXBUF and SCIRXEMU registers
A programmablebaud generator
Data-memory-mapped controland statusregistersenabletheCPU toaccesstheI2C module registers and FIFOs. The SCI receiverand transmittercan operateeitherindependentlyorsimultaneously.

6.3.5.2 Multiprocessorand Asynchronous Communication Modes

The SCI has two multiprocessorprotocols:the idle-linemultiprocessormode and the address-bit multiprocessormode. These protocolsallowefficientdatatransferbetween multipleprocessors. The SCI offersthe universalasynchronous receiver/transmitter(UART) communications mode for interfacingwithmany popularperipherals.The asynchronousmode requirestwo linesto interfacewith many standarddevicessuch as terminalsand printersthatuse RS-232-C formats. Data transmissioncharacteristicsinclude:

One startbit
One toeightdatabits
An even/oddparitybitorno paritybit
One ortwo stopbitswitha programmed frequency.The I2C inputclockisequivalenttotheCPU clock and isthen dividedtwicemore insidethe I2C module to produce the module clockand the master clock.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.3.6 C28x SerialPeripheralInterface(SPI)

Thisdevicehas one C28x serialperipheralinterface(SPI).The serialperipheralinterface(SPI)isa high- speed synchronousserialinput/output(I/O)portthatallowsa serialbitstreamofprogrammed length(1to 16 bits)to be shiftedintoand out of the deviceat a programmed bit-transferrate.The SPI isnormally used forcommunicationsbetween the DSP controllerand externalperipheralsor anothercontroller. TypicalapplicationsincludeexternalI/O or peripheralexpansionvia devicessuch as shiftregisters, displaydrivers,and analog-to-digitalconverters(ADCs).Multi-devicecommunicationsare supportedby the master/slaveoperationof the SPI. The portsupportsa 16-level,receive-and-transmitFIFO for reducingCPU servicingoverhead. The SPI module featuresinclude:

SPISOMI: SPI slave-output/master-inputpin
SPISIMO: SPI slave-input/master-outputpin
SPISTE: SPI slavetransmit-enablepin
SPICLK: SPI serial-clockpin NOTE: Allfourpinscan be used as GPIO, iftheSPI module isnotused.
Two operationalmodes: masterand slave
Baud rate:125 differentprogrammablerates.The maximum baud ratethatcan be employed islimited by themaximum speed oftheI/Obuffersused on theSPI pins.
Data word length:1 to16 databits
Fourclockingschemes (controlledby clockpolarityand clockphase bits)include: – Fallingedge withoutphase delay:SPICLK active-high.SPI transmitsdataon thefallingedge ofthe SPICLK signaland receivesdataon therisingedge oftheSPICLK signal. – Fallingedge withphase delay:SPICLK active-high.SPI transmitsdataone half-cycleahead ofthe fallingedge oftheSPICLK signaland receivesdataon thefallingedge oftheSPICLK signal. – Risingedge withoutphase delay:SPICLK inactive-low.SPI transmitsdataon therisingedge ofthe SPICLK signaland receivesdataon thefallingedge oftheSPICLK signal. – Risingedge withphase delay:SPICLK inactive-low.SPI transmitsdataone half-cycleahead ofthe fallingedge oftheSPICLK signaland receivesdataon therisingedge oftheSPICLK signal.
Simultaneousreceive-and-transmitoperation(transmitfunctioncan be disabledinsoftware)
Transmitterand receiveroperationsare accomplished through eitherinterrupt-drivenor polled algorithms.
TwelveSPI module controlregisters:Locatedincontrolregisterframebeginningataddress7040h. NOTE Allregistersinthismodule are 16-bitregistersthatare connectedto PeripheralFrame 2. When a registerisaccessed,theregisterdataisinthelowerbyte(bits7−0),and theupper byte(bits15−8)isreadas zeros.Writingtotheupperbytehas no effect.
16-leveltransmitand receiveFIFO

PRODUCT□PREVIEW PIN SPISOMIA SPISIMOA PIN GPIO_MUX1 SPI (C28) SPIRXINA INTR TX FIFO (1) RX FIFO (1) C28x PIE C28x CPU REGISTER ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK SPIA_ENCLK MASTER SUBSYSTEM SPI BIT RATEC28LSPCLK /14 RX INTERRUPT LOGIC SPITXINA TX INTERRUPT LOGIC REGISTER ACCESS SPICCR REG SPICTL REG SPIST REG SPIBRR REG SPIRXEMU REG SPIRXBUF REG SPITXBUF REG SPIDAT REG SPIFFTX REG SPIFFRX REG SPIFFCT REG SPIPRI REG PIN SPICLKA SPISTEA PIN TX DELAY TX/RX LOGIC (1) RX FIFO AND TX FIFO CAN BE BYPASSED BY CONFIGURING BIT SPIF FENA OF THE SPIFFTX REGISTER F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-21.SPI (C28x)

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

6.3.6.1 FunctionalOverview

The SPI operatesinmaster or slavemode. The master initiatesdata transferby sendingthe SPICLK signal.For both the slaveand the master,data isshiftedout of the shiftregisterson one edge of the SPICLK and latchedintotheshiftregisteron theoppositeSPICLK clockedge.IftheCLOCK PHASE bit (SPICTL.3)ishigh,dataistransmittedand receiveda half-cyclebeforetheSPICLK transition.As a result, bothcontrollerssend and receivedatasimultaneously.The applicationsoftwaredetermineswhetherthe dataismeaningfulordummy data.Therearethreepossiblemethods fordatatransmission:

Mastersends data;slavesends dummy data
Mastersends data;slavesends data
Mastersends dummy data;slavesends data The mastercan initiatea datatransferatany timebecause itcontrolstheSPICLK signal.The software, however,determineshow themasterdetectswhen theslaveisreadytobroadcastdata. Copyright© 2011–2012,Texas InstrumentsIncorporated PeripheralInformationand Timings 181 SubmitDocumentationFeedback

PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com

6.3.7 C28x MultichannelBufferedSerialPort(McBSP)

Thisdeviceprovidesone high-speedmultichannelbufferedserialport(McBSP) thatallowsdirectinterface tocodecs and otherdevices.The CPU accessesdata,control,and statusinformation.The MCBSP also supportsµDMA transfers. The McBSP consistsof a data-flowpath and a controlpath connectedto externaldevicesby sixpins. Data is communicated to devices interfacedwith the McBSP via the data transmit(DX) pin for transmissionand viathedatareceive(DR) pinforreception.Controlinformationintheform ofclocking and framesynchronizationiscommunicated viathefollowingpins:CLKX (transmitclock),CLKR (receive clock),FSX (transmitframesynchronization),and FSR (receiveframesynchronization). The CPU and theDMA controllercommunicate withtheMcBSP through16-bit-wideregistersaccessible viathe internalperipheralbus.The CPU or the DMA controllerwritesthe data to be transmittedto the datatransmitregisters(DXR1, DXR2). Data writtentotheDXRs isshiftedouttoDX viathetransmitshift registers(XSR1, XSR2). Similarly,receivedata on the DR pinisshiftedintothe receiveshiftregisters (RSR1, RSR2) and copiedintothereceivebufferregisters(RBR1, RBR2). The contentsoftheRBRs is then copiedto the DRRs, which can be read by the CPU or the DMA controller.Thismethod allows simultaneousmovement ofinternaland externaldatacommunications. DRR2, RBR2, RSR2, DXR2, and XSR2 arenotused (written,read,orshifted)iftheserialword lengthis 8 bits,12 bits,or16 bits.For largerword lengths,theseregistersareneeded toholdthemost significant bits. The frameand clockloop-backisimplementedatchipleveltoenableCLKX and FSX todriveCLKR and FSR. Ifthe loop-backisenabled,the CLKR and FSR get theirsignalsfrom the CLKX and FSX pads insteadoftheCLKR and FSR pins.

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Full-duplexcommunication
Double-bufferedtransmissionand triple-bufferedreception,allowinga continuousdatastream
Independentclockingand framingforreceptionand transmission
The capabilitytosend interruptstotheCPU and tosend DMA eventstotheDMA controller
128 channelsfortransmissionand reception
Multichannelselectionmodes thatenableordisableblocktransfersineach ofthechannels
Directinterfaceto industry-standardcodecs, analog interfacechips (AICs),and other serially connectedA/D and D/A devices
Supportforexternalgenerationofclocksignalsand frame-synchronizationsignals
A programmable sample rategeneratorforinternalgenerationand controlofclocksignalsand frame synchronizationsignals
Programmable polarityforframe-synchronizationpulsesand clocksignals
Directinterfaceto: – T1/E1 framers – IOM-2 compliantdevices – AC97-compliantdevices(thenecessarymulti-phaseframecapabilityisprovided) – I2Scompliantdevices – SPI devices
A wideselectionofdatasizes:8,12,16,20,24,and 32 bits NOTE A valueof the chosen data sizeisreferredto as a serialword or word inthissection. Elsewhere,word isused todescribea 16-bitvalue.
µ-lawand A-lawcompanding
The optionoftransmitting/receiving8-bitdatawiththeLSB first
Statusbitsforflaggingexception/errorconditions

PRODUCT□PREVIEW GPIO_MUX1 MRINTA INTR C28x PIE C28x CPU ALL REG ACCESS SYSTEM CONTROL REGISTERS C28CLKIN C28SYSCLK MCBSPA_ENCLK MASTER SUBSYSTEM C28LSPCLK /14 MXINTA REG ACCESS PIN MFSRA MCLKRA PIN MDRA PIN PIN MFSXA MCLKXA PIN MDXA PIN C28 DMA DRR / DXR REG ACCESS DRR1 REG DRR2 REG DXR2 REG DXR1 REG EXPAND COMPRESS RBR REG RSR REG XSR REG SPCR2 REG SPCR1 REG SRGR2 REG SRGR1 REG SPCR2 REG SPCR1 REG XCR2 REG XCR1 REG GENERATION AND CONTROL OF CLOCK AND FRAME SYNC PERIPH LOGIC RX/TX INTERRUPT LOGIC MFFINT REG MCR2 REG RCERA REG RCERB REG RCERC REG RCERD REG RCERE REG RCERF REG RCERG REG RCERH REG XCERA REG XCERB REG XCERC REG XCERD REG XCERE REG XCERF REG XCERG REG XCERH REG MCR1 REG PCR REG MULTI - CHANNEL SELECTION MCBSP (128 CHAN) F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com Figure6-22.McBSP (C28x)

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

7 Device and Documentation Support

7.1 Device Support

7.1.1 Development Support

TI offersan extensivelineof development tools,includingtoolsto evaluatethe performanceof the processors,generatecode,developalgorithmimplementations,and fullyintegrateand debug software and hardware modules. The tool'ssupportdocumentationis electronicallyavailablewithinthe Code Composer Studio™ IntegratedDevelopmentEnvironment(IDE). The followingproductssupportdevelopmentofprocessorapplications: Software Development Tools: Code Composer Studio™ IntegratedDevelopment Environment(IDE): includingEditorC/C++/Assembly Code Generation,and Debug plus additionaldevelopment tools Scalable,Real-TimeFoundationSoftware(SYS/BIOS),whichprovidesthebasicrun-timetargetsoftware needed tosupportany processorapplication. Hardware Development Tools:ExtendedDevelopmentSystem (XDS ™ )Emulator For a completelistingofdevelopment-supporttoolsfortheprocessorplatform,visittheTexas Instruments websiteatwww.ti.com.For informationon pricingand availability,contactthenearestTIfieldsalesoffice orauthorizeddistributor.

7.1.2 Device Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall Concerto™ MCU devicesand supporttools.Each Concerto™ MCU commercialfamilymember has one ofthreeprefixes:x,p,orno prefix(forexample,xF28M35 H52C1RFPT). Texas Instrumentsrecommends two ofthreepossibleprefixdesignatorsforitssupporttools:TMDX and TMDS. These prefixesrepresent evolutionarystagesof productdevelopmentfrom engineeringprototypes(withprefixx fordevicesand TMDX fortools)throughfullyqualifiedproductiondevices/tools(withno prefixfordevicesand TMDS, insteadofTMDX, fortools). xF28M35... Experimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice's electricalspecifications pF28M35... Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompletedqualityand reliabilityverification F28M35... Fullyqualifiedproductiondevice Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproductthathas notyetcompletedTexas Instrumentsinternal qualificationtesting TMDS Fullyqualifieddevelopment-supportproduct Devices withprefixx or p and TMDX development-supporttoolsare shipped againstthe following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." Productiondevicesand TMDS development-supporttoolshave been characterizedfully,and thequality and reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies. Predictionsshow thatprototypedeviceswithprefixofx orp have a greaterfailureratethanthestandard productiondevices.Texas Instrumentsrecommends thatthesedevicesnot be used inany production systembecause theirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobe used. Copyright© 2011–2012,Texas InstrumentsIncorporated Deviceand DocumentationSupport 185 SubmitDocumentationFeedback

PRODUCT□PREVIEW PREFIX x x p no prefix experimental device prototype device qualified device F28M3 DEVICE FAMILY F28M3 = Concerto TM C B Connectivity Base PERIPHERALS C 2 = 256KB each core 3 = additional 256KB to one core 5 = 512KB each core (A) FLASH 72KB additional 64KB of masterable RAM RAM H M E 150 / 75 MHz or 100 / 100 MHz 75 / 75 MHz 60 / 60 MHz PERFORMANCE (C28x Speed / Cortex -M3 Speed) TM TM H SERIES NUMBER 1 = 144 pins PINS RFP PACKAGE TYPE 144-Pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) TM TEMPERATURE RANGE T −40°C to 105°C −40°C to 125°C −40°C to 125°C (Q refers to Q100 qualification for automotive applications.) T S Q F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 SPRS742D –JUNE 2011–REVISED AUGUST 2012 www.ti.com TI devicenomenclaturealso includesa suffixwiththe devicefamilyname. This suffixindicatesthe package type(forexample,RFP) and temperaturerange(forexample,T). For devicepartnumbers and furtherorderinginformationofF28M35x devicesintheRFP package type, see theTIwebsite(www.ti.com)orcontactyourTIsalesrepresentative. For additionaldescriptionof the devicenomenclaturemarkings on the die,see the F28M35H20B1, F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1, F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto MCU SiliconErrata (literaturenumber SPRZ357 ). A. The additional256KB isadded totheCortex™ -M3 core(ConnectivityDevices)ortotheC28x™ core(BaseDevices). Figure7-1.Device Nomenclature

7.2 Documentation Support

The followingdocuments describetheMCU. Copies ofthesedocuments are availableon theInternetat www.ti.com.Tip:Entertheliteraturenumber inthesearchbox. SPRUH22 Concerto F28M35x TechnicalReferenceManual SPRZ357 F28M35H20B1, F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1, F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto MCU SiliconErrata

7.3 Community Resources

The followinglinksconnectto TI community resources.Linkedcontentsare provided"AS IS"by the respectivecontributors.They do notconstituteTI specificationsand do notnecessarilyreflectTI'sviews; see TI'sTerms ofUse. TIE2E Community TI's Engineer-to-Engineer(E2E) Community. Created to fostercollaboration among engineers.Ate2e.ti.com,you can ask questions,shareknowledge,exploreideasand helpsolveproblemswithfellowengineers. TIEmbedded Processors Wiki Texas InstrumentsEmbedded Processors Wiki.Establishedto help developersget startedwithEmbedded Processorsfrom Texas Instrumentsand to foster innovationand growthofgeneralknowledge aboutthehardwareand softwaresurrounding thesedevices.

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PRODUCT□PREVIEW F28M35H20B1,F28M35H20C1 F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1 F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1 www.ti.com SPRS742D –JUNE 2011–REVISED AUGUST 2012

8 MechanicalPackaging and OrderableInformation

8.1 Thermal Data forPackage

Table8-1shows thethermaldata.See Section5.2formore informationon thermaldesignconsiderations. Table8-1.Thermal Model 144-PinRFP Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] Highk PCB 18.8 11.5 10.0 8.6 ΨJB 4.8 4.6 4.5 4.4 θJC 6.3 θJB 4.4

8.2 Packaging Information

The followingpackaging informationand addendum reflectthe most currentdata availableforthe designateddevices.Thisdataissubjecttochange withoutnoticeand withoutrevisionofthisdocument. Copyright© 2011–2012,Texas InstrumentsIncorporated MechanicalPackagingand OrderableInformation 187 SubmitDocumentationFeedback

www.ti.com 20-Jun-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) F28M35H20B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI

www.ti.com 20-Jun-2012 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) XF28M35H52C1RFPT ACTIVE HTQFP RFP 144 1 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,enhancements,improvementsand other changes toitssemiconductorproductsand servicesperJESD46, latestissue,and todiscontinueany productorserviceperJESD48, latest issue.Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.Allsemiconductorproducts(alsoreferredtohereinas “components”)aresoldsubjecttoTI’s termsand conditionsofsale suppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitscomponents tothespecificationsapplicableatthetimeofsale,inaccordancewiththewarrantyinTI’s terms and conditionsofsaleofsemiconductorproducts.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessary tosupportthiswarranty.Exceptwhere mandated by applicablelaw,testingofallparametersofeach component isnotnecessarily performed. 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Product Information

F28M35H52B1RFPS specifications and overview.

Summary

Concerto Microcontrollers Embedded Memory AUGUST2012

Description

Concerto Microcontrollers Embedded Memory AUGUST2012

Source title F28M35H52B1RFPS Datasheet(PDF) - Texas Instruments

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