Microcontroller

F28377D-SEP

Texas Instruments

F28377D-SEP Dual-Core Real-Time Microcontroller OCTOBER 2025

Manufacturer variants: 1

Selected specification: Texas Instruments

Documents: 1

Request Quote Download Datasheet Read online HTML view

Compare manufacturer specifications More from Texas Instruments Browse F parts

Manufacturer Specifications

Compare F28377D-SEP variants.

Select a manufacturer to view its specifications, local PDF, and searchable HTML text.

1 manufacturers / 1 documents

Manufacturer	Series	Package	Documents	Available	Select specification
Texas Instruments	-	-	1	PDF HTML	Viewing

Online Datasheet

Read the Texas Instruments document online.

F28377D-SEP Dual-Core Real-Time Microcontroller datasheet (Rev. A)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SPRSPB1,A]
PDF pages: 220

Technical content

F28377D-SEP Dual-Core Real-Time Microcontroller

1 Features

VID - V62/25638
Radiation hardened – Single Event Latch-up (SEL) immune to 45MeV-cm2/mg at 125°C – Total Ionizing Dose (TID) RLAT for every wafer lot up to 30krad (Si)
Space enhanced plastic – Controlled baseline – Gold (Au) wire – One assembly/test site – One fabrication site – Available in extended temperature range (–55°C to 125°C) – Extended product life cycle – Extended product change notification – Product traceability – Enhanced mold compound for low outgassing
Dual-core architecture – Two TMS320C28x 32-bit CPUs – 200MHz – IEEE 754 single-precision Floating-Point Unit (FPU) – Trigonometric Math Unit (TMU) – Viterbi/Complex Math Unit (VCU-II)
Two programmable Control Law Accelerators (CLAs) – 200MHz – IEEE 754 single-precision floating-point instructions – Executes code independently of main CPU
On-chip memory – 512KB (256KW) or 1MB (512KW) of flash (ECC-protected) – 172KB (86KW) or 204KB (102KW) of RAM (ECC-protected or parity-protected) – Dual-zone security supporting third-party development – Unique identification number
Clock and system control – Two internal zero-pin 10MHz oscillators – On-chip crystal oscillator – Windowed watchdog timer module – Missing clock detection circuitry
1.2V core, 3.3V I/O design
System peripherals – Two External Memory Interfaces (EMIFs) with ASRAM and SDRAM support – Dual 6-channel Direct Memory Access (DMA) controllers – Up to 169 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins with input filtering – Expanded Peripheral Interrupt controller (ePIE) – Multiple Low-Power Mode (LPM) support with external wakeup
Communications peripherals – USB 2.0 (MAC + PHY) – Support for 12-pin 3.3V-compatible Universal Parallel Port (uPP) interface – Two Controller Area Network (CAN) modules (pin-bootable) – Three high-speed (up to 50MHz) SPI ports (pin- bootable) – Two Multichannel Buffered Serial Ports (McBSPs) – Four Serial Communications Interfaces (SCI/ UART) (pin-bootable) – Two I2C interfaces (pin-bootable)
Analog subsystem – Up to four Analog-to-Digital Converters (ADCs)
16-bit mode – 1.1MSPS each (up to 4.4MSPS system throughput) – Differential inputs – Up to 12 external channels
12-bit mode – 3.5MSPS each (up to 14MSPS system throughput) – Single-ended inputs – Up to 24 external channels
Single Sample-and-Hold (S/H) on each ADC
Hardware-integrated post-processing of ADC conversions – Saturating offset calibration – Error from setpoint calculation – High, low, and zero-crossing compare, with interrupt capability – Trigger-to-sample delay capture – Eight windowed comparators with 12-bit Digital- to-Analog Converter (DAC) references – Three 12-bit buffered DAC outputs
Enhanced control peripherals – 24 Pulse Width Modulator (PWM) channels with enhanced features – 16 High-Resolution Pulse Width Modulator (HRPWM) channels
High resolution on both A and B channels of

8 PWM modules

Dead-band support (on both standard and high resolution) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

– Six Enhanced Capture (eCAP) modules – Three Enhanced Quadrature Encoder Pulse (eQEP) modules – Eight Sigma-Delta Filter Module (SDFM) input channels, 2 parallel filters per channel

Standard SDFM data filtering
Comparator filter for fast action for out of range
Supports defense and aerospace applications – Controlled baseline – One assembly/test site – One fabrication site – Extended product lifecycle – Product traceability – Outgassing test performed per ASTM E595
Package: – 176-pin PowerPAD™ Thermally Enhanced Low- Profile Quad Flatpack (HLQFP) [PTP suffix]
Hardware Built-in Self Test (HWBIST)
Temperature: – –55°C to 150°C junction

2 Applications

Aerospace and Avionics
Support Low Earth Orbit Space Applications
Motors and Actuators – Attitude and Orbit Control Systems
Reaction Wheel Assembly
Control Moment Gyroscope (momentum wheel)
Thruster Gimbal Mechanism – Optical Communication
Beam Steering Gimbal
Fast Steering Mirror – Antenna Pointing Mechanism – Cryocooler Compressor
Digital Power – Spacecraft Electrical Power System
Power Control & Distribution Limit
Space-Grade DC-DC Converter Module (inc. Resonant topology) – Satellite Electrical Power Systems
Inertial Measurement Unit (IMU)

3 Description

C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop performance in real-time control applications such as industrial motor drives ; solar inverters and digital power ; electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes the Premium performance MCUs and the Entry performance MCUs. The TMS320F2837xD is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial motor drives ; solar inverters and digital power ; electrical vehicles and transportation ; and sensing and signal processing . To accelerate application development, the DigitalPower software development kit (SDK) for C2000 MCUs and the MotorControl software development kit (SDK) for C2000 ™ MCUs are available. The F2837xD supports a new dual-core C28x architecture that significantly boosts system performance. The integrated analog and control peripherals also let designers consolidate control architectures and eliminate multiprocessor use in high-end systems. The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide 200MHz of signal processing performance in each core. The C28x CPUs are further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex math operations common in encoded applications. The F2837xD microcontroller family features two CLA real-time control coprocessors. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. The dual C28x+CLA architecture enables intelligent partitioning between various system tasks. For example, one C28x+CLA core can be used to track speed and position, while the other C28x+CLA core can be used to control torque and current loops. The TMS320F2837xD supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC) and up to 204KB (102KW) of SRAM. Two 128-bit secure zones are also available on each CPU for code protection. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

2 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Performance analog and control peripherals are also integrated on the F2837xD MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals. Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F2837xD. The uPP interface is a new feature of the C2000™ MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application. Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000 ™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page. The Getting Started With C2000 ™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out the TMDSCNCD28379D or LAUNCHXL-F28379D evaluation board sand download C2000Ware. To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.

Package Information

PART NUMBER GRADE(1) PACKAGE(2) PACKAGE SIZE(3) BODY SIZE(4) F28377DPTPSEP 30krad (Si) RLAT PTP (HLQFP, 176) 26mm × 26mm 24mm × 24mm Mass = 2.15g (1) For additional information about the part grade, view part ratings. (2) For more information, see Mechanical, Packaging, and Orderable Information. (3) The package size (length × width) is a nominal value and includes pins, where applicable. (4) The mass is a nominal value and the body size (length × width) is a nominal value and does not include pins. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: F28377D-SEP

3.1 Functional Block Diagram

The Functional Block Diagram shows the CPU system and associated peripherals on the F2837xD devices. See Table 4-1 for the features and peripherals that are available on the F28377D-SEP device. 16-/12-bit ADC Analog MUX ADC Result Regs Peripheral Frame 1 Global Shared 16x 4Kx16 GS0-GS15 RAMs CPU1 to CPU2 1Kx16 MSG RAM GPIO MUX, Input X-BAR, Output X-BAR CPU1.M0 RAM 1Kx16 CPU1.M1 RAM 1Kx16 CPU2.M0 RAM 1Kx16 CPU2.M1 RAM 1Kx16 PSWDPSWD Secure Memories shown in Red MEMCPU2 CPU2 to CPU1 1Kx16 MSG RAM MEMCPU1 CPU1 Buses CPU2 Buses A5:0 B5:0 C5:2 ADCIN14 ADCIN15 D5:0 Comparator Subsystem (CMPSS) DAC Config CPU1.CLA1 Bus CPU2.CLA1 Bus C28 CPU-1 FPU VCU-II TMU CPU Timer 0 CPU Timer 1 CPU Timer 2 ePIE (up to 192 interrupts) WD Timer NMI-WDT C28 CPU-2 FPU VCU-II TMU CPU Timer 0 CPU Timer 1 CPU Timer 2 ePIE (up to 192 interrupts) WD Timer NMI-WDTCPU1.CLA1 Data ROM (4Kx16) CPU1.CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1.CLA1 128x16 MSG RAM CPU1.D0 RAM 2Kx16 CPU1.D1 RAM 2Kx16 Boot-ROM 32Kx16 Nonsecure Secure-ROM 32Kx16 Secure CPU1 Local Shared 6x 2Kx16 LS0-LS5 RAMs CPU2 to CPU2.CLA1 128x16 MSG RAM CPU2.CLA1 to CPU2 128x16 MSG RAM CPU2.D0 RAM 2Kx16 CPU2.D1 RAM 2Kx16 CPU2.CLA1 Data ROM (4Kx16) Boot-ROM 32Kx16 Nonsecure Secure-ROM 32Kx16 Secure CPU2 Local Shared LS0-LS5 RAMs CPU1.CLA1 CPU1.DMA CPU2.DMA CPU2.CLA1 Data Bus Bridge ePWM-1/../12 eCAP- 1/../6 eQEP-1/2/3 SDFM-1/2 EXTSYNCINEXTSYNCOUTTZ1-TZ6 ECAPxEQEPxAEQEPxBEPWMxAEPWMxB EQEPxIEQEPxSSDx_DySDx_Cy A B C D JTAG AUXCLKIN External Crystal or Oscillator Watchdog 1/2 Main PLL Aux PLL INTOSC1 INTOSC2 Low-Power Mode Control GPIO MUX TRST TCK TDI TMS TDO 6x 2Kx16 Dual Code Security Module Emulation Code Security Logic (ECSL) Dual Code Security Module Emulation Code Security Logic (ECSL) Interprocessor Communication (IPC) Module PUMP OTP/Flash Wrapper FLASH 256K x 16 Secure User Configurable DCSM OTP 1K x 16 OTP/Flash Wrapper FLASH 256K x 16 Secure User Configurable DCSM OTP 1K x 16 SCI- A/B/C/D (16L FIFO) I2C-A/B (16L FIFO) Data Bus Bridge SCITXDx SCIRXDx SDAxSCLx CAN- A/B (32-MBOX) Data Bus Bridge CANRXx CANTXx GPIO Data Bus Bridge GPIOn Data Bus Bridge USB Ctrl / PHY USBDPUSBDM USB Ctrl / PHY EMIF1 Data Bus Bridge EM1DxEM1AxEM1CTLx EMIF2 Data Bus Bridge EM2DxEM2AxEM2CTLx Peripheral Frame 2 SPI- A/B/C (16L FIFO) SPISIMOxSPISOMIxSPICLKxSPISTEx McBSP- A/B MDXxMDRxMCLKXxMCLKRxMFSXxMFSRx uPP RAM UPPAD[7:0]UPPAENUPPASTUPPAWTUPPACLK HRPWM-1/../8 (CPU1 only) Figure 3-1. F2837xD Functional Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

4 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

7.13 Nonmaskable Interrupt With Watchdog Timer

9.1 Device and Development Support Tool

11 Mechanical, Packaging, and Orderable

4 Device Comparison

Table 4-1 lists the features of the F28377D-SEP device. Table 4-1. Device Comparison FEATURE(1) F28377D-SEP Package Type (PTP is an HLQFP package.) 176-Pin PTP Processor and Accelerators C28x Number 2 Frequency (MHz) 200 Floating-Point Unit (FPU) Yes VCU-II Yes TMU – Type 0 Yes CLA – Type 1 Number 2 Frequency (MHz) 200 6-Channel DMA – Type 0 2 Memory Flash (16-bit words) 1MB (512KW) [512KB (256KW) per CPU] RAM (16-bit words) Dedicated and Local Shared RAM 72KB (36KW) [36KB (18KW) per CPU] Global Shared RAM 128KB (64KW) Message RAM 4KB (2KW) [2KB (1KW) per CPU] Total RAM 204KB (102KW) Code security for on-chip flash, RAM, and OTP blocks Yes Boot ROM Yes System Configurable Logic Block (CLB) No 32-bit CPU timers 6 (3 per CPU) Watchdog timers 2 (1 per CPU) Nonmaskable Interrupt Watchdog (NMIWD) timers 2 (1 per CPU) Crystal oscillator/External clock input 1 0-pin internal oscillator 2 I/O pins (shared) GPIO 97 External interrupts 5 EMIF EMIF1 (16-bit or 32-bit) 1 EMIF2 (16-bit) – Analog Peripherals ADC 16-bit mode MSPS 1.1 Conversion Time (ns)(2) 915 Input pins 20 Channels (differential) 9 ADC 12-bit mode MSPS 3.5 Conversion Time (ns)(2) 280 Input pins 20 Channels (single-ended) 20 Number of 16-bit or 12-bit ADCs 4 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

6 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 4-1. Device Comparison (continued) FEATURE(1) F28377D-SEP Package Type (PTP is an HLQFP package.) 176-Pin PTP Number of 12-bit only ADCs – Temperature sensor 1 CMPSS (each CMPSS has two comparators and two internal DACs) 8 Buffered DAC 3 Control Peripherals eCAP inputs – Type 0 6 Enhanced Pulse Width Modulator (ePWM) channels – Type 4 24 eQEP modules – Type 0 3 High-resolution ePWM channels – Type 4 16 SDFM channels – Type 0 8 Communication Peripherals Controller Area Network (CAN) – Type 0(3) 2 Inter-Integrated Circuit (I2C) – Type 0 2 Multichannel Buffered Serial Port (McBSP) – Type 1 2 Serial Communications Interface (SCI) - Type 0 (UART Compatible) 4 Serial Peripheral Interface (SPI) – Type 2 3 USB – Type 0 1 uPP – Type 0 1 Temperature and Qualification Junction Temperature (TJ) –55°C to 150°C Yes (1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time Microcontrollers Peripherals Reference Guide. (2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion. (3) The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this peripheral.

4.1 Related Products

For information about similar products, see the following links: TMS320F2837xD Microcontrollers The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package. TMS320F2837xS Microcontrollers The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the TMS320F2807x series. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: F28377D-SEP

5 Pin Configuration and Functions

5.1 Pin Diagrams

Figure 5-1 shows the pin assignments on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 1201 19 1 18 1 17 1 16 1 15 1 14 1 13 1 121 1 11 10109 108 107 106 105 104 103 102 101 10099 98 97 96 95 94 93 92 91 90 89 VDD VDD VDDA VREFHIB VREFLOB VREFLOD VREFHID VSSA GPIO40 GPIO39 GPIO38 GPIO37 TCK TMS TDO TDI GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO29 GPIO28 GPIO30 ADCIND4 ADCIND3 ADCIND2 ADCIND1 ADCIND0 ADCINB3 ADCINB2 ADCINB1 ADCINB0 ADCIN15 FL T1 FL T2 TRST GPIO36 VDDIO VDDIO VDDIO VDDIO VDDIO VDD3VFL GPIO67 GPIO133GPIO45GPIO44 GPIO66 GPIO65 GPIO64 GPIO63 GPIO62 GPIO61GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 GPIO55GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49GPIO48 GPIO41ERRORSTSVREGENZX1 X2XRSGPIO43 GPIO42 GPIO47 GPIO46 VSSOSCVDD VDDVDDIOVDDOSC VDDOSC VDDIOVDDIO VDDIO VDDIO VDDIO GPIO10GPIO1 1GPIO12GPIO13GPIO14GPIO15GPIO16GPIO17GPIO18GPIO19GPIO20 GPIO8 GPIO9 GPIO22GPIO23GPIO24GPIO25GPIO26GPIO27ADCINC4ADCINC3ADCINC2 ADCINA5ADCINA4ADCINA3ADCINA2ADCINA1ADCINA0ADCIN14GPIO21 VSSA VDDA VREFHIC VREFLOCVREFLOA VREFHIA VDD GPIO99 VDD VDDIO VDDIO VDDIO VDDIOVDDIO GPIO68 GPIO69 GPIO70 GPIO71 GPIO72 GPIO73 GPIO74 GPIO75 GPIO76 GPIO77 GPIO78 GPIO79 GPIO80 GPIO81 GPIO82 GPIO83 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO84 GPIO85 GPIO86 GPIO87 VDD VDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDD A. Only the GPIO function is shown on GPIO pins. See the Signal Descriptions section for the complete, muxed signal name. Figure 5-1. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

8 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

The exposed lead frame die pad of the PowerPAD™ package serves two functions: to remove heat from the die and to provide ground path for the digital ground (analog ground is provided through dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB because this will provide both the digital ground path and good thermal conduction path. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD package. Note PCB footprints and schematic symbols are available for download in a vendor-neutral format, which can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE Symbols section in the product folder for each device, under the Packaging section. These footprints and symbols can also be searched for at https://webench.ti.com/cad/. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: F28377D-SEP

5.2 Signal Descriptions

Section 5.2.1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 4-1 for details. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups are not enabled at reset.

5.2.1 Signal Descriptions

Table 5-1. Signal Descriptions TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. ADC, DAC, AND COMPARATOR SIGNALS VREFHIA 37 I ADC-A high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. NOTE: Do not load this pin externally. VREFHIB 53 I ADC-B high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. NOTE: Do not load this pin externally. VREFHIC 35 I ADC-C high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. NOTE: Do not load this pin externally. VREFHID 55 I ADC-D high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHID and VREFLOD pins. NOTE: Do not load this pin externally. VREFLOA 33 I ADC-A low reference VREFLOB 50 I ADC-B low reference VREFLOC 32 I ADC-C low reference VREFLOD 51 I ADC-D low reference ADCIN14 I Input 14 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference. CMPIN4P I Comparator 4 positive input ADCIN15 I Input 15 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference. CMPIN4N I Comparator 4 negative input ADCINA0 I ADC-A input 0. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. DACOUTA O DAC-A output ADCINA1 I ADC-A input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. DACOUTB O DAC-B output F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

10 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. ADCINA2 I ADC-A input 2 CMPIN1P I Comparator 1 positive input ADCINA3 I ADC-A input 3 CMPIN1N I Comparator 1 negative input ADCINA4 I ADC-A input 4 CMPIN2P I Comparator 2 positive input ADCINA5 I ADC-A input 5 CMPIN2N I Comparator 2 negative input ADCINB0 I ADC-B input 0. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin. VDAC I Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin. ADCINB1 I ADC-B input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. DACOUTC O DAC-C output ADCINB2 I ADC-B input 2 CMPIN3P I Comparator 3 positive input ADCINB3 I ADC-B input 3 CMPIN3N I Comparator 3 negative input ADCINB4 – I ADC-B input 4 ADCINB5 – I ADC-B input 5 ADCINC2 I ADC-C input 2 CMPIN6P I Comparator 6 positive input ADCINC3 I ADC-C input 3 CMPIN6N I Comparator 6 negative input ADCINC4 I ADC-C input 4 CMPIN5P I Comparator 5 positive input ADCINC5 I ADC-C input 5 CMPIN5N I Comparator 5 negative input ADCIND0 I ADC-D input 0 CMPIN7P I Comparator 7 positive input ADCIND1 I ADC-D input 1 CMPIN7N I Comparator 7 negative input ADCIND2 I ADC-D input 2 CMPIN8P I Comparator 8 positive input ADCIND3 I ADC-D input 3 CMPIN8N I Comparator 8 negative input www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. ADCIND4 60 I ADC-D input 4 ADCIND5 – I ADC-D input 5 GPIO AND PERIPHERAL SIGNALS GPIO0 0, 4, 8, 12 160 I/O General-purpose input/output 0 EPWM1A 1 O Enhanced PWM1 output A (HRPWM-capable) SDAA 6 I/OD I2C-A data open-drain bidirectional port GPIO1 0, 4, 8, 12 161 I/O General-purpose input/output 1 EPWM1B 1 O Enhanced PWM1 output B (HRPWM-capable) MFSRB 3 I/O McBSP-B receive frame synch SCLA 6 I/OD I2C-A clock open-drain bidirectional port GPIO2 0, 4, 8, 12 162 I/O General-purpose input/output 2 EPWM2A 1 O Enhanced PWM2 output A (HRPWM-capable) OUTPUTXBAR1 5 O Output 1 of the output XBAR SDAB 6 I/OD I2C-B data open-drain bidirectional port GPIO3 0, 4, 8, 12 163 I/O General-purpose input/output 3 EPWM2B 1 O Enhanced PWM2 output B (HRPWM-capable) OUTPUTXBAR2 2 O Output 2 of the output XBAR MCLKRB 3 I/O McBSP-B receive clock OUTPUTXBAR2 5 O Output 2 of the output XBAR SCLB 6 I/OD I2C-B clock open-drain bidirectional port GPIO4 0, 4, 8, 12 164 I/O General-purpose input/output 4 EPWM3A 1 O Enhanced PWM3 output A (HRPWM-capable) OUTPUTXBAR3 5 O Output 3 of the output XBAR CANTXA 6 O CAN-A transmit GPIO5 0, 4, 8, 12 165 I/O General-purpose input/output 5 EPWM3B 1 O Enhanced PWM3 output B (HRPWM-capable) MFSRA 2 I/O McBSP-A receive frame synch OUTPUTXBAR3 3 O Output 3 of the output XBAR CANRXA 6 I CAN-A receive GPIO6 0, 4, 8, 12 166 I/O General-purpose input/output 6 EPWM4A 1 O Enhanced PWM4 output A (HRPWM-capable) OUTPUTXBAR4 2 O Output 4 of the output XBAR EXTSYNCOUT 3 O External ePWM synch pulse output EQEP3A 5 I Enhanced QEP3 input A CANTXB 6 O CAN-B transmit GPIO7 0, 4, 8, 12 167 I/O General-purpose input/output 7 EPWM4B 1 O Enhanced PWM4 output B (HRPWM-capable) MCLKRA 2 I/O McBSP-A receive clock OUTPUTXBAR5 3 O Output 5 of the output XBAR EQEP3B 5 I Enhanced QEP3 input B CANRXB 6 I CAN-B receive F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

12 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO8 0, 4, 8, 12 I/O General-purpose input/output 8 EPWM5A 1 O Enhanced PWM5 output A (HRPWM-capable) CANTXB 2 O CAN-B transmit ADCSOCAO 3 O ADC start-of-conversion A output for external ADC EQEP3S 5 I/O Enhanced QEP3 strobe SCITXDA 6 O SCI-A transmit data GPIO9 0, 4, 8, 12 I/O General-purpose input/output 9 EPWM5B 1 O Enhanced PWM5 output B (HRPWM-capable) SCITXDB 2 O SCI-B transmit data OUTPUTXBAR6 3 O Output 6 of the output XBAR EQEP3I 5 I/O Enhanced QEP3 index SCIRXDA 6 I SCI-A receive data GPIO10 0, 4, 8, 12 I/O General-purpose input/output 10 EPWM6A 1 O Enhanced PWM6 output A (HRPWM-capable) CANRXB 2 I CAN-B receive ADCSOCBO 3 O ADC start-of-conversion B output for external ADC EQEP1A 5 I Enhanced QEP1 input A SCITXDB 6 O SCI-B transmit data UPP-WAIT 15 I/O Universal parallel port wait. Receiver asserts to request a pause in transfer. GPIO11 0, 4, 8, 12 I/O General-purpose input/output 11 EPWM6B 1 O Enhanced PWM6 output B (HRPWM-capable) SCIRXDB 2, 6 I SCI-B receive data OUTPUTXBAR7 3 O Output 7 of the output XBAR EQEP1B 5 I Enhanced QEP1 input B UPP-START 15 I/O Universal parallel port start. Transmitter asserts at start of DMA line. GPIO12 0, 4, 8, 12 I/O General-purpose input/output 12 EPWM7A 1 O Enhanced PWM7 output A (HRPWM-capable) CANTXB 2 O CAN-B transmit MDXB 3 O McBSP-B transmit serial data EQEP1S 5 I/O Enhanced QEP1 strobe SCITXDC 6 O SCI-C transmit data UPP-ENA 15 I/O Universal parallel port enable. Transmitter asserts while data bus is active. GPIO13 0, 4, 8, 12 I/O General-purpose input/output 13 EPWM7B 1 O Enhanced PWM7 output B (HRPWM-capable) CANRXB 2 I CAN-B receive MDRB 3 I McBSP-B receive serial data EQEP1I 5 I/O Enhanced QEP1 index SCIRXDC 6 I SCI-C receive data UPP-D7 15 I/O Universal parallel port data line 7 www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO14 0, 4, 8, 12 I/O General-purpose input/output 14 EPWM8A 1 O Enhanced PWM8 output A (HRPWM-capable) SCITXDB 2 O SCI-B transmit data MCLKXB 3 I/O McBSP-B transmit clock OUTPUTXBAR3 6 O Output 3 of the output XBAR UPP-D6 15 I/O Universal parallel port data line 6 GPIO15 0, 4, 8, 12 I/O General-purpose input/output 15 EPWM8B 1 O Enhanced PWM8 output B (HRPWM-capable) SCIRXDB 2 I SCI-B receive data MFSXB 3 I/O McBSP-B transmit frame synch OUTPUTXBAR4 6 O Output 4 of the output XBAR UPP-D5 15 I/O Universal parallel port data line 5 GPIO16 0, 4, 8, 12 I/O General-purpose input/output 16 SPISIMOA 1 I/O SPI-A slave in, master out CANTXB 2 O CAN-B transmit OUTPUTXBAR7 3 O Output 7 of the output XBAR EPWM9A 5 O Enhanced PWM9 output A SD1_D1 7 I Sigma-Delta 1 channel 1 data input UPP-D4 15 I/O Universal parallel port data line 4 GPIO17 0, 4, 8, 12 I/O General-purpose input/output 17 SPISOMIA 1 I/O SPI-A slave out, master in CANRXB 2 I CAN-B receive OUTPUTXBAR8 3 O Output 8 of the output XBAR EPWM9B 5 O Enhanced PWM9 output B SD1_C1 7 I Sigma-Delta 1 channel 1 clock input UPP-D3 15 I/O Universal parallel port data line 3 GPIO18 0, 4, 8, 12 I/O General-purpose input/output 18 SPICLKA 1 I/O SPI-A clock SCITXDB 2 O SCI-B transmit data CANRXA 3 I CAN-A receive EPWM10A 5 O Enhanced PWM10 output A SD1_D2 7 I Sigma-Delta 1 channel 2 data input UPP-D2 15 I/O Universal parallel port data line 2 GPIO19 0, 4, 8, 12 I/O General-purpose input/output 19 SPISTEA 1 I/O SPI-A slave transmit enable SCIRXDB 2 I SCI-B receive data CANTXA 3 O CAN-A transmit EPWM10B 5 O Enhanced PWM10 output B SD1_C2 7 I Sigma-Delta 1 channel 2 clock input UPP-D1 15 I/O Universal parallel port data line 1 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

14 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO20 0, 4, 8, 12 I/O General-purpose input/output 20 EQEP1A 1 I Enhanced QEP1 input A MDXA 2 O McBSP-A transmit serial data CANTXB 3 O CAN-B transmit EPWM11A 5 O Enhanced PWM11 output A SD1_D3 7 I Sigma-Delta 1 channel 3 data input UPP-D0 15 I/O Universal parallel port data line 0 GPIO21 0, 4, 8, 12 I/O General-purpose input/output 21 EQEP1B 1 I Enhanced QEP1 input B MDRA 2 I McBSP-A receive serial data CANRXB 3 I CAN-B receive EPWM11B 5 O Enhanced PWM11 output B SD1_C3 7 I Sigma-Delta 1 channel 3 clock input UPP-CLK 15 I/O Universal parallel port transmit clock GPIO22 0, 4, 8, 12 I/O General-purpose input/output 22 EQEP1S 1 I/O Enhanced QEP1 strobe MCLKXA 2 I/O McBSP-A transmit clock SCITXDB 3 O SCI-B transmit data EPWM12A 5 O Enhanced PWM12 output A SPICLKB 6 I/O SPI-B clock SD1_D4 7 I Sigma-Delta 1 channel 4 data input GPIO23 0, 4, 8, 12 I/O General-purpose input/output 23 EQEP1I 1 I/O Enhanced QEP1 index MFSXA 2 I/O McBSP-A transmit frame synch SCIRXDB 3 I SCI-B receive data EPWM12B 5 O Enhanced PWM12 output B SPISTEB 6 I/O SPI-B slave transmit enable SD1_C4 7 I Sigma-Delta 1 channel 4 clock input GPIO24 0, 4, 8, 12 I/O General-purpose input/output 24 OUTPUTXBAR1 1 O Output 1 of the output XBAR EQEP2A 2 I Enhanced QEP2 input A MDXB 3 O McBSP-B transmit serial data SPISIMOB 6 I/O SPI-B slave in, master out SD2_D1 7 I Sigma-Delta 2 channel 1 data input GPIO25 0, 4, 8, 12 I/O General-purpose input/output 25 OUTPUTXBAR2 1 O Output 2 of the output XBAR EQEP2B 2 I Enhanced QEP2 input B MDRB 3 I McBSP-B receive serial data SPISOMIB 6 I/O SPI-B slave out, master in SD2_C1 7 I Sigma-Delta 2 channel 1 clock input www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO26 0, 4, 8, 12 I/O General-purpose input/output 26 OUTPUTXBAR3 1 O Output 3 of the output XBAR EQEP2I 2 I/O Enhanced QEP2 index MCLKXB 3 I/O McBSP-B transmit clock OUTPUTXBAR3 5 O Output 3 of the output XBAR SPICLKB 6 I/O SPI-B clock SD2_D2 7 I Sigma-Delta 2 channel 2 data input GPIO27 0, 4, 8, 12 I/O General-purpose input/output 27 OUTPUTXBAR4 1 O Output 4 of the output XBAR EQEP2S 2 I/O Enhanced QEP2 strobe MFSXB 3 I/O McBSP-B transmit frame synch OUTPUTXBAR4 5 O Output 4 of the output XBAR SPISTEB 6 I/O SPI-B slave transmit enable SD2_C2 7 I Sigma-Delta 2 channel 2 clock input GPIO28 0, 4, 8, 12 I/O General-purpose input/output 28 SCIRXDA 1 I SCI-A receive data EM1CS4 2 O External memory interface 1 chip select 4 OUTPUTXBAR5 5 O Output 5 of the output XBAR EQEP3A 6 I Enhanced QEP3 input A SD2_D3 7 I Sigma-Delta 2 channel 3 data input GPIO29 0, 4, 8, 12 I/O General-purpose input/output 29 SCITXDA 1 O SCI-A transmit data EM1SDCKE 2 O External memory interface 1 SDRAM clock enable OUTPUTXBAR6 5 O Output 6 of the output XBAR EQEP3B 6 I Enhanced QEP3 input B SD2_C3 7 I Sigma-Delta 2 channel 3 clock input GPIO30 0, 4, 8, 12 I/O General-purpose input/output 30 CANRXA 1 I CAN-A receive EM1CLK 2 O External memory interface 1 clock OUTPUTXBAR7 5 O Output 7 of the output XBAR EQEP3S 6 I/O Enhanced QEP3 strobe SD2_D4 7 I Sigma-Delta 2 channel 4 data input GPIO31 0, 4, 8, 12 I/O General-purpose input/output 31 CANTXA 1 O CAN-A transmit EM1WE 2 O External memory interface 1 write enable OUTPUTXBAR8 5 O Output 8 of the output XBAR EQEP3I 6 I/O Enhanced QEP3 index SD2_C4 7 I Sigma-Delta 2 channel 4 clock input GPIO32 0, 4, 8, 12 I/O General-purpose input/output 32 SDAA 1 I/OD I2C-A data open-drain bidirectional port EM1CS0 2 O External memory interface 1 chip select 0 GPIO33 0, 4, 8, 12 I/O General-purpose input/output 33 SCLA 1 I/OD I2C-A clock open-drain bidirectional port EM1RNW 2 O External memory interface 1 read not write F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

16 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO34 0, 4, 8, 12 I/O General-purpose input/output 34 OUTPUTXBAR1 1 O Output 1 of the output XBAR EM1CS2 2 O External memory interface 1 chip select 2 SDAB 6 I/OD I2C-B data open-drain bidirectional port GPIO35 0, 4, 8, 12 I/O General-purpose input/output 35 SCIRXDA 1 I SCI-A receive data EM1CS3 2 O External memory interface 1 chip select 3 SCLB 6 I/OD I2C-B clock open-drain bidirectional port GPIO36 0, 4, 8, 12 I/O General-purpose input/output 36 SCITXDA 1 O SCI-A transmit data EM1WAIT 2 I External memory interface 1 Asynchronous SRAM WAIT CANRXA 6 I CAN-A receive GPIO37 0, 4, 8, 12 I/O General-purpose input/output 37 OUTPUTXBAR2 1 O Output 2 of the output XBAR EM1OE 2 O External memory interface 1 output enable CANTXA 6 O CAN-A transmit GPIO38 0, 4, 8, 12 I/O General-purpose input/output 38 EM1A0 2 O External memory interface 1 address line 0 SCITXDC 5 O SCI-C transmit data CANTXB 6 O CAN-B transmit GPIO39 0, 4, 8, 12 I/O General-purpose input/output 39 EM1A1 2 O External memory interface 1 address line 1 SCIRXDC 5 I SCI-C receive data CANRXB 6 I CAN-B receive GPIO40 0, 4, 8, 12 I/O General-purpose input/output 40 EM1A2 2 O External memory interface 1 address line 2 SDAB 6 I/OD I2C-B data open-drain bidirectional port GPIO41 0, 4, 8, 12 I/O General-purpose input/output 41. For applications using the Hibernate low-power mode, this pin serves as the GPIOHIBWAKE signal. For details, see the Low Power Modes section of the System Control chapter in the TMS320F2837xD Dual-Core Real- Time Microcontrollers Technical Reference Manual. EM1A3 2 O External memory interface 1 address line 3 SCLB 6 I/OD I2C-B clock open-drain bidirectional port GPIO42 0, 4, 8, 12 130 I/O General-purpose input/output 42 SDAA 6 I/OD I2C-A data open-drain bidirectional port SCITXDA 15 O SCI-A transmit data USB0DM Analog I/O USB PHY differential data GPIO43 0, 4, 8, 12 131 I/O General-purpose input/output 43 SCLA 6 I/OD I2C-A clock open-drain bidirectional port SCIRXDA 15 I SCI-A receive data USB0DP Analog I/O USB PHY differential data GPIO44 0, 4, 8, 12 113 I/O General-purpose input/output 44 EM1A4 2 O External memory interface 1 address line 4 www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO45 0, 4, 8, 12 115 I/O General-purpose input/output 45 EM1A5 2 O External memory interface 1 address line 5 GPIO46 0, 4, 8, 12 128 I/O General-purpose input/output 46 EM1A6 2 O External memory interface 1 address line 6 SCIRXDD 6 I SCI-D receive data GPIO47 0, 4, 8, 12 129 I/O General-purpose input/output 47 EM1A7 2 O External memory interface 1 address line 7 SCITXDD 6 O SCI-D transmit data GPIO48 0, 4, 8, 12 I/O General-purpose input/output 48 OUTPUTXBAR3 1 O Output 3 of the output XBAR EM1A8 2 O External memory interface 1 address line 8 SCITXDA 6 O SCI-A transmit data SD1_D1 7 I Sigma-Delta 1 channel 1 data input GPIO49 0, 4, 8, 12 I/O General-purpose input/output 49 OUTPUTXBAR4 1 O Output 4 of the output XBAR EM1A9 2 O External memory interface 1 address line 9 SCIRXDA 6 I SCI-A receive data SD1_C1 7 I Sigma-Delta 1 channel 1 clock input GPIO50 0, 4, 8, 12 I/O General-purpose input/output 50 EQEP1A 1 I Enhanced QEP1 input A EM1A10 2 O External memory interface 1 address line 10 SPISIMOC 6 I/O SPI-C slave in, master out SD1_D2 7 I Sigma-Delta 1 channel 2 data input GPIO51 0, 4, 8, 12 I/O General-purpose input/output 51 EQEP1B 1 I Enhanced QEP1 input B EM1A11 2 O External memory interface 1 address line 11 SPISOMIC 6 I/O SPI-C slave out, master in SD1_C2 7 I Sigma-Delta 1 channel 2 clock input GPIO52 0, 4, 8, 12 I/O General-purpose input/output 52 EQEP1S 1 I/O Enhanced QEP1 strobe EM1A12 2 O External memory interface 1 address line 12 SPICLKC 6 I/O SPI-C clock SD1_D3 7 I Sigma-Delta 1 channel 3 data input GPIO53 0, 4, 8, 12 I/O General-purpose input/output 53 EQEP1I 1 I/O Enhanced QEP1 index EM1D31 2 I/O External memory interface 1 data line 31 EM2D15 3 I/O External memory interface 2 data line 15 SPISTEC 6 I/O SPI-C slave transmit enable SD1_C3 7 I Sigma-Delta 1 channel 3 clock input F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

18 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO54 0, 4, 8, 12 I/O General-purpose input/output 54 SPISIMOA 1 I/O SPI-A slave in, master out EM1D30 2 I/O External memory interface 1 data line 30 EM2D14 3 I/O External memory interface 2 data line 14 EQEP2A 5 I Enhanced QEP2 input A SCITXDB 6 O SCI-B transmit data SD1_D4 7 I Sigma-Delta 1 channel 4 data input GPIO55 0, 4, 8, 12 100 I/O General-purpose input/output 55 SPISOMIA 1 I/O SPI-A slave out, master in EM1D29 2 I/O External memory interface 1 data line 29 EM2D13 3 I/O External memory interface 2 data line 13 EQEP2B 5 I Enhanced QEP2 input B SCIRXDB 6 I SCI-B receive data SD1_C4 7 I Sigma-Delta 1 channel 4 clock input GPIO56 0, 4, 8, 12 101 I/O General-purpose input/output 56 SPICLKA 1 I/O SPI-A clock EM1D28 2 I/O External memory interface 1 data line 28 EM2D12 3 I/O External memory interface 2 data line 12 EQEP2S 5 I/O Enhanced QEP2 strobe SCITXDC 6 O SCI-C transmit data SD2_D1 7 I Sigma-Delta 2 channel 1 data input GPIO57 0, 4, 8, 12 102 I/O General-purpose input/output 57 SPISTEA 1 I/O SPI-A slave transmit enable EM1D27 2 I/O External memory interface 1 data line 27 EM2D11 3 I/O External memory interface 2 data line 11 EQEP2I 5 I/O Enhanced QEP2 index SCIRXDC 6 I SCI-C receive data SD2_C1 7 I Sigma-Delta 2 channel 1 clock input GPIO58 0, 4, 8, 12 103 I/O General-purpose input/output 58 MCLKRA 1 I/O McBSP-A receive clock EM1D26 2 I/O External memory interface 1 data line 26 EM2D10 3 I/O External memory interface 2 data line 10 OUTPUTXBAR1 5 O Output 1 of the output XBAR SPICLKB 6 I/O SPI-B clock SD2_D2 7 I Sigma-Delta 2 channel 2 data input SPISIMOA 15 I/O SPI-A slave in, master out(2) GPIO59 0, 4, 8, 12 104 I/O General-purpose input/output 59(3) MFSRA 1 I/O McBSP-A receive frame synch EM1D25 2 I/O External memory interface 1 data line 25 EM2D9 3 I/O External memory interface 2 data line 9 OUTPUTXBAR2 5 O Output 2 of the output XBAR SPISTEB 6 I/O SPI-B slave transmit enable SD2_C2 7 I Sigma-Delta 2 channel 2 clock input SPISOMIA 15 I/O SPI-A slave out, master in(2) www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO60 0, 4, 8, 12 105 I/O General-purpose input/output 60 MCLKRB 1 I/O McBSP-B receive clock EM1D24 2 I/O External memory interface 1 data line 24 EM2D8 3 I/O External memory interface 2 data line 8 OUTPUTXBAR3 5 O Output 3 of the output XBAR SPISIMOB 6 I/O SPI-B slave in, master out SD2_D3 7 I Sigma-Delta 2 channel 3 data input SPICLKA 15 I/O SPI-A clock(2) GPIO61 0, 4, 8, 12 107 I/O General-purpose input/output 61(3) MFSRB 1 I/O McBSP-B receive frame synch EM1D23 2 I/O External memory interface 1 data line 23 EM2D7 3 I/O External memory interface 2 data line 7 OUTPUTXBAR4 5 O Output 4 of the output XBAR SPISOMIB 6 I/O SPI-B slave out, master in SD2_C3 7 I Sigma-Delta 2 channel 3 clock input SPISTEA 15 I/O SPI-A slave transmit enable(2) GPIO62 0, 4, 8, 12 108 I/O General-purpose input/output 62 SCIRXDC 1 I SCI-C receive data EM1D22 2 I/O External memory interface 1 data line 22 EM2D6 3 I/O External memory interface 2 data line 6 EQEP3A 5 I Enhanced QEP3 input A CANRXA 6 I CAN-A receive SD2_D4 7 I Sigma-Delta 2 channel 4 data input GPIO63 0, 4, 8, 12 109 I/O General-purpose input/output 63 SCITXDC 1 O SCI-C transmit data EM1D21 2 I/O External memory interface 1 data line 21 EM2D5 3 I/O External memory interface 2 data line 5 EQEP3B 5 I Enhanced QEP3 input B CANTXA 6 O CAN-A transmit SD2_C4 7 I Sigma-Delta 2 channel 4 clock input SPISIMOB 15 I/O SPI-B slave in, master out(2) GPIO64 0, 4, 8, 12 110 I/O General-purpose input/output 64(3) EM1D20 2 I/O External memory interface 1 data line 20 EM2D4 3 I/O External memory interface 2 data line 4 EQEP3S 5 I/O Enhanced QEP3 strobe SCIRXDA 6 I SCI-A receive data SPISOMIB 15 I/O SPI-B slave out, master in(2) GPIO65 0, 4, 8, 12 111 I/O General-purpose input/output 65 EM1D19 2 I/O External memory interface 1 data line 19 EM2D3 3 I/O External memory interface 2 data line 3 EQEP3I 5 I/O Enhanced QEP3 index SCITXDA 6 O SCI-A transmit data SPICLKB 15 I/O SPI-B clock(2) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

20 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO66 0, 4, 8, 12 112 I/O General-purpose input/output 66(3) EM1D18 2 I/O External memory interface 1 data line 18 EM2D2 3 I/O External memory interface 2 data line 2 SDAB 6 I/OD I2C-B data open-drain bidirectional port SPISTEB 15 I/O SPI-B slave transmit enable(2) GPIO67 0, 4, 8, 12 132 I/O General-purpose input/output 67 EM1D17 2 I/O External memory interface 1 data line 17 EM2D1 3 I/O External memory interface 2 data line 1 GPIO68 0, 4, 8, 12 133 I/O General-purpose input/output 68 EM1D16 2 I/O External memory interface 1 data line 16 EM2D0 3 I/O External memory interface 2 data line 0 GPIO69 0, 4, 8, 12 134 I/O General-purpose input/output 69 EM1D15 2 I/O External memory interface 1 data line 15 SCLB 6 I/OD I2C-B clock open-drain bidirectional port SPISIMOC 15 I/O SPI-C slave in, master out(2) GPIO70 0, 4, 8, 12 135 I/O General-purpose input/output 70(3) EM1D14 2 I/O External memory interface 1 data line 14 CANRXA 5 I CAN-A receive SCITXDB 6 O SCI-B transmit data SPISOMIC 15 I/O SPI-C slave out, master in(2) GPIO71 0, 4, 8, 12 136 I/O General-purpose input/output 71 EM1D13 2 I/O External memory interface 1 data line 13 CANTXA 5 O CAN-A transmit SCIRXDB 6 I SCI-B receive data SPICLKC 15 I/O SPI-C clock(2) GPIO72 0, 4, 8, 12 139 I/O General-purpose input/output 72.(3) This is the factory default boot mode select pin 1. EM1D12 2 I/O External memory interface 1 data line 12 CANTXB 5 O CAN-B transmit SCITXDC 6 O SCI-C transmit data SPISTEC 15 I/O SPI-C slave transmit enable(2) GPIO73 0, 4, 8, 12 140 I/O General-purpose input/output 73 EM1D11 2 I/O External memory interface 1 data line 11 XCLKOUT 3 O/Z External clock output. This pin outputs a divided-down version of a chosen clock signal from within the device. The clock signal is chosen using the CLKSRCCTL3.XCLKOUTSEL bit field while the divide ratio is chosen using the XCLKOUTDIVSEL.XCLKOUTDIV bit field. CANRXB 5 I CAN-B receive SCIRXDC 6 I SCI-C receive GPIO74 0, 4, 8, 12 141 I/O General-purpose input/output 74 EM1D10 2 I/O External memory interface 1 data line 10 GPIO75 0, 4, 8, 12 142 I/O General-purpose input/output 75 EM1D9 2 I/O External memory interface 1 data line 9 www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO76 0, 4, 8, 12 143 I/O General-purpose input/output 76 EM1D8 2 I/O External memory interface 1 data line 8 SCITXDD 6 O SCI-D transmit data GPIO77 0, 4, 8, 12 144 I/O General-purpose input/output 77 EM1D7 2 I/O External memory interface 1 data line 7 SCIRXDD 6 I SCI-D receive data GPIO78 0, 4, 8, 12 145 I/O General-purpose input/output 78 EM1D6 2 I/O External memory interface 1 data line 6 EQEP2A 6 I Enhanced QEP2 input A GPIO79 0, 4, 8, 12 146 I/O General-purpose input/output 79 EM1D5 2 I/O External memory interface 1 data line 5 EQEP2B 6 I Enhanced QEP2 input B GPIO80 0, 4, 8, 12 148 I/O General-purpose input/output 80 EM1D4 2 I/O External memory interface 1 data line 4 EQEP2S 6 I/O Enhanced QEP2 strobe GPIO81 0, 4, 8, 12 149 I/O General-purpose input/output 81 EM1D3 2 I/O External memory interface 1 data line 3 EQEP2I 6 I/O Enhanced QEP2 index GPIO82 0, 4, 8, 12 150 I/O General-purpose input/output 82 EM1D2 2 I/O External memory interface 1 data line 2 GPIO83 0, 4, 8, 12 151 I/O General-purpose input/output 83 EM1D1 2 I/O External memory interface 1 data line 1 GPIO84 0, 4, 8, 12 154 I/O General-purpose input/output 84. This is the factory default boot mode select pin 0. SCITXDA 5 O SCI-A transmit data MDXB 6 O McBSP-B transmit serial data MDXA 15 O McBSP-A transmit serial data GPIO85 0, 4, 8, 12 155 I/O General-purpose input/output 85 EM1D0 2 I/O External memory interface 1 data line 0 SCIRXDA 5 I SCI-A receive data MDRB 6 I McBSP-B receive serial data MDRA 15 I McBSP-A receive serial data GPIO86 0, 4, 8, 12 156 I/O General-purpose input/output 86 EM1A13 2 O External memory interface 1 address line 13 EM1CAS 3 O External memory interface 1 column address strobe SCITXDB 5 O SCI-B transmit data MCLKXB 6 I/O McBSP-B transmit clock MCLKXA 15 I/O McBSP-A transmit clock GPIO87 0, 4, 8, 12 157 I/O General-purpose input/output 87 EM1A14 2 O External memory interface 1 address line 14 EM1RAS 3 O External memory interface 1 row address strobe SCIRXDB 5 I SCI-B receive data MFSXB 6 I/O McBSP-B transmit frame synch MFSXA 15 I/O McBSP-A transmit frame synch F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

22 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO88 0, 4, 8, 12 170 I/O General-purpose input/output 88 EM1A15 2 O External memory interface 1 address line 15 EM1DQM0 3 O External memory interface 1 Input/output mask for byte 0 GPIO89 0, 4, 8, 12 171 I/O General-purpose input/output 89 EM1A16 2 O External memory interface 1 address line 16 EM1DQM1 3 O External memory interface 1 Input/output mask for byte 1 SCITXDC 6 O SCI-C transmit data GPIO90 0, 4, 8, 12 172 I/O General-purpose input/output 90 EM1A17 2 O External memory interface 1 address line 17 EM1DQM2 3 O External memory interface 1 Input/output mask for byte 2 SCIRXDC 6 I SCI-C receive data GPIO91 0, 4, 8, 12 173 I/O General-purpose input/output 91 EM1A18 2 O External memory interface 1 address line 18 EM1DQM3 3 O External memory interface 1 Input/output mask for byte 3 SDAA 6 I/OD I2C-A data open-drain bidirectional port GPIO92 0, 4, 8, 12 174 I/O General-purpose input/output 92 EM1A19 2 O External memory interface 1 address line 19 EM1BA1 3 O External memory interface 1 bank address 1 SCLA 6 I/OD I2C-A clock open-drain bidirectional port GPIO93 0, 4, 8, 12 175 I/O General-purpose input/output 93 EM1BA0 3 O External memory interface 1 bank address 0 SCITXDD 6 O SCI-D transmit data GPIO94 0, 4, 8, 12 176 I/O General-purpose input/output 94 SCIRXDD 6 I SCI-D receive data GPIO95 0, 4, 8, 12 – I/O General-purpose input/output 95 GPIO96 0, 4, 8, 12 I/O General-purpose input/output 96 EM2DQM1 3 O External memory interface 2 Input/output mask for byte 1 EQEP1A 5 I Enhanced QEP1 input A GPIO97 0, 4, 8, 12 I/O General-purpose input/output 97 EM2DQM0 3 O External memory interface 2 Input/output mask for byte 0 EQEP1B 5 I Enhanced QEP1 input B GPIO98 0, 4, 8, 12 I/O General-purpose input/output 98 EM2A0 3 O External memory interface 2 address line 0 EQEP1S 5 I/O Enhanced QEP1 strobe GPIO99 0, 4, 8, 12 I/O General-purpose input/output 99 EM2A1 3 O External memory interface 2 address line 1 EQEP1I 5 I/O Enhanced QEP1 index GPIO100 0, 4, 8, 12 I/O General-purpose input/output 100 EM2A2 3 O External memory interface 2 address line 2 EQEP2A 5 I Enhanced QEP2 input A SPISIMOC 6 I/O SPI-C slave in, master out www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO101 0, 4, 8, 12 I/O General-purpose input/output 101 EM2A3 3 O External memory interface 2 address line 3 EQEP2B 5 I Enhanced QEP2 input B SPISOMIC 6 I/O SPI-C slave out, master in GPIO102 0, 4, 8, 12 I/O General-purpose input/output 102 EM2A4 3 O External memory interface 2 address line 4 EQEP2S 5 I/O Enhanced QEP2 strobe SPICLKC 6 I/O SPI-C clock GPIO103 0, 4, 8, 12 I/O General-purpose input/output 103 EM2A5 3 O External memory interface 2 address line 5 EQEP2I 5 I/O Enhanced QEP2 index SPISTEC 6 I/O SPI-C slave transmit enable GPIO104 0, 4, 8, 12 I/O General-purpose input/output 104 SDAA 1 I/OD I2C-A data open-drain bidirectional port EM2A6 3 O External memory interface 2 address line 6 EQEP3A 5 I Enhanced QEP3 input A SCITXDD 6 O SCI-D transmit data GPIO105 0, 4, 8, 12 I/O General-purpose input/output 105 SCLA 1 I/OD I2C-A clock open-drain bidirectional port EM2A7 3 O External memory interface 2 address line 7 EQEP3B 5 I Enhanced QEP3 input B SCIRXDD 6 I SCI-D receive data GPIO106 0, 4, 8, 12 I/O General-purpose input/output 106 EM2A8 3 O External memory interface 2 address line 8 EQEP3S 5 I/O Enhanced QEP3 strobe SCITXDC 6 O SCI-C transmit data GPIO107 0, 4, 8, 12 I/O General-purpose input/output 107 EM2A9 3 O External memory interface 2 address line 9 EQEP3I 5 I/O Enhanced QEP3 index SCIRXDC 6 I SCI-C receive data GPIO108 0, 4, 8, 12 I/O General-purpose input/output 108 EM2A10 3 O External memory interface 2 address line 10 GPIO109 0, 4, 8, 12 I/O General-purpose input/output 109 EM2A11 3 O External memory interface 2 address line 11 GPIO110 0, 4, 8, 12 I/O General-purpose input/output 110 EM2WAIT 3 I External memory interface 2 Asynchronous SRAM WAIT GPIO111 0, 4, 8, 12 I/O General-purpose input/output 111 EM2BA0 3 O External memory interface 2 bank address 0 GPIO112 0, 4, 8, 12 I/O General-purpose input/output 112 EM2BA1 3 O External memory interface 2 bank address 1 GPIO113 0, 4, 8, 12 I/O General-purpose input/output 113 EM2CAS 3 O External memory interface 2 column address strobe GPIO114 0, 4, 8, 12 I/O General-purpose input/output 114 EM2RAS 3 O External memory interface 2 row address strobe F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

24 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO115 0, 4, 8, 12 I/O General-purpose input/output 115 EM2CS0 3 O External memory interface 2 chip select 0 GPIO116 0, 4, 8, 12 I/O General-purpose input/output 116 EM2CS2 3 O External memory interface 2 chip select 2 GPIO117 0, 4, 8, 12 I/O General-purpose input/output 117 EM2SDCKE 3 O External memory interface 2 SDRAM clock enable GPIO118 0, 4, 8, 12 I/O General-purpose input/output 118 EM2CLK 3 O External memory interface 2 clock GPIO119 0, 4, 8, 12 I/O General-purpose input/output 119 EM2RNW 3 O External memory interface 2 read not write GPIO120 0, 4, 8, 12 I/O General-purpose input/output 120 EM2WE 3 O External memory interface 2 write enable USB0PFLT 15 I/O USB external regulator power fault indicator GPIO121 0, 4, 8, 12 I/O General-purpose input/output 121 EM2OE 3 O External memory interface 2 output enable USB0EPEN 15 I/O USB external regulator enable GPIO122 0, 4, 8, 12 I/O General-purpose input/output 122 SPISIMOC 6 I/O SPI-C slave in, master out SD1_D1 7 I Sigma-Delta 1 channel 1 data input GPIO123 0, 4, 8, 12 I/O General-purpose input/output 123 SPISOMIC 6 I/O SPI-C slave out, master in SD1_C1 7 I Sigma-Delta 1 channel 1 clock input GPIO124 0, 4, 8, 12 I/O General-purpose input/output 124 SPICLKC 6 I/O SPI-C clock SD1_D2 7 I Sigma-Delta 1 channel 2 data input GPIO125 0, 4, 8, 12 I/O General-purpose input/output 125 SPISTEC 6 I/O SPI-C slave transmit enable SD1_C2 7 I Sigma-Delta 1 channel 2 clock input GPIO126 0, 4, 8, 12 I/O General-purpose input/output 126 SD1_D3 7 I Sigma-Delta 1 channel 3 data input GPIO127 0, 4, 8, 12 I/O General-purpose input/output 127 SD1_C3 7 I Sigma-Delta 1 channel 3 clock input GPIO128 0, 4, 8, 12 I/O General-purpose input/output 128 SD1_D4 7 I Sigma-Delta 1 channel 4 data input GPIO129 0, 4, 8, 12 I/O General-purpose input/output 129 SD1_C4 7 I Sigma-Delta 1 channel 4 clock input GPIO130 0, 4, 8, 12 I/O General-purpose input/output 130 SD2_D1 7 I Sigma-Delta 2 channel 1 data input GPIO131 0, 4, 8, 12 I/O General-purpose input/output 131 SD2_C1 7 I Sigma-Delta 2 channel 1 clock input GPIO132 0, 4, 8, 12 I/O General-purpose input/output 132 SD2_D2 7 I Sigma-Delta 2 channel 2 data input www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO133/AUXCLKIN 0, 4, 8, 12 118 I/O General-purpose input/output 133. The AUXCLKIN function of this GPIO pin could be used to provide a single-ended 3.3-V level clock signal to the Auxiliary Phase-Locked Loop (AUXPLL), whose output is used for the USB module. The AUXCLKIN clock may also be used for the CAN module. SD2_C2 7 I Sigma-Delta 2 channel 2 clock input GPIO134 0, 4, 8, 12 I/O General-purpose input/output 134 SD2_D3 7 I Sigma-Delta 2 channel 3 data input GPIO135 0, 4, 8, 12 I/O General-purpose input/output 135 SCITXDA 6 O SCI-A transmit data SD2_C3 7 I Sigma-Delta 2 channel 3 clock input GPIO136 0, 4, 8, 12 I/O General-purpose input/output 136 SCIRXDA 6 I SCI-A receive data SD2_D4 7 I Sigma-Delta 2 channel 4 data input GPIO137 0, 4, 8, 12 I/O General-purpose input/output 137 SCITXDB 6 O SCI-B transmit data SD2_C4 7 I Sigma-Delta 2 channel 4 clock input GPIO138 0, 4, 8, 12 I/O General-purpose input/output 138 SCIRXDB 6 I SCI-B receive data GPIO139 0, 4, 8, 12 I/O General-purpose input/output 139 SCIRXDC 6 I SCI-C receive data GPIO140 0, 4, 8, 12 I/O General-purpose input/output 140 SCITXDC 6 O SCI-C transmit data GPIO141 0, 4, 8, 12 I/O General-purpose input/output 141 SCIRXDD 6 I SCI-D receive data GPIO142 0, 4, 8, 12 I/O General-purpose input/output 142 SCITXDD 6 O SCI-D transmit data GPIO143 0, 4, 8, 12 – I/O General-purpose input/output 143 GPIO144 0, 4, 8, 12 – I/O General-purpose input/output 144 GPIO145 0, 4, 8, 12 I/O General-purpose input/output 145 EPWM1A 1 O Enhanced PWM1 output A (HRPWM-capable) GPIO146 0, 4, 8, 12 I/O General-purpose input/output 146 EPWM1B 1 O Enhanced PWM1 output B (HRPWM-capable) GPIO147 0, 4, 8, 12 I/O General-purpose input/output 147 EPWM2A 1 O Enhanced PWM2 output A (HRPWM-capable) GPIO148 0, 4, 8, 12 I/O General-purpose input/output 148 EPWM2B 1 O Enhanced PWM2 output B (HRPWM-capable) GPIO149 0, 4, 8, 12 I/O General-purpose input/output 149 EPWM3A 1 O Enhanced PWM3 output A (HRPWM-capable) GPIO150 0, 4, 8, 12 I/O General-purpose input/output 150 EPWM3B 1 O Enhanced PWM3 output B (HRPWM-capable) GPIO151 0, 4, 8, 12 I/O General-purpose input/output 151 EPWM4A 1 O Enhanced PWM4 output A (HRPWM-capable) GPIO152 0, 4, 8, 12 I/O General-purpose input/output 152 EPWM4B 1 O Enhanced PWM4 output B (HRPWM-capable) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

26 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. GPIO153 0, 4, 8, 12 I/O General-purpose input/output 153 EPWM5A 1 O Enhanced PWM5 output A (HRPWM-capable) GPIO154 0, 4, 8, 12 I/O General-purpose input/output 154 EPWM5B 1 O Enhanced PWM5 output B (HRPWM-capable) GPIO155 0, 4, 8, 12 I/O General-purpose input/output 155 EPWM6A 1 O Enhanced PWM6 output A (HRPWM-capable) GPIO156 0, 4, 8, 12 I/O General-purpose input/output 156 EPWM6B 1 O Enhanced PWM6 output B (HRPWM-capable) GPIO157 0, 4, 8, 12 I/O General-purpose input/output 157 EPWM7A 1 O Enhanced PWM7 output A (HRPWM-capable) GPIO158 0, 4, 8, 12 I/O General-purpose input/output 158 EPWM7B 1 O Enhanced PWM7 output B (HRPWM-capable) GPIO159 0, 4, 8, 12 I/O General-purpose input/output 159 EPWM8A 1 O Enhanced PWM8 output A (HRPWM-capable) GPIO160 0, 4, 8, 12 I/O General-purpose input/output 160 EPWM8B 1 O Enhanced PWM8 output B (HRPWM-capable) GPIO161 0, 4, 8, 12 I/O General-purpose input/output 161 EPWM9A 1 O Enhanced PWM9 output A GPIO162 0, 4, 8, 12 I/O General-purpose input/output 162 EPWM9B 1 O Enhanced PWM9 output B GPIO163 0, 4, 8, 12 I/O General-purpose input/output 163 EPWM10A 1 O Enhanced PWM10 output A GPIO164 0, 4, 8, 12 I/O General-purpose input/output 164 EPWM10B 1 O Enhanced PWM10 output B GPIO165 0, 4, 8, 12 I/O General-purpose input/output 165 EPWM11A 1 O Enhanced PWM11 output A GPIO166 0, 4, 8, 12 I/O General-purpose input/output 166 EPWM11B 1 O Enhanced PWM11 output B GPIO167 0, 4, 8, 12 I/O General-purpose input/output 167 EPWM12A 1 O Enhanced PWM12 output A GPIO168 0, 4, 8, 12 I/O General-purpose input/output 168 EPWM12B 1 O Enhanced PWM12 output B RESET XRS 124 I/OD Device Reset (in) and Watchdog Reset (out). The devices have a built-in power-on reset (POR) circuit. During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset or NMI watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. CLOCKS X1 123 I On-chip crystal-oscillator input. To use this oscillator, a quartz crystal must be connected across X1 and X2. If this pin is not used, it must be tied to GND. This pin can also be used to feed a single-ended 3.3-V level clock. In this case, X2 is a No Connect (NC). X2 121 O On-chip crystal-oscillator output. A quartz crystal may be connected across X1 and X2. If X2 is not used, it must be left unconnected. NO CONNECT NC – No connect JTAG TCK 81 I JTAG test clock with internal pullup (see the Electrical Characteristics section) TDI 77 I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 78 O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.(3) TMS 80 I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST 79 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST must be maintained low at all times during normal device operation, so an external pulldown resistor is required on this pin for protection against noise spikes. The value of this resistor should be as small as possible, so long as the JTAG debug probe is still able to drive the TRST pin high. A resistor between 2.2-kΩ and 10- kΩ generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debug probe and the application. This pin has an internal 50-ns (nominal) glitch filter. INTERNAL VOLTAGE REGULATOR CONTROL VREGENZ 119 I Internal voltage regulator enable with internal pulldown. The internal VREG is not supported and must be disabled. Connect VREGENZ to VDDIO. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

28 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. ANALOG, DIGITAL, AND I/O POWER VDD 1.2-V digital logic power pins. There are two options for placing the decoupling capacitors.

Option 1 - Even Distribution: Distribute decoupling capacitance evenly across each VDD pin with a minimum total capacitance of approximately 20uF.
Option 2 - Bulk Capacitance: Place a 1uF capacitor near each VDD pin and place the remainder of the minimum total 20uF capacitance as bulk capacitance on the VDD net . The exact value of the decoupling capacitance should be determined by your system voltage regulation solution. 117 126 137 153 158 169 VDD3VFL 72 3.3-V Flash power pin. Place a minimum 0.1-µF decoupling capacitor on each pin.– VDDA 36 3.3-V analog power pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin.54 www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. VDDIO 3.3-V digital I/O power pins. Place a minimum 0.1-µF decoupling capacitor on each pin. The exact value of the decoupling capacitance should be determined by your system voltage regulation solution. 106 114 116 127 138 147 152 159 168 VDDOSC 120 Power pins for the 3.3-V on-chip crystal oscillator (X1 and X2) and the two zero-pin internal oscillators (INTOSC). Place a 0.1-μF (minimum) decoupling capacitor on each pin.125 VSS PWR PAD (177) Device ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB. VSSOSC 122 Crystal oscillator (X1 and X2) ground pin. When using an external crystal, do not connect this pin to the board ground. Instead, connect it to the ground reference of the external crystal oscillator circuit. If an external crystal is not used, this pin may be connected to the board ground. VSSA Analog ground F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

30 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-1. Signal Descriptions (continued) TERMINAL I/O/Z(1) DESCRIPTION NAME MUX POSITION PTP PIN NO. SPECIAL FUNCTIONS ERRORSTS 92 O Error status output. This pin has an internal pulldown. TEST PINS FLT1 73 I/O Flash test pin 1. Reserved for TI. Must be left unconnected. FLT2 74 I/O Flash test pin 2. Reserved for TI. Must be left unconnected. (1) I = Input, O = Output, OD = Open Drain, Z = High Impedance (2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR). (3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system PCB characteristics. If this is a concern, the user should take precautions such as adding a 39Ω (10% tolerance) series termination resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be performed with the provided IBIS models. The termination is not required if this pin is used for input function.

5.3 Pins With Internal Pullup and Pulldown

Some pins on the device have internal pullups or pulldowns. Table 5-2 lists the pull direction and when it is active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a particular package. Other pins noted in Table 5-2 with pullups and pulldowns are always on and cannot be disabled. Table 5-2. Pins With Internal Pullup and Pulldown PIN RESET ( XRS = 0) DEVICE BOOT APPLICATION SOFTWARE GPIOx Pullup disabled Pullup disabled(1) Pullup enable is application- defined TRST Pulldown active TCK Pullup active TMS Pullup active TDI Pullup active XRS Pullup active VREGENZ Pulldown active ERRORSTS Pulldown active Other pins No pullup or pulldown present (1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: F28377D-SEP

5.4 Pin Multiplexing

5.4.1 GPIO Muxed Pins

Table 5-3 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from alternate mux selections. Columns not shown and blank cells are reserved GPIO Mux settings. Table 5-3. GPIO Muxed Pins GPIO Mux Selection(1) (2) GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15 GPyGMUXn. GPIOz = 00b, 01b, 10b, 11b 00b 01b 11b GPyMUXn. GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b GPIO0 EPWM1A (O) SDAA (I/OD) GPIO1 EPWM1B (O) MFSRB (I/O) SCLA (I/OD) GPIO2 EPWM2A (O) OUTPUTXBAR1 (O) SDAB (I/OD) GPIO3 EPWM2B (O) OUTPUTXBAR2 (O) MCLKRB (I/O) OUTPUTXBAR2 (O) SCLB (I/OD) GPIO4 EPWM3A (O) OUTPUTXBAR3 (O) CANTXA (O) GPIO5 EPWM3B (O) MFSRA (I/O) OUTPUTXBAR3 (O) CANRXA (I) GPIO6 EPWM4A (O) OUTPUTXBAR4 (O) EXTSYNCOUT (O) EQEP3A (I) CANTXB (O) GPIO7 EPWM4B (O) MCLKRA (I/O) OUTPUTXBAR5 (O) EQEP3B (I) CANRXB (I) GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O) EQEP3S (I/O) SCITXDA (O) GPIO9 EPWM5B (O) SCITXDB (O) OUTPUTXBAR6 (O) EQEP3I (I/O) SCIRXDA (I) GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O) EQEP1A (I) SCITXDB (O) UPP-WAIT (I/O) GPIO11 EPWM6B (O) SCIRXDB (I) OUTPUTXBAR7 (O) EQEP1B (I) SCIRXDB (I) UPP-START (I/O) GPIO12 EPWM7A (O) CANTXB (O) MDXB (O) EQEP1S (I/O) SCITXDC (O) UPP-ENA (I/O) GPIO13 EPWM7B (O) CANRXB (I) MDRB (I) EQEP1I (I/O) SCIRXDC (I) UPP-D7 (I/O) GPIO14 EPWM8A (O) SCITXDB (O) MCLKXB (I/O) OUTPUTXBAR3 (O) UPP-D6 (I/O) GPIO15 EPWM8B (O) SCIRXDB (I) MFSXB (I/O) OUTPUTXBAR4 (O) UPP-D5 (I/O) GPIO16 SPISIMOA (I/O) CANTXB (O) OUTPUTXBAR7 (O) EPWM9A (O) SD1_D1 (I) UPP-D4 (I/O) GPIO17 SPISOMIA (I/O) CANRXB (I) OUTPUTXBAR8 (O) EPWM9B (O) SD1_C1 (I) UPP-D3 (I/O) GPIO18 SPICLKA (I/O) SCITXDB (O) CANRXA (I) EPWM10A (O) SD1_D2 (I) UPP-D2 (I/O) GPIO19 SPISTEA (I/O) SCIRXDB (I) CANTXA (O) EPWM10B (O) SD1_C2 (I) UPP-D1 (I/O) GPIO20 EQEP1A (I) MDXA (O) CANTXB (O) EPWM11A (O) SD1_D3 (I) UPP-D0 (I/O) GPIO21 EQEP1B (I) MDRA (I) CANRXB (I) EPWM11B (O) SD1_C3 (I) UPP-CLK (I/O) GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) EPWM12A (O) SPICLKB (I/O) SD1_D4 (I) GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I) EPWM12B (O) SPISTEB (I/O) SD1_C4 (I) GPIO24 OUTPUTXBAR1 (O) EQEP2A (I) MDXB (O) SPISIMOB (I/O) SD2_D1 (I) GPIO25 OUTPUTXBAR2 (O) EQEP2B (I) MDRB (I) SPISOMIB (I/O) SD2_C1 (I) GPIO26 OUTPUTXBAR3 (O) EQEP2I (I/O) MCLKXB (I/O) OUTPUTXBAR3 (O) SPICLKB (I/O) SD2_D2 (I) GPIO27 OUTPUTXBAR4 (O) EQEP2S (I/O) MFSXB (I/O) OUTPUTXBAR4 (O) SPISTEB (I/O) SD2_C2 (I) GPIO28 SCIRXDA (I) EM1CS4 (O) OUTPUTXBAR5 (O) EQEP3A (I) SD2_D3 (I) GPIO29 SCITXDA (O) EM1SDCKE (O) OUTPUTXBAR6 (O) EQEP3B (I) SD2_C3 (I) GPIO30 CANRXA (I) EM1CLK (O) OUTPUTXBAR7 (O) EQEP3S (I/O) SD2_D4 (I) GPIO31 CANTXA (O) EM1WE (O) OUTPUTXBAR8 (O) EQEP3I (I/O) SD2_C4 (I) GPIO32 SDAA (I/OD) EM1CS0 (O) GPIO33 SCLA (I/OD) EM1RNW (O) GPIO34 OUTPUTXBAR1 (O) EM1CS2 (O) SDAB (I/OD) GPIO35 SCIRXDA (I) EM1CS3 (O) SCLB (I/OD) GPIO36 SCITXDA (O) EM1WAIT (I) CANRXA (I) GPIO37 OUTPUTXBAR2 (O) EM1OE (O) CANTXA (O) GPIO38 EM1A0 (O) SCITXDC (O) CANTXB (O) GPIO39 EM1A1 (O) SCIRXDC (I) CANRXB (I) GPIO40 EM1A2 (O) SDAB (I/OD) GPIO41 EM1A3 (O) SCLB (I/OD) GPIO42 SDAA (I/OD) SCITXDA (O) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

32 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-3. GPIO Muxed Pins (continued) GPIO Mux Selection(1) (2) GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15 GPyGMUXn. GPIOz = 00b, 01b, 10b, 11b 00b 01b 11b GPyMUXn. GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b GPIO43 SCLA (I/OD) SCIRXDA (I) GPIO44 EM1A4 (O) GPIO45 EM1A5 (O) GPIO46 EM1A6 (O) SCIRXDD (I) GPIO47 EM1A7 (O) SCITXDD (O) GPIO48 OUTPUTXBAR3 (O) EM1A8 (O) SCITXDA (O) SD1_D1 (I) GPIO49 OUTPUTXBAR4 (O) EM1A9 (O) SCIRXDA (I) SD1_C1 (I) GPIO50 EQEP1A (I) EM1A10 (O) SPISIMOC (I/O) SD1_D2 (I) GPIO51 EQEP1B (I) EM1A11 (O) SPISOMIC (I/O) SD1_C2 (I) GPIO52 EQEP1S (I/O) EM1A12 (O) SPICLKC (I/O) SD1_D3 (I) GPIO53 EQEP1I (I/O) EM1D31 (I/O) EM2D15 (I/O) SPISTEC (I/O) SD1_C3 (I) GPIO54 SPISIMOA (I/O) EM1D30 (I/O) EM2D14 (I/O) EQEP2A (I) SCITXDB (O) SD1_D4 (I) GPIO55 SPISOMIA (I/O) EM1D29 (I/O) EM2D13 (I/O) EQEP2B (I) SCIRXDB (I) SD1_C4 (I) GPIO56 SPICLKA (I/O) EM1D28 (I/O) EM2D12 (I/O) EQEP2S (I/O) SCITXDC (O) SD2_D1 (I) GPIO57 SPISTEA (I/O) EM1D27 (I/O) EM2D11 (I/O) EQEP2I (I/O) SCIRXDC (I) SD2_C1 (I) GPIO58 MCLKRA (I/O) EM1D26 (I/O) EM2D10 (I/O) OUTPUTXBAR1 (O) SPICLKB (I/O) SD2_D2 (I) SPISIMOA(3) (I/O) GPIO59 MFSRA (I/O) EM1D25 (I/O) EM2D9 (I/O) OUTPUTXBAR2 (O) SPISTEB (I/O) SD2_C2 (I) SPISOMIA(3) (I/O) GPIO60 MCLKRB (I/O) EM1D24 (I/O) EM2D8 (I/O) OUTPUTXBAR3 (O) SPISIMOB (I/O) SD2_D3 (I) SPICLKA(3) (I/O) GPIO61 MFSRB (I/O) EM1D23 (I/O) EM2D7 (I/O) OUTPUTXBAR4 (O) SPISOMIB (I/O) SD2_C3 (I) SPISTEA (3) (I/O) GPIO62 SCIRXDC (I) EM1D22 (I/O) EM2D6 (I/O) EQEP3A (I) CANRXA (I) SD2_D4 (I) GPIO63 SCITXDC (O) EM1D21 (I/O) EM2D5 (I/O) EQEP3B (I) CANTXA (O) SD2_C4 (I) SPISIMOB(3) (I/O) GPIO64 EM1D20 (I/O) EM2D4 (I/O) EQEP3S (I/O) SCIRXDA (I) SPISOMIB(3) (I/O) GPIO65 EM1D19 (I/O) EM2D3 (I/O) EQEP3I (I/O) SCITXDA (O) SPICLKB(3) (I/O) GPIO66 EM1D18 (I/O) EM2D2 (I/O) SDAB (I/OD) SPISTEB (3) (I/O) GPIO67 EM1D17 (I/O) EM2D1 (I/O) GPIO68 EM1D16 (I/O) EM2D0 (I/O) GPIO69 EM1D15 (I/O) SCLB (I/OD) SPISIMOC(3) (I/O) GPIO70 EM1D14 (I/O) CANRXA (I) SCITXDB (O) SPISOMIC(3) (I/O) GPIO71 EM1D13 (I/O) CANTXA (O) SCIRXDB (I) SPICLKC(3) (I/O) GPIO72 EM1D12 (I/O) CANTXB (O) SCITXDC (O) SPISTEC (3) (I/O) GPIO73 EM1D11 (I/O) XCLKOUT (O) CANRXB (I) SCIRXDC (I) GPIO74 EM1D10 (I/O) GPIO75 EM1D9 (I/O) GPIO76 EM1D8 (I/O) SCITXDD (O) GPIO77 EM1D7 (I/O) SCIRXDD (I) GPIO78 EM1D6 (I/O) EQEP2A (I) GPIO79 EM1D5 (I/O) EQEP2B (I) GPIO80 EM1D4 (I/O) EQEP2S (I/O) GPIO81 EM1D3 (I/O) EQEP2I (I/O) GPIO82 EM1D2 (I/O) GPIO83 EM1D1 (I/O) GPIO84 SCITXDA (O) MDXB (O) MDXA (O) GPIO85 EM1D0 (I/O) SCIRXDA (I) MDRB (I) MDRA (I) GPIO86 EM1A13 (O) EM1CAS (O) SCITXDB (O) MCLKXB (I/O) MCLKXA (I/O) GPIO87 EM1A14 (O) EM1RAS (O) SCIRXDB (I) MFSXB (I/O) MFSXA (I/O) GPIO88 EM1A15 (O) EM1DQM0 (O) GPIO89 EM1A16 (O) EM1DQM1 (O) SCITXDC (O) GPIO90 EM1A17 (O) EM1DQM2 (O) SCIRXDC (I) GPIO91 EM1A18 (O) EM1DQM3 (O) SDAA (I/OD) GPIO92 EM1A19 (O) EM1BA1 (O) SCLA (I/OD) GPIO93 EM1BA0 (O) SCITXDD (O) www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: F28377D-SEP

Table 5-3. GPIO Muxed Pins (continued) GPIO Mux Selection(1) (2) GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15 GPyGMUXn. GPIOz = 00b, 01b, 10b, 11b 00b 01b 11b GPyMUXn. GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b GPIO94 SCIRXDD (I) GPIO95 GPIO96 EM2DQM1 (O) EQEP1A (I) GPIO97 EM2DQM0 (O) EQEP1B (I) GPIO98 EM2A0 (O) EQEP1S (I/O) GPIO99 EM2A1 (O) EQEP1I (I/O) GPIO100 EM2A2 (O) EQEP2A (I) SPISIMOC (I/O) GPIO101 EM2A3 (O) EQEP2B (I) SPISOMIC (I/O) GPIO102 EM2A4 (O) EQEP2S (I/O) SPICLKC (I/O) GPIO103 EM2A5 (O) EQEP2I (I/O) SPISTEC (I/O) GPIO104 SDAA (I/OD) EM2A6 (O) EQEP3A (I) SCITXDD (O) GPIO105 SCLA (I/OD) EM2A7 (O) EQEP3B (I) SCIRXDD (I) GPIO106 EM2A8 (O) EQEP3S (I/O) SCITXDC (O) GPIO107 EM2A9 (O) EQEP3I (I/O) SCIRXDC (I) GPIO108 EM2A10 (O) GPIO109 EM2A11 (O) GPIO110 EM2WAIT (I) GPIO111 EM2BA0 (O) GPIO112 EM2BA1 (O) GPIO113 EM2CAS (O) GPIO114 EM2RAS (O) GPIO115 EM2CS0 (O) GPIO116 EM2CS2 (O) GPIO117 EM2SDCKE (O) GPIO118 EM2CLK (O) GPIO119 EM2RNW (O) GPIO120 EM2WE (O) USB0PFLT GPIO121 EM2OE (O) USB0EPEN GPIO122 SPISIMOC (I/O) SD1_D1 (I) GPIO123 SPISOMIC (I/O) SD1_C1 (I) GPIO124 SPICLKC (I/O) SD1_D2 (I) GPIO125 SPISTEC (I/O) SD1_C2 (I) GPIO126 SD1_D3 (I) GPIO127 SD1_C3 (I) GPIO128 SD1_D4 (I) GPIO129 SD1_C4 (I) GPIO130 SD2_D1 (I) GPIO131 SD2_C1 (I) GPIO132 SD2_D2 (I) GPIO133/ AUXCLKIN SD2_C2 (I) GPIO134 SD2_D3 (I) GPIO135 SCITXDA (O) SD2_C3 (I) GPIO136 SCIRXDA (I) SD2_D4 (I) GPIO137 SCITXDB (O) SD2_C4 (I) GPIO138 SCIRXDB (I) GPIO139 SCIRXDC (I) GPIO140 SCITXDC (O) GPIO141 SCIRXDD (I) GPIO142 SCITXDD (O) GPIO143 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

34 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Table 5-3. GPIO Muxed Pins (continued) GPIO Mux Selection(1) (2) GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15 GPyGMUXn. GPIOz = 00b, 01b, 10b, 11b 00b 01b 11b GPyMUXn. GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b GPIO144 GPIO145 EPWM1A (O) GPIO146 EPWM1B (O) GPIO147 EPWM2A (O) GPIO148 EPWM2B (O) GPIO149 EPWM3A (O) GPIO150 EPWM3B (O) GPIO151 EPWM4A (O) GPIO152 EPWM4B (O) GPIO153 EPWM5A (O) GPIO154 EPWM5B (O) GPIO155 EPWM6A (O) GPIO156 EPWM6B (O) GPIO157 EPWM7A (O) GPIO158 EPWM7B (O) GPIO159 EPWM8A (O) GPIO160 EPWM8B (O) GPIO161 EPWM9A (O) GPIO162 EPWM9B (O) GPIO163 EPWM10A (O) GPIO164 EPWM10B (O) GPIO165 EPWM11A (O) GPIO166 EPWM11B (O) GPIO167 EPWM12A (O) GPIO168 EPWM12B (O) (1) I = Input, O = Output, OD = Open Drain (2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved. (3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR). www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: F28377D-SEP

5.4.2 Input X-BAR

The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to external interrupts (XINT) (see Figure 5-2 ). Table 5-4 shows the input X-BAR destinations. For details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . Input X-BAR CPU PIE CLA GPIO0 GPIOx EXT Y N1S NCI EXT Y N2S NCI eCAP1 INPUT7 eCAP2 eCAP3 eCAP4 eCAP5 eCAP6 TRIP4 TRIP5 TRIP7 TRIP8 TRIP9 TRIP10 TRIP11 TRIP12 XINT5 XINT2 XINT1 XINT3 XINT4 ePWM and eCAP Sync Chain Asynchronous Synchronous Sync. + Qual. ADCEXTSOC ADC TZ1,TRIP1 TZ2,TRIP2 TZ3,TRIP3 TRIP6 INPUT8 INPUT9 INPUT10 INPUT11 INPUT12 Output X-BAR ePWM ModulesePWM X-BAR EXT Y N2S NCI INPUT4 INPUT13 INPUT14 INPUT6 INPUT5 INPUT3 INPUT2 INPUT1 Figure 5-2. Input X-BAR Table 5-4. Input X-BAR Destinations INPUT DESTINATIONS INPUT1 EPWM[TZ1,TRIP1], EPWM X-BAR, Output X-BAR INPUT2 EPWM[TZ2,TRIP2], EPWM X-BAR, Output X-BAR INPUT3 EPWM[TZ3,TRIP3], EPWM X-BAR, Output X-BAR INPUT4 XINT1, EPWM X-BAR, Output X-BAR INPUT5 XINT2, ADCEXTSOC, EXTSYNCIN1, EPWM X-BAR, Output X-BAR INPUT6 XINT3, EPWM[TRIP6], EXTSYNCIN2, EPWM X-BAR, Output X-BAR INPUT7 ECAP1 INPUT8 ECAP2 INPUT9 ECAP3 INPUT10 ECAP4 INPUT11 ECAP5 INPUT12 ECAP6 INPUT13 XINT4 INPUT14 XINT5 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

36 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

5.4.3 Output X-BAR and ePWM X-BAR

The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The ePWM X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for both the Output X-BAR and ePWM X-BAR are shown in Figure 5-3. For details on the Output X-BAR and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . CMPSSx MCPWM and eCAP Sync ADCSOCAO Select Ckt ADCSOCBO Select Ckt eCAPx ADCx Input X-Bar CTRIPOUTH CTRIPOUTL CTRIPH CTRIPL EXTSYNCOUT ADCSOCAO ADCSOCBO ECAPxOUT EVT1 INPUT1-6 INPUT7-14 (PWM X-BAR ONLY) GPIO Mux OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8 Output X-BAR X-BAR Flags (shared) All MCPWM Modules TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 TZ7 TZ8 PWM X-BAR (Output X-BAR only) (PWM X-BAR only) EVT2 EVT3 CLOCKFAIL PIEERR EMUSTOP (PWMXBARONLY) EQEP1ERR (PWMXBARONLY) ECCDBLERR (PWMXBARONLY) ERRORSTS Figure 5-3. Output X-BAR and ePWM X-BAR www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: F28377D-SEP

5.4.4 USB Pin Muxing

Table 5-5 shows assignment of the alternate USB function mapping. These can be configured with the GPBAMSEL register. Table 5-5. Alternate USB Function GPIO GPBAMSEL SETTING USB FUNCTION GPIO42 GPBAMSEL[10] = 1b USB0DM GPIO43 GPBAMSEL[11] = 1b USB0DP

5.4.5 High-Speed SPI Pin Muxing

The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special GPIO configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI when not in high-speed mode (HS_MODE = 0). To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX registers as shown in Table 5-6. Table 5-6. GPIO Configuration for High-Speed SPI GPIO SPI SIGNAL MUX CONFIGURATION SPIA GPIO58 SPISIMOA GPBGMUX2[21:20]=11b GPBMUX2[21:20]=11b GPIO59 SPISOMIA GPBGMUX2[23:22]=11b GPBMUX2[23:22]=11b GPIO60 SPICLKA GPBGMUX2[25:24]=11b GPBMUX2[25:24]=11b GPIO61 SPISTEA GPBGMUX2[27:26]=11b GPBMUX2[27:26]=11b SPIB GPIO63 SPISIMOB GPBGMUX2[31:30]=11b GPBMUX2[31:30]=11b GPIO64 SPISOMIB GPCGMUX1[1:0]=11b GPCMUX1[1:0]=11b GPIO65 SPICLKB GPCGMUX1[3:2]=11b GPCMUX1[3:2]=11b GPIO66 SPISTEB GPCGMUX1[5:4]=11b GPCMUX1[5:4]=11b SPIC GPIO69 SPISIMOC GPCGMUX1[11:10]=11b GPCMUX1[11:10]=11b GPIO70 SPISOMIC GPCGMUX1[13:12]=11b GPCMUX1[13:12]=11b GPIO71 SPICLKC GPCGMUX1[15:14]=11b GPCMUX1[15:14]=11b GPIO72 SPISTEC GPCGMUX1[17:16]=11b GPCMUX1[17:16]=11b F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

38 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

5.5 Connections for Unused Pins

For applications that do not need to use all functions of the device, Table 5-7 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 5-7, any are acceptable. Pins not listed in Table 5-7 must be connected according to the Signal Descriptions section. Table 5-7. Connections for Unused Pins SIGNAL NAME ACCEPTABLE PRACTICE Analog VREFHIx Tie to VDDA VREFLOx Tie to VSSA ADCINx

No Connect
Tie to VSSA Digital GPIOx
No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled) X1 Tie to VSS X2 No Connect TCK
No Connect
Pullup resistor TDI
No Connect
Pullup resistor TDO No Connect TMS No Connect TRST Pulldown resistor (2.2 kΩ or smaller) VREGENZ Tie to VDDIO. VREG is not supported. ERRORSTS No Connect FLT1 No Connect FLT2 No Connect Power and Ground VDD All VDD pins must be connected per the Signal Descriptions section. VDDA If a dedicated analog supply is not used, tie to VDDIO. VDDIO All VDDIO pins must be connected per the Signal Descriptions section. VDD3VFL Must be tied to VDDIO VDDOSC Must be tied to VDDIO VSS All VSS pins must be connected to board ground. VSSA If a dedicated analog ground is not used, tie to VSS. VSSOSC If an external crystal is not used, this pin may be connected to the board ground. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: F28377D-SEP

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT Supply voltage VDDIO with respect to VSS –0.3 4.6 V VDD3VFL with respect to VSS –0.3 4.6 VDDOSC with respect to VSS –0.3 4.6 VDD with respect to VSS –0.3 1.5 Analog voltage VDDA with respect to VSSA –0.3 4.6 V Input voltage VIN (3.3 V) –0.3 4.6 V Output voltage VO –0.3 4.6 V Input clamp current Digital input (per pin), IIK (VIN < VSS or VIN > VDDIO) –20 20 mA Analog input (per pin), IIKANALOG (VIN < VSSA or VIN > VDDA) –20 20 Total for all inputs, IIKTOTAL (VIN < VSS/VSSA or VIN > VDDIO/VDDA) –20 20 Output current Digital output (per pin), IOUT –20 20 mA Operating junction temperature TJ –55 150 °C Storage temperature(3) Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see Semiconductor and IC Package Thermal Metrics.

6.2 ESD Ratings

F28377D-SEP in 176-pin PTP package V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) All pins ±2000 VCharged device model (CDM), per AEC Q100-011 All pins ±500 Corner pins on 176-pin PTP: 1, 44, 45, 88, 89, 132, 133, 176 ±750 (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

40 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.3 Recommended Operating Conditions

Device supply voltage, I/O, VDDIO (1) 3.14 3.3 3.47 V Device supply voltage, VDD 1.14 1.2 1.26 V Supply ground, VSS 0 V Analog supply voltage, VDDA 3.14 3.3 3.47 V Analog ground, VSSA 0 V Junction temperature, TJ (2) –55 150 °C (1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other. (2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded Processors for more information. Te m p e r a tu r e (  C ) Life (hrs) 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 A. Silicon operating life design goal is 100000 power-on hours (POH) at 105°C junction temperature (does not include package interconnect life). B. The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics. Figure 6-1. F28377D-SEP Operating Life Derating Chart www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: F28377D-SEP

6.4 Power Consumption Summary

Current values listed in this section are representative for the test conditions given and not the absolute maximum possible. The actual device currents in an application will vary with application code and pin configurations. Section 6.4.1 shows the device current consumption at 200-MHz SYSCLK.

6.4.1 Device Current Consumption at 200-MHz SYSCLK

IDD IDDIO (1) IDDA IDD3VFL TYP(5) MAX(4) TYP(5) MAX(4) TYP(5) MAX(4) TYP(5) MAX(4) Operational

Code is running out of RAM.(6)
All I/O pins are left unconnected.
Peripherals not active have their clocks disabled.
FLASH is read and in active state.
XCLKOUT is enabled at SYSCLK/4. 325 mA 495 mA 30 mA 13 mA 20 mA 33 mA 40 mA IDLE
Both CPU1 and CPU2 are in IDLE mode.
Flash is powered down.
XCLKOUT is turned off. 105 mA 250 mA 3 mA 10 mA 10 µA 150 µA 10 µA 150 µA STANDBY
Both CPU1 and CPU2 are in STANDBY mode.
Flash is powered down.
XCLKOUT is turned off. 30 mA 170 mA 3 mA 10 mA 5 µA 150 µA 10 µA 150 µA HALT(2)
CPU1 watchdog is running.
Flash is powered down.
XCLKOUT is turned off. 1.5 mA 120 mA 750 µA 2 mA 5 µA 150 µA 10 µA 150 µA HIBERNATE(3)
CPU1.M0 and CPU1.M1 RAMs are in low-power data retention mode.
CPU2.M0 and CPU2.M1 RAMs are in low-power data retention mode. 300 µA 5 mA 750 µA 2 mA 5 µA 75 µA 1 µA 50 µA Flash Erase/Program(7)
CPU1 is running from RAM.
CPU2 is running from Flash.
All I/O pins are left unconnected.
Peripheral clocks are disabled.
CPU1 is performing Flash Erase and Programming.
CPU2 is accessing Flash locations to keep bank active.
XCLKOUT is turned off. 242 mA 360 mA 3 mA 10 mA 10 µA 150 µA 53 mA 65 mA F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

42 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.4.1 Device Current Consumption at 200-MHz SYSCLK (continued)

IDD IDDIO (1) IDDA IDD3VFL TYP(5) MAX(4) TYP(5) MAX(4) TYP(5) MAX(4) TYP(5) MAX(4) RESET

CPU is held in reset via external low signal driven onto XRSn
XRSn held low through power-up 10 mA 20 mA 0.01 mA 0.8 mA 0.02 mA 1 mA 2.5 mA 8 mA (1) IDDIO current is dependent on the electrical loading on the I/O pins. (2) CPU2 must go into IDLE mode before CPU1 enters HALT mode. (3) CPU2 must go into reset/IDLE/STANDBY mode before CPU1 enters HIBERNATE mode. (4) MAX: Vmax, 125°C (5) TYP: Vnom, 30°C (6) The following is executed in a loop on CPU1:
All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to I2C-B; McBSP-A to McBSP-B; USB
SDFM1 to SDFM4 active
ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
CPU TIMERs active
DMA does 32-bit burst transfers
CLA1 does multiply-accumulate tasks
All ADCs perform continuous conversion
All DACs ramp voltage up/down at 150 kHz
CMPSS1 to CMPSS8 active The following is executed in a loop on CPU2:
CPU TIMERs active
CLA1 does multiply-accumulate tasks
VCU does complex multiply/accumulate with parallel load
TMU calculates a cosine
FPU does multiply/accumulate with parallel load (7) Brownout events during flash programming can corrupt flash data. Programming environments using alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system components with sufficient margin to avoid supply brownout conditions. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: F28377D-SEP

6.4.2 Current Consumption Graphs

Figure 6-2 and Figure 6-3 are a typical representation of the relationship between frequency and current consumption/power on the device. The operational test from Section 6.4.1 was run across frequency at Vmax and high temperature. Actual results will vary based on the system implementation and conditions. 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 V DD V DDIO V DDA V DD3VFL SYSCLK (MHz) Current (A) Figure 6-2. Operational Current Versus Frequency 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Po wer Power (W) SYSCLK (MHz) Figure 6-3. Power Versus Frequency F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

44 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.4.3 Reducing Current Consumption

The F2837xD devices provide some methods to reduce the device current consumption:

Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered during idle periods in the application.
The flash module may be powered down if the code is run from RAM.
Disable the pullups on pins that assume an output function.
Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be achieved by turning off the clock to any peripheral that is not used in a given application. Table 6-1 indicates the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual to ensure each module is powered down as well. Table 6-1. Current on VDD Supply by Various Peripherals (at 200 MHz) PERIPHERAL MODULE(1) (2) IDD CURRENT REDUCTION (mA) ADC(3) 3.3 CAN 3.3 CLA 1.4 CMPSS(3) 1.4 CPUTIMER 0.3 DAC(3) 0.6 DMA 2.9 eCAP 0.6 EMIF1 2.9 EMIF2 2.6 ePWM1 to ePWM4(4) 4.5 ePWM5 to ePWM12(4) 1.7 HRPWM(4) 1.7 I2C 1.3 McBSP 1.6 SCI 0.9 SDFM 2 SPI 0.5 uPP 7.3 USB and AUXPLL at 60 MHz 23.8 (1) At Vmax and 125°C. (2) All peripherals are disabled upon reset. Use the PCLKCRx register to individually enable peripherals. For peripherals with multiple instances, the current quoted is for a single module. (3) This number represents the current drawn by the digital portion of the ADC, CMPSS, and DAC modules. (4) The ePWM is at /2 of SYSCLK. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

46 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = IOH MIN VDDIO * 0.8 V IOH = –100 μA VDDIO – 0.2 VOL Low-level output voltage IOL = IOL MAX 0.4 V IOL = 100 µA 0.2 IOH High-level output source current for all output pins –4 mA IOL Low-level output sink current for all output pins 4 mA VIH High-level input voltage (3.3 V) GPIO0–GPIO7, GPIO42–GPIO43, GPIO46–GPIO47 VDDIO * 0.7 VDDIO + 0.3 V All other pins 2.0 VDDIO + 0.3 VIL Low-level input voltage (3.3 V) VSS – 0.3 0.8 V VHYSTERESIS Input hysteresis 150 mV Ipulldown Input current Digital inputs with pulldown(1) VDDIO = 3.3 V VIN = VDDIO 120 µA Ipullup Input current Digital inputs with pullup enabled(1) VDDIO = 3.3 V VIN = 0 V 150 µA ILEAK Pin leakage Digital Pullups disabled

0 V ≤ VIN ≤ VDDIO

µA Analog (except ADCINB0 or DACOUTx)

0 V ≤ VIN ≤ VDDA

ADCINB0 2 11(2) DACOUTx 66 CI Input capacitance 2 pF VDDIO-POR VDDIO power-on reset voltage 2.3 V (1) See Table 5-2 for a list of pins with a pullup or pulldown. (2) The MAX input leakage shown on ADCINB0 is at high temperature. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: F28377D-SEP

6.6 Thermal Resistance Characteristics

6.6.1 PTP Package

°C/W(1) AIR FLOW (lfm)(2) RΘJC Junction-to-case thermal resistance 6.97 N/A RΘJB Junction-to-board thermal resistance 6.05 N/A RΘJA (High k PCB) Junction-to-free air thermal resistance 17.8 0 RΘJMA Junction-to-moving air thermal resistance 12.8 150 11.4 250 10.1 500 PsiJT Junction-to-package top 0.11 0 0.24 150 0.33 250 0.42 500 PsiJB Junction-to-board 6.1 0 5.5 150 5.4 250 5.3 500 (1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements (2) lfm = linear feet per minute

6.7 Thermal Design Considerations

Based on the end application design and operational profile, the I DD and I DDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (T A) varies with the end application and product design. The critical factor that affects reliability and functionality is T J, the junction temperature, not the ambient temperature. Hence, care should be taken to keep T J within the specified limits. T case should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and definitions. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

48 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8 System

6.8.1 Power Sequencing

6.8.1.1 Signal Pin Requirements

Before powering the device, no voltage larger than 0.3 V above V DDIO can be applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).

6.8.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements

The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional operation.

6.8.1.3 VDD Requirements

The internal VREG is not supported. The VREGENZ pin must be tied to V DDIO and an external source used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO. VDDOSC and V DD must be powered on and off at the same time. V DDOSC should not be powered on when V DD is off. For applications not powering V DDOSC and V DD at the same time, see the "INTOSC: V DDOSC Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . There is an internal 12.8-mA current source from V DD3VFL to V DD when the flash banks are active. When the flash banks are active and the device is in a low-activity state (for example, a low-power mode), this internal current source can cause V DD to rise to approximately 1.3 V. There will be zero current load to the external system V DD regulator while in this condition. This is not an issue for most regulators; however, if the system voltage regulator requires a minimum load for proper operation, then an external 82 Ω resistor can be added to the board to ensure a minimal current load on V DD. See the "Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata .

6.8.1.4 Supply Ramp Rate

6.8.1.4.1 Supply Ramp Rate

Supply ramp rate VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS 330 105 V/s

6.8.1.5 Supply Supervision

An internal power-on-reset (POR) circuit keeps the I/Os in a high-impedance state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS low when supplies are outside operational specifications. Note If the supply voltage is held near the POR threshold, then the device may drive periodic resets onto the XRS pin.

6.8.2 Reset Timing

XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset. A resistor with a value from 2.2 k Ω to 10 k Ω should be placed between XRS and VDDIO. A capacitor should be placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Figure 6-5 shows the recommended reset circuit. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: F28377D-SEP

/c163100 nF 2.2 k – 10 k/c87 /c87 VDDIO Figure 6-5. Reset Circuit

6.8.2.1 Reset Sources

The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . The parameter th(boot-mode) must account for a reset initiated from any of these sources. CAUTION Some reset sources are internally driven by the device. Some of these sources will drive XRS low. Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by other devices in the system. The boot configuration has a provision for changing the boot pins in OTP; for more details, see the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

6.8.2.2 Reset Electrical Data and Timing

switching characteristics. Figure 6-6 shows the power-on reset. Figure 6-7 shows the warm reset.

6.8.2.2.1 Reset ( XRS) Timing Requirements

th(boot-mode) Hold time for boot-mode pins 1.5 ms tw(RSL2) Pulse duration, XRS low on warm reset All cases 3.2 µsLow-power modes used in application and SYSCLKDIV > 16 3.2 * (SYSCLKDIV/16)

6.8.2.2.2 Reset ( XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulse duration, XRS driven low by device after supplies are stable 100 µs tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

50 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.3 Clock Specifications

6.8.3.1 Clock Sources

Table 6-2 lists four possible clock sources. Figure 6-8 provides an overview of the device's clocking system. Table 6-2. Possible Reference Clock Sources CLOCK SOURCE MODULES CLOCKED COMMENTS INTOSC1 Can be used to provide clock for:

Watchdog block
Main PLL
CPU-Timer 2 Internal oscillator 1. Zero-pin overhead 10-MHz internal oscillator. INTOSC2(1) Can be used to provide clock for:
Main PLL
Auxiliary PLL
CPU-Timer 2 Internal oscillator 2. Zero-pin overhead 10-MHz internal oscillator. XTAL Can be used to provide clock for:
Main PLL
Auxiliary PLL
CPU-Timer 2 External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1 pin. AUXCLKIN Can be used to provide clock for:
Auxiliary PLL
CPU-Timer 2 Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin should be used to provide the input clock. (1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK). F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

52 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

CPU2.SYSCLK CPU1.SYSCLK LOSPCP To GS RAMs, GPIOs, NMIWDs, and IPC To ePWMs To SCIs, SPIs, and McBSPs To USB bit clock To watchdog timers One per SYSCLK peripheral One per LSPCLK peripheral INTOSC1 INTOSC2 X1 (XTAL) AUXCLKIN To CANs One per CAN module To ePIEs, LS RAMs, CLA message RAMs, and DCSMs To local memories To local memories To peripherals One per ePWM EPWMCLK EPWMCLKDIV To HRPWM Registers HRPWM PLLSYSCLK AUXPLLCLK CPU2.CPUCLK CPU1.CPUCLK CPU1.SYSCLK CPU2.SYSCLK PERx.LSPCLK HRPWMCLK CAN Bit Clock SYSCLK Divider SYSCLKDIVSELSYSPLLCTL1CLKSRCCTL1 CPU1.PCLKCRx CPUSELx CPU2.PCLKCRx CPU1.PCLKCRx CPUSELx CPU2.PCLKCRx PERx.SYSCLK CPU1.PCLKCRx CPUSELx CPU2.PCLKCRx CPU1.PCLKCRx CPUSELx CLKSRCCTL2 AUXCLKDIVSELAUXPLLCTL1 AUXCLK Divider CLKSRCCTL2 Figure 6-8. Clocking System www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: F28377D-SEP

6.8.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.

6.8.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times

Resistance (ESR) Requirements table shows the crystal equivalent series resistance requirements. Section times for the Main PLL and the USB PLL. MIN MAX UNIT f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz f(X1) Frequency, X1, from external oscillator 2 25 MHz f(AUXI) Frequency, AUXCLKIN, from external oscillator 2 60 MHz over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V MIN MAX UNIT tf(X1) Fall time, X1 6 ns tr(X1) Rise time, X1 6 ns tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55% tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55% MIN MAX UNIT tf(AUXI) Fall time, AUXCLKIN 6 ns tr(AUXI) Rise time, AUXCLKIN 6 ns tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55% tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55% F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

54 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

t(PLL) Lock time, Main PLL (X1, from external oscillator) 50 µs + 2500 * tc(OSCCLK) (1) µs t(USB) Lock time, USB PLL (AUXCLKIN, from external oscillator) 50 µs + 2500 * tc(OSCCLK) (1) µs (1) The PLL lock time here defines the typical time of execution for the PLL workaround as defined in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . Cycle count includes code execution of the PLL initialization routine, which could vary depending on compiler optimizations and flash wait states. TI recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock(). For the auxiliary PLL, see InitAuxPll() or SysCtl_setAuxClock().

6.8.3.2.2 Internal Clock Frequencies

f(SYSCLK) Frequency, device (system) clock 2 200(2) MHz tc(SYSCLK) Period, device (system) clock 5(2) 500 ns f(PLLRAWCLK) Frequency, system PLL output (before SYSCLK divider) 120 400 MHz f(AUXPLLRAWCLK) Frequency, auxiliary PLL output (before AUXCLK divider) 120 400 MHz f(AUXPLL) Frequency, AUXPLLCLK 2 60 60 MHz f(PLL) Frequency, PLLSYSCLK 2 200(2) MHz f(LSP) Frequency, LSPCLK 2 200(2) MHz tc(LSPCLK) Period, LSPCLK 5(2) 500 ns f(OSCCLK) Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or X1) See respective clock MHz f(EPWM) Frequency, EPWMCLK(1) 100 MHz f(HRPWM) Frequency, HRPWMCLK 60 100 MHz (1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK. (2) Using an external clock source. If INTOSC1 or INTOSC2 is used as the clock source, then the maximum frequency is 194 MHz and the minimum period is 5.15 ns.

6.8.3.2.3 Output Clock Frequency and Switching Characteristics

characteristics of the output clock, XCLKOUT. MIN MAX UNIT f(XCO) Frequency, XCLKOUT 50 MHz over recommended operating conditions (unless otherwise noted) PARAMETER(1) (2) MIN MAX UNIT tf(XCO) Fall time, XCLKOUT 5 ns tr(XCO) Rise time, XCLKOUT 5 ns tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns (1) A load of 40 pF is assumed for these parameters. (2) H = 0.5tc(XCO) www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: F28377D-SEP

6.8.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 6-9 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as XTAL) and AUXCLKIN. X1 X2 CRYST AL X1 X2 X1 X2 3.3V OUTVDD GND CLK R D C L2 C L1 RESONATOR 3.3V OSCILLATOR NC vssosc GPIO133/AUXCLKIN 3.3V OUTVDD GND CLK 3.3V OSCILLATOR vssosc vssosc Figure 6-9. Connecting Input Clocks to a F28377D-SEP Device

6.8.3.4 XTAL Oscillator

6.8.3.4.1 Introduction

The crystal oscillator in this device is an embedded electrical oscillator that, when paired with a compatible quartz crystal (or a ceramic resonator), can generate the system clock required by the device.

6.8.3.4.2 Overview

The following sections describe the components of the electrical oscillator and crystal. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

56 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

The electrical oscillator in this device is a Pierce oscillator. It is a positive feedback inverter circuit that requires a tuning circuit in order to oscillate. When this oscillator is paired with a compatible crystal, a tank circuit is formed. This tank circuit oscillates at the fundamental frequency of the crystal. On this device, the oscillator is designed to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure 6-10 illustrates the components of the electrical oscillator and the tank circuit. MCU GPIO XCLKOUT Circuit CL1 XTAL Oscillator Internal External Internal External CL2 Rd To Rest of Chip Crystal Rbias Pierce Inverter VSSOSC XCLKOUT Figure 6-10. Electrical Oscillator Block Diagram The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode. In the crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2. There is an internal bias resistor for the feedback loop so an external one should not be used. Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias point of operation and possibly leading to clipped waveforms, out-of-specification duty cycle, and reduction in the effective negative resistance. In this mode of operation, the resultant clock on X1 is passed to the rest of the chip. The clock on X1 needs to meet the VIH and VIL of the comparator. See the XTAL Oscillator Characteristics table for the VIH and VIL requirements of the comparator. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: F28377D-SEP

In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz crystal should not be used in this mode. In this mode of operation, the clock on X1 is passed to the rest of the chip. See the X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input requirements of the buffer. A single-ended clock may also be connected to GPIO133/AUXCLKIN pin. The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for observation by configuring the CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers. See the GPIO Muxed Pins table for a list of GPIOs that XCLKOUT comes out on. Electrically, a quartz crystal can be represented by an LCR (Inductor-Capacitor-Resistor) circuit. However, unlike an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped. Components of the crystal are shown in Figure 6-11 and explained below. Cm Rm Lm C0 CL Quartz Crystal ExternalInternal Figure 6-11. Crystal Electrical Representation Cm (Motional capacitance): Denotes the elasticity of the crystal. Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but can be approximated as such depending on the values of the other crystal components. Lm (Motional inductance): Denotes the vibrating mass of the crystal. C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package capacitance. CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external to the crystal. The frequency ppm specified in the crystal data sheet is usually tied to the CL parameter. Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins, while some crystal manufacturers specify CL as the capacitance on just one of the crystal pins. Check with the crystal manufacturer for how the CL is specified in order to use the correct values in calculations. From Figure 6-10, CL1 and CL2 are in series; so, to find the equivalent total capacitance seen by the crystal, the capacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1 = CL2. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

58 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

It is recommended that a stray PCB capacitance be added to this value. 3 pF to 5 pF are reasonable estimates, but the actual value will depend on the PCB in question. Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has to satisfy both the electrical oscillator and the crystal. The effect of CL on the crystal is frequency-pulling. If the effective load capacitance is lower than the target, the crystal frequency will increase and vice versa. However, the effect of frequency-pulling is usually very minimal and typically results in less than 10-ppm variation from the nominal frequency.

6.8.3.4.3 Functional Operation

Effective Series Resistance is the resistive load the crystal presents to the electrical oscillator at resonance. The higher the ESR, the lower the Q, and less likely the crystal will start up or maintain oscillation. The relationship between ESR and the crystal components is indicated below. E SR = Rm * 1 + C 0 CL (1) Note that ESR is not the same as motional resistance of the crystal, but can be approximated as such if the effective load capacitance is much greater than the shunt capacitance. Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount of energy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. Rneg depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of the circuit. The generally accepted practice is to have Rneg > 3x ESR to 5x ESR to ensure the crystal starts up under all conditions. Note that it takes slightly more energy to start up the crystal than it does to sustain oscillation; therefore, if it can be ensured that the negative resistance requirement is met at start-up, then oscillation sustenance will not be an issue. Figure 6-12 and Figure 6-13 show the variation between negative resistance and the crystal components for this device. As can be seen from the graphs, the crystal shunt capacitance (C0) and effective load capacitance (CL) greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs; so, refer to Table 6-3 for minimum and maximum values for design considerations. Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned in the Rneg – Negative Resistance section, for reliable start-up across all conditions, it is recommended that the Rneg > 3x ESR to 5x ESR of the crystal. Crystal ESR and the dampening resistor (Rd) greatly affect the start-up time. The higher the two values, the longer the crystal takes to start up. Longer start-up times are usually a sign that the crystal and components are not a correct match. Refer to the Crystal Oscillator Specifications section for the typical start-up times. Note that the numbers specified here are typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question and the external components. Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The maximum drive level specified in the crystal manufacturer’s data sheet is usually the maximum the crystal can dissipate without damage or significant reduction in operating life. On the other hand, the drive level specified by the electrical oscillator is the maximum power it can provide. The actual power provided by the electrical oscillator is not necessarily the maximum power and depends on the crystal and board components. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: F28377D-SEP

For cases where the actual drive level from the electrical oscillator exceeds the maximum drive level specification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce the power dissipated by the crystal. Note that Rd reduces the circuit gain; and therefore, the actual value to use should be evaluated to make sure all other conditions for start-up and sustained oscillation are met.

6.8.3.4.4 How to Choose a Crystal

Using Crystal Oscillator Specifications as a reference: 1. Pick a crystal frequency (for example, 20 MHz). 2. Check that the ESR of the crystal <=50 Ω per specifications for 20 MHz. 3. Check that the load capacitance requirement of the crystal manufacturer is within 6 pF and 12 pF per specifications for 20 MHz.

As mentioned, CL1 and CL2 are in series; so, provided CL1 = CL2, effective load capacitance CL = [CL1]/2.
Adding board parasitics to this results in CL = [CL1]/2 + Cstray 4. Check that the maximum drive level of the crystal >= 1 mW. If this requirement is not met, a dampening resistor Rd can be used. Refer to DL – Drive Level on other points to consider when using Rd.

6.8.3.4.5 Testing

It is recommended that the user have the crystal manufacturer completely characterize the crystal with their board to ensure the crystal always starts up and maintains oscillation. Below is a brief overview of some measurements that can be performed: Due to how sensitive the crystal circuit is to capacitance, it is recommended that scope probes not be connected to X1 and X2. If scope probes must be used to monitor X1/X2, an active probe with less than 1-pF input capacitance should be used. Frequency 1. Bring out the XTAL on XCLKOUT. 2. Measure this frequency as the crystal frequency. Negative Resistance 1. Bring out the XTAL on XCLKOUT. 2. Place a potentiometer in series with the crystal between the load capacitors. 3. Increase the resistance of the potentiometer until the clock on XCLKOUT stops. 4. This resistance plus the crystal’s actual ESR is the negative resistance of the electrical oscillator. Start-Up Time 1. Turn off the XTAL. 2. Bring out the XTAL on XCLKOUT. 3. Turn on the XTAL and measure how long it takes the clock on XCLKOUT to stay within 45% and 55% duty cycle.

6.8.3.4.6 Common Problems and Debug Tips

Go through the How to Choose a Crystal section and make sure there are no violations. Crystal Takes a Long Time to Start Up
If a dampening resistor Rd is installed, it is too high.
If no dampening resistor is installed, either the crystal ESR is too high or the overall circuit gain is too low due to high load capacitance. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

60 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.3.4.7 Crystal Oscillator Specifications

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Start-up time(1) f = 10 MHz ESR MAX = 110 Ω CL1 = CL2 = 24 pF C0 = 7 pF 4 ms f = 20 MHz ESR MAX = 50 Ω CL1 = CL2 = 24 pF C0 = 7 pF 2 ms Crystal drive level (DL) 1 mW (1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the application with the chosen crystal. For the Crystal Equivalent Series Resistance (ESR) Requirements table: 1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF. 2. ESR = Negative Resistance/3 Table 6-3. Crystal Equivalent Series Resistance (ESR) Requirements CRYSTAL FREQUENCY (MHz) MAXIMUM ESR (Ω) (CL1 = CL2 = 12 pF) MAXIMUM ESR (Ω) (CL1 = CL2 = 24 pF) 10 55 110 12 50 95 14 50 90 16 45 75 18 45 65 20 45 50 Effective CL (pF) Rneg (Ohms) Negative Resistance vs. 10MHz Crystal 2 4 6 8 10 12 14 16 500 1000 1500 2000 2500 3000 C0 (pF) Figure 6-12. Negative Resistance Variation at 10 MHz www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: F28377D-SEP

Effective CL (pF) Rneg (Ohms) Negative Resistance vs. 20MHz Crystal 2 4 6 8 10 12 14 16 200 400 600 800 1000 1200 1400 1600 C0 (pF) Figure 6-13. Negative Resistance Variation at 20 MHz F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

62 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.3.5 Internal Oscillators

To reduce production board costs and application development time, all F2837xD devices contain two independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the backup clock source. INTOSC1 can also be manually configured as the system reference clock (OSCCLK). Section 6.8.3.5.1 provides the electrical characteristics of the internal oscillators to determine if this module meets the clocking requirements of the application. Note This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to frequencies above 194 MHz.

6.8.3.5.1 Internal Oscillator Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(INTOSC) Frequency, INTOSC1 and INTOSC2 9.7 10.0 10.3 MHz f(INTOSC-STABILITY) Frequency stability at room temperature 30°C, Nominal VDD ±0.1% Frequency stability over VDD 30°C ±0.2% Frequency stability –3.0% 3.0% f(INTOSC-ST) Start-up and settling time 20 µs www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: F28377D-SEP

6.8.4 Flash Parameters

The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when migrating from the previous generation of MCUs. This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM), which cannot be erased after it is programmed. Table 6-4 shows the minimum required flash wait states at different frequencies. Section 6.8.4.1 shows the flash parameters. Table 6-4. Flash Wait States CPUCLK (MHz) MINIMUM WAIT STATES (1) EXTERNAL OSCILLATOR OR CRYSTAL INTOSC1 OR INTOSC2 150 < CPUCLK ≤ 200 145 < CPUCLK ≤ 194 3 100 < CPUCLK ≤ 150 97 < CPUCLK ≤ 145 2 50 < CPUCLK ≤ 100 48 < CPUCLK ≤ 97 1 CPUCLK ≤ 50 CPUCLK ≤ 48 0 (1) Minimum required FRDCNTL[RWAIT].

6.8.4.1 Flash Parameters

PARAMETER MIN TYP MAX UNIT Program Time(1) 128 data bits + 16 ECC bits 40 300 µs 8KW sector 90 180 ms 32KW sector 360 720 ms Erase Time(2) at < 25 cycles 8KW or 32KW sector 30 55 ms Erase Time(2) at 1000 cycles 8KW or 32KW sector 40 350 Erase Time(2) at 2000 cycles 8KW or 32KW sector 50 600 ms Erase Time(2) at 20k cycles 8KW or 32KW sector 110 4000 Nwec Write/erase cycles per sector 20000 cycles Nwec Write/Erase Cycles for entire Flash (combined all sectors)(3) 100000 cycles tretention Data retention duration at TJ = 85°C 20 years (1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include the time to transfer the following into RAM:

Code that uses flash API to program the flash
Flash API itself
Flash data to be programmed In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used. Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does. Erase time includes Erase verify by the CPU and does not involve any data transfer. (2) Erase time includes Erase verify by the CPU. (3) Each sector, by itself, can only be erased/programmed 20,000 times. If you choose to use a sector (or multiple sectors) like an EEPROM, you can erase/program only those sectors (still limited to 20,000 cycles) without erasing/programming the entire Flash memory. Therefore, the total number of W/E cycles from a device perspective can exceed 20,000 cycles. However, even this number should not exceed 100,000 cycles. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

64 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum Programming Word Size" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata .

6.8.5 RAM Specifications

Table 6-5. CPU1 RAM Parameters RAM TYPE SIZE FETCH TIME (Cycles) READ TIME (Cycles) STORE TIME (Cycles) BUS WIDTH NUMBER OF BUSSES AVAILABLE(1) NUMBER OF WAIT STATES BURST ACCESS GS RAM 128KB 2 2 1 16/32 bits 4 0 No LS RAM 24KB 2 2 1 16/32 bits 2 0 No M0 2KB 2 2 1 16/32 bits 1 0 No M1 2KB 2 2 1 16/32 bits 1 0 No CLA1 to CPU Message RAM 256B 2 2 1 16/32 bits 2 0 No CPU to CLA1 Message RAM 256B 2 2 1 16/32 bits 2 0 No CPU1 to CPU2 Message RAM 2KB 2 2 1 16/32 bits 4 0 No CPU2 to CPU1 Message RAM 2KB 2 2 1 16/32 bits 4 0 No (1) “Number of Buses Available” indicates how many masters (CLA, DMA, CPU) have access to this memory. Table 6-6. CPU2 RAM Parameters RAM TYPE SIZE FETCH TIME (Cycles) READ TIME (Cycles) STORE TIME (Cycles) BUS WIDTH NUMBER OF BUSSES AVAILABLE(1) NUMBER OF WAIT STATES BURST ACCESS GS RAM 128KB 2 2 1 16/32 bits 4 0 No LS RAM 24KB 2 2 1 16/32 bits 2 0 No M0 2KB 2 2 1 16/32 bits 1 0 No M1 2KB 2 2 1 16/32 bits 1 0 No CLA1 to CPU Message RAM 256B 2 2 1 16/32 bits 2 0 No CPU to CLA1 Message RAM 256B 2 2 1 16/32 bits 2 0 No CPU1 to CPU2 Message RAM 2KB 2 2 1 16/32 bits 4 0 No CPU2 to CPU1 Message RAM 2KB 2 2 1 16/32 bits 4 0 No (1) “Number of Buses Available” indicates how many masters (CLA, DMA, CPU) have access to this memory. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: F28377D-SEP

6.8.6 ROM Specifications

Table 6-7. CPU1 ROM Parameters ROM TYPE SIZE FETCH TIME (Cycles) READ TIME (Cycles) STORE TIME (Cycles) BUS WIDTH NUMBER OF BUSSES AVAILABLE(1) NUMBER OF WAIT STATES BURST ACCESS Boot ROM 64KB 2 2 1 16/32 bits 1 1 No Secure ROM 64KB 2 2 1 16/32 bits 1 1 No CLA Data ROM 8KB 2 2 1 16/32 bits 2 0 No (1) “Number of Buses Available” indicates how many masters (CLA, DMA, CPU) have access to this memory. Table 6-8. CPU2 ROM Parameters ROM TYPE SIZE FETCH TIME (Cycles) READ TIME (Cycles) STORE TIME (Cycles) BUS WIDTH NUMBER OF BUSSES AVAILABLE(1) NUMBER OF WAIT STATES BURST ACCESS Boot ROM 64KB 2 2 1 16/32 bits 1 1 No Secure ROM 64KB 2 2 1 16/32 bits 1 1 No CLA Data ROM 8KB 2 2 1 16/32 bits 2 0 No (1) “Number of Buses Available” indicates how many masters (CLA, DMA, CPU) have access to this memory. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

66 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.7 Emulation/JTAG

The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be pulled down through a 2.2-k Ω pulldown resistor on the board. This MCU does not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 k Ω to 4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used. See Figure 6-14 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 6-15 shows how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not used and should be grounded. The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board 3.3-V supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). Header terminal RESET is an open-drain output from the JTAG debug probe header that enables board components to be reset through JTAG debug probe commands (available only through the 20-pin header). Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise, each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω resistors should be placed in series on each JTAG signal. For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints for C28x in CCS. For more information about JTAG emulation, see the XDS Target Connection Guide. TMS TDI TDO PD RTCK TCK EMU0 TRST TDIS GND KEY GND GND EMU1 GND TCK TDO TDI TMS TRST GND 1 2 3 4 5 6 7 8 9 10 11 12 1413 3.3 V 3.3 V 100 /c87 2.2 k/c87 4.7 k/c874.7 k/c87 3.3 V Distance between the header and the target should be less than 6 inches (15.24 cm). MCU Figure 6-14. Connecting to the 14-Pin JTAG Header www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: F28377D-SEP

A low pulse from the JTAG debug probe can be tied with other reset sources to reset the board. 1 2 3 4 5 6 7 8 9 10 11 12 1413 1615 1817 2019 3.3 V3.3 V 3.3V 100 /c87 2.2 k/c87 4.7 k/c874.7 k/c87 GND GND MCU Distance between the header and the target should be less than 6 inches (15.24 cm). Figure 6-15. Connecting to the 20-Pin JTAG Header F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

68 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.7.1 JTAG Electrical Data and Timing

Figure 6-16 shows the JTAG timing.

6.8.7.1.1 JTAG Timing Requirements

NO. MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 66.66 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.66 ns 1b tw(TCKL) Pulse duration, TCK low (40% of tc) 26.66 ns tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 13 ns tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 13 ns th(TCKH-TDI) Input hold time, TDI valid from TCK high 7 ns th(TCKH-TMS) Input hold time, TMS valid from TCK high 7 ns

6.8.7.1.2 JTAG Switching Characteristics

over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN MAX UNIT 2 td(TCKL-TDO) Delay time, TCK low to TDO valid 6 25 ns TCK TDO TDI/TMS 1a 1b Figure 6-16. JTAG Timing www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: F28377D-SEP

6.8.8 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches. The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s), ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

6.8.8.1 GPIO - Output Timing

purpose output timing.

6.8.8.1.1 General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tr(GPO) Rise time, GPIO switching low to high All GPIOs 8(1) ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 8(1) ns tfGPO Toggling frequency, GPO pins 25 MHz (1) Rise time and fall time vary with load. These values assume a 40-pF load. GPIO tf(GPO) tr(GPO) Figure 6-17. General-Purpose Output Timing F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

70 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.8.2 GPIO - Input Timing

6.8.8.2.1 General-Purpose Input Timing Requirements

tw(SP) Sampling period QUALPRD = 0 1tc(SYSCLK) cycles QUALPRD ≠ 0 2tc(SYSCLK) * QUALPRD cycles tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles tw(GPI) (2) Pulse duration, GPIO low/high Synchronous mode 2tc(SYSCLK) cycles With input qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles (1) "n" represents the number of qualification samples as defined by GPxQSELn register. (2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal. GPIO Signal Sampling Window 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 SYSCLK (A) GPxQSELn = 1,0 (6 samples) (D) Output From Qualifier QUALPRD = 1 (SYSCLK/2) tw(IQSW) tw(SP) (SYSCLK cycle * 2 * QUALPRD) * 5 (C) Sampling Period determined by GPxCTRL[QUALPRD] (B) A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled). B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins. C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition. Figure 6-18. Sampling Mode www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: F28377D-SEP

6.8.8.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLK. Sampling frequency = SYSCLK/(2 QUALPRD), if QUALPRD 0/c180 /c185 (2) Sampling frequency = SYSCLK, if QUALPRD 0/c61 (3) Sampling period = SYSCLK cycle 2 QUALPRD, if QUALPRD 0/c180 /c185/c180 (4) In Equation 2, Equation 3, and Equation 4, SYSCLK cycle indicates the time period of SYSCLK. Sampling period = SYSCLK cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register. Case 1: Qualification using 3 samples Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0 Case 2: Qualification using 6 samples Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0 Figure 6-19 shows the general-purpose input timing. GPIOxn SYSCLK tw(GPI) Figure 6-19. General-Purpose Input Timing F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

72 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.9 Interrupts

Figure 6-20 provides a high-level view of the interrupt architecture. As shown in Figure 6-20, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins. In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group. INPUTXBAR4 CPU1.WDINT CPU2.WDINT CPU1.LPMINT CPU2.LPMINT CPU1.WAKEINT CPU2.WAKEINT CPU1.TINT0 CPU1. ePIE INT13 INT14 NMI CPU1 INT1 to INT12 NMI CPU2 INT1 to INT12 INPUTXBAR13 INPUTXBAR5 INPUTXBAR6 INPUTXBAR14 GPIO0 GPIO1 ... ... GPIOx CPU1.TIMER0 CPU2.TINT0CPU2.TIMER0 CPU2 ePIE CPU1.TINT1CPU1.TIMER1 CPU1.TINT2CPU1.TIMER2 CPU1.TINT2 INT13 INT14 CPU2.TINT1CPU2.TIMER1 CPU2.TINT2CPU2.TIMER2 LPM Logic CPU2.WD Peripherals IPC

4 Interrupts

CPU1.XINT1 Control CPU1.XINT5 Control CPU1.XINT3 Control CPU1.XINT4 Control CPU1.XINT2 Control CPU2.XINT1 Control CPU2.XINT5 Control CPU2.XINT3 Control CPU2.XINT4 Control CPU2.XINT2 Control Input X-BAR LPM Logic CPU1.WD CPU1.NMIWD CPU2.NMIWD Figure 6-20. External and ePIE Interrupt Sources www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: F28377D-SEP

6.8.9.1 External Interrupt (XINT) Electrical Data and Timing

switching characteristics. Figure 6-21 shows the external interrupt timing.

6.8.9.1.1 External Interrupt Timing Requirements

MIN MAX UNIT(1) tw(INT) Pulse duration, INT input low/high Synchronous 2tc(SYSCLK) cycles With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles

6.8.9.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1) PARAMETER MIN MAX UNIT td(INT) Delay time, INT low/high to interrupt-vector fetch(2) tw(IQSW) + 14tc(SYSCLK) tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles (2) This assumes that the ISR is in a single-cycle memory. Interrupt Vector XINT1, XINT2, XINT3, XINT4, XINT5 Address bus (internal) tw(INT) td(INT) Figure 6-21. External Interrupt Timing F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

74 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.10 Low-Power Modes

This device has three clock-gating low-power modes and a special power-gating mode. Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low Power Modes section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual .

6.8.10.1 Clock-Gating Low-Power Modes

IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 6-9 describes the effect on the system when any of the clock-gating low-power modes are entered. Table 6-9. Effect of Clock-Gating Low-Power Modes on the Device MODULES/ CLOCK DOMAIN CPU1 IDLE CPU1 STANDBY CPU2 IDLE CPU2 STANDBY HALT CPU1.CLKIN Active Gated N/A N/A Gated CPU1.SYSCLK Active Gated N/A N/A Gated CPU1.CPUCLK Gated Gated N/A N/A Gated CPU2.CLKIN N/A N/A Active Gated Gated CPU2.SYSCLK N/A N/A Active Gated Gated CPU2.CPUCLK N/A N/A Gated Gated Gated Clock to modules Connected to PERx.SYSCLK Active Gated if CPUSEL.PERx = CPU1 Active Gated if CPUSEL.PERx = CPU2 Gated CPU1.WDCLK Active Active N/A N/A Gated if CLKSRCCTL1.WDHALTI = 0 CPU2.WDCLK N/A N/A Active Active Gated AUXPLLCLK Active Active Active Active Gated PLL Powered Powered Powered Powered Software must power down PLL before entering HALT INTOSC1 Powered Powered Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0 INTOSC2 Powered Powered Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0 Flash Powered Powered Powered Powered Software-Controlled X1/X2 Crystal Oscillator Powered Powered Powered Powered Powered-Down

6.8.10.2 Power-Gating Low-Power Modes

HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the supply voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote wakeup capability, and can be used to save power during long periods of inactivity. Table 6-10 describes the effects on the system when the HIBERNATE mode is entered. Table 6-10. Effect of Power-Gating Low-Power Mode on the Device MODULES/POWER DOMAINS HIBERNATE M0 and M1 memories ● Remain on with memory retention if LPMCR.M0M1MODE = 0x00

Are off when LPMCR.M0M1MODE = 0x01 CPU1, CPU2, digital peripherals Powered down Dx, LSx, GSx memories Power down, memory contents are lost I/Os On with output state preserved Oscillators, PLL, analog peripherals, Flash Enters Low-Power Mode www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: F28377D-SEP

6.8.10.3 Low-Power Mode Wakeup Timing

characteristics, and Figure 6-22 shows the timing diagram for IDLE mode.

6.8.10.3.1 IDLE Mode Timing Requirements

MIN MAX UNIT(1) tw(WAKE) Pulse duration, external wake-up signal Without input qualifier 2tc(SYSCLK) cycles With input qualifier 2tc(SYSCLK) + tw(IQSW)

6.8.10.3.2 IDLE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN MAX UNIT td(WAKE-IDLE) Delay time, external wake signal to program execution resume (2) cycles

Wakeup from Flash – Flash module in active state Without input qualifier 40tc(SYSCLK) With input qualifier 40tc(SYSCLK) + tw(WAKE)
Wakeup from Flash – Flash module in sleep state Without input qualifier 6700tc(SYSCLK) (3) With input qualifier 6700tc(SYSCLK) (3) + tw(WAKE)
Wakeup from RAM Without input qualifier 25tc(SYSCLK) With input qualifier 25tc(SYSCLK) + tw(WAKE) (2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up signal) involves additional latency. (3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860. WAKE (A) XCLKOUT Address/Data (internal) tw(WAKE) td(WAKE-IDLE) A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. Figure 6-22. IDLE Entry and Exit Timing Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

76 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

characteristics, and Figure 6-23 shows the timing diagram for STANDBY mode.

6.8.10.3.3 STANDBY Mode Timing Requirements

tw(WAKE-INT) Pulse duration, external wake-up signal QUALSTDBY = 0 | 2tc(OSCCLK) 3tc(OSCCLK) cyclesQUALSTDBY > 0 | (2 + QUALSTDBY)tc(OSCCLK) (1) (2 + QUALSTDBY) * tc(OSCCLK) (1) QUALSTDBY is a 6-bit field in the LPMCR register.

6.8.10.3.4 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 16tc(INTOSC1) cycles td(WAKE-STBY) Delay time, external wake signal to program execution resume(1) cycles

Wakeup from flash – Flash module in active state 175tc(SYSCLK) + tw(WAKE-INT)
Wakeup from flash – Flash module in sleep state 6700tc(SYSCLK) (2) + tw(WAKE- INT)
Wakeup from RAM 3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) (1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up signal) involves additional latency. (2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: F28377D-SEP

(A) Device Status STANDBY Normal ExecutionSTANDBY (G)(B) (C) (D)(E) (F) td(IDLE-XCOS) tw(WAKE-INT) td(WAKE-STBY) A. IDLE instruction is executed to put the device into STANDBY mode. B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly. C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. D. The external wake-up signal is driven active. E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses. F. After a latency period, the STANDBY mode is exited. G. Normal execution resumes. The device will respond to the interrupt (if enabled). Figure 6-23. STANDBY Entry and Exit Timing Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

78 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

characteristics, and Figure 6-24 shows the timing diagram for HALT mode.

6.8.10.3.5 HALT Mode Timing Requirements

tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles (1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/layout external to the device. See the Crystal Oscillator Electrical Characteristics section for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK, see Section 6.8.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is powered externally to the device.

6.8.10.3.6 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 16tc(INTOSC1) cycles td(WAKE-HALT) Delay time, external wake signal end to CPU1 program execution resume cycles

Wakeup from flash – Flash module in active state 75tc(OSCCLK)
Wakeup from flash – Flash module in sleep state 17500tc(OSCCLK) (1)
Wakeup from RAM 75tc(OSCCLK) (1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: F28377D-SEP

(A) (C) (D)(E) (F) (B) (G) td(IDLE-XCOS) tw(WAKE-GPIO) td(WAKE-HALT) Oscillator Start-up Time A. IDLE instruction is executed to put the device into HALT mode. B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly. C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode. E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses. F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now exited. G. Normal operation resumes. H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock. Figure 6-24. HALT Entry and Exit Timing Diagram Note CPU2 should enter IDLE mode before CPU1 puts the device into HALT mode. CPU1 should verify that CPU2 has entered IDLE mode using the LPMSTAT register before calling the IDLE instruction to enter HALT. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

80 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

characteristics, and Figure 6-25 shows the timing diagram for HIBERNATE mode.

6.8.10.3.7 HIBERNATE Mode Timing Requirements

tw(HIBWAKE) Pulse duration, HIBWAKE signal 40 µs tw(WAKEXRS) Pulse duration, XRS wake-up signal 40 µs

6.8.10.3.8 HIBERNATE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 30tc(SYSCLK) cycles td(WAKE-HIB) Delay time, external wake signal to lORestore function start 1.5 ms www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: F28377D-SEP

Enabled Bypassed & Powered -Down On Powered Down Powering up On HIBERNATE CPU1 Boot ROMDevice Status INTOSC1,INTOSC2, X1/X2 GPIOHIBWAKEn , XRSn PLLs I/O Isolation IoRestore() or Application Specific OperationCPU1 HIB config (A) (B) (C) (D) tw(HIBWAKEn ), tw(XRSn) (F) (G)(H) (I)(J) Application SpecificOperation (E) td(IDLE-XCOS) Td(WAKE-HIB) A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if using I/O Isolation. Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank, USB-PHY, CMPSS, DAC, and ADC using their register configurations. The application should also power down the PLL and peripheral clocks before entering HIBERNATE. In dual-core applications, CPU1 should confirm that CPU2 has entered IDLE/STANDBY using the LPMSTAT register. B. IDLE instruction is executed to put the device into HIBERNATE mode. C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained. CPU1 and CPU2 are powered down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash are in their software-controlled Low-Power modes. Dx, LSx, and GSx memories are also powered down, and their memory contents lost. D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2, and X1/X2 OSC. The wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of these clock sources. E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of the remainder of the device. F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the CPU1.REC.HIBRESETn bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined IoRestore function if it has been configured. G. At this point, the device is out of HIBERNATE mode, and the application may continue. H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O isolation, reconfigure the PLL, restore peripheral configurations, or branch to application code. This is up to the application requirements. I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will disable I/O isolation automatically if it was not taken care of inside of IoRestore. CPU2 will be brought out of reset at this point as well. J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information. Figure 6-25. HIBERNATE Entry and Exit Timing Diagram Note 1. If the IORESTOREADDR is configured as the default value, the BootROM will continue its execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information. 2. The user may choose to disable I/O Isolation at any point in the IoRestore function. Regardless if the user has disabled Isolation in the IoRestore function or if IoRestore is not defined, the BootROM will automatically disable isolation before booting as determined by the HIBBOOTMODE register. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

82 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

For applications using both CPU1 and CPU2, TI recommends that the application puts CPU2 in either IDLE or STANDBY before entering HIBERNATE mode. If any GPIOs are used and the state is to be preserved, data can be stored in M0/M1 memory of CPU1 to be reconfigured upon wakeup. This should be done before step A of Figure 6-25.

6.8.11 External Memory Interface (EMIF)

The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous memories (SRAM, NOR flash) or synchronous memory (SDRAM).

6.8.11.1 Asynchronous Memory Support

The EMIF supports asynchronous memories:

SRAMs
NOR Flash memories There is an external wait input that allows slower asynchronous memories to extend the memory access. The EMIF module supports up to three chip selects ( EMIF_CS[4:2]). Each chip select has the following individually programmable attributes:
Data bus width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turnaround time
Extended wait option with programmable time-out
Select strobe option

6.8.11.2 Synchronous DRAM Support

The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit data bus. The EMIF has a single SDRAM chip select ( EMIF_CS[0]). The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of the program address bus and can only be accessed through the data bus, which places a restriction on the C compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the user is advised to copy data (using the DMA) from external memory to RAM before working on it. See the examples in C2000Ware (C2000Ware for C2000 MCUs ) and the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . SDRAM configurations supported are:

One-bank, two-bank, and four-bank SDRAM devices
Devices with 8-, 9-, 10-, and 11-column addresses
CAS latency of two or three clock cycles
16-bit/32-bit data bus width
3.3-V LVCMOS interface Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The EMIF module does not support mobile SDRAM devices. On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to an external SDRAM device will have CAS latency. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: F28377D-SEP

6.8.11.3 EMIF Electrical Data and Timing

6.8.11.3.1 Asynchronous RAM

the EMIF asynchronous memory switching characteristics. Figure 6-26 through Figure 6-29 show the EMIF asynchronous memory timing diagrams. NO.(1) MIN MAX UNIT Reads and Writes E EMIF clock period tc(SYSCLK) ns 2 tw(EM_WAIT) Pulse duration, EMxWAIT assertion and deassertion 2E ns Reads 12 tsu(EMDV-EMOEH) Setup time, EMxD[y:0] valid before EMxOE high 15 ns 13 th(EMOEH-EMDIV) Hold time, EMxD[y:0] valid after EMxOE high 0 ns 14 tsu(EMOEL-EMWAIT) Setup Time, EMxWAIT asserted before end of Strobe Phase(2) 4E+20 ns Writes 28 tsu(EMWEL-EMWAIT) Setup Time, EMxWAIT asserted before end of Strobe Phase(2) 4E+20 ns (1) E = EMxCLK period in ns. (2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended wait states. Figure 6-27 and Figure 6-29 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. NO.(1) (2) (3) PARAMETER MIN MAX UNIT Reads and Writes 1 td(TURNAROUND) Turn around time (TA)*E–3 (TA)*E+2 ns Reads 3 tc(EMRCYCLE) EMIF read cycle time (EW = 0) (RS+RST+RH)*E–3 (RS+RST+RH)*E+2 ns EMIF read cycle time (EW = 1)(4) (RS+RST+RH+ (MEWC*16))*E–3 (RS+RST+RH+ (MEWC*16))*E+2 ns 4 tsu(EMCEL-EMOEL) Output setup time, EMxCS[y:2] low to EMxOE low (SS = 0) (RS)*E–3 (RS)*E+2 ns Output setup time, EMxCS[y:2] low to EMxOE low (SS = 1) –3 2 ns 5 th(EMOEH-EMCEH) Output hold time, EMxOE high to EMxCS[y:2] high (SS = 0) (RH)*E–3 (RH)*E ns Output hold time, EMxOE high to EMxCS[y:2] high (SS = 1) –3 0 ns 6 tsu(EMBAV-EMOEL) Output setup time, EMxBA[y:0] valid to EMxOE low (RS)*E–3 (RS)*E+2 ns 7 th(EMOEH-EMBAIV) Output hold time, EMxOE high to EMxBA[y:0] invalid (RH)*E–3 (RH)*E ns 8 tsu(EMAV-EMOEL) Output setup time, EMxA[y:0] valid to EMxOE low (RS)*E–3 (RS)*E+2 ns 9 th(EMOEH-EMAIV) Output hold time, EMxOE high to EMxA[y:0] invalid (RH)*E–3 (RH)*E ns F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

84 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

NO.(1) (2) (3) PARAMETER MIN MAX UNIT 10 tw(EMOEL) EMxOE active low width (EW = 0) (RST)*E–1 (RST)*E+1 ns EMxOE active low width (EW = 1) (4) (RST+(MEWC*16))*E–1 (RST+(MEWC*16))*E+1 ns 11 td(EMWAITH-EMOEH) Delay time from EMxWAIT deasserted to EMxOE high 4E+10 5E+15 ns 29 tsu(EMDQMV-EMOEL) Output setup time, EMxDQM[y:0] valid to EMxOE low (RS)*E–3 (RS)*E+2 ns 30 th(EMOEH-EMDQMIV) Output hold time, EMxOE high to EMxDQM[y:0] invalid (RH)*E–3 (RH)*E ns Writes 15 tc(EMWCYCLE) EMIF write cycle time (EW = 0) (WS+WST+WH)*E–3 (WS+WST+WH)*E+1 ns EMIF write cycle time (EW = 1)(4) (WS+WST+WH+ (MEWC*16))*E–3 (WS+WST+WH+ (MEWC*16))*E+1 ns 16 tsu(EMCEL-EMWEL) Output setup time, EMxCS[y:2] low to EMxWE low (SS = 0) (WS)*E–3 (WS)*E+1 ns Output setup time, EMxCS[y:2] low to EMxWE low (SS = 1) –3 1 ns 17 th(EMWEH-EMCEH) Output hold time, EMxWE high to EMxCS[y:2] high (SS = 0) (WH)*E–3 (WH)*E ns Output hold time, EMxWE high to EMxCS[y:2] high (SS = 1) –3 0 ns 18 tsu(EMDQMV-EMWEL) Output setup time, EMxDQM[y:0] valid to EMxWE low (WS)*E–3 (WS)*E+1 ns 19 th(EMWEH-EMDQMIV) Output hold time, EMxWE high to EMxDQM[y:0] invalid (WH)*E–3 (WH)*E ns 20 tsu(EMBAV-EMWEL) Output setup time, EMxBA[y:0] valid to EMxWE low (WS)*E–3 (WS)*E+1 ns 21 th(EMWEH-EMBAIV) Output hold time, EMxWE high to EMxBA[y:0] invalid (WH)*E–3 (WH)*E ns 22 tsu(EMAV-EMWEL) Output setup time, EMxA[y:0] valid to EMxWE low (WS)*E–3 (WS)*E+1 ns 23 th(EMWEH-EMAIV) Output hold time, EMxWE high to EMxA[y:0] invalid (WH)*E–3 (WH)*E ns 24 tw(EMWEL) EMxWE active low width (EW = 0) (WST)*E–1 (WST)*E+1 ns EMxWE active low width (EW = 1)(4) (WST+(MEWC*16))*E–1 (WST+(MEWC*16))*E+1 ns 25 td(EMWAITH-EMWEH) Delay time from EMxWAIT deasserted to EMxWE high 4E+10 5E+15 ns 26 tsu(EMDV-EMWEL) Output setup time, EMxD[y:0] valid to EMxWE low (WS)*E–3 (WS)*E+1 ns 27 th(EMWEH-EMDIV) Output hold time, EMxWE high to EMxD[y:0] invalid (WH)*E–3 (WH)*E ns (1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16– 1], WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information. (2) E = EMxCLK period in ns. (3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information. (4) Maximum wait time-out condition. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: F28377D-SEP

EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxOE EMxD[y:0] EMxWE EMxDQM[y:0] 3029 Figure 6-26. Asynchronous Memory Read Timing 1 1 Asserted Deasserted EMxWAIT SETUP Extended Due to EMxWAIT STROBE HOLD STROBE EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxOE EMxD[y:0] Figure 6-27. EMxWAIT Read Timing Requirements F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

86 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.8.11.3.2 Synchronous RAM

the EMIF synchronous memory switching characteristics. Figure 6-30 and Figure 6-31 show the synchronous memory timing diagrams. NO. MIN MAX UNIT 19 tsu(EMIFDV-EM_CLKH) Input setup time, read data valid on EMxD[y:0] before EMxCLK rising 2 ns 20 th(CLKH-DIV) Input hold time, read data valid on EMxD[y:0] after EMxCLK rising 1.5 ns NO. PARAMETER MIN MAX UNIT 1 tc(CLK) Cycle time, EMIF clock EMxCLK 10 ns 2 tw(CLK) Pulse width, EMIF clock EMxCLK high or low 3 ns 3 td(CLKH-CSV) Delay time, EMxCLK rising to EMxCS[y:2] valid 8 ns 4 toh(CLKH-CSIV) Output hold time, EMxCLK rising to EMxCS[y:2] invalid 1 ns 5 td(CLKH-DQMV) Delay time, EMxCLK rising to EMxDQM[y:0] valid 8 ns 6 toh(CLKH-DQMIV) Output hold time, EMxCLK rising to EMxDQM[y:0] invalid 1 ns 7 td(CLKH-AV) Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid 8 ns 8 toh(CLKH-AIV) Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid 1 ns 9 td(CLKH-DV) Delay time, EMxCLK rising to EMxD[y:0] valid 8 ns 10 toh(CLKH-DIV) Output hold time, EMxCLK rising to EMxD[y:0] invalid 1 ns 11 td(CLKH-RASV) Delay time, EMxCLK rising to EMxRAS valid 8 ns 12 toh(CLKH-RASIV) Output hold time, EMxCLK rising to EMxRAS invalid 1 ns 13 td(CLKH-CASV) Delay time, EMxCLK rising to EMxCAS valid 8 ns 14 toh(CLKH-CASIV) Output hold time, EMxCLK rising to EMxCAS invalid 1 ns 15 td(CLKH-WEV) Delay time, EMxCLK rising to EMxWE valid 8 ns 16 toh(CLKH-WEIV) Output hold time, EMxCLK rising to EMxWE invalid 1 ns 17 td(CLKH-DHZ) Delay time, EMxCLK rising to EMxD[y:0] tri-stated 8 ns 18 toh(CLKH-DLZ) Output hold time, EMxCLK rising to EMxD[y:0] driving 1 ns F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

88 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

2 EM_CLK Delay

EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxD[y:0] EMxWE EMxDQM[y:0] Figure 6-30. Basic SDRAM Read Operation www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: F28377D-SEP

EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxD[y:0] EMxWE EMxDQM[y:0] Figure 6-31. Basic SDRAM Write Operation F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

90 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9 Analog Peripherals

The analog subsystem module is described in this section. The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS. The analog subsystem has the following features:

Flexible voltage references – The ADCs are referenced to VREFHIx and VREFLOx pins.
VREFHIx pin voltage must be driven in externally.
The buffered DACs are referenced to VREFHIx and VSSA. – Alternately, these DACs can be referenced to the VDAC pin and VSSA.
The comparator DACs are referenced to VDDA and VSSA. – Alternately, these DACs can be referenced to the VDAC pin and VSSA.
Flexible pin usage – Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
Internal connection to VREFLO on all ADCs for offset self-calibration Figure 6-32 shows the Analog Subsystem Block Diagram for the 176-pin PTP package. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: F28377D-SEP

(selectable) ADC-B 16-bits or 12-bits (selectable) ADC-D 16-bits or 12-bits (selectable) DACOUTA/ADCINA0 DACOUTB/ADCINA1 CMPIN1P/ADCINA2 CMPIN1N/ADCINA3 CMPIN4N/ADCIN15 TEMP SENSOR VDAC/ADCINB0 DACOUTC/ADCINB1 CMPIN3P/ADCINB2 CMPIN3N/ADCINB3 CMPIN7P/ADCIND0 CMPIN7N/ADCIND1 CMPIN8P/ADCIND2 CMPIN8N/ADCIND3 12-bit Buffered DAC CMPIN2P/ADCINA4 CMPIN2N/ADCINA5 ADCIND4 VREFHIA VREFLOB REFHI VREFHIA DACOUTADACOUTB VREFLOD VREFLOB VREFLOB VDAC VREFLOD VREFLOD VREFLOA VREFLOA CMPIN4P/ADCIN14 CMPIN1P CMPIN3P CMPIN2P CMPIN4P Comparator Subsystem 1 VDDA or VDAC CMPIN1N CTRIPOUT1H Digital Filter CTRIP1H CTRIP1L CMPIN2N CTRIP2L CTRIP2H CMPIN3N CTRIPOUT3H CTRIP3H CTRIP3L CMPIN4N CTRIPOUT4H CTRIP4H CTRIP4L Digital Filter CTRIPOUT1L CTRIPOUT2H CTRIPOUT2L CTRIPOUT3L CTRIPOUT4L CMPIN5P CMPIN6P CTRIPOUT5H CTRIP5H CTRIP5L CMPIN6N CTRIPOUT6H CTRIP6H CTRIP6L CTRIPOUT5L CTRIPOUT6L CMPIN7P CMPIN8P CMPIN7N CTRIPOUT7H CTRIP7H CTRIP7L CMPIN8N CTRIPOUT8H CTRIP8H CTRIP8L CTRIPOUT7L CTRIPOUT8L 12-bit Buffered DAC VREFHIA VDAC 12-bit Buffered DAC VREFHIB DACOUTC VDAC REFHI DAC12 DAC12 Comparator Subsystem 2 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 Comparator Subsystem 3 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 Comparator Subsystem 4 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 Comparator Subsystem 5 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 Comparator Subsystem 6 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 Comparator Subsystem 7 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 Comparator Subsystem 8 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 REFLO VREFLOA VREFHIB REFLO VREFHID REFHI REFLO VSSA VSSA VSSA DACREFSEL DACREFSEL DACREFSEL ADC-C 16-bits or 12-bits (selectable) CMPIN6P/ADCINC2 CMPIN6N/ADCINC3 CMPIN5P/ADCINC4 VREFLOC VREFLOC VREFLOC VREFHIC REFHI REFLO Figure 6-32. Analog Subsystem Block Diagram (176-Pin PTP) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

92 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.1 Analog-to-Digital Converter (ADC)

The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of either 16 bits or 12 bits . There are multiple ADC modules which allow simultaneous sampling. The ADC wrapper is start-of-conversion (SOC) based [see the SOC Principle of Operation section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . Each ADC has the following features:

Selectable resolution of 16 bits or 12 bits
Ratiometric external reference set by VREFHI and VREFLO
Differential signal conversions (16-bit mode only)
Single-ended signal conversions (12-bit mode only)
Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
16 configurable SOCs
16 individually addressable result registers
Multiple trigger sources – Software immediate start – All ePWMs – GPIO XINT2 – CPU timers – ADCINT1 or 2
Four flexible PIE interrupts
Burst mode
Four post-processing blocks, each with: – Saturating offset calibration – Error from setpoint calculation – High, low, and zero-crossing compare, with interrupt and ePWM trip capability – Trigger-to-sample delay capture www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: F28377D-SEP

Figure 6-33 shows the ADC module block diagram. Analog to Digital Wrapper LogicAnalog to Digital Core Input Circuit Reference Voltage Levels SOC Arbitration & Control SOCx (0-15) ADCIN0 Converter ADCIN1 ADCIN2 ADCIN3 ADCIN4 ADCIN5 ADCIN6 ADCIN7 Interrupt Block (1-4) Triggers ADCIN8 ADCIN9 ADCIN10 ADCIN11 VREFLO VREFHI CHSEL ADCSOC [15:0] ADCINT1-4 ADCIN12 ADCIN13 ADCIN14 ADCIN15 TRIGSELACQPS CHSEL RESOLUTION SIGNALMODE Post Processing Block (1-4) [15:0] SIGNALMODE RESOLUTION RESULT ADCRESULT 0–15 Regs ADCPPBxRESULT Event Logic ADCEVTINT [15:0] ADCEVT TRIGGER[15:0] Trigger Timestamp SOC Delay Timestamp ADCCOUNTER ADCPPBxOFFCAL ADCPPBxOFFREF S+ - saturate S + - SOCxSTART[15:0] EOCx[15:0] CONFIG S/H Circuit VIN+ VIN- DOUT Figure 6-33. ADC Module Block Diagram

6.9.1.1 ADC Configurability

Some ADC configurations are individually controlled by the SOCs, while others are controlled by each ADC module. Table 6-11 summarizes the basic ADC options and their level of configurability. Table 6-11. ADC Options and Configuration Levels OPTIONS CONFIGURABILITY Clock By the module(1) Resolution By the module(1) Signal mode By the module Reference voltage source Not configurable (external reference only) Trigger source By the SOC(1) Converted channel By the SOC Acquisition window duration By the SOC(1) EOC location By the module Burst mode By the module(1) (1) Writing these values differently to different ADC modules could cause the ADCs to operate asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously, see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter in the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

94 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.1.1.1 Signal Mode

The ADC supports two signal modes: single-ended and differential. In single-ended mode, the input voltage to the converter is sampled through a single pin (ADCINx), referenced to VREFLO. In differential signaling mode, the input voltage to the converter is sampled through a pair of input pins, one of which is the positive input (ADCINxP) and the other is the negative input (ADCINxN). The actual input voltage is the difference between the two (ADCINxP – ADCINxN). Figure 6-34 shows the differential signaling mode. Figure 6-35 shows the single-ended signaling mode. VREFHI VREFLO (VSSA) VREFHI/2 Pin Voltages ADCINxP ADCINxN ADC ADCINxN ADCINxP VREFLO VREFHI VREFHI VREFLO (VSSA) Input Common Mode VREFHI/2 ± 50mVVin Common Mode +VREFHI -VREFHI Effective Input Voltage ADC Vin 2n - 1 Digital Output ADC Vin Figure 6-34. Differential Signaling Mode www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: F28377D-SEP

(VSSA) VREFHI/2 Pin Voltage ADCINx ADC ADCINx VREFLO VREFHI 2n - 1 Digital Output ADC Vin Figure 6-35. Single-ended Signaling Mode F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

96 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.1.2 ADC Electrical Data and Timing

6.9.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted) MIN TYP MAX UNIT ADCCLK (derived from PERx.SYSCLK) 5 50 MHz Sample window duration (set by ACQPS and PERx.SYSCLK)(1) 320 ns VREFHI 2.4 2.5 or 3.0 VDDA V VREFLO VSSA 0 VSSA V VREFHI – VREFLO 2.4 VDDA V ADC input conversion range VREFLO VREFHI V ADC input signal common mode voltage(2) (3) VREFCM – 50 VREFCM VREFCM + 50 mV (1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation. (2) VREFCM = (VREFHI + VREFLO)/2 (3) The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO. Note The ADC inputs should be kept below V DDA + 0.3 V during operation. If an ADC input exceeds this level, the V REF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same VREF. Note The VREFHI pin must be kept below V DDA + 0.3 V to ensure proper functional operation. If the V REFHI pin exceeds this level, a blocking circuit may activate, and the internal value of V REFHI may float to 0 V internally, giving improper ADC conversion or DAC output. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: F28377D-SEP

6.9.1.2.2 ADC Characteristics (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)(6) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC conversion cycles(1) 29.6 31 ADCCLKs Power-up time (after setting ADCPWDNZ to first conversion) 500 µs Gain error –64 ±9 64 LSBs Offset error(2) –16 ±9 16 LSBs Channel-to-channel gain error ±6 LSBs Channel-to-channel offset error ±3 LSBs ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±6 LSBs ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±3 LSBs DNL(3) > –1 ±0.5 1 LSBs INL –3 ±1.5 3 LSBs SNR(4) (11) VREFHI = 2.5 V, fin = 10 kHz 90.2 dB THD(4) (11) VREFHI = 2.5 V, fin = 10 kHz –105 dB SFDR(4) (11) VREFHI = 2.5 V, fin = 10 kHz 106 dB SINAD(4) (11) VREFHI = 2.5 V, fin = 10 kHz 90.0 dB ENOB(4) (11) VREFHI = 2.5 V, fin = 10 kHz, single ADC(7) 14.65 bitsVREFHI = 2.5 V, fin = 10 kHz, synchronous ADCs(8) 14.65 VREFHI = 2.5 V, fin = 10 kHz, asynchronous ADCs(9) Not supported PSRR VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz 77 dB PSRR VDDA = 3.3-V DC + 200 mV Sine at 800 kHz 74 dB CMRR DC to 1 MHz 60 dB VREFHI input current 190 µA ADC-to-ADC isolation(11) (5) (10) VREFHI = 2.5 V, synchronous ADCs(8) –2 2 LSBs VREFHI = 2.5 V, asynchronous ADCs(9) Not supported (2) Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM. (3) No missing codes. (4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source. (5) Maximum DC code deviation due to operation of multiple ADCs simultaneously. (6) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V. (7) One ADC operating while all other ADCs are idle. (8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution. (9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution. (10) Value based on characterization. (11) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and crosstalk. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

98 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode)

6.9.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode)

over recommended operating conditions (unless otherwise noted)(5) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC conversion cycles(1) 10.1 11 ADCCLKs Power-up time 500 µs Gain error –5 ±3 5 LSBs Offset error –4 ±2 4 LSBs Channel-to-channel gain error ±4 LSBs Channel-to-channel offset error ±2 LSBs ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±4 LSBs ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±2 LSBs DNL(2) > –1 ±0.5 1 LSBs INL –2 ±1.0 2 LSBs SNR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 69.1 dB THD(3) (10) VREFHI = 2.5 V, fin = 100 kHz –88 dB SFDR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 89 dB SINAD(3) (10) VREFHI = 2.5 V, fin = 100 kHz 69.0 dB ENOB(3) (10) VREFHI = 2.5 V, fin = 100 kHz, single ADC(6), all packages 11.2 bits VREFHI = 2.5 V, fin = 100 kHz, synchronous ADCs(7), all packages 11.2 VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 176-pin PTP package 9.7 www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: F28377D-SEP

6.9.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode) (continued)

over recommended operating conditions (unless otherwise noted)(5) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz 60 dB PSRR VDDA = 3.3-V DC + 200 mV Sine at 800 kHz 57 dB ADC-to-ADC isolation(10) (4) (9) VREFHI = 2.5 V, synchronous ADCs(7), all packages –1 1 LSBs VREFHI = 2.5 V, asynchronous ADCs(8), 176-pin PTP package –9 9 VREFHI input current 130 µA (1) See the ADC Timing Diagrams section. (2) No missing codes. (3) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source. (4) Maximum DC code deviation due to operation of multiple ADCs simultaneously. (5) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V. (6) One ADC operating while all other ADCs are idle. (7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution. (8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution. (9) Value based on characterization. (10) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and crosstalk.

6.9.1.2.5 ADCEXTSOC Timing Requirements

MIN(1) MAX UNIT tw(INT) Pulse duration, INT input low/high Synchronous 2tc(SYSCLK) cycles With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

100 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.1.2.6 ADC Input Models

ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA. DESCRIPTION VALUE (16-BIT MODE) Cp Parasitic input capacitance See Table 6-12 Ron Sampling switch resistance 700 Ω Ch Sampling capacitor 16.5 pF Rs Nominal source impedance 50 Ω ADC RonSwitch ADCINxN Ch Cp ADCINxP AC Rs RonSwitch Rs Cp VSSA Figure 6-36. Differential Input Model For single-ended operation, the ADC input characteristics are given by Single-Ended Input Model Parameters 2837xD, 2837xS, SopranoSEP, and SopranoEP and Figure 6-37. DESCRIPTION VALUE (12-BIT MODE) Cp Parasitic input capacitance See Table 6-12 Ron Sampling switch resistance 425 Ω Ch Sampling capacitor 14.5 pF Rs Nominal source impedance 50 Ω ADC RonSwitch VREFLO ChCp ADCINx AC Rs Figure 6-37. Single-Ended Input Model Table 6-12 shows the parasitic capacitance on each channel. Also, enabling a comparator adds approximately 1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs. Table 6-12. Per-Channel Parasitic Capacitance ADC CHANNEL Cp (pF) COMPARATOR DISABLED COMPARATOR ENABLED ADCINA0 12.9 N/A ADCINA1 10.3 N/A www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: F28377D-SEP

Table 6-12. Per-Channel Parasitic Capacitance (continued) ADC CHANNEL Cp (pF) COMPARATOR DISABLED COMPARATOR ENABLED ADCINA2 5.9 7.3 ADCINA3 6.3 8.8 ADCINA4 5.9 7.3 ADCINA5 6.3 8.8 ADCINB0(1) 117.0 N/A ADCINB1 10.6 N/A ADCINB2 5.9 7.3 ADCINB3 6.2 8.7 ADCINB4 5.2 N/A ADCINB5 5.1 N/A ADCINC2 5.5 6.9 ADCINC3 5.8 8.3 ADCINC4 5.0 6.4 ADCINC5 5.3 7.8 ADCIND0 5.3 6.7 ADCIND1 5.7 8.2 ADCIND2 5.3 6.7 ADCIND3 5.6 8.1 ADCIND4 4.3 N/A ADCIND5 4.3 N/A ADCIN14 8.6 10.0 ADCIN15 9.0 11.5 (1) The increased capacitance is due to VDAC functionality. These input models should be used along with actual signal source impedance to determine the acquisition window duration. See the Choosing an Acquisition Window Duration section of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more information. Also refer to Charge-Sharing Driving Circuits for C2000 ADCs and ADC Input Circuit Evaluation for C2000 MCUs for more details on evaluating ADC circuit performance. The user should analyze the ADC input setting assuming worst-case initial conditions on C h. This will require assuming that Ch could start the S+H window completely charged to V REFHI or completely discharged to VREFLO. When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-versa, the actual initial voltage on C h will be close to being completely discharged to V REFLO. For even-to-even or odd-to- odd channel transitions, the initial voltage on Ch will be close to the voltage of the previously converted channel. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

102 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.1.2.7 ADC Timing Diagrams

timings in 16-bit mode. Figure 6-38 and Figure 6-39 show the ADC conversion timings for two SOCs given the following assumptions:

SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module). Table 6-13 lists the descriptions of the ADC timing parameters that are in Figure 6-38 and Figure 6-39 . Table 6-13. ADC Timing Parameters PARAMETER DESCRIPTION tSH The duration of the S+H window. At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH will not necessarily be the same for different SOCs. Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window regardless of device clock settings. tLAT The time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register. If the ADCRESULTx register is read before this time, the previous conversion results will be returned. tEOC The time from the end of the S+H window until the next ADC conversion S+H window can begin. The subsequent sample can start before the conversion results are latched. tINT The time from the end of the S+H window until an ADCINT flag is set (if configured). If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being latched into the result register. If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken to ensure the read occurs after the results latch (otherwise, the previous results will be read). www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: F28377D-SEP

ADCCLK PRESCALE SYSCLK CYCLES ADCCLK CYCLES ADCCTL2 [PRESCALE] RATIO ADCCLK:SYSCLK tEOC tLAT (1) tINT(EARLY) tINT(LATE) tEOC 0 1 11 13 1 11 11.0 1 1.5 Invalid 2 2 21 23 1 21 10.5 3 2.5 26 28 1 26 10.4 4 3 31 34 1 31 10.3 5 3.5 36 39 1 36 10.3 6 4 41 44 1 41 10.3 7 4.5 46 49 1 46 10.2 8 5 51 55 1 51 10.2 9 5.5 56 60 1 56 10.2 10 6 61 65 1 61 10.2 11 6.5 66 70 1 66 10.2 12 7 71 76 1 71 10.1 13 7.5 76 81 1 76 10.1 14 8 81 86 1 81 10.1 15 8.5 86 91 1 86 10.1 (1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

104 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

ADCSOCFLG.SOC0 ADCSOCFLG.SOC1 ADC S+H ADCCLK SOC0 Input on SOC0.CHSEL Input on SOC1.CHSEL ADCRESULT0 ADCRESULT1 ADCINTFLG.ADCINTx SOC1 (old data) (old data) Sample n Sample n+1 Sample n Sample n+1 tSH tLAT tEOC tINT Figure 6-38. ADC Timings for 12-Bit Mode www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: F28377D-SEP

ADCCLK PRESCALE SYSCLK CYCLES ADCCLK CYCLES ADCCTL2 [PRESCALE] RATIO ADCCLK:SYSCLK tEOC tLAT (1) tINT(EARLY) tINT(LATE) tEOC 0 1 31 32 1 31 31.0 1 1.5 Invalid 2 2 60 61 1 60 30.0 3 2.5 75 75 1 75 30.0 4 3 90 91 1 90 30.0 5 3.5 104 106 1 104 29.7 6 4 119 120 1 119 29.8 7 4.5 134 134 1 134 29.8 8 5 149 150 1 149 29.8 9 5.5 163 165 1 163 29.6 10 6 178 179 1 178 29.7 11 6.5 193 193 1 193 29.7 12 7 208 209 1 208 29.7 13 7.5 222 224 1 222 29.6 14 8 237 238 1 237 29.6 15 8.5 252 252 1 252 29.6 (1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

106 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

ADCSOCFLG.SOC0 ADCSOCFLG.SOC1 ADC S+H ADCCLK SOC0 Input on SOC0.CHSEL Input on SOC1.CHSEL ADCRESULT0 ADCRESULT1 ADCINTFLG.ADCINTx SOC1 (old data) (old data) Sample n Sample n+1 Sample n Sample n+1 tSH tLAT tEOC tINT Figure 6-39. ADC Timings for 16-Bit Mode www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 107 Product Folder Links: F28377D-SEP

6.9.1.3 Temperature Sensor Electrical Data and Timing

The temperature sensor can be used to measure the device junction temperature. The temperature sensor is sampled through an internal connection to the ADC and translated into a temperature through TI-provided

6.9.1.3.1 Temperature Sensor Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT Temperature accuracy ±15 °C Start-up time (TSNSCTL[ENABLE] to sampling temperature sensor) 500 µs ADC acquisition time 700 ns F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

108 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.2 Comparator Subsystem (CMPSS)

Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs), two digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of these inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the positive input of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the negative comparator inputs. There are two comparators, and therefore two outputs from the CMPSS module, which are connected to the input of a digital filter module before being passed on to the Comparator TRIP crossbar and either PWM modules or directly to a GPIO pin. Figure 6-40 shows the CMPSS connectivity on the 176-pin PTP package. CTRIPOUT1H CTRIP1H CTRIP1L CTRIP2L CTRIPOUT2H CTRIP2H CTRIPOUT8H CTRIP8H CTRIP8L ePWMsePWM X-BAR CTRIPOUT2L CTRIPOUT8L CTRIP1H CTRIP1L CTRIP2H CTRIP2L CTRIP8H CTRIP8L GPIO MuxOutput X-BAR CTRIPOUT1H CTRIPOUT1L CTRIPOUT2H CTRIPOUT2L CTRIPOUT8H CTRIPOUT8L Comparator Subsystem 1 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 CTRIPOUT1L Comparator Subsystem 2 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 Comparator Subsystem 8 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 CMPIN1P Pin CMPIN1N Pin CMPIN2N Pin CMPIN8N Pin CMPIN2P Pin CMPIN8P Pin Figure 6-40. CMPSS Connectivity (176-Pin PTP) www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: F28377D-SEP

6.9.2.1 CMPSS Electrical Data and Timing

input referred offset. Figure 6-42 shows the CMPSS comparator hysteresis.

6.9.2.1.1 Comparator Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power-up time 500(2) µs Comparator input (CMPINxx) range 0 VDDA V Input referred offset error Low common mode, inverting input set to 50 mV –20 20 mV Hysteresis(1) 1x 4 12 20 CMPSS DAC LSB 2x 17 24 33 3x 25 36 50 4x 30 48 67 Response time (delay from CMPINx input change to output on ePWM X-BAR or Output X-BAR) Step response 21 60 nsRamp response (1.65 V/µs) 26 Ramp response (8.25 mV/µs) 30 Power Supply Rejection Ratio (PSRR) Up to 250 kHz 46 dB Common Mode Rejection Ratio (CMRR) 40 dB (1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations. (2) See the "Analog Bandgap References" advisory of the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . Note The CMPSS inputs must be kept below V DDA + 0.3 V to ensure proper functional operation. If a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from the external pin until the external pin voltage returns below V DDA + 0.3 V. During this time, the internal comparator input will be floating and can decay below V DDA within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect result depending on the value of the other comparator input. CTRIPx = 0

0 CMPINxN or

CTRIPx = 1 Input Referred Offset COMPINxP Voltage CTRIPx Logic Level Figure 6-41. CMPSS Comparator Input Referred Offset F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

110 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

CTRIPx = 0 CTRIPx = 1 Hysteresis COMPINxP Voltage CTRIPx Logic Level Figure 6-42. CMPSS Comparator Hysteresis static offset. Figure 6-44 shows the CMPSS DAC static gain. Figure 6-45 shows the CMPSS DAC static linearity.

6.9.2.1.2 CMPSS DAC Static Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMPSS DAC output range Internal reference 0 VDDA (1) V External reference 0 VDAC Static offset error(2) –25 25 mV Static gain error(2) –2 2 % of FSR Static DNL Endpoint corrected >–1 4 LSB Static INL Endpoint corrected –16 16 LSB Settling time Settling to 1 LSB after full-scale output change 1 µs Resolution 12 bits CMPSS DAC output disturbance(3) Error induced by comparator trip or CMPSS DAC code change within the same CMPSS module –100 100 LSB CMPSS DAC disturbance time(3) 200 ns VDAC reference voltage When VDAC is reference 2.4 2.5 or 3.0 VDDA V VDAC load(4) When VDAC is reference 6 kΩ (1) The maximum output voltage is VDDA when VDAC > VDDA. (2) Includes comparator input referred errors. (3) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip. (4) Per active CMPSS module. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: F28377D-SEP

Figures not drawn to scale. Offset Error Figure 6-43. CMPSS DAC Static Offset Actual Linear Range Ideal Gain Actual Gain Figure 6-44. CMPSS DAC Static Gain F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

112 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

Figure 6-45. CMPSS DAC Static Linearity www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: F28377D-SEP

6.9.3 Buffered Digital-to-Analog Converter (DAC)

The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that is capable of driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage when the output buffer is disabled. This pulldown resistor cannot be disabled and remains as a passive component on the pin, even for other shared pin mux functions. Software writes to the DAC value register can take effect immediately or can be synchronized with EPWMSYNCPER events. Each buffered DAC has the following features:

12-bit programmable internal DAC
Selectable reference voltage
Pulldown resistor on output
Ability to synchronize with EPWMSYNCPER The block diagram for the buffered DAC is shown in Figure 6-46. EPWM1SYNCPER VREFHI VDDA VSSA VDAC DACCTL[DACREFSEL] DACCTL[LOADMODE]SYSCLK DACCTL[SYNCSEL] EPWM2SYNCPER EPWM3SYNCPER EPWMnSYNCPER ... D Q D Q DACVALS Y n-1 DACVALA Buffer12-bit DAC VSSA DACOUT DACREF RPD EN Figure 6-46. DAC Module Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

114 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.3.1 Buffered DAC Electrical Data and Timing

Figure 6-48 shows the buffered DAC gain. Figure 6-49 shows the buffered DAC linearity.

6.9.3.1.1 Buffered DAC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power-up time 500(8) µs Offset error Midpoint –10 10 mV Gain error(2) –2.5 2.5 % of FSR DNL(3) Endpoint corrected > –1 ±0.4 1 LSB INL Endpoint corrected –5 ±2 5 LSB DACOUTx settling time Settling to 2 LSBs after 0.3V-to-3V transition 2 µs Resolution 12 bits Voltage output range(4) 0.3 VDDA – 0.3 V Capacitive load Output drive capability 100 pF Resistive load Output drive capability 5 kΩ RPD pulldown resistor 50 kΩ Reference voltage(5) VDAC or VREFHI 2.4 2.5 or 3.0 VDDA V Reference input resistance(6) VDAC or VREFHI 170 kΩ Output noise Integrated noise from 100 Hz to 100 kHz 500 µVrms Noise density at 10 kHz 711 nVrms/√Hz Glitch energy 1.5 V-ns PSRR(7) DC up to 1 kHz 70 dB 100 kHz 30 SNR 1020 Hz 67 dB THD 1020 Hz –63 dB SFDR

1020 Hz, including harmonics and spurs 66

1020 Hz, including only spurs 104

(1) Typical values are measured with VREFHI = 3.3 V unless otherwise noted. Minimum and Maximum values are tested or characterized with VREFHI = 2.5 V. (2) Gain error is calculated for linear output range. (3) The DAC output is monotonic. (4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear due to the buffer. (5) For best PSRR performance, VDAC or VREFHI should be less than VDDA. (6) Per active Buffered DAC module. (7) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine. (8) See the "Analog Bandgap References" advisory of the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . Note The VDAC pin must be kept below V DDA + 0.3 V to ensure proper functional operation. If the VDAC pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V internally, giving improper DAC output. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: F28377D-SEP

The VREFHI pin must be kept below V DDA + 0.3 V to ensure proper functional operation. If the V REFHI pin exceeds this level, a blocking circuit may activate, and the internal value of V REFHI may float to 0 V internally, giving improper ADC conversion or DAC output. Offset Error Code 2048 Figure 6-47. Buffered DAC Offset F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

116 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.9.3.2 CMPSS DAC Dynamic Error

When using the ramp generator to control the internal DAC, the step size can vary based on the application need. Since the step size of the DAC is less than a full scale transition, the settling time is improved from the electrical specification listed in the CMPSS DAC Static Electrical Characteristics table. The equation below and Figure 6-50 can give guidance on the expected voltage error from ideal based on different RAMPxDECVALA values. DY N AMI C ERR OR = m × R A MPxD EC V AL A + b (5) Table 6-14. DAC Max Dynamic Error Terms EQUATION PARAMETER MIN (LSB) MAX (LSB) m 0.167 0.30 b 3.7 5.6 Note Above error terms are based on the max SYSCLK of the target device. If operating below the max SYSCLK then the "m" error term should be scaled accordingly. R A M P x D E C V A L DYNAMIC ERROR (LSB) 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 M a x E r r o r M in E r r o r Figure 6-50. CMPSS DAC Dynamic Error F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

118 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.10 Control Peripherals

For the actual number of each peripheral on a specific device, see the Device Comparison table.

6.10.1 Enhanced Capture (eCAP)

The eCAP module can be used in systems where accurate timing of external events is important. Applications for eCAP include:

Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors The eCAP module includes the following features:
4-event time-stamp registers (each 32 bits)
Edge-polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event timestamps
Continuous mode capture of timestamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All of the above resources dedicated to a single input pin
When not used in capture mode, the eCAP module can be configured as a single-channel PWM output (APWM). The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins Figure 6-51 shows the block diagram of an eCAP module. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: F28377D-SEP

(counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 PRD [0−31] CMP [0−31] CTR [0−31] eCAPx Interrupt Trigger and Flag control to PIE CTR=CMP ACMP shadow Event Prescale CTRPHS (phase register−32 bit) SYNCOut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR=PRD CTR_OVF PWM compare logic CTR [0−31] PRD [0−31] CMP [0−31] CTR=CMP CTR=PRD CTR_OVFOVF APWM mode Delta−mode SYNC 4Capture events CEVT[1:4] APRD shadow

32 MODE SELECT

Figure 6-51. eCAP Block Diagram The eCAP module is clocked by PERx.SYSCLK. The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually (for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

120 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.10.1.1 eCAP Electrical Data and Timing characteristics. 6.10.1.1.1 eCAP Timing Requirement MIN(1) MAX UNIT tw(CAP) Capture input pulse width Asynchronous 2tc(SYSCLK) cycles Synchronous 2tc(SYSCLK) cycles With input qualifier 1tc(SYSCLK) + tw(IQSW) cycles 6.10.1.1.2 eCAP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(APWM) Pulse duration, APWMx output high/low 20 ns www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: F28377D-SEP

6.10.2 Enhanced Pulse Width Modulator (ePWM)

The ePWM peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-zone functionality, and global register reload capabilities. Figure 6-52 shows the signal interconnections with the ePWM. Figure 6-53 shows the ePWM trip input connectivity. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

122 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

TBPRD Shadow (16) TBPRD Active (16) Counter Up/Down (16 Bit) TBCTR Active (16) TBCTL[PHSEN] CTR=PRD Phase Control CTR=ZERO CTR_Dir Time-Base (TB) TBPHS Active (16) CTR=PRD CTR=ZERO CTR_Dir Event Trigger and Interrupt (ET) MCPWMx_INT ADCSOCAO ADCSOCBO SOCA On-chip ADC Action Qualifier (AQ) Dead Band (DB) Trip Zone (TZ) CTR_PWMx_CMPA PWMx_CMPB(16) PWMx_CMPBS(16) CTR=PRD or ZERO PWMx_CMPA(16) PWMx_CMPAS(16) CTR=PWMx_CMPB CTR=CMPC CTR=PWMx_CMPA CTR=CMPD CTR=CMPC TBCNT(16) CMPC[15-0] CTR=CMPD TBCNT(16) CMPD[15-0] Counter Compare (CC) CMPD Active (16) CMPD Shadow (16) CMPC Active (16) CMPC Shadow (16) Sync Out SelectCTR=CMPO MCPWMxSYNCO TBCTL[SYNCOSEL] SOCB ADCSOCOUTSELECT MCPWMxSYNCI CTR=CMPD CTR=ZERO SWSYNC TZ1 to TZ8 MCPWMx_1A MCPWMx_1B MCPWMx_2A MCPWMx_2B MCPWMx_3A MCPWMx_3B PWM1A PWM1B PWM2A PWM2B PWM3A PWM3B Select and pulse stretch for external ADC CTR_PWMx_CMPB SOCC SOCD A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs. Figure 6-52. ePWM Submodules and Critical Internal Signal Interconnects www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 123 Product Folder Links: F28377D-SEP

Figure 6-53. ePWM Trip Input Connectivity F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

124 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.10.2.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization chain on the device provides flexibility in partitioning the ePWM and eCAP modules between CPU1 and CPU2 and allows localized synchronization within the modules belonging to the same CPU. Like the other peripherals, the partitioning of the ePWM and eCAP modules needs to be done using the CPUSELx registers. Figure 6-54 shows the synchronization chain architecture. EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM1 1 EPWM12 ECAP1 EXTSYNCIN1 EXTSYNCOUT Pulse -Stretched (8 PLLSYSCLK Cycles ) SYNCSELECT .EPWM4SYNCIN EXTSYNCIN2 SYNCSELECT . SYNCOUT SYNCSELECT .EPWM7SYNCIN SYNCSELECT .ECAP 4SYNCIN SYNCSELECT .ECAP 1SYNCIN SYNCSELECT .EPWM 10SYNCIN EPWM 1SYNCOUT EPWM4SYNCOUT EPWM7SYNCOUT EPWM 10SYNCOUT ECAP 1SYNCOUT ECAP2 ECAP3 ECAP4 ECAP5 ECAP6 Figure 6-54. Synchronization Chain Architecture www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 125 Product Folder Links: F28377D-SEP

6.10.2.2 ePWM Electrical Data and Timing characteristics. 6.10.2.2.1 ePWM Timing Requirements MIN(1) MAX UNIT f(EPWM) Frequency, EPWMCLK(2) 100 MHz tw(SYNCIN) Sync input pulse width Asynchronous 2tc(EPWMCLK) cycles Synchronous 2tc(EPWMCLK) cycles With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles (2) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK. 6.10.2.2.2 ePWM Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(PWM) Pulse duration, PWMx output high/low 20 ns tw(SYNCOUT) Sync output pulse width 8tc(SYSCLK) cycles td(TZ-PWM) Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low Delay time, trip input active to PWM Hi-Z 25 ns

6.10.2.2.3 Trip-Zone Input Timing

characteristics. MIN(1) MAX UNIT tw(TZ) Pulse duration, TZx input low Asynchronous 1tc(EPWMCLK) cycles Synchronous 2tc(EPWMCLK) cycles With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles PWM (B) TZ (A) EPWMCLK tw(TZ) td(TZ-PWM) A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12 B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-55. PWM Hi-Z Characteristics F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

126 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.10.2.3 External ADC Start-of-Conversion Electrical Data and Timing

ADCSOCAO or ADCSOCBO timing.

6.10.2.3.1 External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(SYSCLK) cycles ADCSOCAO ADCSOCBO or tw(ADCSOCL) Figure 6-56. ADCSOCAO or ADCSOCBO Timing www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 127 Product Folder Links: F28377D-SEP

6.10.3 Enhanced Quadrature Encoder Pulse (eQEP)

The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and speed information from rotating machines used in high-performance motion and position-control systems. Each eQEP peripheral comprises five major functional blocks:

Quadrature Capture Unit (QCAP)
Position Counter/Control Unit (PCCU)
Quadrature Decoder Unit (QDU)
Unit Time Base for speed and frequency measurement (UTIME)
Watchdog timer for detecting stalls (QWDOG) The eQEP peripherals are clocked by PERx.SYSCLK. Figure 6-57 shows the eQEP block diagram. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

128 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

(QCAP) QCPRDLAT QCTMRLAT QFLG QEPSTS QEPCTL Registers Used by Multiple Units QCLK QDIR QI QS PHE PCSOUT Quadrature Decoder (QDU) QDECCTL Position Counter/ Control Unit (PCCU)QPOSLAT QPOSSLAT QPOSILAT EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE GPIO MUX EQEPxA/XCLK EQEPxB/XDIR EQEPxS EQEPxI QPOSCMP QEINT QFRC QCLR QPOSCTL 1632 QPOSCNT QPOSMAX QPOSINIT PIE EQEPxINT eQEP Peripheral System Control Registers QCTMR QCPRD 1616 QCAPCTL EQEPxENCLK SYSCLK To CPU Data Bus Figure 6-57. eQEP Block Diagram www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 129 Product Folder Links: F28377D-SEP

6.10.3.1 eQEP Electrical Data and Timing characteristics. 6.10.3.1.1 eQEP Timing Requirements MIN(1) MAX UNIT tw(QEPP) QEP input period Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles With input qualifier 2[1tc(SYSCLK) + tw(IQSW)] cycles tw(INDEXH) QEP Index Input High time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles tw(INDEXL) QEP Index Input Low time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles tw(STROBH) QEP Strobe High time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles tw(STROBL) QEP Strobe Input Low time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles (2) See the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata for limitations in the asynchronous mode. 6.10.3.1.2 eQEP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(CNTR)xin Delay time, external clock to counter increment 4tc(SYSCLK) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SYSCLK) cycles F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

130 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.10.4 High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. For each ePWM module, there are two HR outputs:

HR Duty and Deadband control on Channel A
HR Duty and Deadband control on Channel B The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge control for frequency/period modulation.
Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B, phase, period and deadband registers of the ePWM module. Note The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.

6.10.4.1 HRPWM Electrical Data and Timing

PWM switching characteristics.

6.10.4.1.1 High-Resolution PWM Timing Requirements

f(EPWM) Frequency, EPWMCLK(1) 100 MHz f(HRPWM) Frequency, HRPWMCLK 60 100 MHz (1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

6.10.4.1.2 High-Resolution PWM Characteristics

PARAMETER MIN TYP MAX UNIT Micro Edge Positioning (MEP) step size(1) 150 310 ps (1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher temperature and lower voltage and decrease with lower temperature and higher voltage. Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per SYSCLK period dynamically while the HRPWM is in operation. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: F28377D-SEP

6.10.5 Sigma-Delta Filter Module (SDFM)

The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position decoding in motor control applications. Each channel can receive an independent sigma-delta ( ΣΔ) modulated bit stream. The bit streams are processed by four individually programmable digital decimation filters. The filter set includes a fast comparator for immediate digital threshold comparisons for overcurrent and undercurrent monitoring. Figure 6-58 shows a block diagram of the SDFMs. SDFM features include:

Eight external pins per SDFM module: – Four sigma-delta data input pins per SDFM module (SDx_Dy, where x = 1 to 2 and y = 1 to 4) – Four sigma-delta clock input pins per SDFM module (SDx_Cy, where x = 1 to 2 and y = 1 to 4)
Four different configurable modulator clock modes: – Modulator clock rate equals modulator data rate – Modulator clock rate running at half the modulator data rate – Modulator data is Manchester encoded. Modulator clock not required. – Modulator clock rate is double that of modulator data rate
Four independent configurable comparator units: – Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available – Ability to detect over-value and under-value conditions – Comparator Over-Sampling Ratio (COSR) value for comparator programmable from 1 to 32
Four independent configurable data filter units: – Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available – Data filter Over-Sampling Ratio (DOSR) value for data filter unit programmable from 1 to 256 – Ability to enable or disable individual filter module – Ability to synchronize all four independent filters of a SDFM module using the Master Filter Enable (MFE) bit or the PWM signals.
Filter data can be 16-bit or 32-bit representation
PWMs can be used to generate modulator clock for sigma-delta modulators F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

132 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

SDFM- Sigma Delta Filter Module Input Ctrl Streams Data busRegister Map R R Comparator filter Data filter FILRES Filter Channel 4 Filter Channel 3 Filter Channel 2 PIE Interrupt Unit IEL IEH SD1INT Filter Channel 1 SDFM- Sigma Delta Filter Module Input Ctrl Streams Data busRegister Map R R Comparator filter Data filter Filter Channel 4 Filter Channel 3 Filter Channel 2 Interrupt Unit IEL IEH SD2INT Output XBar SD1FLT1.IEH SD1FLT1.IEL SD1FLT2.IEH SD1FLT2.IEL SD1FLT3.IEH SD1FLT3.IEL SD1FLT4.IEH SD1FLT4.IEL SD2FLT1.IEH SD2FLT1.IEL SD2FLT2.IEH SD2FLT2.IEL SD2FLT3.IEH SD2FLT3.IEL SD2FLT4.IEH SD2FLT4.IEL PWM11.CMPC PWM11.CMPD FILRES FILRES FILRES PWM12.CMPC FILRES PWM12.CMPD FILRES FILRES Data filter FILRES GPIO MUX SD2_D1 SD2_C1 SD2_D2 SD2_C2 SD2_D3 SD2_C3 SD2_D4 SD2_C4 SD1_D4 SD1_C4 SD1_D3 SD1_C3 SD1_D2 SD1_C2 SD1_D1 SD1_C1 Figure 6-58. SDFM Block Diagram www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 133 Product Folder Links: F28377D-SEP

6.10.5.1 SDFM Electrical Data and Timing (Using ASYNC)

SDFM timing requirements when using the asynchronous GPIO (ASYNC) option. Figure 6-59 through Figure 6-62 show the SDFM timing diagrams.

6.10.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option

tc(SDC)M0 Cycle time, SDx_Cy 40 256 * SYSCLK period ns tw(SDCH)M0 Pulse duration, SDx_Cy high 10 tc(SDC)M0 – 10 ns tsu(SDDV-SDCH)M0 Setup time, SDx_Dy valid before SDx_Cy goes high 5 ns th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns Mode 1 tc(SDC)M1 Cycle time, SDx_Cy 80 256 * SYSCLK period ns tw(SDCH)M1 Pulse duration, SDx_Cy high 10 tc(SDC)M1 – 10 ns tsu(SDDV-SDCL)M1 Setup time, SDx_Dy valid before SDx_Cy goes low 5 ns tsu(SDDV-SDCH)M1 Setup time, SDx_Dy valid before SDx_Cy goes high 5 ns th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 5 ns th(SDCH-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns Mode 2 tc(SDD)M2 Cycle time, SDx_Dy 8 * tc(SYSCLK) 20 * tc(SYSCLK) ns tw(SDDH)M2 Pulse duration, SDx_Dy high 10 ns tw(SDD_LONG_KEEPOUT)M2 SDx_Dy long pulse duration keepout, where the long pulse must not fall within the MIN or MAX values listed. Long pulse is defined as the high or low pulse which is the full width of the Manchester bit-clock period. This requirement must be satisfied for any integer between 8 and 20. (N * tc(SYSCLK)) – 0.5 (N * tc(SYSCLK)) + 0.5 ns tw(SDD_SHORT)M2 SDx_Dy Short pulse duration for a high or low pulse (SDD_SHORT_H or SDD_SHORT_L). Short pulse is defined as the high or low pulse which is half the width of the Manchester bit-clock period. tw(SDD_LONG) / 2 – tc(SYSCLK) tw(SDD_LONG) / 2 + tc(SYSCLK) ns tw(SDD_LONG_DUTY)M2 SDx_Dy Long pulse variation (SDD_LONG_H – SDD_LONG_L) – tc(SYSCLK) tc(SYSCLK) ns tw(SDD_SHORT_DUTY)M2 SDx_Dy Short pulse variation (SDD_SHORT_H – SDD_SHORT_L) – tc(SYSCLK) tc(SYSCLK) ns Mode 3 tc(SDC)M3 Cycle time, SDx_Cy 40 256 * SYSCLK period ns tw(SDCH)M3 Pulse duration, SDx_Cy high 10 tc(SDC)M3 – 5 ns tsu(SDDV-SDCH)M3 Setup time, SDx_Dy valid before SDx_Cy goes high 5 ns th(SDCH-SDD)M3 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

134 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

The SDFM clock inputs (SDx_Cy pins) directly clock the SDFM module when there is no GPIO input synchronization. Any glitches or ringing noise on these inputs can corrupt the SDFM module operation. Special precautions should be taken on these signals to ensure a clean and noise-free signal that meets SDFM timing requirements. Precautions such as series termination for ringing due to any impedance mismatch of the clock driver and spacing of traces from other noisy signals are recommended. WARNING See the "SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter Results Under Several Conditions" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: F28377D-SEP

Mode 0 tw(SDCH)M0 tc(SDC)M0 th(SDCH-SDD)M0tsu(SDDV-SDCH)M0 SDx_Cy SDx_Dy Figure 6-59. SDFM Timing Diagram – Mode 0 tw(SDCH)M1 tc(SDC)M1 th(SDCL-SDD)M1 th(SDCH-SDD)M1 tsu(SDDV-SDCL)M1 tsu(SDDV-SDCH)M1 SDx_Cy SDx_Dy Mode 1 Figure 6-60. SDFM Timing Diagram – Mode 1 Modulator Internal data tc(SDD)M2 tw(SDDH)M2 Modulator Internal clock tw(SDD_LONG_KEEPOUT) SDx-Dy N x tc(SYSCLK) + 0.5 N x tc(SYSCLK) ±0.5 tw(SDD_LONG_L) tw(SDD_SHORT_H) tw(SDD_SHORT_L) tw(SDD_LONG_H) N x SYSCLK SYSCLK Mode 2 (Manchester-encoded-bit stream) 1 1 0 1 0 1 0 1 1 Figure 6-61. SDFM Timing Diagram – Mode 2 Mode 3 SDx_Cy SDx_Dy (CLKx is driven externally) tc(SDC)M3 tw(SDCH)M3 tsu(SDDV-SDCH)M3 th(SDCH-SDD)M3 Figure 6-62. SDFM Timing Diagram – Mode 3 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

136 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.10.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)

SDFM operation with qualified GPIO (3-sample window) is defined by setting GPyQSELn = 0b01. When using this qualified GPIO (3-sample window) mode, the timing requirement for the t w(GPI) pulse duration of 2t c(SYSCLK) must be met. It is important for both SD-Cx and SD-Dx pairs to be configured with the same GPIO qualification window) option. Figure 6-59 through Figure 6-62 show the SDFM timing diagrams.

6.10.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option

MIN(1) MAX UNIT Mode 0 tc(SDC)M0 Cycle time, SDx_Cy 10 * SYSCLK period 256 * SYSCLK period ns tw(SDCHL)M0 Pulse duration, SDx_Cy high/low 4 * SYSCLK period 6 * SYSCLK period ns tw(SDDHL)M0 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns tsu(SDDV-SDCH)M0 Setup time, SDx_Dy valid before SDx_Cy goes high 2 * SYSCLK period ns th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns Mode 1 tc(SDC)M1 Cycle time, SDx_Cy 20 * SYSCLK period 256 * SYSCLK period ns tw(SDCH)M1 Pulse duration, SDx_Cy high 4 * SYSCLK period 6 * SYSCLK period ns tw(SDDHL)M1 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns tsu(SDDV-SDCL)M1 Setup time, SDx_Dy valid before SDx_Cy goes low 2 * SYSCLK period ns tsu(SDDV-SDCH)M1 Setup time, SDx_Dy valid before SDx_Cy goes high 2 * SYSCLK period ns th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 2 * SYSCLK period ns th(SDCH-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns Mode 2 tc(SDD)M2 Cycle time, SDx_Dy Option unavailable tw(SDDH)M2 Pulse duration, SDx_Dy high Mode 3 tc(SDC)M3 Cycle time, SDx_Cy 10 * SYSCLK period 256 * SYSCLK period ns tw(SDCHL)M3 Pulse duration, SDx_Cy high 4 * SYSCLK period 6 * SYSCLK period ns tw(SDDHL)M3 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns tsu(SDDV-SDCH)M3 Setup time, SDx_Dy valid before SDx_Cy goes high 2 * SYSCLK period ns th(SDCH-SDD)M3 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns (1) SDFM timing requirements apply only when the GPIO input qualification type is the 3-sample window (GPyQSELx = 1; QUALPRD = 0) option. It is important that both the SD-Cx and SD-Dx pairs be configured with the 3-sample window option. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: F28377D-SEP

The SDFM Qualified GPIO (3-sample) mode provides protection against SDFM module corruption due to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip and filter output. For more details, refer to the "SDFM: Use Caution While Using SDFM Under Noisy Conditions" usage note in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . The SDFM Qualified GPIO (3-sample) mode does not provide protection against persistent violations of the above timing requirements. Timing violations will result in data corruption proportional to the number of bits which violate the requirements. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

138 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11 Communications Peripherals

For the actual number of each peripheral on a specific device, see the Device Comparison table.

6.11.1 Controller Area Network (CAN)

The CAN module performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbps. A CAN transceiver chip is required for the connection to the physical layer (CAN bus). For communication on a CAN network, individual message objects can be configured. The message objects and identifier masks are stored in the Message RAM. All functions concerning the handling of messages are implemented in the message handler. These functions are: acceptance filtering; the transfer of messages between the CAN Core and the Message RAM; and the handling of transmission requests. The register set of the CAN may be accessed directly by the CPU through the module interface. These registers are used to control and configure the CAN core and the message handler, and to access the message RAM. The CAN module implements the following features:

Complies with ISO11898-1 (Bosch® CAN protocol specification 2.0 A and B)
Bit rates up to 1 Mbps
Multiple clock sources
32 message objects (“message objects” are also referred to as “mailboxes” in this document; the two terms are used interchangeably), each with the following properties: – Configurable as receive or transmit – Configurable with standard (11-bit) or extended (29-bit) identifier – Supports programmable identifier receive mask – Supports data and remote frames – Holds 0 to 8 bytes of data – Parity-checked configuration and data RAM
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus-on, after bus-off state by a programmable 32-bit timer
Message-RAM parity-check mechanism
Two interrupt lines Note For a CAN bit clock of 200 MHz, the smallest bit rate possible is 7.8125 kbps. Note Depending on the timing settings used, the accuracy of the on-chip zero-pin oscillator (specified in the data manual) may not meet the requirements of the CAN protocol. In this situation, an external clock source must be used. Figure 6-63 shows the CAN block diagram. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 139 Product Folder Links: F28377D-SEP

Object Access (IFx) Module Interface Message RAM Message Objects (Mailboxes) CAN Test Modes Only 3.3V CAN Transceiver CANx RX pin CANx TX pin CAN_H CAN_L CAN Bus CANINT0 CANINT1 CPU Bus External connections Device (to ePIE) Figure 6-63. CAN Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

140 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11.2 Inter-Integrated Circuit (I2C)

The I2C module has the following features:

Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
One 16-byte receive FIFO and one 16-byte transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: F28377D-SEP

Figure 6-64 shows how the I2C peripheral module interfaces within the device. I2CXSR I2CDXR I2CRSR I2CDRR Clock Synchronizer Prescaler Noise Filters Arbitrator I2C INT Peripheral Bus Interrupt to CPU/PIE SDA SCL Control/Status Registers CPU I C Module TX FIFO RX FIFO FIFO Interrupt to CPU/PIE Figure 6-64. I2C Peripheral Module Interfaces F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

142 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11.2.1 I2C Electrical Data and Timing

Figure 6-65 shows the I2C timing diagram. Note To meet all of the I2C protocol timing specifications, the I2C module clock must be configured in the range from 7 MHz to 12 MHz. A pullup resistor must be chosen to meet the I2C standard timings. In most circumstances, 2.2 k Ω of total bus resistance to VDDIO is sufficient. For evaluating pullup resistor values for a particular design, see the I2C Bus Pullup Resistor Calculation Application Report.

6.11.2.1.1 I2C Timing Requirements

NO. MIN MAX UNIT Standard mode T0 fmod I2C module frequency 7 12 MHz T1 th(SDA-SCL)START Hold time, START condition, SCL fall delay after SDA fall 4.0 µs T2 tsu(SCL-SDA)START Setup time, Repeated START, SCL rise before SDA fall delay 4.7 µs T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs T4 tsu(DAT-SCL) Setup time, data before SCL rise 250 ns T5 tr(SDA) Rise time, SDA 1000(1) ns T6 tr(SCL) Rise time, SCL 1000(1) ns T7 tf(SDA) Fall time, SDA 300 ns T8 tf(SCL) Fall time, SCL 300 ns T9 tsu(SCL-SDA)STOP Setup time, STOP condition, SCL rise before SDA rise delay 4.0 µs T10 tw(SP) Pulse duration of spikes that will be suppressed by filter 0 50 ns T11 Cb capacitance load on each bus line 400 pF Fast mode T0 fmod I2C module frequency 7 12 MHz T1 th(SDA-SCL)START Hold time, START condition, SCL fall delay after SDA fall 0.6 µs T2 tsu(SCL-SDA)START Setup time, Repeated START, SCL rise before SDA fall delay 0.6 µs T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs T4 tsu(DAT-SCL) Setup time, data before SCL rise 100 ns T5 tr(SDA) Rise time, SDA 20 300 ns T6 tr(SCL) Rise time, SCL 20 300 ns T7 tf(SDA) Fall time, SDA 11.4 300 ns T8 tf(SCL) Fall time, SCL 11.4 300 ns T9 tsu(SCL-SDA)STOP Setup time, STOP condition, SCL rise before SDA rise delay 0.6 µs T10 tw(SP) Pulse duration of spikes that will be suppressed by filter 0 50 ns T11 Cb capacitance load on each bus line 400 pF (1) In order to minimize the rise time, TI recommends using a strong pullup on both the SDA and SCL bus lines on the order of 2.2-kΩ net pullup resistance. It is also recommended that the value of the pullup resistance used on both SCL and SDA pins be matched. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 143 Product Folder Links: F28377D-SEP

6.11.2.1.2 I2C Switching Characteristics

over recommended operating conditions (unless otherwise noted) NO. PARAMETER TEST CONDITIONS MIN MAX UNIT Standard mode S1 fSCL SCL clock frequency 0 100 kHz S2 TSCL SCL clock period 10 µs S3 tw(SCLL) Pulse duration, SCL clock low 4.7 µs S4 tw(SCLH) Pulse duration, SCL clock high 4.0 µs S5 tBUF Bus free time between STOP and START conditions 4.7 µs S6 tv(SCL-DAT) Valid time, data after SCL fall 3.45 µs S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 3.45 µs S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA Fast mode S1 fSCL SCL clock frequency 0 400 kHz S2 TSCL SCL clock period 2.5 µs S3 tw(SCLL) Pulse duration, SCL clock low 1.3 µs S4 tw(SCLH) Pulse duration, SCL clock high 0.6 µs S5 tBUF Bus free time between STOP and START conditions 1.3 µs S6 tv(SCL-DAT) Valid time, data after SCL fall 0.9 µs S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 0.9 µs S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA

6.11.2.1.3 I2C Timing Diagram

Contd... Contd... Repeated START 9th clock STOP ACK ACK Figure 6-65. I2C Timing Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

144 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11.3 Multichannel Buffered Serial Port (McBSP)

The McBSP module has the following features:

Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
Full-duplex communication
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
8-bit data transfer mode can be configured to transmit with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices
Supports AC97, I2S, and SPI protocols
McBSP clock rate, /c40 /c41 CLKSRGCLKG = 1 + CLKGDV where CLKSRG source could be LSPCLK, CLKX, or CLKR. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 145 Product Folder Links: F28377D-SEP

Figure 6-66 shows the block diagram of the McBSP module. MDXx MDRx Expand Logic DRR1 Receive Buffer RX Interrupt RBR1 RegisterRBR2 Register MCLKXx MFSXx MCLKRx MFSRx Compand Logic DXR2 Transmit Buffer RSR1 XSR2 XSR1 Peripheral Read Bus 1616 RSR2 DXR1 Transmit BufferPERx.LSPCLK MRINT To CPU RX Interrupt Logic TX InterruptMXINT To CPU TX Interrupt Logic 1616 16 16 Peripheral Bus DRR2 Receive Buffer Peripheral Write Bus Bridge DMA BusCPU CPU CPU McBSP Transmit Interrupt Select Logic McBSP Receive Interrupt Select Logic Figure 6-66. McBSP Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

146 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11.3.1 McBSP Electrical Data and Timing

6.11.3.1.1 McBSP Transmit and Receive Timing

characteristics. Figure 6-67 and Figure 6-68 show the McBSP timing diagrams. NO.(1) (2) MIN MAX UNIT McBSP module clock (CLKG, CLKX, CLKR) range 1 kHz

25 MHz

McBSP module cycle time (CLKG, CLKX, CLKR) range 40 ns 1 ms M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 7 ns M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 18 ns CLKR ext 2 M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 0 ns CLKR ext 6 M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 18 ns CLKR ext 5 M18 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 0 ns CLKR ext 3 M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 18 ns CLKX ext 2 M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 0 ns CLKX ext 6 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2). www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 147 Product Folder Links: F28377D-SEP

over recommended operating conditions (unless otherwise noted) NO.(1) (2) PARAMETER MIN MAX UNIT M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5 (3) D + 5 (3) ns M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5 (3) C + 5 (3) ns M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -7 7.5 ns CLKR ext 3 27 M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int -5 6 ns CLKX ext 3 27 M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance following last data bit CLKX int –8 8 ns CLKX ext 3 15 M7 td(CKXH-DXV) Delay time, CLKX high to DX valid. CLKX int –3 9 ns This applies to all bits except the first bit transmitted. CLKX ext 5 25 Delay time, CLKX high to DX valid DXENA = 0 CLKX int –3 8 CLKX ext 5 20 Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 CLKX int P – 3 P + 8 CLKX ext P + 5 P + 20 M8 ten(CKXH-DX) Enable time, CLKX high to DX driven DXENA = 0 CLKX int -6 ns CLKX ext 4 Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 CLKX int P - 6 CLKX ext P + 4 M9 td(FXH-DXV) Delay time, FSX high to DX valid DXENA = 0 FSX int 8 ns FSX ext 17 Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. DXENA = 1 FSX int P + 8 FSX ext P + 17 M10 ten(FXH-DX) Enable time, FSX high to DX driven DXENA = 0 FSX int -3 ns FSX ext 6 Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode DXENA = 1 FSX int P - 3 FSX ext P + 6 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. (3) C = CLKRX low pulse width = P D = CLKRX high pulse width = P F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

148 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11.3.1.2 McBSP as SPI Master or Slave Timing

Figure 6-69 through Figure 6-72 show the McBSP as SPI master or slave timing diagrams. NO. MIN MAX UNIT CLOCK tc(CLKG) Cycle time, CLKG(1) 2 * tc(LSPCLK) ns P Cycle time, LSPCLK(1) tc(LSPCLK) ns M33, M42, M52, M61 tc(CKX) Cycle time, CLKX 2P ns CLKSTP = 10b, CLKXP = 0 M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 ns M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 ns CLKSTP = 11b, CLKXP = 0 M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 ns CLKSTP = 10b, CLKXP = 1 M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 ns CLKSTP = 11b, CLKXP = 1 M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 ns M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 ns (1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

150 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

over operating free-air temperature range (unless otherwise noted) NO. PARAMETER MIN TYP MAX UNIT CLOCK M33 tc(CLKG) Cycle time, CLKG(1) (n * tc(LSPCLK)) 40 ns P Half CLKG cycle; 0.5 * tc(CLKG) 20 ns n LSPCLK to CLKG divider 2 ns CLKSTP = 10b, CLKXP = 0 M24 th(CKXL-FXL) Hold time, FSX high after CLKX low 2P – 6 ns M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P – 6 ns M26 td(CLKXH-DXV) Delay time, CLKX high to DX valid [check clock polarity and add to timing diagram] –4 6 ns M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX low [redefine timing diagram] P – 8 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid P – 3 P + 6 ns CLKSTP = 11b, CLKXP = 0 M34 th(CKXL-FXH) Hold time, FSX high after CLKX low P – 6 ns M35 td(FXL-CKXH) Delay time, FSX low to CLKX high P – 6 ns M36 td(CLKXL-DXV) Delay time, CLKX low to DX valid [check clock polarity and add to timing diagram] –4 6 ns M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low P – 6 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns CLKSTP = 10b, CLKXP = 1 M43 th(CKXH-FXH) Hold time, FSX high after CLKX high 2P – 6 ns M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P – 6 ns M45 td(CLKXL-DXV) Delay time, CLKX low to DX valid [check clock polarity and add to timing diagram] –4 6 ns M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX low [redefine timing diagram] P – 6 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns CLKSTP = 11b, CLKXP = 1 M53 th(CKXH-FXH) Hold time, FSX high after CLKX high P – 6 ns M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P – 6 ns M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –4 6 ns M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high P – 8 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns (1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 151 Product Folder Links: F28377D-SEP

NO. MIN MAX UNIT CLOCK tc(CLKG) Cycle time, CLKG(1) 2 * tc(LSPCLK) ns P Cycle time, LSPCLK(1) tc(LSPCLK) ns M33, M42, M52, M61 tc(CKX) Cycle time, CLKX(2) 16P ns na tskew(CKX-Data) Worst skew between Clock and Data to ensure GBD for sampled clock and datas ns CLKSTP = 10b, CLKXP = 0 M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P+10 ns CLKSTP = 11b, CLKXP = 0 M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P+10 ns CLKSTP = 10b, CLKXP = 1 M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P+10 ns CLKSTP = 11b, CLKXP = 1 M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P+10 ns (1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1 (2) For SPI slave modes CLKX must be a minimum of 8 CLKG cycles F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

152 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

over operating free-air temperature range (unless otherwise noted) NO. PARAMETER MIN TYP MAX UNIT CLOCK 2P Cycle time, CLKG ns CLKSTP = 10b, CLKXP = 0 M26 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6P + 6 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns CLKSTP = 11b, CLKXP = 0 M36 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7P + 6 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns CLKSTP = 10b, CLKXP = 1 M45 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6P + 6 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns CLKSTP = 11b, CLKXP = 1 M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7P + 6 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX M30 M31 DR M24 M29 M25 LSB MSBM32 M33 M28 M26 Figure 6-69. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M35 M37 M40M39 M38 M34 LSB MSBM41 M42 M36 Figure 6-70. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 153 Product Folder Links: F28377D-SEP

Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M44 M48 M49 M43 LSB MSB M52 M47 M45 Figure 6-71. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M54 M58 M56 M53 M55 M59 M57 LSB MSBM60 M61 Figure 6-72. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

154 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11.4 Serial Communications Interface (SCI)

The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit baud-select register. Figure 6-73 shows the SCI block diagram. Features of the SCI module include:

Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin Note NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates
Data-word format – One start bit – Data-word length programmable from 1 to 8 bits – Optional even/odd/no parity bit – 1 or 2 stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wakeup multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Auto baud-detect hardware logic
16-level transmit and receive FIFO Note All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 155 Product Folder Links: F28377D-SEP

TX FIFO_0 TX FIFO_1 TX FIFO_N Transmit Data Buffer Register SCITXBUF.7-0 RXSHF Register RX FIFO_0 RX FIFO_1 RX FIFO_N Receive Data Buffer Register SCIRXBUF.7-0 RXENA SCICTL1.0 TX FIFO Interrupts RX FIFO Interrupts Baud Rate MSB/LSB Registers SCIHBAUD.15-8 SCILBAUD.7-0 LSPCLK Frame Format and Mode Parity SCICCR.6 SCICCR.5 Even/Odd Enable SCICTL1.3 TXWAKE WUT SCICTL1.1 TXENA RXENA SCICTL2.6 TXEMPTY RXFFOVF SCICTL2.7 TXRDY SCICTL2.0 TXINTENA SCIRXST.6 RXRDY SCIRXST.5 BRKDT SCICTL2.1 RXBKINTENA TX Interrupt Logic RX Interrupt Logic SCIRXST.7 RXERROR SCICTL1.6 RXERRINTENA SCI RX Interrupt Select Logic 0 1 0 1 0 1 0 1 SCIFFENA SCIFFTX.14 RXWAKE SCIRXST.1 Auto Baud Detect Logic TXINT To CPU RXINT To CPU SCITXD SCIRXD BRKDT FE OE PE SCIRXST.5-2 SCICTL1.0 SCIFFRX.15 SCI TX Interrupt Select Logic Figure 6-73. SCI Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

156 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

The major elements used in full-duplex operation include:

A transmitter (TX) and its major registers: – SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be transmitted – TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto the SCITXD pin, 1 bit at a time
A receiver (RX) and its major registers: – RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time – SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU registers
A programmable baud generator
Data-memory-mapped control and status registers enable the CPU to access the I2C module registers and FIFOs. The SCI receiver and transmitter operate independently. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 157 Product Folder Links: F28377D-SEP

6.11.5 Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the microcontroller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The port supports 16-level receive and transmit FIFOs for reducing CPU servicing overhead. The SPI module features include:

SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Two operational modes: master and slave
Baud rate: 125 different programmable rates
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
16-level transmit and receive FIFO
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
DMA support
High-speed mode for up to 50-MHz full-duplex communication The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive data simultaneously. The application software determines whether the data is meaningful or dummy data. There are three possible methods for data transmission:
Master sends data; slave sends dummy data
Master sends data; slave sends data
Master sends dummy data; slave sends data The master can initiate a data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

158 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: F28377D-SEP

6.11.5.1 SPI Electrical Data and Timing

All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK, SPISIMO, and SPISOMI. For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see Section 5.4.5).

6.11.5.1.1 SPI Master Mode Timings

characteristics (clock phase = 1). Figure 6-75 shows the SPI master mode external timing where the clock phase = 0. Figure 6-76 shows the SPI master mode external timing where the clock phase = 1. NO. (BRR + 1) CONDITION(1) MIN MAX UNIT High Speed Mode 8 tsu(SOMI)M Setup time, SPISOMI valid before SPICLK Even, Odd 1 ns 9 th(SOMI)M Hold time, SPISOMI valid after SPICLK Even, Odd 5 ns Normal Mode 8 tsu(SOMI)M Setup time, SPISOMI valid before SPICLK Even, Odd 20 ns 9 th(SOMI)M Hold time, SPISOMI valid after SPICLK Even, Odd 0 ns (1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is greater than 3. over recommended operating conditions (unless otherwise noted) NO. PARAMETER (BRR + 1) CONDITION(1) MIN MAX UNIT General 1 tc(SPC)M Cycle time, SPICLK Even 4tc(LSPCLK) 128tc(LSPCLK) ns Odd 5tc(LSPCLK) 127tc(LSPCLK) 2 tw(SPC1)M Pulse duration, SPICLK, first pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M +0.5tc(LSPCLK) – 1 0.5tc(SPC)M +0.5tc(LSPCLK) + 1 3 tw(SPC2)M Pulse duration, SPICLK, second pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – 0.5tc(SPC)M –0.5tc(LSPCLK) + 1 23 td(SPC)M Delay time, SPISTE active to SPICLK Even 1.5tc(SPC)M - 3tc(SYSCLK) – 1.5tc(SPC)M - 3tc(SYSCLK) + ns Odd 1.5tc(SPC)M - 4tc(SYSCLK) – 1.5tc(SPC)M - 4tc(SYSCLK) + F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

over recommended operating conditions (unless otherwise noted) NO. PARAMETER (BRR + 1) CONDITION(1) MIN MAX UNIT 24 tv(STE)M Valid time, SPICLK to SPISTE inactive Even 0.5tc(SPC)M – 7 0.5tc(SPC)M + 5 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – 0.5tc(SPC)M –0.5tc(LSPCLK) + 5 High Speed Mode 4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 1 ns 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 2 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – Normal Mode 4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 6 ns 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 5 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – (1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is greater than 3. over recommended operating conditions (unless otherwise noted) NO. PARAMETER (BRR + 1) CONDITION(1) MIN MAX UNIT General 1 tc(SPC)M Cycle time, SPICLK Even 4tc(LSPCLK) 128tc(LSPCLK) ns Odd 5tc(LSPCLK) 127tc(LSPCLK) 2 tw(SPCH)M Pulse duration, SPICLK, first pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.5tc(LSPCLK) + 1 3 tw(SPC2)M Pulse duration, SPICLK, second pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1 23 td(SPC)M Delay time, SPISTE valid to SPICLK Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 7 2tc(SPC)M – 3tc(SYSCLK) + 5 ns 24 tv(STE)M Valid time, SPICLK to SPISTE invalid Even – 7 +5 ns Odd – 7 +5 High Speed Mode 4 td(SIMO)M Delay time, SPISIMO valid to SPICLK Even 0.5tc(SPC)M – 1 ns Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 2 ns Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 2 Normal Mode 4 td(SIMO)M Delay time, SPISIMO valid to SPICLK Even 0.5tc(SPC)M – 5 ns Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 5 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 5 ns Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 5 (1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is greater than 3. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: F28377D-SEP

(clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is V alid SPISTE (A) 23 24 A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-75. SPI Master Mode External Timing (Clock Phase = 0) SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is V alid 23 24 SPISTE (A) A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-76. SPI Master Mode External Timing (Clock Phase = 1) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

6.11.5.1.2 SPI Slave Mode Timings

switching characteristics. Figure 6-77 shows the SPI slave mode external timing where the clock phase = 0. Figure 6-78 shows the SPI slave mode external timing where the clock phase = 1. NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns 13 tw(SPC1)S Pulse duration, SPICLK, first pulse 2tc(SYSCLK) – 1 ns 14 tw(SPC2)S Pulse duration, SPICLK, second pulse 2tc(SYSCLK) – 1 ns 19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns 20 th(SIMO)S Hold time, SPISIMO valid after SPICLK 1.5tc(SYSCLK) ns 25 tsu(STE)S Setup time, SPISTE valid before SPICLK (Clock Phase = 0) 2tc(SYSCLK) + 4 ns Setup time, SPISTE valid before SPICLK (Clock Phase = 1) 2tc(SYSCLK) + 14 ns 26 th(STE)S Hold time, SPISTE invalid after SPICLK 1.5tc(SYSCLK) ns over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN MAX UNIT High Speed Mode 15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 9 ns 16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns Normal Mode 15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 20 ns 16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 163 Product Folder Links: F28377D-SEP

(clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid SPISTE Figure 6-77. SPI Slave Mode External Timing (Clock Phase = 0) SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid 19 16 SPISTE Data ValidData Valid 1413 25 26 Figure 6-78. SPI Slave Mode External Timing (Clock Phase = 1) F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

6.11.6 Universal Serial Bus (USB) Controller

The USB controller operates as a full-speed or low-speed function controller during point-to-point communications with USB host or device functions. The USB module has the following features:

USB 2.0 full-speed and low-speed operation
Integrated PHY
Three transfer types: control, interrupt, and bulk
32 endpoints – One dedicated control IN endpoint and one dedicated control OUT endpoint – 15 configurable IN endpoints and 15 configurable OUT endpoints
4KB of dedicated endpoint memory Figure 6-79 shows the USB block diagram. Packet Encode/Decode Endpoint Control EP0 –31 Control Transmit Receive Combine Endpoints Host Transaction Scheduler Packet Encode Packet Decode CRC Gen/Check FIFO RAM Controller Cycle Control Rx Buff Rx Buff Tx Buff Tx Buff CPU Interface Interrupt Control EP Reg. Decoder Common Regs Cycle Control FIFO Decoder Interrupts CPU BusUTM Synchronization Data Sync HNP/SRP Timers USB FS/LS PHY USB DataLines D+ andD- Figure 6-79. USB Block Diagram Note The accuracy of the on-chip zero-pin oscillator ( Section 6.8.3.5.1, Internal Oscillator Electrical Characteristics) will not meet the accuracy requirements of the USB protocol. An external clock source must be used for applications using USB. For applications using the USB boot mode, see Section 7.10 (Boot ROM and Peripheral Booting) for clock frequency requirements. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: F28377D-SEP

6.11.6.1 USB Electrical Data and Timing

USB output ports DP and DM switching characteristics.

6.11.6.1.1 USB Input Ports DP and DM Timing Requirements

V(CM) Differential input common mode range 0.8 2.5 V Z(IN) Input impedance 300 kΩ VCRS Crossover voltage 1.3 2.0 V VIL Static SE input logic-low level 0.8 V VIH Static SE input logic-high level 2.0 V VDI Differential input voltage 0.2 V

6.11.6.1.2 USB Output Ports DP and DM Switching Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VOH D+, D– single-ended USB 2.0 load conditions 2.8 3.6 V VOL D+, D– single-ended USB 2.0 load conditions 0 0.3 V Z(DRV) D+, D– impedance 28 44 Ω tr Rise time Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 20 ns tf Fall time Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 20 ns F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

6.11.7 Universal Parallel Port (uPP) Interface

The uPP interface is a high-speed parallel interface with dedicated data lines and minimal control signals. The uPP interface is designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width. It can also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode or transmit mode (simplex mode). The uPP interface includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use internal DMA to feed data to or retrieve data from the I/O channels. Even though there is only one I/O channel, the DMA controller includes two DMA channels to support data interleave mode, in which all DMA resources service a single I/O channel. On this device, the uPP interface is the dedicated resource for the CPU1 subsystem. CPU1, CPU1.CLA1, and CPU1.DMA have access to this module. Two dedicated 512-byte data RAMs (also known as MSG RAMs) are tightly coupled with the uPP module (one for each, TX and RX). These data RAMs are used to store the bulk of data to avoid frequent interruptions to the CPU. Only CPU1 and CPU1.CLA1 have access to these data RAMs. Figure 6-80 shows the integration of the uPP on this device. CPU1.CLA1 CPU1.DMA Arbi t Arbiter X SECMSEL.PF2SEL uPP (Universal Parallel Port) RX -DATARAM

512 Byte

(Dual Port Memory) TX -DATARAM (Dual Port Memory) Arbi t CPU1 Arbiter Y Arbi t Arbiter Y CPU1 CPU1.CLA1 CPU1 CPU1.CLA1 WRITE READ I/O Interface uPP DMA READ uPP DMA WRITE Figure 6-80. uPP Integration Note On some TI devices, the uPP module is also called the Radio Peripheral Interface (RPI) module. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 167 Product Folder Links: F28377D-SEP

The uPP interface supports the following:

Mainstream high-speed data converters with parallel conversion interface.
Mainstream high-speed streaming interface with frame START indication.
Mainstream high-speed streaming interface with data ENABLE indication.
Mainstream high-speed streaming interface with synchronization WAIT signal.
SDR (single-data-rate) or DDR (double-data-rate, interleaved) interface.
Multiplexing of interleaved data in SDR transmit case.
Demultiplexing and multiplexing of interleaved data in DDR case.
I/O interface clock frequency up to 50 MHz for SDR, and 25 MHz for DDR.
Single-channel 8-bit input receive or output transmit mode.
Max throughput is 50MB/s for pure read or pure write.
Available as a DSP to FPGA general-purpose streaming interface. Figure 6-81 shows the uPP functional block diagram. Arbit Internal DMA Arbi t I-FIFO Arbi Q-FIFO Data Interleaving (TX/RX)

64 Bit

CLKDIVIDERCPU1.SYSCLK Receive Timing and ControlInterrupt/Trigger Configuration I/F G P I O M U X and I/O C O N T R O L ENABLE OUT START OUT WAIT IN ENABLE IN START IN WAIT OUT ENABLE/GPIOx ST ART/GPIOx WAIT/GPIOx CLK OUT CLK IN CLK/GPIOx DATA OUT DATA IN DATA[7:0]/GPIOx uPP Control Mux MMR Figure 6-81. uPP Functional Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

6.11.7.1 uPP Electrical Data and Timing characteristics. Figure 6-82 through Figure 6-85 show the uPP timing diagrams. 6.11.7.1.1 uPP Timing Requirements NO. MIN MAX UNIT 1 tc(CLK) Cycle time, CLK SDR mode 20 ns DDR mode 40 2 tw(CLKH) Pulse width, CLK high SDR mode 8 ns DDR mode 18 3 tw(CLKL) Pulse width, CLK low SDR mode 8 ns DDR mode 18 4 tsu(STV-CLKH) Setup time, START valid before CLK high 4 ns 5 th(CLKH-STV) Hold time, START valid after CLK high 0.8 ns 6 tsu(ENV-CLKH) Setup time, ENABLE valid before CLK high 4 ns 7 th(CLKH-ENV) Hold time, ENABLE valid after CLK high 0.8 ns 8 tsu(DV-CLKH) Setup time, DATA valid before CLK high 4 ns 9 th(CLKH-DV) Hold time, DATA valid after CLK high 0.8 ns 10 tsu(DV-CLKL) Setup time, DATA valid before CLK low 4 ns 11 th(CLKL-DV) Hold time, DATA valid after CLK low 0.8 ns 19 tsu(WTV-CLKH) Setup time, WAIT valid before CLK high SDR mode 20 ns 20 th(CLKH-WTV) Hold time, WAIT valid after CLK high SDR mode 0 ns 21 tsu(WTV-CLKL) Setup time, WAIT valid before CLK low DDR mode 20 ns 22 th(CLKL-WTV) Hold time, WAIT valid after CLK low DDR mode 0 ns 6.11.7.1.2 uPP Switching Characteristics over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN MAX UNIT 12 tc(CLK) Cycle time, CLK SDR mode 20 ns DDR mode 40 13 tw(CLKH) Pulse width, CLK high SDR mode 8 ns DDR mode 18 14 tw(CLKL) Pulse width, CLK low SDR mode 8 ns DDR mode 18 15 td(CLKH-STV) Delay time, START valid after CLK high 3 12 ns 16 td(CLKH-ENV) Delay time, ENABLE valid after CLK high 3 12 ns 17 td(CLKH-DV) Delay time, DATA valid after CLK high 3 12 ns 18 td(CLKL-DV) Delay time, DATA valid after CLK low 3 12 ns www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: F28377D-SEP

DA T A[n:0] Data2Data1 Data3 Data4 WAIT Data5 Data6 Data7 Data8 Data9 Figure 6-82. uPP Single Data Rate (SDR) Receive Timing 21 3 Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 CLK ST ART ENABLE DA T A[n:0] WAIT Figure 6-83. uPP Double Data Rate (DDR) Receive Timing F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7 Detailed Description

7.1 Overview

The TMS320F2837xD is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial motor drives ; solar inverters and digital power ; electrical vehicles and transportation ; and sensing and signal processing . Complete development packages for digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives. The F2837xD supports a new dual-core C28x architecture that significantly boosts system performance. The integrated analog and control peripherals also let designers consolidate control architectures and eliminate multiprocessor use in high-end systems. The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide 200 MHz of signal processing performance in each core. The C28x CPUs are further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex math operations common in encoded applications. The F2837xD microcontroller family features two CLA real-time control coprocessors. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. The dual C28x+CLA architecture enables intelligent partitioning between various system tasks. For example, one C28x+CLA core can be used to track speed and position, while the other C28x+CLA core can be used to control torque and current loops. The TMS320F2837xD supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC) and up to 204KB (102KW) of SRAM. Two 128-bit secure zones are also available on each CPU for code protection. Performance analog and control peripherals are also integrated on the F2837xD MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals. Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F2837xD. The uPP interface is a new feature of the C2000 MCUs and supports high- speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application. Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000 ™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page. The Getting Started With C2000 ™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out the TMDSCNCD28379D or LAUNCHXL-F28379D evaluation boards and download C2000Ware. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.2 Functional Block Diagram

The Functional Block Diagram shows the CPU system and associated peripherals on the F2837xD devices. See Table 4-1 for the features and peripherals that are available on the F28377D-SEP device. 16-/12-bit ADC Analog MUX ADC Result Regs Peripheral Frame 1 Global Shared 16x 4Kx16 GS0-GS15 RAMs CPU1 to CPU2 1Kx16 MSG RAM GPIO MUX, Input X-BAR, Output X-BAR CPU1.M0 RAM 1Kx16 CPU1.M1 RAM 1Kx16 CPU2.M0 RAM 1Kx16 CPU2.M1 RAM 1Kx16 PSWDPSWD Secure Memories shown in Red MEMCPU2 CPU2 to CPU1 1Kx16 MSG RAM MEMCPU1 CPU1 Buses CPU2 Buses A5:0 B5:0 C5:2 ADCIN14 ADCIN15 D5:0 Comparator Subsystem (CMPSS) DAC Config CPU1.CLA1 Bus CPU2.CLA1 Bus C28 CPU-1 FPU VCU-II TMU CPU Timer 0 CPU Timer 1 CPU Timer 2 ePIE (up to 192 interrupts) WD Timer NMI-WDT C28 CPU-2 FPU VCU-II TMU CPU Timer 0 CPU Timer 1 CPU Timer 2 ePIE (up to 192 interrupts) WD Timer NMI-WDTCPU1.CLA1 Data ROM (4Kx16) CPU1.CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1.CLA1 128x16 MSG RAM CPU1.D0 RAM 2Kx16 CPU1.D1 RAM 2Kx16 Boot-ROM 32Kx16 Nonsecure Secure-ROM 32Kx16 Secure CPU1 Local Shared 6x 2Kx16 LS0-LS5 RAMs CPU2 to CPU2.CLA1 128x16 MSG RAM CPU2.CLA1 to CPU2 128x16 MSG RAM CPU2.D0 RAM 2Kx16 CPU2.D1 RAM 2Kx16 CPU2.CLA1 Data ROM (4Kx16) Boot-ROM 32Kx16 Nonsecure Secure-ROM 32Kx16 Secure CPU2 Local Shared LS0-LS5 RAMs CPU1.CLA1 CPU1.DMA CPU2.DMA CPU2.CLA1 Data Bus Bridge ePWM-1/../12 eCAP- 1/../6 eQEP-1/2/3 SDFM-1/2 EXTSYNCINEXTSYNCOUTTZ1-TZ6 ECAPxEQEPxAEQEPxBEPWMxAEPWMxB EQEPxIEQEPxSSDx_DySDx_Cy A B C D JTAG AUXCLKIN External Crystal or Oscillator Watchdog 1/2 Main PLL Aux PLL INTOSC1 INTOSC2 Low-Power Mode Control GPIO MUX TRST TCK TDI TMS TDO 6x 2Kx16 Dual Code Security Module Emulation Code Security Logic (ECSL) Dual Code Security Module Emulation Code Security Logic (ECSL) Interprocessor Communication (IPC) Module PUMP OTP/Flash Wrapper FLASH 256K x 16 Secure User Configurable DCSM OTP 1K x 16 OTP/Flash Wrapper FLASH 256K x 16 Secure User Configurable DCSM OTP 1K x 16 SCI- A/B/C/D (16L FIFO) I2C-A/B (16L FIFO) Data Bus Bridge SCITXDx SCIRXDx SDAxSCLx CAN- A/B (32-MBOX) Data Bus Bridge CANRXx CANTXx GPIO Data Bus Bridge GPIOn Data Bus Bridge USB Ctrl / PHY USBDPUSBDM USB Ctrl / PHY EMIF1 Data Bus Bridge EM1DxEM1AxEM1CTLx EMIF2 Data Bus Bridge EM2DxEM2AxEM2CTLx Peripheral Frame 2 SPI- A/B/C (16L FIFO) SPISIMOxSPISOMIxSPICLKxSPISTEx McBSP- A/B MDXxMDRxMCLKXxMCLKRxMFSXxMFSRx uPP RAM UPPAD[7:0]UPPAENUPPASTUPPAWTUPPACLK HRPWM-1/../8 (CPU1 only) Figure 7-1. F2837xD Functional Block Diagram www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 173 Product Folder Links: F28377D-SEP

7.3 Memory

7.3.1 C28x Memory Map

Both C28x CPUs on the device have the same memory map except where noted in Table 7-1. The GSx_RAM (Global Shared RAM) should be assigned to either CPU by the GSxMSEL register. Memories accessible by the CLA or DMA (direct memory access) are noted as well. Table 7-1. C28x Memory Map MEMORY SIZE START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS M0 RAM 1K × 16 0x0000 0000 0x0000 03FF M1 RAM 1K × 16 0x0000 0400 0x0000 07FF PieVectTable 512 × 16 0x0000 0D00 0x0000 0EFF CPUx.CLA1 to CPUx MSGRAM 128 × 16 0x0000 1480 0x0000 14FF Yes CPUx to CPUx.CLA1 MSGRAM 128 × 16 0x0000 1500 0x0000 157F Yes UPP TX MSG RAM 512 × 16 0x0000 6C00 0x0000 6DFF Yes (CPU1.CLA1 only) UPP RX MSG RAM 512 × 16 0x0000 6E00 0x0000 6FFF Yes (CPU1.CLA1 only) LS0 RAM 2K × 16 0x0000 8000 0x0000 87FF Yes LS1 RAM 2K × 16 0x0000 8800 0x0000 8FFF Yes LS2 RAM 2K × 16 0x0000 9000 0x0000 97FF Yes LS3 RAM 2K × 16 0x0000 9800 0x0000 9FFF Yes LS4 RAM 2K × 16 0x0000 A000 0x0000 A7FF Yes LS5 RAM 2K × 16 0x0000 A800 0x0000 AFFF Yes D0 RAM 2K × 16 0x0000 B000 0x0000 B7FF D1 RAM 2K × 16 0x0000 B800 0x0000 BFFF GS0 RAM(1) 4K × 16 0x0000 C000 0x0000 CFFF Yes GS1 RAM(1) 4K × 16 0x0000 D000 0x0000 DFFF Yes GS2 RAM(1) 4K × 16 0x0000 E000 0x0000 EFFF Yes GS3 RAM(1) 4K × 16 0x0000 F000 0x0000 FFFF Yes GS4 RAM(1) 4K × 16 0x0001 0000 0x0001 0FFF Yes GS5 RAM(1) 4K × 16 0x0001 1000 0x0001 1FFF Yes GS6 RAM(1) 4K × 16 0x0001 2000 0x0001 2FFF Yes GS7 RAM(1) 4K × 16 0x0001 3000 0x0001 3FFF Yes GS8 RAM(1) 4K × 16 0x0001 4000 0x0001 4FFF Yes GS9 RAM(1) 4K × 16 0x0001 5000 0x0001 5FFF Yes GS10 RAM(1) 4K × 16 0x0001 6000 0x0001 6FFF Yes GS11 RAM(1) 4K × 16 0x0001 7000 0x0001 7FFF Yes GS12 RAM(1) 4K × 16 0x0001 8000 0x0001 8FFF Yes GS13 RAM(1) 4K × 16 0x0001 9000 0x0001 9FFF Yes GS14 RAM(1) 4K × 16 0x0001 A000 0x0001 AFFF Yes GS15 RAM(1) 4K × 16 0x0001 B000 0x0001 BFFF Yes CPU2 to CPU1 MSGRAM(1) 1K × 16 0x0003 F800 0x0003 FBFF Yes CPU1 to CPU2 MSGRAM(1) 1K × 16 0x0003 FC00 0x0003 FFFF Yes CAN A Message RAM(1) 2K × 16 0x0004 9000 0x0004 97FF CAN B Message RAM(1) 2K × 16 0x0004 B000 0x0004 B7FF Flash 256K × 16 0x0008 0000 0x000B FFFF Secure ROM 32K × 16 0x003F 0000 0x003F 7FFF Boot ROM 32K × 16 0x003F 8000 0x003F FFBF Vectors 64 × 16 0x003F FFC0 0x003F FFFF (1) Shared between CPU subsystems. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.3.2 Flash Memory Map

On the F28377D-SEP device, each CPU has its own flash bank [512KB (256KW)], the total flash for each device is 1MB (512KW). Only one bank can be programmed or erased at a time and the code to program the flash should be executed out of RAM. The following table shows the addresses of flash sectors on CPU1 and CPU2 for F28377D-SEP. Table 7-2. Addresses of Flash Sectors on CPU1 and CPU2 for F28377D-SEP SECTOR SIZE START ADDRESS END ADDRESS OTP Sectors TI OTP 1K x 16 0x0007 0000 0x0007 03FF User configurable DCSM OTP 1K x 16 0x0007 8000 0x0007 83FF Sectors Sector 0 8K x 16 0x0008 0000 0x0008 1FFF Sector 1 8K x 16 0x0008 2000 0x0008 3FFF Sector 2 8K x 16 0x0008 4000 0x0008 5FFF Sector 3 8K x 16 0x0008 6000 0x0008 7FFF Sector 4 32K x 16 0x0008 8000 0x0008 FFFF Sector 5 32K x 16 0x0009 0000 0x0009 7FFF Sector 6 32K x 16 0x0009 8000 0x0009 FFFF Sector 7 32K x 16 0x000A 0000 0x000A 7FFF Sector 8 32K x 16 0x000A 8000 0x000A FFFF Sector 9 32K x 16 0x000B 0000 0x000B 7FFF Sector 10 8K x 16 0x000B 8000 0x000B 9FFF Sector 11 8K x 16 0x000B A000 0x000B BFFF Sector 12 8K x 16 0x000B C000 0x000B DFFF Sector 13 8K x 16 0x000B E000 0x000B FFFF Flash ECC Locations TI OTP ECC 128 x 16 0x0107 0000 0x0107 007F User-configurable DCSM OTP ECC 128 x 16 0x0107 1000 0x0107 107F Flash ECC (Sector 0) 1K x 16 0x0108 0000 0x0108 03FF Flash ECC (Sector 1) 1K x 16 0x0108 0400 0x0108 07FF Flash ECC (Sector 2) 1K x 16 0x0108 0800 0x0108 0BFF Flash ECC (Sector 3) 1K x 16 0x0108 0C00 0x0108 0FFF Flash ECC (Sector 4) 4K x 16 0x0108 1000 0x0108 1FFF Flash ECC (Sector 5) 4K x 16 0x0108 2000 0x0108 2FFF Flash ECC (Sector 6) 4K x 16 0x0108 3000 0x0108 3FFF Flash ECC (Sector 7) 4K x 16 0x0108 4000 0x0108 4FFF Flash ECC (Sector 8) 4K x 16 0x0108 5000 0x0108 5FFF Flash ECC (Sector 9) 4K x 16 0x0108 6000 0x0108 6FFF Flash ECC (Sector 10) 1K x 16 0x0108 7000 0x0108 73FF Flash ECC (Sector 11) 1K x 16 0x0108 7400 0x0108 77FF www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 175 Product Folder Links: F28377D-SEP

Table 7-2. Addresses of Flash Sectors on CPU1 and CPU2 for F28377D-SEP (continued) SECTOR SIZE START ADDRESS END ADDRESS Flash ECC (Sector 12) 1K x 16 0x0108 7800 0x0108 7BFF Flash ECC (Sector 13) 1K x 16 0x0108 7C00 0x0108 7FFF

7.3.3 EMIF Chip Select Memory Map

The EMIF1 memory map is the same for both CPU subsystems. EMIF2 is available only on the CPU1 subsystem. The EMIF memory map is shown in Table 7-3. Table 7-3. EMIF Chip Select Memory Map EMIF CHIP SELECT SIZE(2) START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS EMIF1_CS0n - Data 256M × 16 0x8000 0000 0x8FFF FFFF Yes EMIF1_CS2n - Program + Data(3) 2M × 16 0x0010 0000 0x002F FFFF Yes EMIF1_CS3n - Program + Data 512K × 16 0x0030 0000 0x0037 FFFF Yes EMIF1_CS4n - Program + Data 393K × 16 0x0038 0000 0x003D FFFF Yes EMIF2_CS0n - Data(1) 32M × 16 0x9000 0000 0x91FF FFFF EMIF2_CS2n - Program + Data(1) 4K × 16 0x0000 2000 0x0000 2FFF Yes (Data only) (1) Available only on the CPU1 subsystem. (2) Available memory size listed in this table is the maximum possible size assuming 32-bit memory. This may not apply to other memory sizes because of pin mux setting. See Section 5.4.1 to find the available address lines for your use case. (3) The 2M × 16 size is for a 32-bit interface with the assumption that 16-bit accesses are not performed; hence, byte enables are not used (tied to active value on board). If byte enables are used, then the maximum size is smaller because byte enables are muxed with address pins (see Section 5.4.1) . If 16-bit memory is used, then the maximum size is 1M × 16.

7.3.4 Peripheral Registers Memory Map

The peripheral registers memory map can be found in Table 7-4. The peripheral registers can be assigned to either the CPU1 or CPU2 subsystems except where noted in Table 7-4. Registers in the peripheral frames share a secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for details on the CPU subsystem and secondary master selection. Note None of the device peripherals have program bus access. Table 7-4. Peripheral Registers Memory Map REGISTERS STRUCTURE NAME START ADDRESS END ADDRESS PROTECTED (1) CLA ACCESS DMA ACCESS AdcaResultRegs ADC_RESULT_REGS 0x0000 0B00 0x0000 0B1F Yes Yes AdcbResultRegs ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes AdccResultRegs ADC_RESULT_REGS 0x0000 0B40 0x0000 0B5F Yes Yes AdcdResultRegs ADC_RESULT_REGS 0x0000 0B60 0x0000 0B7F Yes Yes CpuTimer0Regs (2) CPUTIMER_REGS 0x0000 0C00 0x0000 0C07 CpuTimer1Regs (2) CPUTIMER_REGS 0x0000 0C08 0x0000 0C0F CpuTimer2Regs (2) CPUTIMER_REGS 0x0000 0C10 0x0000 0C17 PieCtrlRegs (2) (5) PIE_CTRL_REGS 0x0000 0CE0 0x0000 0CFF Cla1SoftIntRegs (5) CLA_SOFTINT_REGS 0x0000 0CE0 0x0000 0CFF Yes – CLA only, no CPU access DmaRegs (2) DMA_REGS 0x0000 1000 0x0000 11FF Cla1Regs (2) CLA_REGS 0x0000 1400 0x0000 147F Peripheral Frame 1 EPwm1Regs EPWM_REGS 0x0000 4000 0x0000 40FF Yes Yes Yes F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

Table 7-4. Peripheral Registers Memory Map (continued) REGISTERS STRUCTURE NAME START ADDRESS END ADDRESS PROTECTED (1) CLA ACCESS DMA ACCESS EPwm2Regs EPWM_REGS 0x0000 4100 0x0000 41FF Yes Yes Yes EPwm3Regs EPWM_REGS 0x0000 4200 0x0000 42FF Yes Yes Yes EPwm4Regs EPWM_REGS 0x0000 4300 0x0000 43FF Yes Yes Yes EPwm5Regs EPWM_REGS 0x0000 4400 0x0000 44FF Yes Yes Yes EPwm6Regs EPWM_REGS 0x0000 4500 0x0000 45FF Yes Yes Yes EPwm7Regs EPWM_REGS 0x0000 4600 0x0000 46FF Yes Yes Yes EPwm8Regs EPWM_REGS 0x0000 4700 0x0000 47FF Yes Yes Yes EPwm9Regs EPWM_REGS 0x0000 4800 0x0000 48FF Yes Yes Yes EPwm10Regs EPWM_REGS 0x0000 4900 0x0000 49FF Yes Yes Yes EPwm11Regs EPWM_REGS 0x0000 4A00 0x0000 4AFF Yes Yes Yes EPwm12Regs EPWM_REGS 0x0000 4B00 0x0000 4BFF Yes Yes Yes ECap1Regs ECAP_REGS 0x0000 5000 0x0000 501F Yes Yes Yes ECap2Regs ECAP_REGS 0x0000 5020 0x0000 503F Yes Yes Yes ECap3Regs ECAP_REGS 0x0000 5040 0x0000 505F Yes Yes Yes ECap4Regs ECAP_REGS 0x0000 5060 0x0000 507F Yes Yes Yes ECap5Regs ECAP_REGS 0x0000 5080 0x0000 509F Yes Yes Yes ECap6Regs ECAP_REGS 0x0000 50A0 0x0000 50BF Yes Yes Yes EQep1Regs EQEP_REGS 0x0000 5100 0x0000 513F Yes Yes Yes EQep2Regs EQEP_REGS 0x0000 5140 0x0000 517F Yes Yes Yes EQep3Regs EQEP_REGS 0x0000 5180 0x0000 51BF Yes Yes Yes DacaRegs DAC_REGS 0x0000 5C00 0x0000 5C0F Yes Yes Yes DacbRegs DAC_REGS 0x0000 5C10 0x0000 5C1F Yes Yes Yes DaccRegs DAC_REGS 0x0000 5C20 0x0000 5C2F Yes Yes Yes Cmpss1Regs CMPSS_REGS 0x0000 5C80 0x0000 5C9F Yes Yes Yes Cmpss2Regs CMPSS_REGS 0x0000 5CA0 0x0000 5CBF Yes Yes Yes Cmpss3Regs CMPSS_REGS 0x0000 5CC0 0x0000 5CDF Yes Yes Yes Cmpss4Regs CMPSS_REGS 0x0000 5CE0 0x0000 5CFF Yes Yes Yes Cmpss5Regs CMPSS_REGS 0x0000 5D00 0x0000 5D1F Yes Yes Yes Cmpss6Regs CMPSS_REGS 0x0000 5D20 0x0000 5D3F Yes Yes Yes Cmpss7Regs CMPSS_REGS 0x0000 5D40 0x0000 5D5F Yes Yes Yes Cmpss8Regs CMPSS_REGS 0x0000 5D60 0x0000 5D7F Yes Yes Yes Sdfm1Regs SDFM_REGS 0x0000 5E00 0x0000 5E7F Yes Yes Yes Sdfm2Regs SDFM_REGS 0x0000 5E80 0x0000 5EFF Yes Yes Yes Peripheral Frame 2 McbspaRegs MCBSP_REGS 0x0000 6000 0x0000 603F Yes Yes Yes McbspbRegs MCBSP_REGS 0x0000 6040 0x0000 607F Yes Yes Yes SpiaRegs SPI_REGS 0x0000 6100 0x0000 610F Yes Yes Yes SpibRegs SPI_REGS 0x0000 6110 0x0000 611F Yes Yes Yes SpicRegs SPI_REGS 0x0000 6120 0x0000 612F Yes Yes Yes UppRegs (3) UPP_REGS 0x0000 6200 0x0000 62FF Yes Yes Yes WdRegs (2) WD_REGS 0x0000 7000 0x0000 703F Yes NmiIntruptRegs (2) NMI_INTRUPT_REGS 0x0000 7060 0x0000 706F Yes XintRegs (2) XINT_REGS 0x0000 7070 0x0000 707F Yes SciaRegs SCI_REGS 0x0000 7200 0x0000 720F Yes ScibRegs SCI_REGS 0x0000 7210 0x0000 721F Yes ScicRegs SCI_REGS 0x0000 7220 0x0000 722F Yes ScidRegs SCI_REGS 0x0000 7230 0x0000 723F Yes I2caRegs I2C_REGS 0x0000 7300 0x0000 733F Yes www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 177 Product Folder Links: F28377D-SEP

Table 7-4. Peripheral Registers Memory Map (continued) REGISTERS STRUCTURE NAME START ADDRESS END ADDRESS PROTECTED (1) CLA ACCESS DMA ACCESS I2cbRegs I2C_REGS 0x0000 7340 0x0000 737F Yes AdcaRegs ADC_REGS 0x0000 7400 0x0000 747F Yes Yes AdcbRegs ADC_REGS 0x0000 7480 0x0000 74FF Yes Yes AdccRegs ADC_REGS 0x0000 7500 0x0000 757F Yes Yes AdcdRegs ADC_REGS 0x0000 7580 0x0000 75FF Yes Yes InputXbarRegs (3) INPUT_XBAR_REGS 0x0000 7900 0x0000 791F Yes XbarRegs (3) XBAR_REGS 0x0000 7920 0x0000 793F Yes TrigRegs (3) TRIG_REGS 0x0000 7940 0x0000 794F Yes DmaClaSrcSelRegs (2) DMA_CLA_SRC_SEL_REGS 0x0000 7980 0x0000 798F Yes EPwmXbarRegs (3) EPWM_XBAR_REGS 0x0000 7A00 0x0000 7A3F Yes OutputXbarRegs (3) OUTPUT_XBAR_REGS 0x0000 7A80 0x0000 7ABF Yes GpioCtrlRegs (3) GPIO_CTRL_REGS 0x0000 7C00 0x0000 7D7F Yes GpioDataRegs (2) GPIO_DATA_REGS 0x0000 7F00 0x0000 7F2F Yes Yes UsbaRegs (3) USB_REGS 0x0004 0000 0x0004 0FFF Yes Emif1Regs EMIF_REGS 0x0004 7000 0x0004 77FF Yes Emif2Regs (3) EMIF_REGS 0x0004 7800 0x0004 7FFF Yes CanaRegs CAN_REGS 0x0004 8000 0x0004 87FF Yes CanbRegs CAN_REGS 0x0004 A000 0x0004 A7FF Yes IpcRegs (2) IPC_REGS_CPU1 IPC_REGS_CPU2 0x0005 0000 0x0005 0023 Yes FlashPumpSemaphoreRegs (2) FLASH_PUMP_SEMAPHORE_REGS 0x0005 0024 0x0005 0025 Yes DevCfgRegs (3) DEV_CFG_REGS 0x0005 D000 0x0005 D17F Yes AnalogSubsysRegs (3) ANALOG_SUBSYS_REGS 0x0005 D180 0x0005 D1FF Yes ClkCfgRegs (4) CLK_CFG_REGS 0x0005 D200 0x0005 D2FF Yes CpuSysRegs (2) CPU_SYS_REGS 0x0005 D300 0x0005 D3FF Yes RomPrefetchRegs (3) ROM_PREFETCH_REGS 0x0005 E608 0x0005 E60B Yes DcsmZ1Regs (2) DCSM_Z1_REGS 0x0005 F000 0x0005 F02F Yes DcsmZ2Regs (2) DCSM_Z2_REGS 0x0005 F040 0x0005 F05F Yes DcsmCommonRegs (2) DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F Yes MemCfgRegs (2) MEM_CFG_REGS 0x0005 F400 0x0005 F47F Yes Emif1ConfigRegs (2) EMIF1_CONFIG_REGS 0x0005 F480 0x0005 F49F Yes Emif2ConfigRegs (3) EMIF2_CONFIG_REGS 0x0005 F4A0 0x0005 F4BF Yes AccessProtectionRegs (2) ACCESS_PROTECTION_REGS 0x0005 F4C0 0x0005 F4FF Yes MemoryErrorRegs (2) MEMORY_ERROR_REGS 0x0005 F500 0x0005 F53F Yes RomWaitStateRegs (3) ROM_WAIT_STATE_REGS 0x0005 F540 0x0005 F541 Yes Flash0CtrlRegs (2) FLASH_CTRL_REGS 0x0005 F800 0x0005 FAFF Yes Flash0EccRegs (2) FLASH_ECC_REGS 0x0005 FB00 0x0005 FB3F Yes (1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that follows a write operation within a protected address range is executed as written by delaying the read operation until the write is initiated. (2) A unique copy of these registers exist on each CPU subsystem. (3) These registers are available only on the CPU1 subsystem. (4) These registers are mapped to either CPU1 or CPU2 based on a semaphore. (5) The address overlap of PieCtrlRegs and Cla1SoftIntRegs is correct. Each CPU, C28x and CLA, only has access to one of the register sets. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.3.5 Memory Types

Table 7-5 provides more information about each memory type. Table 7-5. Memory Types MEMORY TYPE ECC-CAPABLE PARITY SECURITY HIBERNATE RETENTION ACCESS PROTECTION M0, M1 Yes – – Yes – D0, D1 Yes – Yes – Yes LSx – Yes Yes – Yes GSx – Yes – – Yes CPU/CLA MSGRAM – Yes Yes – Yes Boot ROM – – – N/A – Secure ROM – – Yes N/A – Flash Yes – Yes N/A N/A User-configurable DCSM OTP Yes – Yes N/A N/A

7.3.5.1 Dedicated RAM (Mx and Dx RAM)

The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1 memories are small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them). D0/D1 memories are secure blocks and also have the access-protection feature (CPU write/CPU fetch protection).

7.3.5.2 Local Shared RAM (LSx RAM)

RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are called local shared RAMs (LSx RAMs). All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU write/CPU fetch) feature. By default, these memories are dedicated to the CPU only, and the user could choose to share these memories with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately. Table 7-6 shows the master access for the LSx RAM. Table 7-6. Master Access for LSx RAM (With Assumption That all Other Access Protections are Disabled) MSEL_LSx CLAPGM_LSx CPU ALLOWED ACCESS CLA ALLOWED ACCESS COMMENT

00 X All – LSx memory is configured

as CPU dedicated RAM. 01 0 All Data Read Data Write LSx memory is shared between CPU and CLA1. 01 1 Emulation Read Emulation Write Fetch Only LSx memory is CLA1 program memory. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 179 Product Folder Links: F28377D-SEP

7.3.5.3 Global Shared RAM (GSx RAM)

RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs). Each shared RAM block can be owned by either CPU subsystem based on the configuration of respective bits in the GSxMSEL register. All GSx RAM blocks have parity. When a GSx RAM block is owned by a CPU subsystem, the CPUx and CPUx.DMA will have full access to that RAM block whereas the other CPUy and CPUy.DMA will only have read access (no fetch/write access). Table 7-7 shows the master access for the GSx RAM. Table 7-7. Master Access for GSx RAM (With Assumption That all Other Access Protections are Disabled) GSxMSEL CPU INSTRUCTION FETCH READ WRITE CPUx.DMA READ CPUx.DMA WRITE CPU1 Yes Yes Yes Yes Yes CPU2 – Yes – Yes – CPU1 – Yes – Yes – CPU2 Yes Yes Yes Yes Yes The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).

7.3.5.4 CPU Message RAM (CPU MSGRAM)

These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU/DMA read/write access from its own CPU subsystem, and CPU/DMA read only access from the other subsystem. This RAM has parity.

7.3.5.5 CLA Message RAM (CLA MSGRAM)

These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU and CLA both have read access to both MSGRAMs. This RAM has parity. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.4 Identification

Table 7-8 shows the Device Identification Registers. Table 7-8. Device Identification Registers NAME ADDRESS SIZE (x16) DESCRIPTION PARTIDH 0x0005 D00A (CPU1) 0x0007 0202 (CPU2) 2 Device part identification number(1) F28377D-SEP 0xFF 0300 REVID 0x0005 D00C 2 Silicon revision number Revision 0 0x0000 0000 Revision A 0x0000 0000 Revision B 0x0000 0002 Revision C 0x0000 0003 UID_UNIQUE 0x0007 03CC 2 Unique identification number. This number is different on each individual device with the same PARTIDH. This can be used as a serial number in the application. This number is present only on TMS Revision C devices. CPU ID 0x0007 026D 1 CPU identification number CPU1 0xXX01 CPU2 0xXX02 JTAG ID N/A N/A JTAG Device ID 0x0B99 C02F (1) PARTIDH may have one of two values for each part number, with the eight most significant bits identified with '' above being 0x00 or 0x02. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 181 Product Folder Links: F28377D-SEP

7.5 Bus Architecture – Peripheral Connectivity

Table 7-9 shows a broad view of the peripheral and configuration register accessibility from each bus master. Peripherals can be individually assigned to the CPU1 or CPU2 subsystem (for example, ePWM can be assigned to CPU1 and eQEP assigned to CPU2). Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master as a group (if SPI is assigned to CPUx.DMA, then McBSP is also assigned to CPUx.DMA). Table 7-9. Bus Master Peripheral Access PERIPHERALS (BY BUS ACCESS TYPE) CPU1.DMA CPU1.CLA1 CPU1 CPU2 CPU2.CLA1 CPU2.DMA Peripherals that can be assigned to CPU1 or CPU2 and have common selectable Secondary Masters Peripheral Frame 1:

ePWM
SDFM
eCAP(1)
eQEP(1)
CMPSS(1)
DAC(1) Y Y Y Y Y Y Peripheral Frame 1:
HRPWM Y Y Y Peripheral Frame 2:
SPI
McBSP Y Y Y Y Y Y Peripheral Frame 2:
uPP Configuration(1) Y Y Y Peripherals that can be assigned to CPU1 or CPU2 subsystems SCI Y Y I2C Y Y CAN Y Y ADC Configuration Y Y Y Y EMIF1 Y Y Y Y Peripherals and Device Configuration Registers only on CPU1 subsystem EMIF2 Y Y USB Y Device Capability, Peripheral Reset, Peripheral CPU Select Y GPIO Pin Mapping and Configuration Y Analog System Control Y uPP Message RAMs Y Y Reset Configuration Y Accessible by only one CPU at a time with Semaphore Clock and PLL Configuration Y Y F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

Table 7-9. Bus Master Peripheral Access (continued) PERIPHERALS (BY BUS ACCESS TYPE) CPU1.DMA CPU1.CLA1 CPU1 CPU2 CPU2.CLA1 CPU2.DMA Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master (2) System Configuration (WD, NMIWD, LPM, Peripheral Clock Gating) Y Y Flash Configuration(3) Y Y CPU Timers Y Y DMA and CLA Trigger Source Select Y Y GPIO Data(4) Y Y Y Y ADC Results Y Y Y Y Y Y (1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer. (2) Each CPUx and CPUx.CLA1 can only access its own copy of these registers. (3) At any given time, only one CPU can perform program or erase operations on the Flash. (4) The GPIO Data Registers are unique for each CPUx and CPUx.CLAx. When the GPIO Pin Mapping Register is configured to assign a GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO) chapter of the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for more details.

7.6 C28x Processor

The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets. The CPU features include a modified Harvard architecture and circular addressing. The RISC features are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses. For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set Reference Guide.

7.6.1 Floating-Point Unit

The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by adding registers and instructions to support IEEE single-precision floating-point operations. Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit registers. The additional floating-point unit registers are the following:

Eight floating-point result registers, RnH (where n = 0–7)
Floating-point Status Register (STF)
Repeat Block Register (RB) All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in high-priority interrupts for fast context save and restore of the floating-point registers. For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: F28377D-SEP

7.6.2 Trigonometric Math Unit

The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 7-10. Table 7-10. TMU Supported Instructions INSTRUCTIONS C EQUIVALENT OPERATION PIPELINE CYCLES MPY2PIF32 RaH,RbH a = b * 2pi 2/3 DIV2PIF32 RaH,RbH a = b / 2pi 2/3 DIVF32 RaH,RbH,RcH a = b/c 5 SQRTF32 RaH,RbH a = sqrt(b) 5 SINPUF32 RaH,RbH a = sin(b*2pi) 4 COSPUF32 RaH,RbH a = cos(b*2pi) 4 ATANPUF32 RaH,RbH a = atan(b)/2pi 4 QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5 No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions use the existing FPU register set (R0H to R7H) to carry out their operations. A detailed explanation of the workings of the FPU can be found in the TMS320C28x Extended Instruction Sets Technical Reference Manual.

7.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)

The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The VCU-II extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the performance of Fast Fourier Transforms (FFTs) and communications-based algorithms. The C28x+VCU-II supports the following algorithm types:

Viterbi Decoding Viterbi decoding is commonly used in baseband communications applications. The Viterbi decode algorithm consists of three main parts: branch metric calculations, compare-select (Viterbi butterfly), and a traceback operation. Table 7-11 shows a summary of the VCU performance for each of these operations. Table 7-11. Viterbi Decode Performance VITERBI OPERATION VCU CYCLES Branch Metric Calculation (code rate = 1/2) 1 Branch Metric Calculation (code rate = 1/3) 2p Viterbi Butterfly (add-compare-select) 2(1) Traceback per Stage 3(2) (1) C28x CPU takes 15 cycles per butterfly. (2) C28x CPU takes 22 cycles per stage.
Cyclic Redundancy Check Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-bit, 16-bit, 24-bit, and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10 bytes in 10 cycles. A CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

Complex Math Complex math is used in many applications, a few of which are: – Fast Fourier Transform (FFT) The complex FFT is used in spread spectrum communications, as well as in many signal processing algorithms. – Complex filters Complex filters improve data reliability, transmission distance, and power efficiency. The C28x+VCU can perform a complex I and Q multiply with coefficients (four multiplies) in a single cycle. In addition, the C28x+VCU can read/write the real and imaginary parts of 16-bit complex data to memory in a single cycle. Table 7-12 shows a summary of the VCU operations enabled by the VCU. Table 7-12. Complex Math Performance COMPLEX MATH OPERATION VCU CYCLES NOTES Add or Subtract 1 32 +/- 32 = 32-bit (Useful for filters) Add or Subtract 1 16 +/- 32 = 15-bit (Useful for FFT) Multiply 2p 16 x 16 = 32-bit Multiply and Accumulate (MAC) 2p 32 + 32 = 32-bit, 16 x 16 = 32-bit RPT MAC 2p+N Repeat MAC. Single cycle after the first operation. For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: F28377D-SEP

7.7 Control Law Accelerator

The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion. When a task completes, the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP, Comparator and DAC registers. Dedicated message RAMs provide a method to pass additional data between the main CPU and the CLA. Figure 7-2 shows the CLA block diagram. CPU Read Data Bus MR0(32) MVECT1(16) MIFR(16) MPC(16) MIER(16) MIFRC(16) MIRUN(16) MR1(32) MR3(32) MAR0(16) CPU Read/Write Data Bus CLA Execution Register Set CLA Control Register Set MSTF(32) PIE CLA Program Memory (LSx) CLA Data Memory (LSx) SYSCLK CLA Clock Enable SYSRSn MR2(32) MAR1(16) MIOVF(16) MICLR(16) MCTL(16) MICLROVF(16) LUF CLA Message RAMs Shared PeripheralsMEALLOW CLA Data Bus C28x CPU INT11 INT12 MVECT2(16) MVECT3(16) MVECT4(16) MVECT5(16) MVECT6(16) MVECT7(16) MVECT8(16) CPU Data Bus LSxMSEL[MSEL_LSx] LSxCLAPGM[CLAPGM_LSx] CLA Program Bus MPERINT1 to MPERINT8 CLA_INT1 to CLA_INT8 LVF From Shared Peripherals Figure 7-2. CLA Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.8 Direct Memory Access

Each CPU has its own 6-channel DMA module. The DMA module provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into blocks for optimal CPU processing. The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start a DMA transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the interrupt trigger source, there is no mechanism within the module itself to start memory transfers periodically. The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfer has either started or completed. Five of the six channels are exactly the same, while Channel 1 has the ability to be configured at a higher priority than the others. DMA features include:

Six channels with independent PIE interrupts
Peripheral interrupt trigger sources – ADC interrupts and EVT signals – Multichannel buffered serial port transmit and receive – External interrupts – CPU timers – EPWMxSOC signals – SPIx transmit and receive – SDFM – Software trigger
Data sources and destinations: – GSx RAM – CPU message RAM (IPC RAM) – ADC result registers – ePWMx – SPI – McBSP – EMIF
Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
Throughput: four cycles/word (without arbitration) www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 187 Product Folder Links: F28377D-SEP

Figure 7-3 shows a device-level block diagram of the DMA. DMA_CHx (1-6) DMA_CHx (1-6) Global Shared 16x 4Kx16 GS0-15 RAMs MSG RAM CPU2 to CPU1 1Kx16 MSG RAM CPU1 to CPU2 1Kx16 XINT (5) CPU2 TIMER (3) CPU2SDFM (8) EPWM (12) McBSP (2) SPI (3) EMIF1 PIE PIE C28x CPU1 Bus CPU1.DMA Bus DMA CPU1 C28x CPU1 C28x CPU2 DMA CPU2 C28x CPU2 Bus CPU2.DMA Bus XINT (1-5) TINT (0-2) SOCA (1-12), SOCB (1-12) MXEVT (A-B), MREVT (A-B) SPITX (A-C), SPIRX (A-C) ADC INT (A-D) (1-4), EVT (A-D) XINT (1-5) TINT (0-2) SDxFLTy (x = 1 to 2, y = 1 to 4) ADC RESULTS (4) ADC WRAPPER (4) CPU1 XINT (5) CPU1 TIMER (3) DMA Trigger Source Selection DMACHSRCSEL1.CHx DMACHSRCSEL2.CHx CHx.MODE.PERINTSEL (x = 1 to 6)DMA Trigger Source Selection DMACHSRCSEL1.CHx DMACHSRCSEL2.CHx CHx.MODE.PERINTSEL (x = 1 to 6) DMA Trigger Source CPU and DMA Data Path eQEPeCAPCMPSSDAC Figure 7-3. DMA Block Diagram F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.9 Interprocessor Communication Module

The IPC module supports several methods of interprocessor communication:

Thirty-two IPC flags per CPU, which can be used to signal events or indicate status through software polling. Four flags per CPU can generate interrupts.
Shared data registers, which can be used to send commands or other small pieces of information between CPUs. Although the register names were chosen to support a command/response system, they can be used for any purpose as defined in software.
Boot mode and status registers, which allow CPU1 to control the CPU2 boot process.
A general-purpose free-running 64-bit counter.
Two shared message RAMs, which can be used to transfer bulk data. Each RAM can be read by both CPUs. CPU1 can write to one RAM and CPU2 can write to the other. Figure 7-4 shows the IPC architecture. CPU2 Gen Int Pulse (on FLG 0->1) Gen Int Pulse (on FLG 0->1) SET31 CLR31 FLG31 ACK31 SET0 CLR0 FLG0 ACK0 SET31 CLR31 FLG31 ACK31 SET0 CLR0 FLG0 ACK0 CPU2.EmulationHalt PLLSYSCLK R=0/W=1 C1TOC2IPCINT1/2/3/4 R=0/W=1 R=0/W=1 R R R R R IPCSET[31:0] IPCCLR[31:0] R R R R R IPCACK[31:0] R IPCSENDCOM[31:0] IPCRECVCOM[31:0] IPCRECVCOM[31:0] IPCRECV ADDR[31:0] IPCRECV ADDR[31:0] IPCRECVDA T A[31:0] IPCRECVDA T A[31:0] IPCLOCALREPL Y[31:0] IPCLOCALREPL Y[31:0] IPCSENDADDR[31:0] IPCSENDADDR[31:0] IPCSENDDA T A[31:0] IPCSENDDA T A[31:0] R/W R/W R/W R/W R/W R/W R/W R/W R 64-bit Free Run Counter IPCCOUNTERH/L[31:0] C1TOC2IPCCOM[31:0] C1TOC2IPCADDR[31:0] C1TOC2IPCDAT AW[31:0] C1TOC2IPCDAT AR[31:0] R=0/W=1 IPCACK[31:0] IPCSET[31:0] IPCCLR[31:0] RIPCFLG[31:0] R=0/W=1 R=0/W=1 R IPCSTS[31:0] C2TOC1IPCCOM[31:0] C2TOC1IPCADDR[31:0] C2TOC1IPCDAT AW[31:0] C2TOC1IPCDAT AR[31:0] CPU1 C2TOC1IPCINT1/2/3/4 R R/W R/W R IPCBOOTMODE[31:0] IPCBOOTSTS[31:0] CPU1.EmulationHalt IPCFLG[31:0] IPCREMOTEREPL Y[31:0] IPCREMOTEREPL Y[31:0] IPCSTS[31:0] IPCSENDCOM[31:0] CPU2. ePIE CPU1. ePIE Figure 7-4. IPC Architecture www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: F28377D-SEP

7.10 Boot ROM and Peripheral Booting

The device boot ROM (on both the CPUs) contains bootloading software. The CPU1 boot ROM does the system initialization before bringing CPU2 out of reset. The device boot ROM is executed each time the device comes out of reset. Users can configure the device to boot to flash (using GET mode) or choose to boot the device through one of the bootable peripherals by configuring the boot mode GPIO pins. The CPU1 boot ROM, being master, owns the boot mode GPIO and boot configurations. The CPU2 boot ROM either boots to flash (if configured to do so through user configurable DCSM OTP) or enters a WAIT BOOT mode if no OTP is programmed. In WAIT BOOT mode, the CPU1 application instructs the CPU2 boot ROM on how to boot further using boot mode IPC commands supported by CPU2 boot ROM. Table 7-13 shows the possible boot modes supported on the device. The default boot mode pins are GPIO72 (boot mode pin 1) and GPIO 84 (boot mode pin 0). Users may choose to have weak pullups for boot mode pins if they use a peripheral on these pins as well, so the pullups can be overdriven. On this device, customers can change the factory default boot mode pins by programming user configurable DCSM OTP locations. This is recommended only for cases in which the factory default boot mode pins do not fit into the customer design. More details on the locations to be programmed is available in the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . Table 7-13. Device Boot Mode MODE NO. CPU1 BOOT MODE CPU2 BOOT MODE TRST GPIO72 (BOOT MODE PIN 1) GPIO84 (BOOT MODE PIN 0)

0 Parallel I/O Boot from Master 0 0 0

1 SCI Mode Boot from Master 0 0 1

2 Wait Boot Mode Boot from master 0 1 0

3 Get Mode Boot from Master 0 1 1

4-7 EMU Boot Mode (JTAG debug probe connected) Boot from Master 1 X X Note The default behavior of Get mode is boot-to-flash. On unprogrammed devices, using Get mode will result in repeated watchdog resets, which may prevent proper JTAG connection and device initialization. Use Wait mode or another boot mode for unprogrammed devices. CAUTION Some reset sources are internally driven by the device. The user must ensure the pins used for boot mode are not actively driven by other devices in the system for these cases. The boot configuration has a provision for changing the boot pins in OTP. For more details, see the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.10.1 EMU Boot or Emulation Boot

The CPU enters this boot when it detects that TRST is HIGH (that is, when a JTAG debug probe/debugger is connected). In this mode, the user can program the EMU_BOOTCTRL control-word (at location 0xD00) to instruct the device on how to boot. If the contents of the EMU_BOOTCTRL location are invalid, then the device would default to WAIT Boot mode. The emulation boot allows users to verify the device boot before programming the boot mode into OTP. Note that EMU_BOOTCTRL is not actually a register, but refers to a location in RAM (PIE RAM). PIE RAM starts at 0xD00, but the first few locations are reserved (when initializing the PIE vector table in application code) for these boot ROM variables.

7.10.2 WAIT Boot Mode

The device in this boot mode loops in the boot ROM. This mode is useful if users want to connect a debugger on a secure device or if users do not want the device to execute an application in flash yet.

7.10.3 Get Mode

The default behavior of Get mode is boot-to-flash. This behavior can be changed by programming the Zx-OTPBOOTCTRL locations in user configurable DCSM OTP. The user configurable DCSM OTP on this device is divided in to two secure zones: Z1 and Z2. The Get mode function in boot ROM first checks if a valid OTPBOOTCTRL value is programmed in Z1. If the answer is yes, then the device boots as per the Z1-OTPBOOTCTRL location. The Z2-OTPBOOTCTRL location is read and decodes only if Z1-OTPBOOTCTRL is invalid or not programmed. If either Zx-OTPBOOTCTRL location is not programmed, then the device defaults to factory default operation, which is to use factory default boot mode pins to boot to flash if the boot mode pins are set to GET MODE. Users can choose the device through which to boot—SPI, I2C, CAN , and USB—by programming proper values into the user configurable DCSM OTP. More details on this can be found in the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual . www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 191 Product Folder Links: F28377D-SEP

7.10.4 Peripheral Pins Used by Bootloaders

Table 7-14 shows the GPIO pins used by each peripheral bootloader. This device supports two sets of GPIOs for each mode, as shown in Table 7-14. Table 7-14. GPIO Pins Used by Each Peripheral Bootloader BOOTLOADER GPIO PINS NOTES SCI-Boot0 SCITXDA: GPIO84 SCIRXDA: GPIO85 SCIA Boot I/O option 1 (default SCI option when chosen through Boot Mode GPIOs) SCI-Boot1 SCIRXDA: GPIO28 SCITXDA: GPIO29 SCIA Boot option 2 – with alternate I/Os. Parallel Boot D0 – GPIO65 D1 – GPIO64 D2 – GPIO58 D3 – GPIO59 D4 – GPIO60 D5 – GPIO61 D6 – GPIO62 D7 – GPIO63 HOST_CTRL – GPIO70 DSP_CTRL – GPIO69 CAN-Boot0 CANRXA: GPIO70 CANTXA: GPIO71 CAN-A Boot – I/O option 1 CAN-Boot1 CANRXA: GPIO62 CANTXA: GPIO63 CAN-A Boot – I/O option 2 I2C-Boot0 SDAA: GPIO91 SCLA: GPIO92 I2CA Boot – I/O option 1 I2C-Boot1 SDAA: GPIO32 SCLA: GPIO33 I2CA Boot – I/O option 2 SPI-Boot0 SPISIMOA - GPIO58 SPISOMIA - GPIO59 SPICLKA - GPIO60 SPISTEA - GPIO61 SPIA Boot – I/O option 1 SPI-Boot1 SPISIMOA – GPIO16 SPISOMIA – GPIO17 SPICLKA – GPIO18 SPISTEA – GPIO19 SPIA Boot – I/O option 2 USB Boot USB0DM - GPIO42 USB0DP - GPIO43 The USB Bootloader will switch the clock source to the external crystal oscillator (X1 and X2 pins). A 20-MHz crystal should be present on the board if this boot mode is selected. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.11 Dual Code Security Module

The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for example, through a debugging tool such as Code Composer Studio™ (CSS). The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory and secure ROM) and allocated secure resource (CLA, LSx RAM, and flash sectors). The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be changed to program a different set of security settings (including passwords) in OTP. Note THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 193 Product Folder Links: F28377D-SEP

7.12 Timers

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If TI-RTOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 2 can be clocked by any one of the following:

SYSCLK (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
X1 (XTAL)
AUXPLLCLK

7.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)

The NMIWD module is used to handle system-level errors. There is an NMIWD module for each CPU. The conditions monitored are:

Missing system clock due to oscillator failure
Uncorrectable ECC error on CPU access to flash memory
Uncorrectable ECC error on CPU, CLA, or DMA access to RAM
Vector fetch error on the other CPU
CPU1 only: Watchdog or NMI watchdog reset on CPU2 If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after a programmable time interval. The default time is 65536 SYSCLK cycles. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

7.14 Watchdog

The watchdog module is the same as the one on previous TMS320C2000™ MCUs, but with an optional lower limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the watchdog is fully backwards-compatible. The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable frequency divider. Figure 7-5 shows the various functional blocks within the watchdog module. /512WDCLK (INTOSC1) Watchdog Prescaler WDCR(WDPS(2:0)) WDCR(WDDIS) SCSR(WDENINT) 1-count delay Overflow SYSRSn Clear 8-bit Watchdog Counter WDCNTR(7:0) WDKEY(7:0) Watchdog Key Detector 55 + AA WDWCR(MIN(7:0)) Watchdog Window Detector Count Good Key Bad Key Out of Window Generate 512-WDCLK Output Pulse Watchdog Time-out WDRSTn WDINTn Figure 7-5. Windowed Watchdog www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 195 Product Folder Links: F28377D-SEP

8 Applications, Implementation, and Layout

8.1 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.2 Key Device Features

Table 8-1. Key Device Features MODULE FEATURE SYSTEM BENEFIT C28x PROCESSING Real-time control CPUs Up to 800 MIPS Two C28x cores: 400 MIPS (2 x 200 MIPS) Two CLA cores: 400 MIPS (2 x 200 MIPS) Flash: Up to 1 MB (512KB on each C28x CPU) RAM : Up to 204 KB 32-bit Floating Point Unit (FPU32) Trigonometric Math Unit (TMU) CRC engine and instructions (VCRC) TI’s two 32-bit C28x DSP cores, provides 400 MHz of signal- processing performance for floating- or fixed-point code running from either on-chip flash or SRAM Provides 400 MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM. CLA: Allows user to execute time-critical control loops concurrently with main CPU FPU32: Native hardware support for IEEE-754 single-precision floating-point operations TMU: Accelerators used to speed up execution of trigonometric and arithmetic operations for faster computation (such as PLL and DQ transform) optimized for control applications. Helps in achieving faster control loops, resulting in higher efficiency and better component sizing. Special instructions to support nonlinear PID control algorithms VCRC: Provides a straightforward method for verifying data integrity over large data blocks, communication packets, or code sections. See Real-time Benchmarks Showcasing C2000™ControlMCU's Optimized Signal Chain. SENSING Analog-to-Digital Converter (ADC) (configurable 12-bit or 16-bit) Four ADC modules 16-bit mode: (1.1 MSPS) Single-ended mode: Up to 24 channels Differential mode : Up to 12 channels 12-bit mode: (3.5 MSPS) Single-ended mode: Up to 24 channels ADC provides precise and concurrent sampling of all three-phase currents and DC bus with zero jitter. ADC post-processing – On-chip hardware reduces ADC ISR complexity and shortens current loop cycles. More ADCs help in multiphase applications. Provide better effective MSPS (oversampling) and typical ENOB for better control-loop performance. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

Table 8-1. Key Device Features (continued) MODULE FEATURE SYSTEM BENEFIT Comparator Subsystem (CMPSS) CMPSS 8 windowed comparators Three 12-bit DACs 60-ns detection to trip time DAC ramp generation Digital filters Slope compensation System protection without false alarms: Comparator Subsystem (CMPSS) modules are useful for applications such as peak-current mode control, switched-mode power, power factor correction, and voltage trip monitoring. PWM trip-triggering and removal of unwanted noise are easy with blanking window and filtering features provided with the analog comparator subsystems. Provides better control accuracy. No need for further CPU configuration to control the PWM with the comparator and 12-bit DAC (CMPSS). Enables protection and control using the same pin. Sigma Delta Filter Module (SDFM) Up to 8 independently configurable digital comparator filter channels Up to 8 independently configurable digital data filter channels Enables galvanic isolation with reinforced delta sigma modulators. SDFMs interface with external delta sigma modulator ADCs, which is ideal for signals that may require isolation. Comparator filter supports overcurrent and undercurrent protection but tripping the PWM without CPU intervention Digital data filter provides higher ENOBs for better control-loop performance Enhanced Quadrature Encoder Pulse (eQEP) 3 eQEP modules Used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine used in a high-performance motion and position-control system. Also can be used in other applications to count input pulses from an external device (such as a sensor). Enhanced Capture (eCAP) 6 eCAP modules Measures elapsed time between events (up to 4 time-stamped events). Connects to any GPIO through the input X- BAR. When not used in capture mode, the eCAP module can be configured as a single- channel PWM output (APWM). Applications for eCAP include: Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors) Elapsed time measurements between position sensor pulses Period and duty-cycle measurements of pulse train signals Decoding current or voltage amplitude derived from duty-cycle encoded current/voltage sensors www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 197 Product Folder Links: F28377D-SEP

Table 8-1. Key Device Features (continued) MODULE FEATURE SYSTEM BENEFIT ACTUATION Enhanced Pulse Width Modulation (ePWM)/High- Resolution Pulse Width Modulation (HRPWM) Up to 24 ePWM channels Ability to generate high-side/low-side PWMs with deadband Supports Valley switching (ability to switch PWM output at valley point) and features like blanking window Flexible PWM waveform generation with best power topology coverage. Shadowed Dead band itself and shadowed action qualifier enable adaptive PWM generation and protection for improved control accuracy and reduced power loss. Enables improvement in Power Factor (PF) and Total Harmonic Distortion (THD), which is especially relevant in Power Factor Correction (PFC) applications. Improves light load efficiency. HRPWM capability: 16 channels provide high-resolution capability (150 ps) Provides 150-ps steps for duty cycle, period, deadband, and phase offsets for 99% greater precision Beneficial for accurate control and enables better-performance high- frequency power conversion. Achieves cleaner waveforms and avoids oscillations/limit cycle at output. One-shot and global reload feature Critical for variable-frequency and multiphase DC-DC applications and helps in attaining high-frequency control loops (>2 MHz). Enables control of interleaved LLC topologies at high frequencies Independent PWM action on a Cycle-by- Cycle (CBC) trip event and an One-Shot Trip (OST) trip event Provides cycle-by-cycle protection and complete shutoff of PWM under fault condition. Helps implement multiphase PFC or DC-DC control. Load on SYNC (support for shadow-to-active load on a SYNC event) Enables variable-frequency applications (allows LLC control in power conversion). Ability to shut down the PWMs without software intervention (no ISR latency) Fast protection under fault condition Delayed Trip Functionality Helps implement the deadband with Peak Current Mode Control (PCMC) Phase-Shifted Full Bride (PSFB) DC-DC easily without occupying much CPU resources (even on trigger events based on comparator, trip, or sync-in events). Dead band Generator (DB) submodule Prevents simultaneous ON conditions of High- and Low-side gates by adding programmable delay to rising (RED) and falling (FED) PWM signal edges. Flexible PWM Phase Relationships and Timer Synchronization Each ePWM module can be synchronized with other ePWM modules or other peripherals. Keeps PWM edges perfectly in synchronization with certain events. Supports flexible ADC scheduling with specific sampling window in synchronization with power device switching. CONNECTIVITY Serial Peripheral Interface (SPI) 3 high-speed SPI port Supports 50 MHz Serial Communication Interface (SCI)

4 SCI (UART) modules Interfaces with controllers

Network (CAN/ DCAN)

2 DCAN module

(can be assigned to Connectivity Manager (M4)) Provides compatibility with classic CAN modules Inter-Integrated Circuit (I2C) 2 I2C modules Interfaces with external EEPROMs, sensors, or controllers Multichannel Buffered Serial Port (McBSP) Up to 2 McBSP modules Interface to high-speed external ADC or additional SPI peripheral F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

Table 8-1. Key Device Features (continued) MODULE FEATURE SYSTEM BENEFIT External Memory Interfaces (EMIFs) with ASRAM and SDRAM support Two EMIF modules, to have a dedicated EMIF for each CPU subsystem. Interface with External ASRAM and SDRAM OTHER SYSTEM FEATURES Security enhancers Dual-zone Code Security Module (DCSM) JTAGLOCK BackGround CRC (BGCRC) Generic CRC (GCRC) Watchdog Write Protection on Register Missing Clock Detection Logic (MCD) Error Correction Code (ECC) and parity DCSM: Prevents duplication and reverse-engineering of proprietary code JTAGLOCK: Ability to block emulation of the device BGCRC: Checks memory integrity with no CPU overhead or system performance impact GCRC: Designated Connectivity Manager module for computing the CRC value on a configurable block of memory Watchdog: Generates reset if CPU gets stuck in endless loops of execution Write Protection on Registers: LOCK protection on system configuration registers Protection against spurious CPU writes MCD: Automatic clock failure detection ECC and parity: Single-bit error correction and double-bit error detection Crossbars (XBARs) Provides flexibility to connect device inputs, outputs, and internal resources in a variety of configurations.

Input X-BAR
Output X-BAR
ePWM X-BAR Enhances hardware design versatility: Input X-BAR: Routes signals from any GPIO to multiple IP blocks within the chip Output XBAR: Routes internal signals onto designated GPIO pins ePWM X-BAR: Routes internal signals from various IP blocks to ePWM Direct Memory Access (DMA) controller 12-channels The direct memory access (DMA) module provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up CPU bandwidth for other system functions. USB Useful for system datalogging and boot to USB for updating on-chip flash www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 199 Product Folder Links: F28377D-SEP

8.3 Application Information

8.3.1 Typical Application

The Typical Applications section details some applications of this device. For a more extensive list of applications, see the Applications section of this data sheet.

8.3.1.1 Solar Micro Inverter

A Solar Micro Inverter consists of a DC-AC inverter power stage and one or more Maximum Power Point Tracking (MPPT) DC-DC power stages. Typical switching frequency for the inverter (DC-AC) is between 20kHz-50kHz and for DC-DC side can be in the range 100kHz-200kHz. A variety of power stage topologies can be used to achieve this and the diagram only depicts a typical power stage and the control & communication requirements. A C2000 microcontroller has on-chip EPWM, ADC and analog comparator modules to implement complete digital control of such micro inverter system.

8.3.1.1.1 System Block Diagram

I Vgrid S1 (S2) interleaved phases PV 27V – 45V GND ADC PWM1 Vref PWM3 PWM2 PWM4 SPI UART CAN Comms C28xGPIO Comparators QEPFlash SRAM 3V3 Aux. DC/DC DC bus 3V3 1A 1B 2A 2B 3A 3B 4 S1 S2 S3 S4 S5 2B3B 4 (Relay) S6 S7 Isolation Active Clamp Flyback with sec Voltage Multiplier DC bus DC – AC Inverter GND Figure 8-1. Solar Micro Inverter F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

8.3.1.1.2 Solar Micro Inverter Resources

Reference Designs and Associated Training Videos How real-time control technologies enable reliable, scalable high-voltage designs Synchronous Rectification Control in CLLLC Converters Based on Hall-Effect Current Sensors Application Report

8.3.1.2 On-Board Charger (OBC)

An On-Board Charger (OBC) consists of two power stages: an AC-DC power converter and a subsequent DC-DC power converter stage. The OBC can be implemented by using a single MCU to control both the AC-DC and DC-DC power converters. For example: an 11-kW OBC can be implemented by using three 3.7-kW single-phase OBC modules, as shown in Figure 8-2. This approach allows us to easily support both single-phase 240 AC (North America) and 3-phase AC (rest of the world). OBC-charging design requirements are as follows:

High-performance and fast digital control loops enabling highly efficient power conversion and increased power density.
Enabling precise control and fast shutdown in an overcurrent scenario by high bandwidth and fast response current sensing.
Safely and efficiently controlling and protecting the power switch [insulated-gate bipolar transistor/silicon carbide (IGBT/SiC)].

8.3.1.2.1 System Block Diagram

Figure 8-2. 11 kW Modular OBC Power Topology (Unidirectional, bridge PFC) www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 201 Product Folder Links: F28377D-SEP

8.3.1.2.2 OBC Resources

Reference Designs and Associated Training Videos High-frequency resonant converter design considerations, Part 1 High-frequency resonant converter design considerations, Part 2 Application Report 6.6kW Bi-directional On-Board Charger (OBC): Introduction and Overview (Video) 6.6kW Bi-directional OBC_CLLLC Resonant DAB Converter (Video) CLLLC vs. DAB for EV onboard chargers Application Report High Voltage Onboard Charger using TI GaN and C2000 real-time MCU (Video)

8.3.1.3 EV Charging Station Power Module

The power module in a DC charging station consists of AC/DC power stage and DC/DC power stage. Each converter associated with its power stage comprises of power switches and gate driver, current and voltage sensing, and a real-time micro-controller. On the input side it has three-phase AC mains which are connected to the AC/DC power stage. This block converts the incoming AC voltage into a fixed DC voltage of around 800 V. This voltage serves as input to the DC/DC power stage which processes power and interfaces directly with the battery on the electric vehicle. Each power stage has a separate real-time micro-controller which is responsible for the processing of analog signals and providing fast control action. The AC/DC stage (also known as the PFC stage) is the first level of power conversion in an EV charging station. It converts the incoming AC power from the grid (380–415 VAC) into a stable DC link voltage of around 800 V. The PFC stage maintains sinusoidal input currents, with typically a THD < 5%, and provides controlled DC output voltage higher than the amplitude of the line-to-line input voltage. The DC/DC stage is the second level of power conversion in an EV charging station. It converts the incoming DC link voltage of 800 V (in case of three-phase systems) to a lower DC voltage to charge the battery of an electric vehicle. The DC/DC converter must be capable of delivering rated power to the battery over a wide range with the capability of charging the battery at constant current or at constant voltage modes, depending on the State Of Charge (SOC) of the battery. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

8.3.1.3.1 System Block Diagram

I_ctl I_hv I_lv Ip_tank LM76003 F280049 Control Card TMDSCNCD280049C LMZ31707 TLV1117LV33 BENCH POWER SUPPLY 15 V 12 V 5 V 3.3 V GND AMC3306 FLT Power architecture OPA320 Primary side measurements Secondary side measurements Planar Transformer ls_tank Cap Bank Output V_lv PGND SGND SiC MOSFETsSiC MOSFETs Cap Bank Input l_hv High Voltage Side (HV) Low Voltage Side (LV) UCC21530 ISO7721 X 2 TPS7B6950Q SN6501 PWMRSTQ1 Primary side gate driver cards

5 VPWM

Secondary side gate driver cards Is_tank V_lv Figure 8-3. Dual-active-bridge DC/DC converter

8.3.1.3.2 EV Charging Station Power Module Resources

Reference Designs and Associated Training Videos www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: F28377D-SEP

9 Device and Documentation Support

9.1 Device and Development Support Tool Nomenclature

Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PTP) and temperature range. Figure 9-1 provides a legend for reading the complete device name for any family member. For device part numbers and further ordering information, see the TI website ( www.ti.com) or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata . Generic Part Number: Orderable Part Number: PREFIX(A) X = experimental device blank = qualified device X F F 28377D 28377D PTP SEP TEMPERATURE RANGE SEP = –55°C to 150°C (TJ) -SEP TECHNOLOGY F = Flash DEVICE 28377D PACKAGE TYPE PTP = 176-pin PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (HLQFP) A. Prefix X is used in orderable part numbers. Figure 9-1. Device Nomenclature F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

9.2 Markings

Figure 9-2 provides an example of the F28377D-SEP device markings and defines each of the markings. The device revision can be determined by the symbols marked on the top of the package as shown in Figure 9-2. Some prototype devices may have markings different from those illustrated. Package Pin 1 F28377DPTPSEP $$#-YMLLLLS Lot Trace Code Wafer Fab Code (one or two characters) Silicon Revision Code 2-digit Year/Month Code Assembly Lot Code Assembly Site Code per QSS 005-120 YMLLLLS YM LLLL S Figure 9-2. Example of Device Markings Table 9-1. Determining Silicon Revision From Lot Trace Code SILICON REVISION CODE SILICON REVISION REVID(1) Address: 0x5D00C COMMENTS Blank 0 0x0000 This silicon revision is available as TMX. A A 0x0000 This silicon revision is available as TMX. B B 0x0002 This silicon revision is available as TMX. C C 0x0003 This silicon revision is available as TMS. (1) Silicon Revision ID www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: F28377D-SEP

9.3 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. To view all available tools and software for C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page. Development Tools F28379D controlCARD for C2000 Real time control development kits The F28379D controlCARD from Texas Instruments is Position Manager-ready and an ideal product for initial software development and short run builds for system prototypes, test stands, and many other projects that require easy access to high-performance controllers. All C2000 controlCARDs are complete board-level modules that utilize a HSEC180 or DIMM100 form factor to provide a low-profile single-board controller solution. The host system needs to provide only a single 5V power rail to the controlCARD for it to be fully functional. F28379D Experimenter Kit C2000™ MCU Experimenter Kits provide a robust hardware prototyping platform for real-time, closed loop control development with Texas Instruments C2000 32-bit microcontroller family. This platform is a great tool to customize and prove-out solutions for many common power electronics applications, including motor control, digital power supplies, solar inverters, digital LED lighting, precision sensing, and more. Software Tools C2000Ware for C2000 MCUs C2000Ware for C2000 microcontrollers is a cohesive set of development software and documentation designed to minimize software development time. From device-specific drivers and libraries to device peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation. C2000Ware is now the recommended content delivery tool versus controlSUITE™. Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers. Pin Mux Tool The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. F021 Flash Application Programming Interface (API) The F021 Flash Application Programming Interface (API) provides a software library of functions to program, erase, and verify F021 on-chip Flash memory. UniFlash Standalone Flash Tool UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting interface. C2000 Third-party search tool TI has partnered with multiple companies to offer a wide range of solutions and services for TI C2000 devices. These companies can accelerate your path to production using C2000 devices. Download this search tool to quickly browse third-party details and find the right third-party to meet your needs. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

Various models are available for download from the product Tools & Software pages. These include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all available models, visit the Models section of the Tools & Software page for each device. Training To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance, TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller family. These training resources have been designed to decrease the learning curve, while reducing development time, and accelerating product time to market. For more information on the various training resources, visit the C2000™ real-time microcontrollers design & development – Educational resources site. Specific F2837xD/F2837xS/F2807x hands-on training resources can be found within the C2000 Academy on TI Resource Explorer. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 207 Product Folder Links: F28377D-SEP

9.4 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The current documentation that describes the processor, related peripherals, and other technical collateral is listed below. Radiation Reports Single-Event Effects (SEE) Radiation Report of the F28377D-SEP Dual-Core Real-Time Microcontroller characterizes the single-event effects (SEE) performance due to heavy-ion irradiation of the F28377D-SEP. Total Ionizing Dose (TID) Report covers the radiation characterization results of the F28377D-SEP, radiation- tolerant 32-bit floating-point microcontroller unit. Errata TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata describes known advisories on silicon and provides workarounds. Technical Reference Manual TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the F2837xD microcontrollers. CPU User's Guides TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference Guide also describes emulation features available on these DSPs. TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and instruction set of the TMU, VCU-II, and FPU accelerators. Peripheral Guides C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x DSPs. Tools Guides TMS320C28x Assembly Language Tools v22.6.0.LTS User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. TMS320C28x Optimizing C/C++ Compiler v22.6.0.LTS User's Guide describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. Application Reports Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor devices for shipment to end users. Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement. An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/ output structures and future trends. F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

Serial Flash Programming of C2000 ™ Microcontrollers discusses using a flash kernel and ROM loaders for serial programming a device. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: F28377D-SEP

9.5 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.6 Trademarks

PowerPAD™, C2000™, Code Composer Studio™, TMS320C2000™, controlSUITE™, and TI E2E™ are trademarks of Texas Instruments. Bosch® is a registered trademark of Robert Bosch GmbH Corporation. All trademarks are the property of their respective owners.

9.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.8 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws.

9.9 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Changes from October 1, 2025 to January 31, 2026 (from Revision * (October 2025) to Revision A (January 2026)) Page F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: F28377D-SEP

www.ti.com PACKAGE OUTLINE C 176X 0.27 0.17 172X 0.5 PIN 1 ID (0.13) TYP 0.15 0.05 0 -7 4X 21.5 TYP26.2 25.8 7.33 6.78 8.07 7.53 4X 0.78 MAX NOTE 4

0.54 MAX

0.2 MAX

BNOTE 324.2 23.8 A NOTE 3 24.2 23.8 0.75 0.45 0.25 GAGE PLANE

1.6 MAX

(1.4) PowerPAD HLQFP - 1.6 mm max height PTP0176F PLASTIC QUAD FLATPACK 4223382/A 03/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold ﬂash, protrusions, or gate burrs. 4. Strap features my not present. 5. Reference JEDEC registration MS-026. TM PowerPAD is a trademark of Texas Instruments. 132 133176

0.08 C A B

SCALE: 12 DETAIL A TYPICAL 0.08 C SCALE 0.550 45 88 132 133176 177 EXPOSED THERMAL PAD F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND (25.5) 172X (0.5) 176X (1.45) 176X (0.3) ( 0.2) TY P VIA (8.07) ( 22) NOTE 10 (R0.05) TYP (1.5 TYP) (1.5 TYP) (7.33) (25.5) PowerPAD HLQFP - 1.6 mm max heightPTP0176F PLASTIC QUAD FLATP ACK 4223382/A 03/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on t he board. See technical brief, Powerpad thermally enhanced package, 9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. 10. Size of metal pad may vary due to creepage requirement. TM LAND P ATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:4X SYMM SY MM 176 133 45 88 132 SOLDER MASK DEFINED PAD METAL COVERED BY SOLDER MASK 177 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL www.ti.com F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: F28377D-SEP

www.ti.com EXAMPLE STENCIL DESIGN (8.07) BASED ON

0.125 THICK STENCIL

172X (0.5) 176X (1.45) 176X (0.3) (R0.05) TYP (25.5) (25.5) (7.33) BASED ON

0.125 THICK

6.82 X 6.20.175 7.37 X 6.690.150 8.07 X 7.33 (SHOWN)0.125 9.02 X 8.20.1 SOLDER STENCIL OPENING STENCIL THICKNESS PowerPAD HLQFP - 1.6 mm max heightPTP0176F PLASTIC QUAD FLATPACK 4223382/A 03/2017 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have diﬀerent recommendations for stencil design. TM SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:4X THICKNESSES FOR OTHER STENCIL DIFFERENT OPENINGS SEE TABLE FOR SYMM SYMM 176 133 45 88 132 BY SOLDER MASK METAL COVERED 177 F28377D-SEP SPRSPB1A – OCTOBER 2025 – REVISED JANUARY 2026 www.ti.com

Product Folder Links: F28377D-SEP

www.ti.com 27-Jan-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) F28377DPTPSEP Active Production HLQFP (PTP) | 176 1 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -55 to 125 F28377DPTPSEP V62/25638-01XE Active Production HLQFP (PTP) | 176 1 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -55 to 125 F28377DPTPSEP (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. HLQFP - 1.6 mm max heightPTP 176 PLASTIC QUAD FLATPACK24 x 24, 0.5 mm pitch 4226435/A

www.ti.com PACKAGE OUTLINE C 176X 0.27 0.17172X 0.5 PIN 1 ID (0.13) TYP 0.15 0.05 0 -7 4X 21.5 TYP26.2 25.8 7.33 6.78 8.07 7.53 4X 0.78 MAX NOTE 4 B NOTE 324.2 23.8 A NOTE 3 24.2 23.8 0.75 0.45 0.25 GAGE PLANE (1.4) PLASTIC QUAD FLATPACK PowerPAD HLQFP - 1.6 mm max heightPTP0176F PLASTIC QUAD FLATPACK 4223382/A 03/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. 4. Strap features my not present. 5. Reference JEDEC registration MS-026. TM PowerPAD is a trademark of Texas Instruments. 132 133176 SCALE: 12 DETAIL A TYPICAL 0.08 C SCALE 0.550 45 88 132 133176 177 EXPOSED THERMAL PAD

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND 0.05 MIN ALL AROUND (25.5) 172X (0.5) 176X (1.45) 176X (0.3) ( 0.2) TYP VIA (8.07) ( 22) NOTE 10 (R0.05) TYP (1.5 TYP) (1.5 TYP) (7.33) (25.5) PowerPAD HLQFP - 1.6 mm max heightPTP0176F PLASTIC QUAD FLATPACK 4223382/A 03/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package, 9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. 10. Size of metal pad may vary due to creepage requirement. 10. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:4X SYMM SYMM 176 133 45 88 132 SOLDER MASK DEFINED PAD METAL COVERED BY SOLDER MASK 177 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (8.07) BASED ON 172X (0.5) 176X (1.45) 176X (0.3) (R0.05) TYP (25.5) (25.5) (7.33) BASED ON 6.82 X 6.20.175 7.37 X 6.690.150 8.07 X 7.33 (SHOWN)0.125 9.02 X 8.20.1 SOLDER STENCIL OPENING STENCIL THICKNESS PowerPAD HLQFP - 1.6 mm max heightPTP0176F PLASTIC QUAD FLATPACK 4223382/A 03/2017 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:4X THICKNESSES FOR OTHER STENCIL DIFFERENT OPENINGS SEE TABLE FOR SYMM SYMM 176 133 45 88 132 BY SOLDER MASK METAL COVERED 177

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025

Selected Specification

Texas Instruments F28377D-SEP overview.

Summary

F28377D-SEP Dual-Core Real-Time Microcontroller OCTOBER 2025

Description

F28377D-SEP Dual-Core Real-Time Microcontroller OCTOBER 2025

Source title F28377D-SEP Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer