F273-CEG-P

ST10F273E STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 179

Technical content

Datasheet sections

• 1 Introduction
• 2 Pin data
• 3 Functional description
• 4 Memory organization
• 5 Internal Flash memory
• 5.1 Overview
• 5.2 Functional description
• 5.2.1 Structure
• 5.2.2 Modules structure
• 5.2.3 Low power mode
• 5.3 Write operation
• 5.4 Registers description
• 5.4.1 Flash control register 0 low
• 5.4.2 Flash control register 0 high
• 5.4.3 Flash control register 1 low
• 5.4.4 Flash control register 1 high
• 5.4.5 Flash data register 0 low
• 5.4.6 Flash data register 0 high
• 5.4.7 Flash data register 1 low
• 5.4.8 Flash data register 1 high
• 5.4.9 Flash address register low
• 5.4.10 Flash address register high
• 5.4.11 Flash error register
• 5.5 Protection strategy
• 5.5.1 Protection registers
• 5.5.2 Flash non volatile write protection I register low
• 5.5.3 Flash non volatile write protection I register high
• 5.5.4 Flash non volatile access protection register
• 5.5.5 Flash non volatile access protection register 1 low
• 5.5.6 Flash non volatile access protection register 1 high

Datasheet sections

• 13.2.1 Open drain mode
• 13.2.2 Input threshold control
• 13.3 Alternate port functions
• 14 A/D converter
• 15 Serial channels
• 15.1 Asynchronous / synchronous serial interfaces
• 15.2 ASCx in asynchronous mode
• 15.3 ASCx in synchronous mode
• 15.4 High speed synchronous serial interfaces
• 16 I2C interface
• 17 CAN modules
• 17.1 Configuration support
• 17.2 CAN bus configurations
• 18 Real time clock
• 19 Watchdog timer
• 20 System reset
• 20.1 Input filter
• 20.2 Asynchronous reset
• 20.3 Synchronous reset (warm reset)
• 20.4 Software reset
• 20.5 Watchdog timer reset
• 20.6 Bidirectional reset
• 20.7 Reset circuitry
• 20.8 Reset application examples
• 20.9 Reset summary
• 21 Power reduction modes
• 21.1 Idle mode
• 21.2 Power down mode

Datasheet sections

• 24.8.8 Voltage controlled oscillator
• 24.8.9 PLL jitter
• 24.8.10 PLL lock / unlock
• 24.8.11 Main oscillator specifications
• 24.8.13 External clock drive XTAL1
• 24.8.14 Memory cycle variables
• 24.8.15 External memory bus timing
• 24.8.16 Multiplexed bus
• 24.8.17 Demultiplexed bus
• 24.8.18 CLKOUT and READY
• 24.8.19 External bus arbitration
• 24.8.20 High-speed synchronous serial interface (SSC) timing
• 25 Package information
• 26 Revision history

16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM Feature summary ■ High performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64 MHz max CPU clock – Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator – Enhanced boolean bit manipulations – Single-cycle context switching support ■ Memory organization – 512 Kbyte on-chip Flash memory single voltage with erase/program controller (full performance, 32-bit fetch) – 100K erasing/programming cycles. – Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I 2C) – 2 Kbyte on-chip internal RAM (IRAM) – 34 Kbyte on-chip extension RAM (XRAM) – Programmable external bus configuration & characteristics for different address ranges – 5 programmable chip-select signals – Hold-acknowledge bus arbitration support ■ Interrupt – 8-channel peripheral event controller for single cycle interrupt driven data transfer – 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns ■ Timers – 2 multifunctional general purpose timer units with 5 timers ■ Two 16-channel capture / compare units ■ 4-channel PWM unit + 4-channel XPWM ■ A/D Converter – 24-channel 10-bit –3 µs Minimum conversion time ■ Serial channels – 2 synch. / asynch. serial channels – 2 high-speed synchronous channels 2C standard interface ■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 messages, C-CAN version) ■ Fail-safe protection – Programmable watchdog timer – Oscillator watchdog ■ On-chip bootstrap loader ■ Clock generation – On-chip PLL and 4 to 12 MHz oscillator – Direct or prescaled clock input ■ Real time clock and 32 kHz on-chip oscillator ■ Up to 111 general purpose I/O lines – Individually programmable as input, output or special function – Programmable threshold (hysteresis) ■ Idle, power down and stand-by modes ■ Single voltage supply: 5 V ±10%. Order codes PQFP144 (28 x 28 x 3.4mm) (Plastic Quad Flat Package) TQFP144 (20 x 20 x 1.4mm) (Thin Quad Flat Package) Part number Package Packing Temperature range(°C) CPU frequency range (MHz) F273-CEG-P PQFP144 Tray -40 to +125 1 to 64 F273-CEG-P-TR Tape & Reel F273-CEG-T TQFP144 Tray -40 to +125 -40 to +105 1 to 40 1 to 48 F273-CEG-T -TR Tape & Reel

Table 41. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 69 Table 42. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 70 Table 43. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 70 Table 44. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 71

Table 71. PLL characteristics [V Table 79. CLKOUT and READY

1 Introduction

The ST10F273E device is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. The ST10F273E combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. ST10F273E is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work at 5 V. The device is upward compatible with the ST10F269 device, with the following set of differences: Flash control interface is now based on STMicroelectronics third generation of stand-alone Flash memories (M29F400 series), with an embedded Program/Erase Controller. This completely frees up the CPU during programming or erasing the Flash. Only one supply pin (ex DC1 in ST10F269, renamed into V18) on the QFP144 package is used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin to 5.0 V external supply. Instead, this pin should be connected to a decoupling capacitor (ceramic type, typical value 10nF , maximum value 100nF). The AC and DC parameters are modified due to a difference in the maximum CPU frequency. A new V DD pin replaces DC2 of ST10F269. EA pin assumes a new alternate functionality: it is also used to provide a dedicated power supply (see VSTBY) to maintain biased a portion of the XRAM (16 Kbytes) when the main Power Supply of the device (V DD and consequently the internally generated V18) is turned off for low power mode, allowing data retention. VSTBY voltage shall be in the range 4.5 to 5.5 volts and a dedicated embedded low power voltage regulator is in charge to provide the

1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator and the Real Time Clock

module when not disabled. It is allowed to exceed the upper limit up to 6 V for a very short period of time during the global life of the device and exceed the lower limit down to 4 V when RTC and 32 kHz on-chip oscillator are not used. A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here SSC0, while the new one is referred as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic SSC and the new XSSC. A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0, while the new one is referred as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic ASC and the new XASC. A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM and the new XPWM. An I2C interface on the XBUS is added (see X-I2C or simply I2C interface).

CLKOUT function can output either the CPU clock (like in ST10F269) or a software programmable prescaled value of the CPU clock. On-chip RAM memory and FLASH size have been increased. PLL multiplication factors have been adapted to new frequency range. A/D Converter is not fully compatible versus ST10F269 (timing and programming model). Formula for the conversion time is still valid, while the sampling phase programming model is different. Besides, additional 8 channels are available on P1L pins as alternate function: The accuracy reachable with these extra channels is reduced with respect to the standard Port5 channels. External Memory bus is affected by limitations on maximum speed and maximum capacitance load: ST10F273E is not able to address an external memory at 64 MHz with 0 wait states. XPERCON register bit mapping modified according to new peripherals implementation (not fully compatible with ST10F269). Bondout chip for emulation (ST10R201) cannot achieve more than 50MHz at room temperature (so no real time emulation possible at maximum speed). Input section characteristics are different. The threshold programmability is extended to all port pins (additional XPICON register); it is possible to select standard TTL (with up to 400mV of hysteresis) and standard CMOS (with up to 750mV of hysteresis). Output transition is not programmable. CAN module is enhanced: ST10F273E implements two C-CAN modules, so the programming model is slightly different. Besides, the possibility to map in parallel the two CAN modules is added (on P4.5/P4.6). On-chip main oscillator input frequency range has been reshaped, reducing it from 1 to 25 MHz down to 4 to 8 MHz. This is a low power oscillator amplifier, that allows a power consumption reduction when Real Time Clock is running in Power down mode, using as reference the on-chip main oscillator clock. When this on-chip amplifier is used as reference for Real Time Clock module, the Power-down consumption is dominated by the consumption of the oscillator amplifier itself. A second on-chip oscillator amplifier circuit (32 kHz) is implemented for low power modes: it can be used to provide the reference to the Real Time Clock counter (either in Power down or Stand-by mode). Pin XTAL3 and XTAL4 replace a couple of V DD/VSS pins of ST10F269.

Figure 1. ST10F273E Logic symbol

2 Pin data

Figure 2. Pin configuration (top view)

Table 1. Pin description drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS).

drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). Table 1. Pin description (continued)

as push-pull or open drain drivers. write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. multiplexed mode, this signal is the latch command of the address lines.

inside the Stand-by portion of the XRAM (16Kbyte). guarantees the proper biasing of all those modules. Port 0 is selectable (TTL or CMOS).

XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input. XTAL2 137 O XTAL2 Main oscillator amplifier circuit output. the AC Characteristics must be observed. external crystal, and not by a different clock source. (end of initialization) instruction is executed. should be pulled high externally. asynchronous reset selection. It can be turned off when Stand-by RAM mode is selected. must be connected between this pin and nearest VSS pin.

3 Functional description

Figure 3. Block diagram

4 Memory organization

space of 16 Mbytes. The entire memory space can be accessed Byte wise or Word wise. to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group. storage for data, user stack and code.

32 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an

(31.25ns access at 64 MHz CPU clock). Byte and Word accesses are allowed. Table 2. Summary of IFlash address range

ST10F273E Memory organization interface, using the BUSCONx register corresponding to address matching ADDRSELx register. The XRAM2 address range is F’0000h-F’7FFFFh if XPEN (bit 2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. The lower portion of the XRAM2 (address range F’0000h-F’3FFFFh) represents also the Stand-by RAM, which can be maintained biased through EA / VSTBY pin when main supply VDD is turned off. As the XRAM appears like external memory, it cannot be used as system stack or as register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function register areas. SFRs are Wordwide registers which are used to control and to monitor the function of the different on-chip units. CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. The CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit 0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64 MHz CPU clock. No tri-state wait states are used. CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit 1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64 MHz CPU clock. No tri-state wait states are used. If one or the two CAN modules are used, Port 4 cannot be programmed to output all eight segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line). RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used. PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 Module access. The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16- bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz CPU clock. No tristate waitstate is used. Only word access is allowed. ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is used. SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus

Memory organization ST10F273E (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used. I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register. Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used. X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON register and bit 10 of the XPERCON register. Accesses to this additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used. The following set of features are provided:

• CLKOUT programmable divider
• XBUS interrupt management registers
• ADC multiplexing on P1L register
• Port1L digital disable register for extra ADC channels
• CAN2 multiplexing on P4.5/P4.6
• CAN1-2 main clock prescaler
• Main voltage regulator disable for Power-down mode
• TTL / CMOS threshold selection for Port0, Port1 and Port5. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external memory can be connected to the microcontroller. Visibility of XBUS peripherals In order to keep the ST10F273E compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the global enabling with XPEN bit in SYSCON register, the corresponding address space, port pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and not available. Refer to Chapter 23: Register set on page 111.

5 Internal Flash memory

5.1 Overview

under modification. Bank 0 is 384 Kbytes wide, Bank 1 is 128 Kbytes wide. This module is on ST10 Internal bus, so it is called IFlash. Figure 4. Flash structure accesses to IFlash. Read/write accesses to IFlash Control Registers area are 16-bit wide.

5.2 Functional description

5.2.1 Structure

Following table shows the Address space reserved to the Flash module.

8 Kbyte test-Flash

Table 3. Address space of the Flash module

5.2.2 Modules structure

by the Flash Program/Erase controller. Table 4. Flash modules sectorization (read operations)

The table above refers to the configuration when bit ROMS1 of SYSCON register is set.

• Test-Flash is seen and available for code fetches (address 00’0000h)
• User I-Flash is only available for read and write accesses
• Write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever ROMS1 bit in SYSCON value
• Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value. In Bootstrap mode, by default ROMS1 = 0, so the first 32 KBytes of IFlash are mapped in segment 0. Example: In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed. Next Table 6 shows the Control Register interface composition: This set of registers can be addressed by the CPU.

Table 5. Flash modules sectorization (1)

1. Write operations or with ROMS1=’1’ or bootstrap mode

5.2.3 Low power mode

consumption is drastically reduced, but exiting this state can require a long time (tPD). it is important to size properly the external circuit on RPD pin.

5.3 Write operation

16-bit instructions (since operates in 16-bit mode when in read/ write). (XFLASHEN) in XPERCON register shall be set. another bank or from the other memory (internal RAM or external memory). Table 6. Control register interface

5.4 Registers description

5.4.1 Flash control register 0 low

the user in Bootstrap mode only. reserved BSY1 BSY0 LOCK res. res. res. res. Table 7. Flash control register 0 low these bits is automatically set again. automatically set when the Flash bit WMS is set. low, the rest of FCR0L and all the other Flash registers are accessible by the user as well.

5.4.2 Flash control register 0 high

the user in Bootstrap mode only. Table 8. Flash control register 0 high Protection Registers, SMOD is automatically reset at the end of the Write Operation. 0x0EDFBF . SPR bit is automatically reset at the end of the Set Protection operation. the end of the Sector Erase operation. This bit must be set to select the Double Word (64 bits) Program operation in the Flash module. reset at the end of the Double Word Program operation. at the end of the Word Program operation.

5.4.3 Flash control register 1 low

status of each sector and bank. high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect.

1. It is forbidden to start a new Write operation with bit SUSP already set.

Table 8. Flash control register 0 high (continued) Table 9. Flash control register 1 low These bits must be set during a Sector Erase operation to select the sectors to erase in Bank 0. reset at the end of a Write operation if no errors are detected.

5.4.4 Flash control register 1 high

status of each sector and bank. Table 10. Flash control register 1 high These bits must be set during a Sector Erase operation to select the sectors to erase in Bank 1. reset at the end of a Write operation if no errors are detected. During any erase operation, this bit is automatically modified and gives the status of the Bank 0. meaning. This bit is automatically reset at the end of a erase operation if no errors are detected. During any erase operation, this bit is automatically modified and gives the status of the Bank 1. meaning. This bit is automatically reset at the end of a erase operation if no errors are detected. Table 11. Banks (BxS) and sectors (BxFy) status bits meaning

5.4.5 Flash data register 0 low

5.4.6 Flash data register 0 high

Table 12. Flash data register 0 low Program (32-bit), Double Word Program (64-bit) and Set Protection. Table 13. Flash data register 0 high Program (32-bit), Double Word Program (64-bit) and Set Protection.

5.4.7 Flash data register 1 low

5.4.8 Flash data register 1 high

5.4.9 Flash address register low

Table 14. Flash data register 1 low Program (32-bit), Double Word Program (64-bit) and Set Protection. Table 15. Flash data register 1 high Program (32-bit), Double Word Program (64-bit) and Set Protection. Table 16. Flash address register low ADD2 must be written to ‘0’.

5.4.10 Flash address register high

5.4.11 Flash error register

only when LOCK bit and BSYx bits are cleared. Table 17. Flash address register high operations: Word Program and Double Word Program. Table 18. Flash error register sector where it occurred must be discarded. This bit has to be software reset. occurred must be discarded. This bit has to be software reset. but only flags that the desired data has not been written. This bit has to be software reset. Operation is executed. This bit has to be software reset.

5.5 Protection strategy

available protections are forced active during reset. Registers paragraph), that can be executed from all the internal or external memories. shown, and architecture limitations are highlighted as well.

5.5.1 Protection registers

The 5 Non Volatile Protection Registers are one time programmable for the user. store the Access Protection fuses. erased and bit WPF is set. This bit has to be software reset.

5.5.2 Flash non volatile writ e protection I register low

5.5.3 Flash non volatile writ e protection I register high

5.5.4 Flash non volatile ac cess protection register 0

Table 19. Flash non volatile write protection register low These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFlash). Table 20. Flash non volatile protection register high These bits, if programmed at 0, disable any write access to the sectors of Bank 1 (IFlash). Table 21. Flash non volatile access protection register 0 address space, unless the current instruction is fetched from IFlash. to run any eventual failure analysis.

5.5.5 Flash non volat ile access protection register 1 low

5.5.6 Flash non volat ile access protection register 1 high

5.5.7 Access protection

way can be executed a maximum of 16 times. external memories will output a dummy data (software trap 0x009Bh). necessary to temporarily unprotect the Flash module. Table 22. Flash non volatile access protection register 1 low at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. Table 23. Flash non volatile access protection register 1 high again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0.

column headers) is shown in the table.

5.5.8 Write protection

5.5.9 Temporary unprotection

operation and writing 1 into these bits. writing are executed from IFlash. execute a Set Protection operation and write 0 into desidered bits. code: it is, in fact, sufficient to execute the updating instructions from another Flash bank. unprotection cannot be detected). Table 24. Summary of access protection level

Internal Flash memory ST10F273E

5.6 Write operation examples

In the following, examples for each kind of Flash write operation are presented. Note: Moreover, direct addressing is not allowed for write accesses to IFlash control registers. This means that both address and data for a writing operation must be loaded in one of ST10 GPR register (R0...R15). Write operation on IBus registers is 16 bit wide. Example of indirect addressing mode: MOV RWm, #ADDRESS; /*Load Add in RWm*/ MOV RWn, #DATA; /*Load Data in RWn*/ MOV [RWm], RWn; /*Indirect addressing*/ Word program Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x025554 FCR0H|= 0x2080; /*Set WPG in FCR0H, SMOD must be set*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x0002; /*Load Add in FARH*/ FDR0L = 0xAAAA; /*Load Data in FDR0L*/ FDR0H = 0xAAAA; /*Load Data in FDR0H*/ FCR0H|= 0x8000; /*Operation start*/ Double word program Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x035558 and data 0xAA55AA55 at address 0x03555C. FCR0H |= 0x1080; /*Set DWPG, SMOD must be set/ FARL = 0x5558; /*Load Add in FARL*/ FARH = 0x0003; /*Load Add in FARH*/ FDR0L = 0x55AA; /*Load Data in FDR0L*/ FDR0H = 0x55AA; /*Load Data in FDR0H*/ FDR1L = 0xAA55; /*Load Data in FDR1L*/ FDR1H = 0xAA55; /*Load Data in FDR1H*/ FCR0H |= 0x8000; /*Operation start*/ Double Word Program is always performed on the Double Word aligned on a even Word: bit ADD2 of FARL is ignored. Sector erase Example: Sector Erase of sectors B0F1 and B0F0 of Bank 0. FCR0H |= 0x0880; /*Set SER in FCR0H, SMOD must be set*/ FCR1L |= 0x0003; /*Set B0F1, B0F0*/ FCR0H |= 0x8000; /*Operation start*/ Suspend and resume Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way: FCR0H |= 0x4000; /*Set SUSP in FCR0H*/

ST10F273E Internal Flash memory Then the operation can be resumed in the following way: FCR0H |= 0x0800; /*Set SER in FCR0H*/ FCR0H |= 0x8000; /*Operation resume*/ Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set. Erase suspend, program and resume A Sector Erase operation can be suspended in order to program (Word or Double Word) another sector. Example: Sector Erase of sector B0F1. FCR0H |= 0x0880; /*Set SER in FCR0H, SMOD must be set*/ FCR1L |= 0x0002; /*Set B0F1*/ FCR0H |= 0x8000; /*Operation start*/ Example: Sector Erase Suspend. FCR0H |= 0x4000; /*Set SUSP in FCR0H*/ do /*Loop to wait for LOCK=0 and WMS=0*/ {tmp1 = FCR0L; tmp2 = FCR0H; } while ((tmp1 && 0x0010) || (tmp2 && 0x8000)); Example: Word Program of data 0x5555AAAA at address 0x045554. FCR0H &= 0xBFFF; /*Rst SUSP in FCR0H*/ FCR0H|= 0x2080;/*Set WPG in FCR0H, SMOD must be set*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x0004; /*Load Add in FARH*/ FDR0L = 0xAAAA; /*Load Data in FDR0L*/ FDR0H = 0x5555; /*Load Data in FDR0H*/ FCR0H |= 0x8000; /*Operation start*/ Once the Program operation is finished, the Erase operation can be resumed in the following way: FCR0H|= 0x0800;/*Set SER in FCR0H*/ FCR0H|= 0x8000;/*Operation resume*/ Notice that during the Program Operation in Erase suspend, bits SER and SUSP are low. A Word or Double Word Program during Erase Suspend cannot be suspended. In summary: A Sector Erase can be suspended by setting SUSP bit.

• To perform a Word Program operation during Erase Suspend, firstly bits SUSP and SER must be reset, then bit WPG and WMS can be set.
• To resume the Sector Erase operation bit SER must be set again.
• In any case it is forbidden to start any write operation with SUSP bit already set.

Internal Flash memory ST10F273E Set Protection Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0. FCR0H |= 0x0100; /*Set SPR in FCR0H*/ FARL = 0xDFB4; /*Load Add of register FNVWPIR in FARL*/ FARH = 0x000E; /*Load Add of register FNVWPIR in FARH*/ FDR0L = 0xFFF0; /*Load Data in FDR0L*/ FDR0H = 0xFFFF; /*Load Data in FDR0H*/ FCR0H |= 0x8000; /*Operation start*/ Notice that SMOD bit of FCR0H must NOT be set. Example 2: Enable Access and Debug Protection. FCR0H |= 0x0100; /*Set SPR in FCR0H*/ FARL = 0xDFB8; /*Load Add of register FNVAPR0 in FARL*/ FARH = 0x000E; /*Load Add of register FNVAPR0 in FARH*/ FDR0L = 0xFFFC; /*Load Data in FDR0L*/ FCR0H |= 0x8000; /*Operation start*/ Notice that SMOD bit of FCR0H must NOT be set. Example 3: Disable in a permanent way Access and Debug Protection. FCR0H |= 0x0100; /*Set SPR in FCR0H*/ FARL = 0xDFBC; /*Load Add of register FNVAPR1L in FARL*/ FARH = 0x000E; /*Load Add of register FNVAPR1L in FARH*/ FDR0L = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/ FCR0H |= 0x8000; /*Operation start*/ Notice that SMOD bit of FCR0H must NOT be set. Example 4: Enable again in a permanent way Access and Debug Protection, after having disabled them. FCR0H |= 0x0100; /*Set SPR in FCR0H*/ FARL = 0xDFBC; /*Load Add register FNVAPR1H in FARL*/ FARH = 0x000E; /*Load Add register FNVAPR1H in FARH*/ FDR0H = 0xFFFE; /*Load Data in FDR0H for clearing PEN0*/ FCR0H |= 0x8000; /*Operation start*/ Notice that SMOD bit of FCR0H must NOT be set. Disable and re-enable of Access and Debug Protection in a permanent way (as shown by examples 3 and 4) can be done for a maximum of 16 times.

5.7 Write operation summary

1. The first instruction is used to select the desired operation by setting its corresponding

selection bit in the Flash Control Register 0.

1. The second step is the definition of the Address and Data for programming or the

Volatile Protection registers.

1. The last instruction is used to start the write operation, by setting the start bit WMS in

Table 25. Flash write operations

6 Bootstrap loader

• Support bootstrap via UART or bootstrap via CAN for the standard bootstrap.
• Support a selective bootstrap loader, to manage the bootstrap sequence in a different way.

6.1 Selection among user-code, st andard or selective bootstrap

signals, as other configuration signals, are latched on the rising edge of RSTIN pin.

• Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) will select the normal mode (also called User mode) and select the user Flash to be mapped from address 00’0000h.
• Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) will select ST10 standard bootstrap mode (Test-Flash is active and overlaps user Flash for code fetches from address 00'0000h; user Flash is active and available for read accesses).
• Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) will activate new verifications to select which bootstrap software to execute: – if the User mode signature in the User Flash is programmed correctly, then a software reset sequence is selected and the User code is executed; – if the User mode signature is not programmed correctly in the user Flash, then the User key location is read again. Its value will determine which communication channel will be enabled for bootstraping.

6.2 Standard bootstrap loader

interface, or a start condition from UART line. bootstrap loader is identical to other ST10 devices (example: ST10F269, ST10F168). Valid dominant bit on CAN1 RxD: ST10F273E start bootstrapping via CAN1. Table 26. ST10F273E boot mode selection

11 User mode: user Flash mapped at 00’0000h

10 Standard bootstrap loader: User Flash mapped from 00’0000h, code fetches

00 R e s e r v e d

ST10F273E Bootstrap loader

6.3 Alternate and selective boot mode (ABM & SBM)

6.3.1 Activation of the ABM and SBM

Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN.

6.3.2 User mode signature integrity check

The behavior of the Selective Boot mode is based on the computing of a signature between the content of 2 memory locations and a comparison with a reference signature. This requires that users who use Selective Boot have reserved and programmed the Flash memory locations.

6.3.3 Selective boot mode

When the user signature is not correct, instead of executing the Standard Bootstrap Loader (triggered by P0L.4 low at reset), additional check is made. Depending on the value at the User key location, following behavior will occur:

• A jump is performed to the Standard Bootstrap Loader
• Only UART is enabled for bootstraping
• Only CAN1 is enabled for bootstraping
• The device enters an infinite loop.

7 Central processing unit (CPU)

unit, a bit-mask generator and a barrel shifter. processed in one instruction cycle independent of the number of bits to be shifted. 16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles. Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area. easy parameter passing, a register bank may overlap others. value upon each stack access for the detection of a stack overflow or underflow. Figure 5. CPU block diagram (MAC unit not included) Data Pg. Ptrs Code Seg. Ptr.

512 Kbyte

7.1 Multiplier-accumulator unit (MAC)

improve the performances of the ST10 Family in signal processing algorithms. enable the CPU to supply the new coprocessor with up to 2 operands per instruction cycle. accumulate, 32-bit signed arithmetic operations. Figure 6. MAC unit architecture

7.2 Instruction set summary

instruction can be found in the “ST10 Family Programming Manual”. Table 27. Standard instruction set summary

Table 27. Standard instruction set summary (continued)

7.3 MAC coprocessor specific instructions

instructions are encoded on 4 bytes. Table 28. MAC instruction set summary

ST10F273E External bus controller

8 External bus controller

All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes:

• 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed
• 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed
• 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed
• 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed In demultiplexed bus modes addresses are output on PORT1 and data is input / output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input / output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to four independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these four address windows are controlled by BUSCON0. Up to five external CS signals (four windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a ‘Ready’ function. A HOLD / HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to’1’ the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an address space of 16M Bytes is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register.

9 Interrupt system

by the Peripheral Event Controller (PEC). each of them offers such fast interrupt-driven data transfer capabilities. related register, each source can be programmed to one of sixteen interrupt priority levels. possible interrupt sources has a dedicated vector location. individual trap (interrupt) number. falling edge or both edges). used to interrupt the system. Table 29. Interrupt sources

Table 29. Interrupt sources (continued)

to a dedicated vector table location). be interrupted by standard interrupt or by PEC interrupts.

9.1 X-Peripheral interrupt

vectors (XP0INT, XP1INT, XP2INT and XP3INT).

• Byte High XIRxSEL[15:8] Interrupt Enable bits
• Byte Low XIRxSEL[7:0] Interrupt Flag bits GPT2 timer 6 T6IR T6IE T6INT 00’0098h 26h GPT2 CAPREL register CRIR CRIE CRINT 00’009Ch 27h A/D conversion complete ADCIR ADCIE ADCINT 00’00A0h 28h A/D overrun error ADEIR ADEIE ADEINT 00’00A4h 29h ASC0 transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah ASC0 transmit buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h ASC0 receive S0RIR S0RIE S0RINT 00’00ACh 2Bh ASC0 error S0EIR S0EIE S0EINT 00’00B0h 2Ch SSC transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh SSC receive SCRIR SCRIE SCRINT 00’00B8h 2Eh SSC error SCEIR SCEIE SCEINT 00’00BCh 2Fh PWM channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh See Section 9.1 XP0IR XP0IE XP0INT 00’0100h 40h See Section 9.1 XP1IR XP1IE XP1INT 00’0104h 41h See Section 9.1 XP2IR XP2IE XP2INT 00’0108h 42h See Section 9.1 XP3IR XP3IE XP3INT 00’010Ch 43h

bits may be implemented inside the user application. Figure 7. X-Interrupt basic structure Table 30. X-Interrupt detailed mapping

9.2 Exception and error traps list

Table 30. X-Interrupt detailed mapping (continued) Table 31. Trap priorities

1. All the class B traps have the same trap number (and vector) and the same lower priority compared to the

class A traps and to the resets. The resets have the highest priority level and the same trap number. The PSW.ILVL CPU priority is forced to the highes t level (15) when these exceptions are serviced.

ST10F273E Capture / compare (CAPCOM) units

10 Capture / compare (CAPCOM) units

The ST10F273E has two 16-channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125ns at 64 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture / compare register, specific actions will be taken based on the selected compare mode. The input frequencies f Tx, for the timer input selector Tx, are determined as a function of the CPU clocks. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in the Table 33 and Table 34 respectively. The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant figures.

Table 32. Compare modes compare events per timer period are possible. Table 33. CAPCOM timer input frequencies, resolutions and periods at 40 MHz Table 34. CAPCOM timer input frequencies, resolutions and periods at 64 MHz

11 General purpose timer unit

11.1 GPT1

In counter mode, the timer is clocked in reference to external events. scaler option at 40MHz and 64MHz CPU clock respectively. the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. sensor signal TOP0 can be connected to an interrupt input. high resolution of long duration measurements. capture registers for timer T3. Table 35. GPT1 timer input frequencies, resolutions and periods at 40 MHz

Figure 8. Block diagram of GPT1 Table 36. GPT1 timer input frequencies, resolutions and periods at 64 MHz

11.2 GPT2

or may additionally be altered dynamically by an external signal on a port pin (TxEUD). which changes its state on each timer overflow/underflow. be performed without software overhead. scaler option at 40MHz and 64MHz CPU clock respectively. Table 37. GPT2 timer input frequencies, resolutions and periods at 40 MHz Table 38. GPT2 timer input frequencies, resolutions and periods at 64 MHz

Figure 9. Block diagram of GPT2

12 PWM modules

generate interrupt requests. Figure 10. Block diagram of PWM module Table 39. PWM unit frequencies and resolutions at 40 MHz CPU clock Table 40. PWM unit frequencies and resolutions at 64 MHz CPU clock

13 Parallel ports

13.1 Introduction

The ST10F273E MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F273E has nine groups of I/O lines gathered as follows:

• Port 0 is a two time 8-bit port named P0L (Low as less significant byte) and P0H (high as most significant byte)
• Port 1 is a two time 8-bit port named P1L and P1H
• Port 2 is a 16-bit port
• Port 3 is a 15-bit port (P3.14 line is not implemented)
• Port 4 is a 8-bit port
• Port 5 is a 16-bit port input only
• Port 6, Port 7 and Port 8 are 8-bit ports These ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers. For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bit- wise) for push-pull or open drain operation using ODPx registers. The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. The threshold is selected with PICON and XPICON registers control bits. A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A read- modify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. I/O lines support an alternate function which is detailed in the following description of each port.

13.2 I/O’s special features

13.2.1 Open drain mode

Some of the I/O ports of ST10F273E support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections) and is controlled through the respective Open Drain Control Registers ODPx.

13.2.2 Input thre shold control

The standard inputs of the ST10F273E determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. The Port Input Control registers PICON and XPICON are used to select these thresholds for each Byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each. All options for individual direction and output mode control are available for each pin, independent of the selected input threshold.

13.3 Alternate port functions

Each port line has one associated programmable alternate input or output function.

• PORT0 and PORT1 may be used as address and data lines when accessing external memory. Besides, PORT1 provides also: – Input capture lines – 8 additional analog input channels to the A/D converter
• Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module and of the ASC1. Port 2 is also used for fast external interrupt inputs and for timer 7 input.
• Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT).
• Port 4 outputs the additional segment address bit A23...A16 in systems where more than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I lines are provided.
• Port 5 is used as analog input channels of the A/D converter or as timer control signals.
• Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals and the SSC1 lines. If the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y=‘1’), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a ‘1’, because its output is ANDed with the alternate output data (except for PWM output signals).

If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=‘0’) if an external device is driving the pin. The input direction is the default after reset. If no external device is connected to the pin, however, one can also set the direction for this pin to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output. There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.

14 A/D converter

A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. The ST10F273E has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description. A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog channels (with higher restrictions when overload conditions occur); in particular, Port 5 channels are more accurate than the Port 1 ones. Refer to Electrical Characteristic section for details. The A/D converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5LSB (2mV) impacting the global TUE (TUE depends also on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave shall be reduced to 800 Hz. If static signal is applied during sampling phase, series resistance shall not be greater than 20kΩ (this taking into account eventual input leakage). It is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an RC filter is necessary the external capacitance must be greater than 10nF to minimize the accuracy impact. Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16+8 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F273E supports different conversion modes:

• Single channel single conversion: The analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register.
• Single channel continuous conversion: The analog level of the selected channel is repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register.
• Auto scan single conversion: The analog level of the selected channels are sampled once and converted. After each conversion the result is stored in the ADDAT register. The data can be transferred to the RAM by interrupt software management or using the powerful Peripheral Event Controller (PEC) data transfer.
• Auto scan continuous conversion: The analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT

register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer.

• Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold.
• Channel injection mode: When using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10-bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed. A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630 CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. No conversion can be performed during this time: the bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a convertion.

15 Serial channels

15.1 Asynchronous / synchronous serial interfaces

15.2 ASCx in asynchronous mode

CPU) is supported in this mode. Table 41. ASC asynchronous baud rates by reload value and deviation errors (f CPU = 40 MHz)

errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency).

15.3 ASCx in synchronous mode

CPU) is possible in this mode. Table 42. ASC asynchronous baud rates by reload value and deviation errors (f CPU = 64 MHz) Table 43. ASC synchronous baud rates by reload value and deviation errors (f CPU = 40 MHz)

15.4 High speed synchronous serial interfaces

microprocessors or external peripherals. 16-bit reload capability, allowing Baud rate generation independent from the timers. Table 44. ASC synchronous baud rates by reload value and deviation errors (f CPU = 64 MHz)

Table 45. Synchronous baud rate and reload values (f CPU = 40 MHz) Table 46. Synchronous baud rate and reload values (f CPU = 64 MHz)

16 I 2C interface

The integrated I2C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I2C Bus specification. The I2C Module can operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s (both Standard and Fast I 2C bus modes are supported). The module can generate three different types of interrupt:

• Requests related to bus events, like start or stop events, arbitration lost, etc.
• Requests related to data transmission
• Requests related to data reception These requests are issued to the interrupt controller by three different lines, and identified as Error, Transmit, and Receive interrupt lines. When the I2C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and P4.7 (where SCL and SDA are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin configuration. When the I 2C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. The speed of the I2C interface may be selected between Standard mode (0 to 100 kHz) and Fast I2C mode (100 to 400 kHz).

17 CAN modules

The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). It is based on the C-CAN specification. Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Because of duplication of the CAN controllers, the following adjustments are to be considered:

• Same internal register addresses of both CAN controllers, but with base addresses differing in address bit A8; separate chip select for each CAN module. Refer to Chapter 4: Memory organization on page 22.
• The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.
• The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.
• Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS interrupt lines together with other X-Peripherals sharing the four vectors.
• The CAN modules must be selected with corresponding CANxEN bit of XPERCON register before the bit XPEN of SYSCON register is set.
• The reset default configuration is: CAN1 enabled, CAN2 disabled. Note: If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line).

17.1 Configuration support

It is possible that both CAN controllers are working on the same CAN bus, supporting together up to 64 message objects. In this configuration, both receive signals and both transmit signals are linked together when using the same CAN transceiver. This configuration is especially supported by providing open drain outputs for the CAN1_Txd and CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4: in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with P4.7 (transmit lines configured to be configured as Open-Drain). The user is also allowed to map internally both CAN modules on the same pins P4.5 and P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used for I 2C interface. This is possible by setting bit CANPAR of XMISC register. To access this register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON register.

17.2 CAN bus configurations

able to support these two cases. Figure 11. Connection to single CAN bus via separate CAN transceivers take in account the wire length and the noise environment. Figure 12. Connection to single CAN bus via common CAN transceivers

18 Real time clock

The real time clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept on running even in idle or power down mode (if enabled to). Registers access is implemented onto the XBUS. This module is designed with the following characteristics:

• Generation of the current time and date for the system
• Cyclic time based interrupt, on Port2 external interrupts every ’RTC basic clock tick’ and after n ’RTC basic clock ticks’ (n is programmable) if enabled
• 58-bit timer for long term measurement
• Capability to exit the ST10 chip from Power down mode (if PWDCFG of SYSCON set) after a programmed delay The real time clock is based on two main blocks of counters. The first block is a prescaler which generates a basic reference clock (for example a 1 second period). This basic reference clock is coming out of a 20-bit DIVIDER. This 20-bit counter is driven by an input clock derived from the on-chip CPU clock, pre-divided by a 1/64 fixed counter. This 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit PRESCALER register. The value of the 20-bit RTCP register determines the period of the basic reference clock. A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The second block of the RTC is a 32-bit counter that may be initialized with the current system time. This counter is driven with the basic reference clock signal. In order to provide an alarm function the contents of the counter is compared with a 32-bit alarm register. The alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI), may be generated when the value of the counter matches the alarm register. The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running power down mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock oscillator when entering the power down mode. The last function implemented in the RTC is to switch off the main on-chip oscillator and the 32 kHz on chip oscillator if the ST10 enters the Power down mode, so that the chip can be fully switched off (if RTC is disabled). At power on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 / XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference clock: when Power down mode is entered, the RTC can either be stopped or left running, and in both the cases the main oscillator is turned off, reducing the power consumption of the device to the minimum required to keep on running the RTC counter and relative reference oscillator. This is valid also if Stand-by mode is entered (switching off the main supply V DD), since both the RTC and the low power oscillator (32 kHz) are biased by the VSTBY. Vice versa, when at power on and after Reset, the 32 kHz is not present, the main oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Stand-by mode, while in Power down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled).

19 Watchdog timer

malfunctioning for long periods of time. the time interval until the EINIT (end of initialization) instruction has been executed.

• Watchdog timer reset in case of an overflow
• Software Reset in case of execution of the SRST instruction
• Short, long and power-on reset in case of hardware reset (and depending of reset pulse duration and RPD pin configuration) The indicated bits are cleared with the EINIT instruction. The source of the reset can be identified during the initialization phase. The watchdog timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced The Table 47 and Ta bl e 4 8 show the watchdog time range for 40 MHz and 64 MHz CPU clock respectively.

Table 47. WDTREL reload value (f CPU = 40 MHz) Table 48. WDTREL reload value (f CPU = 64 MHz)

20 System reset

20.1 Input filter

reset events shall be carefully evaluated taking into account of the above requirements.

• For a CPU clock of 64 MHz, 4 TCL is 31.25ns, so it would be filtered. In this case the minimum becomes the one imposed by the filter (that is 500ns).
• For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula is coherent with the limit imposed by the filter.

Table 49. Reset event definition

1. RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2. See next Section 20.1 for more details on minimum reset pulse duration
3. The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD

20.2 Asynchronous reset

An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F273E is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins. Note: If an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended. Power-on reset The asynchronous reset must be used during the power-on of the device. Depending on crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to stabilize (Refer to Electrical Characteristics Section), with an already stable V DD. The logic of the ST10F273E does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled. At Power-on it is important to respect some additional constraints introduced by the start-up phase of the different embedded modules. In particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8V for the core logic: this time is computed from when the external reference (V DD) becomes stable (inside specification range, that is at least 4.5V). This is a constraint for the application hardware (external voltage regulator): the RSTIN pin assertion shall be extended to guarantee the voltage regulator stabilization. A second constraint is imposed by the embedded FLASH. When booting from internal memory, starting from RSTIN releasing, it needs a maximum of 1ms for its initialization: before that, the internal reset (RST signal) is not released, so the CPU does not start code execution in internal memory. Note: This is not true if external memory is used (pin EA held low during reset phase). In this case, once RSTIN pin is released, and after few CPU clock (Filter delay plus 3...8 TCL), the internal reset signal RST is released as well, so the code execution can start immediately after. Obviously, an eventual access to the data in internal Flash is forbidden before its initialization phase is completed: an eventual access during starting phase will return FFFFh (just at the beginning), while later 009Bh (an illegal opcode trap can be generated). At Power-on, the RSTIN pin shall be tied low for a minimum time that includes also the start- up time of the main oscillator (tSTUP = 1ms for resonator, 10ms for crystal) and PLL synchronization time (tPSUP = 200µs): this means that if the internal FLASH is used, the RSTIN pin could be released before the main oscillator and PLL are stable to recover some time in the start-up phase (FLASH initialization only needs stable V18, but does not need stable system clock since an internal dedicated oscillator is used). Warning: It is recommended to provide the external hardware with a current limitation circuitry. This is necessary to avoid permanent damages of the device during the power-on transient, when the capacitance on V 18 pin is charged. For the on-chip voltage regulator functionality 10nF are

sufficient: anyway, a maximum of 100nF on V18 pin should not generate problems of over-current (higher value is allowed if current is limited by the external hardware). External current limitation is anyway recommended also to avoid risks of damage in case of temporary short between V 18 and ground: the internal 1.8V drivers are sized to drive currents of several tens of Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to Electrical Characteristics Section). In next Figures 15 and 16 Asynchronous Power-on timing diagrams are reported, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages.

Figure 15. Asynchronous power-on RESET (EA = 1)

7 TCL

Figure 16. Asynchronous power-on RESET (EA = 0) It occurs when RSTIN is low and RPD is detected (or becomes) low as well.

8 TCL

Figure 17. Asynchronous hardware RESET (EA = 1)

Figure 18. Asynchronous hardware RESET (EA = 0) 2) 3 to 8 TCL depending on clock source selection.

20.3 Synchronous reset (warm reset)

12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are

register was previously set by software. Note that this bit is always cleared on power-on or after a reset sequence. Short and long synchronous reset Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts. It is 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN is sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short Reset is flagged (Refer to Chapter 19 for details on reset flags); if it is recognized still low, the Long reset is flagged as well. The major difference between Long and Short reset is that during the Long reset, also P0(15:13) become transparent, so it is possible to change the clock options. Warning: In case of a short pulse on RSTIN pin, and when Bidirectional reset is enabled, the RSTIN pin is held low by the internal circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is released, but due to the presence of the input analog filter the internal input reset signal (RSTF in the drawings) is released later (from 50 to 500ns). This delay is in parallel with the additional 8 TCL, at the end of which the internal input reset line (RSTF ) is sampled, to decide if the reset event is Short or Long. In particular:

• If 8 TCL > 500ns (FCPU < 8 MHz), the reset event is always recognized as Short
• If 8 TCL < 500ns (FCPU > 8 MHz), the reset event could be recognized either as Short or Long, depending on the real filter delay (between 50 and 500ns) and the CPU frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the P0(15:13) pins becomes transparent, so the system clock can be re-configured. The port returns not transparent 3-4TCL after the internal RSTF signal becomes high. The same behavior just described, occurs also when unidirectional reset is selected and RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL) and released exactly at that time. Note: When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns); so it might happen that a short reset pulse is not filtered by the analog input filter, but on the other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would generate a FLASH reset but not a system reset. In this condition, the FLASH answers always with FFFFh, which leads to an illegal opcode and consequently a trap event is generated. Exit from synchronous reset state The reset sequence is extended until RSTIN level becomes high. Besides, it is internally prolonged by the FLASH initialization when EA=1 (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F273E starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized in Figures 19 and 20 where a Short Reset event is shown, with particular highlighting on the

typical synchronous Long Reset, again when booting from internal or external memory. Figure 17. There is no effect if RPD comes again above regardless of the RPD status.

Figure 19. Synchronous short / long hardware RESET (EA = 1) 1) RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. operation), the asynchronous reset is immediately entered. 3) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. 4) Bit BDRSTEN is cleared after reset. the internal filter (refer to Section 21.1).

1024 TCL

Figure 20. Synchronous short / long hardware RESET (EA = 0) 1) RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. operation), the asynchronous reset is then immediately entered. 3) 3 to 8 TCL depending on clock source selection. BDRSTEN is cleared after reset. the internal filter (refer to Section 21.1).

Figure 21. Synchronous long hardware RESET (EA = 1) the reset is defnitively taken as asynchronous. the internal filter (refer to Section 21.1).

Figure 22. Synchronous long hardware RESET (EA = 0) operation), the asynchronous reset is then immediately entered. the internal filter (refer to Section 21.1). 3) 3 to 8 TCL depending on clock source selection.

20.4 Software reset

leave bootstrap loader mode, or on a hardware trap that reveals system failure. low even though Bidirectional Reset is selected.

20.5 Watchdog timer reset

during program execution, it will overflow and trigger the reset sequence. external bus cycle is aborted. Then the internal reset sequence is started. low even though Bidirectional Reset is selected. Figure 23. SW / WDT unidirectional RESET (EA = 1)

Figure 24. SW / WDT unidirectional RESET (EA = 0)

20.6 Bidirectional reset

routine, until the protected EINIT instruction (End of Initialization) is completed. execution of EINIT instruction. only can be enabled during the initialization routine, before EINIT instruction is completed.

• After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low 8 TCL periods after the internal reset sequence completion (refer to Figure 19 and Figure 20), the Short Reset becomes a Long Reset. On the contrary, if RSTF is sampled high the device simply exits reset state.
• After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF remains still low for at least 4 TCL periods (minimum time to recognize a Short Hardware reset) after the reset exiting (refer to Figure 25 and Figure 26), the Software P0[7:2] not transparent P0[12:8] transparent not t. P0[1:0] not t.not transparent RST

or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state. The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL). Note: The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of SYSCON is cleared). To be activated again it must be enabled during the initialization routine. WDTCON flags Similarly to what already highlighted in the previous section when discussing about Short reset and the degeneration into Long reset, similar situations may occur when Bidirectional reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed, so it remains still active (low) for a while. It means that depending on the internal clock speed, a short reset may be recognized as a long reset: the WDTCON flags are set accordingly. Besides, when either Software or Watchdog bidirectional reset events occur, again when the RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal (after the filter) remains low for a while, and depending on the clock frequency it is recognized high or low: 8TCL after the completion of the internal sequence, the level of RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and WDTCON will flag this last event, masking the previous one (Software or Watchdog reset). Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently internal signal RSTF) is sufficiently held low by the external hardware to inject a Long Hardware reset. After this occurrence, the initialization routine is not able to recognize a Software or Watchdog bidirectional reset event, since a different source is flagged inside WDTCON register. This phenomenon does not occur when internal FLASH is selected during reset (EA = 1), since the initialization of the FLASH itself extend the internal reset duration well beyond the filter delay. Next Figures 25, 26 and 27 summarize the timing for Software and Watchdog Timer Bidirectional reset events: In particular Figure 27 shows the degeneration into Hardware reset.

Figure 25. SW / WDT bidirectional RESET (EA =1)

Figure 26. SW / WDT bidirectional RESET (EA = 0)

Figure 27. SW / WDT bidirectional RESET (EA =0) followed by a HW RESET

20.7 Reset circuitry

internal reset state signal (synchronous reset, watchdog timer reset or software reset). reset signal but cannot be connected to RSTOUT pin. instruction is executed. RSTOUT pin is pulled high only when EINIT is executed. capacitor connected on RPD pin. internal PLL and the on-chip voltage regulator to stabilize.

20.8 Reset application examples

Figure 31. Example of software or watchdog bidirectional reset (EA = 1)

4 TCL

Figure 32. Example of software or watchdog bidirectional reset (EA = 0)

20.9 Reset summary

A summary of the different reset events is reported in the table below. Table 50. Reset event

described in Table 51 and Figure 33.

1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details).
2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently

flagged (see Section 20.6 for details). Table 50. Reset event (continued) Table 51. PORT0 latched configuration for the different reset events

Figure 33. PORT0 bits latched into the different registers after reset

ST10F273E Power reduction modes

21 Power reduction modes

Three different power reduction modes with different levels of power reduction have been implemented in the ST10F273E. In Idle mode only CPU is stopped, while peripheral still operate. In Power down mode both CPU and peripherals are stopped. In Stand-by mode the main power supply (V DD) can be turned off while a portion of the internal RAM remains powered via VSTBY dedicated power pin. Idle and Power down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections. Stand-by mode is entered simply removing VDD, holding the MCU under reset state. Note: All external bus actions are completed before Idle or Power down mode is entered. However, Idle or Power down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access.

21.1 Idle mode

Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped and the peripherals still run. Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not, the instruction following the IDLE instruction will be executed after return from interrupt (RETI) instruction, then the CPU resumes the normal program.

21.2 Power down mode

Power down mode starts by running PWRDN protected instruction. Internal clock is stopped, all MCU parts are on hold including the watchdog timer. The only exception could be the Real Time Clock if opportunely programmed and one of the two oscillator circuits as a consequence (either the main or the 32 kHz on-chip oscillator). When Real Time Clock module is used, when the device is in Power down mode a reference clock is needed. In this case, two possible configurations may be selected by the user application according to the desired level of power reduction:

• A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4) and running. In this case the main oscillator is stopped when Power down mode is entered, while the Real Time Clock continue counting using 32 kHz clock signal as reference. The presence of a running low-power oscillator is detected after the Power- on: this clock is immediately assumed (if present, or as soon as it is detected) as reference for the Real Time Clock counter and it will be maintained forever (unless specifically disabled via software).
• Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main oscillator is not stopped when Power down is entered, and the Real Time Clock continue counting using the main oscillator clock signal as reference. There are two different operating Power down modes: protected mode and interruptible mode.

behavior (ex: CPU wake-up) and power consumption higher than what specified.

21.2.1 Protected power down mode

mode is only deactivated with an external hardware reset on RSTIN pin.

21.2.2 Interruptible power down mode

This mode is selected when PWDCFG (bit 5) of SYSCON register is set. Interrupt pins are in their inactive level. according the recommendations described in Chapter 20: System reset on page 79. An external RC circuit must be connected to RPD pin, as shown in the Figure 34. Figure 34. External RC circuitry on RPD pin

21.3 Stand-by mode

through the dedicated pin of the ST10F273E. interface is frozen in order to avoid any kind of data corruption.

ST10F273E Power reduction modes In normal running mode (that is when main VDD is on) the VSTBY pin can be tied to VSS during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with VSTBY (see in particular the 32 kHz oscillator used in conjunction with Real Time Clock module), is granted by the active main V DD. It must be noted that Stand-by mode can generate problems associated with the usage of different power supplies in CMOS systems; particular attention must be paid when the ST10F273E I/O lines are interfaced with other external CMOS integrated circuits: if V DD of ST10F273E becomes (for example in Stand-by mode) lower than the output level forced by the I/O lines of these external integrated circuits, the ST10F273E could be directly powered through the inherent diode existing on ST10F273E output driver circuitry. The same is valid for ST10F273E interfaced to active/inactive communication buses during Stand-by mode: current injection can be generated through the inherent diode. Furthermore, the sequence of turning on/off of the different voltage could be critical for the system (not only for the ST10F273E device). The device Stand-by mode current (I STBY) may vary while VDD to VSTBY (and vice versa) transition occurs: some current flows between VDD and VSTBY pins. System noise on both VDD and VSTBY can contribute to increase this phenomenon.

21.3.1 Entering stand-by mode

As already said, to enter Stand-by mode XRAM2EN bit in the XPERCON Register must be cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption. As a consequence of a RESET event, the RAM Power Supply is switched to the internal low-voltage supply V 18SB (derived from VSTBY through the low-power voltage regulator). The RAM interface will remain frozen until the bit XRAM2EN is set again by software initialization routine (at next exit from main V DD power-on reset sequence). Since V18 is falling down (as a consequence of VDD turning off), it can happen that the XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON Register powered by internal V 18. This does not generate any problem, because the Stand- by mode switching dedicated circuit continues to confirm the RAM interface freezing, irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when internal V 18 comes back over internal stand-by reference V18SB. If internal V18 becomes lower than internal stand-by reference (V18SB) of about 0.3 to 0.45V with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a temporary drop on internal V 18 voltage versus internal V18SB during normal code execution, no spurious Stand-by mode switching can occur (the RAM is not frozen and can still be accessed). The ST10F273E Core module, generating the RAM control signals, is powered by internal V 18 supply; during turning off transient these control signals follow the V18, while RAM is switched to V18SB internal reference. It could happen that a high level of RAM write strobe from ST10F273E Core (active low signal) is low enough to be recognized as a logic “0” by the RAM interface (due to V 18 lower than V18SB): The bus status could contain a valid address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism.

Power reduction modes ST10F273E Warning: During power-off phase, it is important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply.

21.3.2 Exiting stand-by mode

After the system has entered the Stand-by mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V 18SB internal reference (derived from VSTBY pin external voltage). It is recommended to held the device under RESET (RSTIN pin forced low) until external VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the device is maintained under reset by the internal low voltage detector circuit (implemented inside the main voltage regulator) till the internal V 18 becomes higher than about 1.0V, there is no warranty that the device stays under reset status if RSTIN is at high level during power ramp up. So, it is important the external hardware is able to guarantee a stable ground level on RSTIN along the power-on phase, without any temporary glitch. The external hardware shall be responsible to drive low the RSTIN pin until the VDD is stable, even though the internal LVD is active. Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to the main V18. At this time, everything becomes stable, and the execution of the initialization routines can start: XRAM2EN bit can be set, enabling the RAM.

21.3.3 Real time clock and stand-by mode

When Stand-by mode is entered (turning off the main supply VDD), the Real Time Clock counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide the reference to the counter. This is not possible if the main oscillator is used as reference for the counter: Being the main oscillator powered by V DD, once this is switched off, the oscillator is stopped.

21.3.4 Power reduc tion modes summary

Power reduction modes is reported. Table 52. Power reduction modes summary

Programmable output clock divider ST10F273E

22 Programmable output clock divider

A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed.

23 Register set

This section summarizes all registers implemented in the ST10F273E, ordered by name.

23.1 Special function registers

Bit-addressable SFRs are marked with the letter “b” in column “Name”. Table 53. List of special function registers

Table 53. List of special function registers (continued)

1. Reset Value depends on different triggered reset event.
2. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus

XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes.

23.2 X-registers

Table 54. List of XBus registers

Table 54. List of XBus registers (continued)

23.3 Flash registers ordered by name

23.4 Identification registers

• A manufacturer identifier
• A chip identifier with its revision
• A internal Flash and size identifier
• Programming voltage description Note: The ST10F273E device is a commercial version based on the ST10F276E silicon, the identification registers provide the values corresponding to the ST10F276E device.

Table 55. List of flash registers

Table 56. IDMANUF 020h: STMicroelectronics manufacturer (JTAG worldwide normalization). Table 57. IDCHIP 114h: ST10F273E identifier (276). Xh: According to revision number. Table 58. IDMEM

Note: All identification words are read only registers. initialization is complete, so all Identification Register bits are correct.

• IDMANUF 0403h
• IDCHIP 114xh (x = silicon revision)
• IDMEM F0D0h
• IDPROG 0040h 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 PROGVPP PROGVDD RR

Table 59. IDPROG following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F273E (5V).

24.1 Absolute maximum ratings

transient, in order to avoid undesired current injection through the on-chip protection diodes. Table 60. Absolute maximum ratings

24.2 Recommended operating conditions

24.3 Power considerations

PI/O represents the Power Dissipation on Input and Output Pins; User Determined. may be obtained by solving equations (1) and (2) iteratively for any value of TA. Table 61. Recommended operating conditions

1. The value of the V STBY voltage is specified in the range 4.5 to 5. 5 Volt. Nevertheless, it is acceptable to

(in the range of tenth of µA).

1. For details on operating conditions concer ning the usage of A/D Converter refer to Section 24.7.

24.4 Parameter interpretation

and its demands on the system. ST10F273E, the symbol “SR” for System Requirement, is included in the “Symbol” column. Table 62. Thermal characteristics Table 63. Product classification

24.5 DC characteristics

Table 64. DC characteristics

0.5 VDD

0.3 VDD

Table 64. DC characteristics (continued)

1. This specification is not valid for out puts which are switched to open drain mode. In this case the respective output will float

and the voltage is imposed by the external circuitry.

1. Port 5 leakage values are granted for not selected A/D C onverter channel. One channels is always selected (by default,

after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.

1. Consult your vendor to know which vers ion of the on-chip oscillator amplifier is enabled (Low-Power or Wide-Swing).
2. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used

for CS output and the open drain function is not enabled.

1. The maximum current may be drawn while the respective signal line remains inactive.
2. The minimum current must be drawn in order to drive the respective signal line active.
3. The power supply current is a function of the operating frequency (f
4. Not 100% tested, guaranteed by design characterization.
5. The power supply current is a function of the operating frequency (f

24.6 Flash characteristics

Table 65. Flash characteristics

1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer).
2. Word and Double Word Programming times are provi ded as average values derived from a full sector
3. Bank Erase is obtained through a multiple Sector Eras e operation (setting bits related to all sectors of the
4. Not 100% tested, guaranteed by Design Characterization

24.7 A/D converter characteristics

Table 66. Flash data retention characteristics

256 Kbyte (code store) 64 Kbyte

Table 67. A/D converter characteristics

24.7.1 Conversion timing control

When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next the sampled voltage is converted to a digital value several successive steps, which correspond to the 10-bit resolution of the ADC. During these steps the internal capacitances are repeatedly charged and discharged via the V AREF pin. The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. The maximum current, however, that a source can deliver, depends on its internal resistance. The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F273E relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjusting the A/D converter of the ST10F273E to the properties of the system: Fast Conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High Internal Resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. The conversion rate in this case may be considerably lower, however. The conversion times are programmed via the upper four bits of register ADCON. Bit fields ADCTC and ADSTC are used to define the basic conversion time and in particular the partition between sample phase and comparison phases. The table below lists the possible 1. V AREF can be tied to ground when A/D Converter is not in use: an extra consumption (around 200µA) on main VDD is added due to internal analogue circuitry not completely turned off: so, it is suggested to maintain the V AREF at VDD level even when not in use, and eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON register. 2. V AIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 0x000H or 0x3FFH, respectively. 3. Not 100% tested, guaranteed by design characterization. 4. During the sample time the input capacitance C AIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depends on programming and can be taken from Table 68: A/D converter programming . 5. This parameter includes the sample time t S, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock t CC depend on programming and can be taken from next Table 68. 6. DNL, INL, OFS and TUE are tested at V AREF = 5.0 V, VAGND = 0V, VDD = 5.0 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. ‘LSB’ has a value of V AREF/1024. For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see IOV specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all Port5 analog input pins does not exceed 10 mA. For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: when an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static injection), the specified TUE is degraded (± 7LSB). To get the same accuracy, the negative injection current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection. 7. The coupling factor is measured on a channel while an ov erload condition occurs on the adjacent not selected channels with the overload current within the different specifi ed ranges (for both positive and negative injection current). 8. Refer to scheme reported in Figure 38.

transfer the digital value to the result register. Table 68. A/D converter programming

24.7.2 A/D conversion accuracy

The A/D Converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage (VAREF) and converts it into 10-bit digital data. The absolute accuracy of the A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors:

• Offset error (OFS)
• Gain Error (GE)
• Quantization error
• Non-Linearity error (Differential and Integral) These four error quantities are explained below using Figure 37. Offset error Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 37, see OFS). Gain error Gain error is the deviation between the actual and ideal A/D conversion characteristics when the digital output value changes from the 3FE to the maximum 3FF , once offset error is subtracted. Gain error combined with offset error represents the so-called full-scale error Figure 37, OFS + GE). Quantization error Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB. Non-linearity error Non-Linearity error is the deviation between actual and the best-fitting A/D conversion characteristics (see Figure 37):
• Differential Non-Linearity error is the actual step dimension versus the ideal one (1 LSB IDEAL).
• Integral Non-Linearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics. Note that for Integral Non- Linearity error, the effect of offset, gain and quantization errors is not included. Note: Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the real characteristic, and 1/2 LSB after the last step again of the real characteristic.

24.7.3 Total una djusted error

The Total Unadjusted Error specifies the maximum deviation from the ideal characteristic: the number provided in the Data Sheet represents the maximum error with respect to the entire characteristic. It is a combination of the Offset, Gain and Integral Linearity errors. The different errors may compensate each other depending on the relative sign of the Offset and Gain errors. Refer to Figure 37, see TUE.

Figure 37. A/D conversion characteristic

24.7.4 Analog reference pins

filter network should be designed to minimize the DC resistance.

1 LSB (ideal)

Figure 38. A/D converter input pins scheme and in general it decreases by one half for each 10° C decrease in temperature.

close), a charge sharing phenomena is installed. Figure 39. Charge sharing timi ng diagram during sampling phase

• A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which C P2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitance CP and CS are in series, and the time constant is: This relation can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D Converter circuitry has been designed to be robust also in the very worst case: the sampling time T S is always much longer than the internal time constant: The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to the following equation:
• A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the VA RS RF RL RSW RAD+++ + REQ 2--- LSB< VA VA1 VA2 tTS VCS Voltage transient on CS ∆V < 0.5 LSB 1 2 τ 1 < (RSW + RAD) CS << TS τ 2 = RL (CS + CP1 + CP2) τ 1 RSW RAD+()= CP CS⋅ τ 1 RSW RAD+()< CS⋅ << TS VA1 CS CP1 CP2++()⋅ VA CP1 CP2+()⋅=

above, it is simple to derive the following relation between the ideal and real sampled voltage on CS: From this formula, in the worst case (when VA is maximum, that is for instance 5V), assuming to accept a maximum error of half a count (~2.44mV), it is immediately evident a constraints on C F value: In the next section an example of how to design the external network is provided, assuming some reasonable values for the internal parameters and making hypothesis on the characteristics of the analog signal to be sampled.

24.7.4.1 Example of external network sizing

The following hypothesis are formulated in order to proceed in designing the external network on A/D Converter input pins:

• Analog Signal Source Bandwidth (f0): 10 kHz
• Conversion Rate (fC): 25 kHz
• Sampling Time (TS): 1 µs
• Pin Input Capacitance (CP1): 5pF
• Pin Input Routing Capacitance (CP2): 1pF
• Sampling Capacitance (CS): 4pF
• Maximum Input Current Injection (IINJ): 3mA
• Maximum Analog Source Voltage (VAM):12V
• Analog Source Impedance (RS): 100 Ω
• Channel Switch Resistance (RSW): 500 Ω
• Sampling Switch Resistance (RAD): 200 Ω VA VA2 CP1 CP2+C F+ CF 2048 C S⋅>

1. Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is: 2. Using the relation between C F and CS and taking some margin (4000 instead of 2048), it is possible to define CF: 3. As a consequence of step 1 and 2, RC can be chosen: 4. Considering the current injection limitation and supposing that the source can go up to 12V, the total series resistance can be defined as: from which is now simple to define the value of RL: 5. Now the three element of the external circuit R F, CF and RL are defined. Some conditions discussed in the previous paragraphs have been used to size the component, the other must now be verified. The relation which allow to minimize the accuracy error introduced by the switched capacitance equivalent resistance is in this case: So the error due to the voltage partitioning between the real resistive path and C S is less then half a count (considering the worst case when VA = 5V): The other conditions to be verified is the time constants of the transients are really and significantly shorter than the sampling period duration TS: For complete set of parameters characterizing the ST10F273E A/D Converter equivalent circuit, refer to Section 24.7: A/D converter characteristics on page 134. RCCF 2πf0 CF 4000 C S⋅ 16nF== RF 2πf0CF RS RF RL VAM IINJ RL VAM IINJ REQ fCCS VA RS RF RL RSW RAD+++ + REQ 2---LSB< τ 1 RSW RAD+()= CS 2.8ns=⋅ TS = 1µs 10 τ 2⋅ 10 R⋅ L= CS CP1 CP2++() 290ns=⋅ TS = 1µs

24.8 AC characteristics

24.8.1 Test waveforms

Figure 41. Input/output waveforms Figure 42. Float waveform AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’. Timing measurements are made at VIH Min. for a logic ‘1’ and VIL max for a logic ‘0’. For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV . It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).

24.8.2 Definition of internal timing

between two consecutive edges of the CPU clock, called “TCL ”. This influence must be regarded when calculating the timings for the ST10F273E. Figure 43 refers to a PLL factor of 4. Figure 43. Generation mechanisms for the CPU clock

24.8.3 Clock ge neration modes

24.8.4 Prescaler operation

internal oscillator (input clock signal) by a 2:1 prescaler. CPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. using the period of fXTAL for any TCL. then the PLL is switched off. Table 69. On-chip clock generator selections no crystal or resonator can be used).

1. The limits on input frequency are 4 to 12 MHz since the us age of the internal oscillator amplifier is required.

shall be used: it is not possible to force any clock though an external clock source.

111 F XTAL x 4 4 to 8 Default configuration

101 F XTAL x 8 4 to 8

011 F XTAL x 1 1 to 64 Direct drive

1. The maximum depends on the duty cycle of the external clock signal: When 64 MHz is used, 50% duty

be accepted (minimum phase, high or low, again equal to 7.8ns).

001 F XTAL / 2 4 to 12 CPU clock via prescaler (2)

24.8.5 Direct drive

When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by the input clock signal on XTAL1 pin. The frequency of CPU clock (f CPU) directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula: For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated, so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin has to be used only once for timings that require an odd number The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXT AL x DCmax) instead of TCLMin. Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.

24.8.6 Oscillator watchdog (OWD)

An on-chip watchdog oscillator is implemented in the ST10F273E. This feature is used for safety operation with external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator). This watchdog oscillator operates as following. The reset default configuration enables the watchdog oscillator. It can be disabled by setting the OWDDIS (bit 4) of SYSCON register. When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the watchdog counter. On each transition of external clock, the watchdog counter is cleared. If an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply current. TCL min 1f⁄ XTAL lxlDCmin= DC duty cycle= 2TCL 1 f XTAL⁄=

24.8.7 Phase locked loop (PLL)

using the minimum TCL that is possible under the respective circumstances. Section 24.8.9: PLL jitter for more details.

24.8.8 Voltage controlled oscillator

table, a detailed summary of the internal settings and VCO frequency is reported. 64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz. Table 70. Internal PLL divider mechanism

• FXT AL = 4 MHz
• P0(15:13) = ‘110’ (multiplication by 3)
• PLL input frequency = 1 MHz
• VCO frequency = 48 MHz
• PLL output frequency = 12 MHz (VCO frequency divided by 4)
• FCPU = 12 MHz (no effect of Output Prescaler) Example 2
• FXT AL = 8 MHz
• P0(15:13) = ‘100’ (multiplication by 5)
• PLL input frequency = 2 MHz
• VCO frequency = 80 MHz
• PLL output frequency = 40 MHz (VCO frequency divided by 2)
• FCPU = 40 MHz (no effect of Output Prescaler)

24.8.9 PLL jitter

The following terminology is hereafter defined:

• Self referred single period jitter Also called “Period Jitter”, it can be defined as the difference of the T max and Tmin, where Tmax is maximum time period of the PLL output clock and Tmin is the minimum time period of the PLL output clock.
• Self referred long term jitter Also called “N period jitter”, it can be defined as the difference of Tmax and Tmin, where Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the minimum time difference between N+1 clock rising edges. Here N should be kept sufficiently large to have the long term jitter. For N=1, this becomes the single period jitter. Jitter at the PLL output can be due to the following reasons:
• Jitter in the input clock
• Noise in the PLL loop Jitter in the input clock PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency jitter (frequency > PLL bandwidth) is attenuated @20dB/decade. Noise in the PLL loop This contribution again can be caused by the following sources:
• Device noise of the circuit in the PLL
• Noise in supply and substrate.

Figure 44. ST10F273E PLL jitter

24.8.10 PLL lock / unlock

sufficient to get the PLL locked starting from free-running mode). Table 71. PLL characteristics [V DD = 5V ± 10%, VSS = 0V, TA = –40°C to +125°C]

24.8.11 Main oscillator specifications

Figure 45. Crystal oscillator a nd resonator connection diagram

1. Not 100% tested, guaranteed by design characterization.

Table 72. Main oscillator characteristics

1. Not 100% tested, guaranteed by design characterization.

Table 73. Main oscillator negative resistance (module)

12 MHz 370 Ω 420 Ω 360 Ω -----

capacitance between XTAL1 and XTAL2 pins is globally assumed equal to 4pF . Figure 46. 32 kHz crystal oscillator connection diagram between XTAL3 and XTAL4 is not necessary, since already present on the silicon. Table 74. 32 kHz oscillator characteristics

1. At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started,

the current biasing is reduced to lower the power consumption of the system.

1. Not 100% tested, guaranteed by design characterization.

Table 75. Minimum values of negative resistance (module) for 32 kHz oscillator

24.8.13 External clock drive XTAL1

targets a maximum CPU frequency of 64 MHz. from crystal or ceramic resonator.

1. The minimum value for the XTAL1 signal period shall be considered as the theoretical minimum. The real

minimum value depends on the duty cycle of the input clock signal.

1. 4 to 8 MHz is the input frequency range when using an external clock source. 64 MHz can be applied with

bypassed so it does not limit the input frequency.

1. The input clock signal must reach the defined levels V IL2 and VIH2.

Figure 47. External clock drive XTAL1 Table 76. External clock drive XTAL1 timing

24.8.14 Memory cycle variables

The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.

24.8.15 External memory bus timing

In next sections the external memory bus timings are reported. The given values are computed for a maximum CPU clock of 40 MHz. It is evident that when higher CPU clock frequency is used (up to 64 MHz), some numbers in the timing formulas become zero or negative, that in most of the cases is not acceptable or not meaningful at all. In these cases, it is necessary to relax the speed of the bus setting properly t A, tC and tF. Note: All external memory bus timings and SSC timings reported in the following tables are granted by design characterization and not fully tested in production. Description Symbol Values ALE extension t A TCL x [ALECTL] Memory cycle time wait states t C 2TCL x (15 - [MCTC]) Memory tri-state time t F 2TCL x (1 - [MTTC])

24.8.16 Multiplexed bus

Table 77. Multiplexed bus timings

Table 77. Multiplexed bus timings (continued)

Figure 48. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE

Figure 49. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE

Figure 50. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS

Figure 51. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS

24.8.17 Demultiplexed bus

Table 78. Demultiplexed bus timings

1. RW-delay and t A refer to the next following bus cycle
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore

address changes before the end of RD have no impact on read cycles. Table 78. Demultiplexed bus timings (continued)

Figure 52. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE

Figure 53. Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE

Figure 54. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS

Figure 55. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS

24.8.18 CLKOUT and READY

Table 79. CLKOUT and READY timings

1. These timings are given for charac terization purposes only, in order to assure recognition at a specific
2. Demultiplexed bus is the worst case. For multiple xed bus 2TCL are to be added to the maximum values.

Figure 56. CLKOUT and READY

1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled

LOW at this sampling point terminates the currently running bus cycle.

1. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
2. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to

guaranteed, if READY is removed in response to the command (see Note 4).

1. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state

without MTTC wait state this delay is zero.

1. The next external bus cycle may start here.

24.8.19 External bus arbitration

Figure 57. External bus arbitration (releasing the bus)

1. The ST10F273E will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t 64.

Table 80. External bus arbitration timings

1. Partially tested, guaranteed by design characterization

Figure 58. External bus arbitration (regaining the bus)

1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated

deactivated without the ST10F273E requesting the bus.

1. The next ST10F273E driven bus cycle may start here.

24.8.20 High-speed synchronous se rial interface (SSC) timing

Table 81. SSC master mode timings

1. Maximum Baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to ‘3h’, or with 48

CPU clock equal to (or lower than) 32 MHz.

1. Formula for SSC Clock Cycle time: t 300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
2. Partially tested, guaranteed by design characterization

Figure 59. SSC master timing

1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

clock edge is low-to-high transition (SSCPO = 0b).

1. The bit timing is repeated for all bits to be transmitted or received.

Table 82. SSC slave mode timings

6.6 MBd (1)

1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to

baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. timings are suitable for the master).

1. Formula for SSC Clock Cycle time: t 310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).

Figure 60. SSC slave timing

1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

clock edge is low-to-high transition (SSCPO = 0b).

1. The bit timing is repeated for all bits to be transmitted or received.

Figure 61. PQFP144 mechanical data and package dimension

Figure 62. TQFP144 mechanical data and package dimension Note 1: Exact shape of each corner is optional.

Table 83. Document revision history 11-May-2006 1 Initial release.