F25L08PA_1 ESMT | Alldatasheet
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Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 1/32 F l a s h 3V Only 8 Mbit Serial Flash Memory with Dual FEATURES y Single supply voltage 2.7~3.6V y Standard, Dual SPI y Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 100MHz (100MHz / 200MHz equivalent Dual SPI) y Low power consumption - Active current: 35 mA - Standby current: 30 μA y Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Program - Byte programming time: 7 μs (typical) - Page programming time: 1.5 ms (typical) y Erase - Chip erase time 10 sec (typical) - Block erase time 1 sec (typical) - Sector erase time 90 ms (typical) y Page Programming - 256 byte per programmable page y Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte Program operations y Lockable 4K bytes OTP security sector y SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 y End of program or erase detection y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID Speed Package COMMENTS F25L08PA –50PIG 50MHz 8 lead SOIC 150mil Pb-free F25L08PA –100PIG 100MHz 8 lead SOIC 150mil Pb-free F25L08PA –50PAIG 50MHz 8 lead SOIC 200mil Pb-free F25L08PA –100PAIG 100MHz 8 lead SOIC 200mil Pb-free F25L08PA –50DIG 50MHz 8 lead PDIP 300mil Pb-free F25L08PA –100DIG 100MHz 8 lead PDIP 300mil Pb-free GENERAL DESCRIPTION The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 4,096 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program inst ruction. The device also can be programmed to decrease total chip programming time with Auto Address Increment (AAI) programming. The device features sector erase architecture. The memory array is divided into 256 uniform sectors with 4K byte each; 16 uniform blocks with 64K byte each. Sect ors can be erased individually without affecting the data in ot her sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feat ure disables both program and erase operations in any combin ation of the sectors of the memory.
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 2/32 1 8 2 7 3 6 4 5 VDD HOLD SCK SI CE SO WP VSS 1 8 2 7 3 6 4 5 VDD HOLD SCK SI CE SO WP VSS PIN CONFIGURATIONS 8-PIN SOIC 8-PIN PDIP
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 3/32 PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing for serial input and output operations SI Serial Data Input To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. CE Chip Enable To activate the device when CE is low. WP Write Protect The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. HOLD Hold To temporality stop serial communication with SPI flash memory without resetting the device. VDD Power Supply To provide power. VSS Ground FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X-Decoder Flash Y-Decoder I/O Butters and Data Latches Serial Interface Control Logic CE SCK SI WPSO HOLD
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 4/32 SECTOR STRUCTURE Table 1: F25L08PA Sector Address Table Block Address Block Sector Sector Size (Kbytes) Address range A19 A18 A17 A16 255 4KB 0FF 000H – 0FFFFFH : : : 15 240 4KB 0F0000H – 0F0FFFH 1 1 1 1 239 4KB 0EF000H – 0EFFFFH : : : 14 224 4KB 0E0000H – 0E0FFFH 1 1 1 0 223 4KB 0DF000H – 0DFFFFH : : : 13 208 4KB 0D0000H – 0D0FFFH 1 1 0 1 207 4KB 0CF000H – 0CFFFFH : : : 12 192 4KB 0C0000H – 0C0FFFH 1 1 0 0 191 4KB 0BF000H – 0BFFFFH : : : 11 176 4KB 0B0000H – 0B0FFFH 1 0 1 1 175 4KB 0AF000H – 0AFFFFH : : : 10 160 4KB 0A0000H – 0A0FFFH 1 0 1 0 159 4KB 09F000H – 09FFFFH : : : 9 144 4KB 090000H – 090FFFH 1 0 0 1 143 4KB 08F000H – 08FFFFH : : : 8 128 4KB 080000H – 080FFFH 1 0 0 0 127 4KB 07F000H – 07FFFFH : : : 7 112 4KB 070000H – 070FFFH 0 1 1 1 111 4KB 06F000H – 06FFFFH : : : 6 96 4KB 060000H – 060FFFH 0 1 1 0 95 4KB 05F000H – 05FFFFH : : : 5 80 4KB 050000H – 050FFFH 0 1 0 1 79 4KB 04F000H – 04FFFFH : : : 4 64 4KB 040000H – 040FFFH 0 1 0 0 63 4KB 03F000H – 03FFFFH : : : 3 48 4KB 030000H – 030FFFH 0 0 1 1
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 5/32 Table 1: F25L08PA Sector Address Table - Continued Block Address Block Sector Sector Size (Kbytes) Address range A19 A18 A17 A16 47 4KB 02F000H – 02FFFFH : : : 2 32 4KB 020000H – 020FFFH 0 0 1 0 31 4KB 01F000H – 01FFFFH : : : 1 16 4KB 010000H – 010FFFH 0 0 0 1 15 4KB 00F000H – 00FFFFH : : : 0 0 4KB 000000H – 000FFFH 0 0 0 0 STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an inter nal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Tabl e 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit Name Function Default at Power-up Read/Write
0 BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress 0 R
1 WEL 1 = Device is memory Write enabled
0 = Device is not memory Write enabled 0 R
2 BP0 Indicate current level of block write protection (See Table 3) 1 R/W
3 BP1 Indicate current level of block write protection (See Table 3) 1 R/W
4 BP2 Indicate current level of block write protection (See Table 3) 1 R/W
5 RESERVED Reserved for future use 0 N/A
6 AAI
Auto Address Increment Programming status 1 = AAI programming mode 0 = Page Program mode 0 R
7 BPL 1 = BP2,BP1,BP0 are read-only bits
0 = BP2,BP1,BP0 are read/writable 0 R/W Note: 1. Only BP0, BP1, BP2 and BPL are writable. 2. All register bits are volatility 3. All area are protected at power-on (BP2=BP1=BP0=1)
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 6/32 WRITE ENABLE LATCH (WEL) The Write-Enable-Latch bit indicate s the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions:
- Power-up
- Write Disable (WRDI) instruction completion
- Page Program instruction completion
- Auto Address Increment (AAI) Programming is completed and reached its highest unprotected memory address
- Sector Erase instruction completion
- Block Erase instruction completion
- Chip Erase instruction completion
- Write Status Register instructions BUSY The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Auto Address Increment (AAI) The Auto-Address-Increment-Programming-Status bit provides status on whether t he device is in AAI Programming mode or Page Program mode. The default at power up is Page Program mode. Table 3: F25L08PA Block Protection Table Status Register Bit Protected Memory Area Protection Level BP2 BP1 BP0 Block Range Address Range 0 0 0 0 None None Upper 1/16 0 0 1 Block 15 F0000H – FFFFFH Upper 1/8 0 1 0 Block 14~15 E0000H – FFFFFH Upper 1/4 0 1 1 Block 12~15 C0000H – FFFFFH Upper 1/2 1 0 0 Block 8~15 80000H – FFFFFH All Blocks 1 0 1 Block 0~15 00000H – FFFFFH All Blocks 1 1 0 Block 0~15 00000H – FFFFFH All Blocks 1 1 1 Block 0~15 00000H – FFFFFH Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Tabl e 3, to be software protected against any memory Write (Progr am or Erase) operations. The Write Status Register (WRSR) instruction is used to program the BP2, BP1, BP0 bits as long as WP is high or the Block- Protection-Look (BPL) bit is 0. Chip Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Block Protection Lock-Down (BPL) WP pin driven low (V IL), enables the Block-Protection- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (V IH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 8/32 INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25L08PA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Auto Address Increment (AAI) Programming, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. Table 5: Device Operation Instructions Bus Cycle 1~3 1 2 3 4 5 6 N Operation Max. Freq SIN S OUT S IN SOUT SIN SOUT SIN SOUT SIN SOUT S IN S OUT SIN SOUT Read 33 MHz 03H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z X D OUT0 X D OUT1 X cont. Fast Read 0BH Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z X X X D OUT0 X cont. Fast Read Dual Output12,13 3BH A 23-A16 A 15-A8 A 7-A0 X D OUT0~1 cont. Sector Erase4 (4K Byte) 20H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Block Erase4, (64K Byte) D8H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Chip Erase 60H / Page Program (PP) 02H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z D IN0 Hi-Z D IN1 Hi-Z Up to 256 bytes Hi-Z Auto Address Increment word programming5 (AAI) ADH Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z D IN0 Hi-Z D IN1 Hi-Z - - Read Status Register (RDSR) 6 05H Hi-Z X D OUT - - - - - - - - - - Enable Write Status Register (EWSR) 7 50H Hi-Z - - - - - - - - - - - - Write Status Register (WRSR) 7 01H Hi-Z D IN Hi-Z - - -. - - - - - - - Write Enable (WREN) 10 06H Hi-Z - - - - - - - - - - - - Write Disable (WRDI)/ Exit secured OTP mode 04H Hi-Z - - - - - - - - - - - - Enter secured OTP mode Read Electronic Signature (RES) 8 ABH Hi-Z X 13H - - - - - - - - - - RES in secured OTP mode & not lock down ABH Hi-Z X 33H - - -. - - - - - - - RES in secured OTP mode & lock down ABH Hi-Z X 73H - - -. - - - - - - - Jedec Read ID (JEDEC-ID) 9 9FH Hi-Z X 8CH X 20H X 14H - - - - - - 00H Hi-Z X 8CH X 13H - - Read ID (RDID) 11 90H Hi-Z 00H Hi-Z 00H Hi-Z 01H Hi-Z X 13H X 8CH - - Enable SO to output RY/ Status during AAI (EBSY) Disable SO to output RY/ Status during AAI (DBSY) 50MHz 100MHz
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 9/32 Note: 1. Operation: S IN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code 2. X = Dummy Input Cycles (V IL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous 3. One bus cycle is eight clock periods. 4. Sector Earse addresses: use A MS -A12, remaining addresses can be VIL or VIH Block Earse addresses: use A MS -A16, remaining addresses can be VIL or VIH 5. To continue programming to the next sequential address location, enter the 8-bi t command, followed by the data to be programmed. 6. The Read-Status-Register is continuo us with ongoing clock cycles until terminated by a low to high transition on CE . 7. The Enable-Write-Status-Regist er (EWSR) instruction and t he Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR inst ruction must be executed immediately (v ery next bus cycle) after the EWSR instruction to make both instructions effective. 8. The Read-Electronic-Signature is contin uous with on going clock cycles until terminated by a low to high transition on CE . 9. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 14H as memory capacity. 10. The Write-Enable (WREN) instruction a nd the Write-Status-Register (WRSR) instru ction must work in conjunction of each other. The WRSR instruction must be execut ed immediately (very next bus cycle) afte r the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR , user just need to execute one of it. A successful WRSR can reset WREN. 11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 12. Dual commands use bidirectional IO pins. D OUT and cont. are serial data out; others are serial data in. 13. Dual output data: IO0 =( D6,D 4,D 2,D 0), (D6,D 4,D 2,D 0) IO1 =( D7,D 5,D 3,D 1), (D7,D 5,D 3,D 1) DOUT0 DOUT1
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 11/32 Fast Read Dual Output (50 MHz; 100 MHz) The Fast Read Dual Output (3BH) instruction is similar to the standard Fast Read (0BH) instruct ion except the data is output on SI and SO pins. This allows data to be transferred from the device at twice the rate of sta ndard SPI devices. This instruction is for quickly downloading code from Flash to RAM upon power-up or for applications that cache code- segments to RAM for execution. The Fast Read Dual Output instru ction is initiated by executing an 8-bit command, 3BH, followed by address bits [A 23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence. Figure 4: Fast Read Dual Output Sequence
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 12/32 Page Program (PP) The Page Program instruction allows many bytes to be programmed in the memory. The bytes must be in the erased state (FFH) when initiating a Program operation. A Page Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Page Program instruction. The Page Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A 23-A0]. Following the address, at least one byte Data is input (the maximum of input data can be up to 256 bytes). If the 8 least significant address bits [A 7-A0] are not all zero, all transmitted data that goes beyo nd the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [A7-A0] are all zero). If more than 256 bytes Data are s ent to the device, previously latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page. If less than 256 bytes Data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CE must be driven high before t he instruction is executed. The user may poll the Busy bit in the so ftware status register or wait TPP for the completion of the internal self-timed Page Program operation. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the Busy bit. It is recommended to wait for a duration of TBP before reading the status register to check the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 7 for the Page Program sequence. Figure 7: Page Program Sequence
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 13/32 Auto Address Increment (AAI) WORD Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the multiple bytes or entire memo ry array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiati ng an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD pr ogram operation, RDSR, WRDI. Users have three options to det ermine the completion of each AAI WORD program cycle: hardw are detection by reading the SO; software detection by polling the BUSY in the software status register or wait T BP. Refer to End of Write Detection section for d e t a i l s . Prior to any write operation, the Write Enable (WREN) instruction must be executed. The AAI WO RD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23 -A0]. Following the addresses, two bytes of data is input sequentially. The data is input sequentially from MSB (bit 7) to LSB (bit 0). The first byte of data (D0) will be programmed into the initial address [A 23 -A1] with A 0 =0; the second byte of data (D1) will be programmed into the initial address [A23 -A1] with A0 =1. CE must be driven high before the AAI WORD program instruction is executed. The us er must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User must check BUSY status after WRDI to determine if the device is ready for any command. Please refer to Figure 10 and Figure 11. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0). End of Write Detection There are three methods to det ermine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The Hardware End of Write Detection method is described in the section below. Hardware End of Write Detection The Hardware End of Write De tection method eliminates the overhead of polling the BUSY bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the SO pin to indica te Flash Busy status during AAI WORD programming (refer to Figure 8). The 8-bit command, 70H, must be executed prior to ex ecuting an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A “0” Indicates the device is busy; a “1” Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8-bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output Software Status Register data during AAI WORD programming (refer to Figure 9). Figure 8: Enable SO as Hardware RY/BY Figure 9: Disable SO as Hardware RY/ BY during AAI Programming during AAI Programming
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 19/32 OTP Sector Address Size Address Range 4K bytes 000000H ~ 000FFFH Note: The OTP sector is an independent Sector. Read-Electronic-Signature (RES) The RES instruction can be us ed to read the 8-bit Electronic Signature of the device on the SO pin. The RES instruction can provide access to the Electronic Signature of the device (except while an Erase, Program or WRSR cycle is in progress), Any RES instruction executed while an Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress. In OTP mode, user also can execute RES to confirm the status. Figure 21: Read-Electronic-Signature (RES) Instruction Table 6: Electronic Signature Data Command Mode Electronic Signature Data Normal 13H In secured OTP mode & non lock down (OTP_lock =0) 33H RES In secured OTP mode & lock down (OTP_lock =1) 73H
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 20/32 JEDEC Read-ID The JEDEC Read-ID instructi on identifies the device as F25L08PA and the manufacturer as ESMT. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 14H, identifies the device as F25L08PA. The instruction sequence is shown in Figure 22. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH). Figure 22: JEDEC Read-ID Sequence Table 7: JEDEC Read-ID Data Device ID Manufacturer’s ID (Byte 1) Memory Type (Byte 2) Memory Capacity (Byte 3) 8CH 20H 14H
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 21/32 Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L08PA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, followed by address bits [A 23 -A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE . Figure 23: Read-ID Sequence Table 8: Product ID Data Address Byte1 Byte2 8CH 13H 00000H Manufacturer’s ID Device ID ESMT F25L08PA 13H 8CH 00001H Device ID ESMT F25L08PA Manufacturer’s ID
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 22/32 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditi ons greater than those define d in the operational sections of this datas heet is not implied. Exposure to absolute maxi mum stress rating conditions may affect device reliability.) Package Power Dissipation Capability (T ( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. ) AC CONDITIONS OF TEST OPERATING RANGE Parameter Symbol Value Unit VDD (for FCLK <= 50MHz) 2.7 ~ 3.6 Operating Supply Voltage VDD (for FCLK = 100MHz) 3.0 ~3.6 V Ambient Operating Temperature T A -40 ~ 85 ℃ Table 9: DC OPERATING CHARACTERISTICS Limits Symbol Parameter Min Max Unit Test Condition Standard 15 IDDR1 Read Current @33 MHz Dual 18 mA CE =0.1 VDD/0.9 VDD, SO=open Standard 20 IDDR2 Read Current @ 50MHz Dual 23 mA CE =0.1 VDD/0.9 VDD, SO=open Standard 25 IDDR3 Read Current @ 100MHz Dual 28 mA CE =0.1 VDD/0.9 VDD, SO=open IDDW Program and Erase Current 35 mA CE =VDD ISB Standby Current 30 µA CE =VDD, VIN =VDD or VSS ILI Input Leakage Current 1 µA V IN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA V OUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V V DD=VDD Min VIH Input High Voltage 0.7 x VDD V V DD=VDD Max VOL Output Low Voltage 0.2 V I OL=100 µA, VDD=VDD Min VOH Output High Voltage VDD-0.2 V I OH=-100 µA, VDD=VDD Min Table 10: LATCH UP CHARACTERISTIC Symbol Parameter Minimum Unit Test Method ILTH
1 Latch Up 100 + I DD mA JEDEC Standard 78
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. See Figures 28 and 29
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 23/32 Table 11: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Unit TPU-READ
1 V DD Min to Read Operation 10 µs
1 V DD Min to Write Operation 10 µs
Table 12: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open) Parameter Description Test Condition Maximum COUT
1 Output Pin Capacitance V OUT = 0V 12 pF
1 Input Capacitance V IN = 0V 6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 13: AC OPERATING CHARACTERISTICS Normal 33MHz Fast 50 MHz Fast 100 MHz Symbol Parameter Min Max Min Max Min Max Unit FCLK Serial Clock Frequency 33 50 100 MHz TSCKH Serial Clock High Time 13 9 5 ns TSCKL Serial Clock Low Time 13 9 5 ns TCES
1 CE Active Setup Time 5 5 5 ns
1 CE Active Hold Time 5 5 5 ns
1 CE Not Active Setup Time 5 5 5 ns
1 CE Not Active Hold Time 5 5 5 ns
TCPH CE High Time 100 100 100 ns TCHZ CE High to High-Z Output 9 9 9 ns TCLZ SCK Low to Low-Z Output 0 0 0 ns TDS Data In Setup Time 3 3 3 ns TDH Data In Hold Time 3 3 3 ns THLS HOLD Low Setup Time 5 5 5 ns THHS HOLD High Setup Time 5 5 5 ns THLH HOLD Low Hold Time 5 5 5 ns THHH HOLD High Hold Time 5 5 5 ns THZ HOLD Low to High-Z Output 9 9 9 ns TLZ HOLD High to Low-Z Output 9 9 9 ns TOH Output Hold from SCK Change 0 0 0 ns TV Output Valid from SCK 12 8 7 ns Note 1: Relative to SCK.
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 24/32 ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Symbol Typ2 Max3 Unit Sector Erase Time TSE 90 200 ms Block Erase Time TBE 1 2 s Chip Erase Time TCE 10 30 s Byte Programming Time T BP 7 30 us Page Programming Time TPP 1.5 5 ms Chip Programming Time 25 100 s Erase/Program Cycles1 100,000 - Cycles Data Retention 20 - Years Notes: 1. Not 100% Tested, Excludes external system level over head. 2. Typical values measured at 25°C, 3V. 3. Maximum values measured at 85°C, V DD(min).
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 28/32 PACKAGING DIMENSIONS 8-LEAD SOIC ( 150 mil ) b e L DETAIL "X" A SEATING PLANE D L1 "X" C 1 4 E H 0.25 GAUGE PLANE Dimension in mm Dimension in inch Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max Controlling dimension : millimenter
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 29/32 PACKING DIMENSIONS 8-LEAD SOIC 200 mil ( o fficial name – 209 mil ) SEATING PLANE D b e E 1 4 8 5 DETAIL "X" θ L A E1 Dimension in mm Dimension in inch Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max Controlling dimension : millimenter
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 30/32 PACKING DIMENSIONS 8-LEAD P-DIP ( 300 mil ) D E 1 E e B AA 12 A Seati ng Pl ane e bb 1 L Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max A 5.00 0.21 A1 0.38 0.015 E 7.62 BSC. 0.300 BSC. e 2.54 TYP . 0.100 TYP . b 0.46 TYP . 0.018 TYP . b1 1.52 TYP . 0.060 TYP . θO 0O 7 O 15 O 0 O 7 O 15 O Controlling dimension : Inch.
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 31/32
Revision History
1.0 2008.11.19 Original 1.1 2009.05.11 1.Modify headline 2.Delete the rating of Temperature Under Bias 1.2 2009.06.04 Add 8 lead SOIC (150mil) package 1.3 2009.07.20 Modify the description of OTP mode
Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 32/32 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this docum ent are believed to be accurate at the time of publication. ESMT assu mes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of o ur products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for us e in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.