F25L004A_09 ESMT | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 30

Technical content

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 1/30 Flash 3V Only 4 Mbit Serial Flash Memory „ FEATURES y Single supply voltage 2.7~3.6V y Speed - Read max frequency : 33MHz - Fast Read max frequency : 50MHz; 75MHz; 100MHz y Low power consumption - Active current : 40mA - Standby current : 75μA y Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Program - Byte program time 7 μs(typical) y Erase - Chip erase time 4s(typical) - Block erase time 1sec (typical) - Sector erase time 90ms(typical) y Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte-Program operations y SPI Serial Interface - SPI Compatible : Mode 0 and Mode3 y End of program or erase detection y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant

ORDERING INFORMATION

Part No. Speed Package COMMENTS F25L004A -50PG 50MHz 8 lead SOIC 150 mil Pb-free F25L004A -100PG 100MHz 8 lead SOIC 150 mil Pb-free F25L004A -50PAG 50MHz 8 lead SOIC 200 mil Pb-free Part No. Speed Package COMMENTS F25L004A –100PAG 100MHz 8 lead SOIC 200 mil Pb-free F25L004A –50DG 50MHz 8 lead PDIP 300 mil Pb-free F25L004A –100DG 100MHz 8 lead PDIP 300 mil Pb-free GENERAL DESCRIPTION The F25L004A is a 4 Megabit 3V only CMOS Serial Flash memory device. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. The F25L004A features a sector erase architecture. The device memory array is divided into 128 uniform sectors with 4K byte each ; 8 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase ca pabilities provide the flexibility to revise the data in the device. The sector protect/unprotect feat ure disables both program and erase operations in any combin ation of the sectors of the memory.

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 2/30 PIN CONFIGURATIONS 8-PIN SOIC 8-PIN PDIP 1 8 2 7 3 6 4 5 VDD HOLD SCK SI CE SO WP VSS 1 8 2 7 3 6 4 5 VDD HOLD SCK SI CE SO WP VSS

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 3/30 PIN Description Symbol Pin Name Functions SCK Serial Clock To provide the timing for serial input and output operations SI Serial Data Input To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. CE Chip Enable To activate the device when CE is low. WP Write Protect The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. HOLD Hold To temporality stop serial communication with SPI flash memory without resetting the device. VDD Power Supply To provide power. VSS Ground SECTOR STRUCTURE Table1 : F25L004A Sector Address Table Block Address Block Sector Sector Size (Kbytes) Address range A18 A17 A16 127 4KB 07F000H – 07FFFFH : : : 112 4KB 070000H – 070FFFH 1 1 1 111 4KB 06F000H – 06FFFFH : : : 96 4KB 060000H – 060FFFH 1 1 0 95 4KB 05F000H – 05FFFFH : : : 80 4KB 050000H – 050FFFH 1 0 1 79 4KB 04F000H – 04FFFFH : : : 64 4KB 040000H – 040FFFH 1 0 0 63 4KB 03F000H – 03FFFFH : : : 48 4KB 030000H – 030FFFH 0 1 1 47 4KB 02F000H – 02FFFFH : : : 32 4KB 020000H – 020FFFH 0 1 0 31 4KB 01F000H – 01FFFFH : : : 16 4KB 010000H – 010FFFH 0 0 1 15 4KB 00F000H – 00FFFFH : : : 0 4KB 000000H – 000FFFH 0 0 0

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 4/30 Table2 : F25L004A Block Protection Table Status Register Bit Protected Memory Area Protection Level BP2 BP1 BP0 Block Range Address Range 0 0 0 0 None None Upper 1/8 0 0 1 Block 7 70000H – 7FFFFH Upper 1/4 0 1 0 Block 6~7 60000H – 7FFFFH Upper 1/2 0 1 1 Block 4~7 40000H – 7FFFFH All Blocks 1 0 0 Blo ck 0~7 00000H – 7FFFFH All Blocks 1 0 1 Blo ck 0~7 00000H – 7FFFFH All Blocks 1 1 0 Blo ck 0~7 00000H – 7FFFFH All Blocks 1 1 1 Blo ck 0~7 00000H – 7FFFFH Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Progr am or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP2, BP1, BP0 bits as long as WP is high or the Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Block Protection Lock-Down (BPL) WP pin driven low (V IL), enables the Block-Protection -Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (V IH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. FUNTIONAL BLOCK DIAGRAM Address Buffers and Latches X-Decoder Flash Y-Decoder I/O Butters and Data Latches Serial Interface Control Logic CE SCK SI WPSO HOLD

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 6/30 Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an inter nal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. TABLE 4: SOFTWARE STATUS REGISTER Bit Name Function Default at Power-up Read/Write

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress 0 R

1 WEL 1 = Device is memory Write enabled

0 = Device is not memory Write enabled 0 R

2 BP0 Indicate current level of block write protection (See Table 2) 1 R/W

3 BP1 Indicate current level of block write protection (See Table 2) 1 R/W

4 BP2 Indicate current level of block write protection (See Table 2) 1 R/W

5 RESERVED Reserved for future use 0 N/A

6 AAI

Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 0 R

7 BPL 1 = BP2,BP1,BP0 are read-only bits

0 = BP2,BP1,BP0 are read/writable 0 R/W Note1 : Only BP0,BP1,BP2 and BPL are writable Note2 : All register bits are volatility Note3 : All area are protected at power-on (BP2=BP1=BP0=1) Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicate s the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is autom atically reset under the following conditions:

  • Power-up
  • Write-Disable (WRDI) instruction completion
  • Byte-Program instruction completion
  • Auto Address Increment ( AAI) programming reached its highest memory address
  • Sector-Erase instruction completion
  • Block-Erase instruction completion
  • Chip-Erase instruction completion
  • Write-Status-Register instructions

Table 5. All instructions are synchronized off a high to low

  1. Operation: S IN = Serial In, SOUT = Serial Out
  2. X = Dummy Input Cycles (V IL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
  3. One bus cycle is eight clock periods.
  4. Sector addresses: use AMS- A12, remaining addresses can be VIL or VIH
  5. Prior to any Byte-Program, Sector-Erase, Block-Erase,or Ch ip-Erase operation, the Write-Enable (WREN) instruction must be
  6. To continue programming to the next se quential address location, enter the 8-bit command, ADH, followed by the data to be
  7. The Read-Status-Register is continuo us with ongoing clock cycles until terminated by a low to high transition on CE .
  8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
  9. The Read-Electronic-Signature is contin uous with on going clock cycles until terminated by a low to high transition on CE .

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 8/30 10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as memory capacity. 11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. Read (33 MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified a ddress location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address spac e, i.e. for 4Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiat ed by executing an 8-bit command, 03H, followed by address bits [A 23-A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2 : READ SEQUENCE CE SCK SI 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 N+4 DOU T N+3 DOUT N+2 D OUT N+1 D OUT N DOUT MSB MSBMSB HIGH IMPENANCE SO MODE3 MODE1 ADD. ADD. ADD.

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 9/30 Fast-Read (50 MHz ; 100 MHz) The High-Speed-Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE must remain active low for the duration of the High- Speed-Read cycle. See Figure 3 for the High-Speed-Read sequence. Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction output s the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH has been read, t he next output will be from address location 000000H. Figure 3 : HIGH-SPEED-READ SEQUENCE CE SCK SI 0 1 2 3 4 5 6 7 8 1 51 6 2 32 4 3 13 2 3 94 0 4 74 8 55 56 63 64 80 N+4 DOU T N+ 3 DOU T N+2 D OUT N+1 D OUT N DOU T MSB MSBMSB HIGH IMPENANCESO 0B ADD. ADD. A DD. MODE3 MODE0 71 72 X Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 10/30 Byte-Program The Byte-Program instruction pr ograms the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE must be driven high before the instructi on is executed. The user may poll the Busy bit in the software stat us register or wait TBP for the completion of the internal self -timed Byte-Program operation. See Figure 4 for the Byte-Program sequence. Figure 4 : BYTE-PROGRAM SEQUENCE CE SCK SI 012345678 1 5 1 6 2 3 2 4 3 1 3 2 39 LSBMSBMSB HIGH IMPENANCESO 02 A DD. ADD. A DD. MODE3 MODE0 DIN MSB

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 11/30 Auto Address Increment (AAI) WORD Program The AAI program instruction allows multiple bytes of data to be programmed without re-i ssuing the next sequential address locat ion. This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI progra m instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) w hen initiating an AAI program instruction. Wh ile within AAI WORD programming sequence, t he only valid instructions are AAI WORD program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware detection by reading the SO; software detection by polling the BUSY in the software status register or wait T BP. Refer to End-of-Write Detection section for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A 23-A0]. Following the addresses, two byte s of data is input sequentially. The data is input sequentially from MSB (bit 7) to LSB (bit 0) . The first byte of data(DO) will be programmed into the initial address [A23-A1] with A 0 =0; The second byte of data(D1) will be programmed into the initial address [A 23-A1] with A 0 =1. CE must be driven high before the AAI WORD program instruction is executed. The us er must check the BUSY status before entering t he next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, c heck the busy status using the hardware met hod or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User mu st check busy status after WRDI to determi ne if the device is ready for any command. Please refer to Figures 7 and Figures 8. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0). End of Write Detection There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The hardware end of write detection method is described in the section below. Hardware End of Write Detection The hardware end of write detection method eliminates the overhead of polling the BUSY bit in the software status register during an AAI Word PROGRAM OPERATION. The 8bit command, 70H, configures the SO to indicate Flash Busy status during AAI WORD programming (refer to figure5). The 8bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A “0” Indicates the device is busy ; a “1” Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output software register data during AAI WORD programming (refer to figure6). FIGURE 5 : ENABLE SO AS HARDWARE BY/RY FIGURE 6 : DISABLE SO AS HARDWARE BY/RY DURING AAI PROGRAMMING DURING AAI PROGRAMMING

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 13/30 64K-Byte Block-Erase The 64K Byte Block-Erase instruction clears all bits in the selected block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (W REN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block-Eras e instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23-A0]. Address bits [A MS-A16] (AMS = Most Significant address) are used to determine the block address (BA X), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The us er may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Eras e cycle. See Figure 9 for the Block-Erase sequence. FIGURE 9 : 64-KBYTE BLOCK-ERASE SEQUENCE

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 14/30 4K-Byte-Sector-Erase The Sector-Erase instruction clears all bits in the selected sector to FFH. A Sector-Erase instru ction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) inst ruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A 23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SA X), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 10 for the Sector-Erase sequence. CE SCK SI 012345678 15 16 23 24 31 MSBMSB HIGH IMPENANCESO 20 ADD. ADD. ADD. MODE3 MODE0 FIGURE 10 : SECTOR-ERASE SEQUENCE

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 15/30 Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be igno red if any of the memory area is protected. Prior to any Wr ite operation, t he Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE must be driven high bef ore the instruction is executed. The user may poll the Bu sy bit in the software status register or wait T CE for the completion of the internal self-timed Chip-Erase cycle. See Figure 11 for the Chip-Erase sequence. FIGURE 11 : CHIP-ERASE SEQUENCE Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows reading of the status register. T he status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 12 for the RDSR instruction sequence. Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE CE SCK SI 0123456789 Bit7 MSB MSB HIGH IMPENANCE SO MODE3 MODE1 10 11 12 13 14 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out CE SCK SI 01234567 MSB HIGH IMPENANCESO 60 or C7 MODE3 MODE0

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 17/30 Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) in struction and opens the status register for alteration. The Enable-Write-Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Wr ite-Status-Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven hi gh before the EWSR instruction is executed. Write-Status-Register (WRSR) The Write-Status-Register instruct ion writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Fi gure 15 for EWSR or WREN and WRSR instruction sequences. Executing the Write-St atus-Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lockdown the status register, but cannot be reset from “1” to “0”. When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (V IH) prior to the low-to-high transition of the CE pin at the end of the WRSR inst ruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions. Figure 15 : ENABLE-WRITE-STATUS-REGISTER (EWSR) or WRITE-ENABLE(WREN) and WRITE-STATUS-REGISTER (WRSR) CE SCK SI 01234567 MSBMSB HIGH IMPENANCESO 50 or 06 MODE3 MODE0 0123456789 1 0 11 12 13 1415 STATUS REGISTER IN 01 7 6 5 4 3 2 1 0

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 19/30 Table 9 : JEDEC READ-ID DATA Device ID Manufacturer’s ID Memory Type Memory Capacity Byte1 Byte 2 Byte 3 8CH 20H 13H Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L004A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE . Figure 18 : Read-Electronic-Signature Table 10 : JEDEC READ-ID DATA Address Byte1 Byte2 Manufacturer’s ID 00000H 8CH 12H Device ID ESMT F25L004A 00001H 12H 8CH

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 20/30 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Note : 1. Output shorted for no more than one second . No more than one output shorted at a time. AC CONDITIONS OF TEST See Figures 23 and 24 OPERATING RANGE Parameter Symbol Value Unit VDD (for FCLK ≦ 75MHz) 2.7~3.6 Operating Supply Voltage VDD (for FCLK = 100MHz) 3.0~3.6 V Ambient Operating Temperature TA 0~70 °C TABLE 6: DC OPERATING CHARACTERISTICS Limits Symbol Parameter Min Max Units Test Conditions IDDR Read Current 15 mA CE =0.1 VDD/0.9 VDD@33 MHz, SO=open IDDW Program and Erase Current 40 mA CE =VDD ISB Standby Current 75 µA CE =VDD, VIN=VDD or VSS ILI Input Leakage Current 1 µA V IN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA V OUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V V DD=VDD Min VIH Input High Voltage 0.7 V DD V V DD=VDD Max VOL Output Low Voltage 0.2 V I OL=100 µA, VDD=VDD Min VOH Output High Voltage V DD-0.2 V I OH=-100 µA, VDD=VDD Min TABLE 7 : RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ

1 V DD Min to Read Operation 10 µs

1 V DD Min to Write Operation 10 µs

  1. This parameter is measured only for in itial qualification and after a design or process change that could affect this parameter.

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 21/30 TABLE 8: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum COUT

1 Output Pin Capacitance V OUT = 0V 12 pF

1 Input Capacitance V IN = 0V 6 pF

  1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Spec ification Units Test Method NEND

1 Endurance 100,000 Cycles JEDEC Standard A117

1 Data Retention 10 Years JEDEC Standard A103

1 Latch Up 100 + IDD mA JEDEC Standard 78

  1. This parameter is measured only for in itial qualification and after a design or process change that could affect this parameter. TABLE 12 : AC OPERATING CHARACTERISTICS Normal 33MHz Fast 50 MHz Fast 100 MHz Symbol Parameter Min Max Min Max Min Max Units FCLK Serial Clock Frequency 33 50 100 MHz TSCKH Serial Clock High Time 13 9 5 ns TSCKL Serial Clock Low Time 13 9 5 ns TCES

1 CE Active Setup Time 5 5 5 ns

1 CE Active Hold Time 5 5 5 ns

1 CE Not Active Setup Time 5 5 5 ns

1 CE Not Active Hold Time 5 5 5 ns

TCPH CE High Time 100 100 100 ns TCHZ CE High to High-Z Output 9 9 9 ns TCLZ SCK Low to Low-Z Output 0 0 0 ns TDS Data In Setup Time 3 3 3 ns TDH Data In Hold Time 3 3 3 ns THLS HOLD Low Setup Time 5 5 5 ns THHS HOLD High Setup Time 5 5 5 ns THLH HOLD Low Hold Time 5 5 5 ns THHH HOLD High Hold Time 5 5 5 ns THZ HOLD Low to High-Z Output 9 9 9 ns TLZ HOLD High to Low-Z Output 9 9 9 ns TOH Output Hold from SCK Change 0 0 0 ns TV Output Valid from SCK 12 8 7 ns 1. Relative to SCK.

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 22/30 ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Symbol Typ.(2) Max.(3) Unit Sector Erase Time TSE 90 200 ms Block Erase Time TBE 1 2 s Chip Erase Time TCE 4 30 s Byte Programming Time TBP 7 30 us Chip Programming Time 12 100 s Erase/Program Cycles (1) 100,000 - Cycles \`Data Retention 20 - Years Notes: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 3V. 3.Maximum values measured at 85°C, VDD(min).

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 26/30 PACKAGING DIAGRAMS 8-LEAD SOIC ( 150 mil ) b e L DETAIL "X" A SEATING PLANE D L1 "X" C 1 4 E H 0.25 GAUGE PLANE Dimension in mm Dimension in inch Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max Controlling dimension : millimenter

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 27/30 PACKING DIMENSIONS 8-LEAD SOIC 200 mil (official name - 209 mil) SEATING PLANE D b e E 1 4 8 5 DETAIL "X" θ L A E1 Dimension in mm Dimension in inch Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max Controlling dimension : millimenter

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 28/30 PACKAGING DIAGRAMS 8-LEAD SOIC ( 150 mil ) b e L DETAIL "X" A SEATING PLANE D L1 "X" C 1 4 E H 0.25 GAUGE PLANE Dimension in mm Dimension in inch Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max Controlling dimension : millimenter

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 29/30

Revision History

1.0 2006.09.27 Original 1.1 2006.11.28 1. Add AAI function. 2. Delete speed grade 75MHz. 3. Modify ISB spec. 1.2 2007.03.06 Correct Ordering Information from F25L004A-50P to F25L004A-50D 2. Modify ordering information. 1.4 2008.07.17 1. Add “All Pb-free products are RoHS-Compliant” in the description of features 2. Delete bottom block protection table 3. Modify tSE timing 4. Add Revision History 1.5 2008.12.10 1. Add operating range table 2. Delete the rating of Temperature Under Bias 3. Add the symbol for erase and byte programming time 4. Correct typo error 1.6 2009.01.12 1. Correct the size of "L" in the packaging diagram of SOIC 150mil 2.Modify headline

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.6 30/30 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this docum ent are believed to be accurate at the time of publication. ESMT assu mes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of o ur products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT 's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.