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F25D08QA

Elite Semiconductor Mem...

Fast Read for SPI mode

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F25D08QA_1 ESMT | Alldatasheet

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Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 1/69 Flash 8 M b i t S e r i a l F l a s h M e m o r y w i t h D u a l a n d Q u a d FEATURES y Single supply voltage 1.65~2V y Speed - Fast Read for SPI mode - Read max frequency: 33MHz - Fast Read max frequency: 104MHz - Fast Read Dual/Quad max frequency: 84MHz/104MHz (168MHz equivalent Dual SPI; 416MHz equivalent Quad SPI) - Fast Read for QPI mode - Fast Read max frequency: 84MHz - Fast Read Quad max frequency: 104MHz (416MHz equivalent Quad QPI) - 8/ 16/ 32/ 64 byte Wrap-Around Burst Read Mode y Low power consumption - Active current: 15mA (typ.) - Standby current: 30μA (typ.) - Deep Power Down current: 5 μA (typ.) y Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Program - Page programming time: 0.4 ms (typical) y Page Programming - 256 byte per programmable page y Program/Erase Suspend y Erase - Chip Erase time 2 sec (typical) - 64K bytes Block Erase time 130 ms (typical) - 32K bytes Block Erase time 100 ms (typical) - 4K bytes Sector Erase time 30 ms (typical) y Status and Security Register Feature y Command Reset y Advanced Security Features - Flexible Block Protection (BP0-BP3) y Lockable 512 bytes OTP security sector y SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 y Support Serial Flash Discoverable Parameters (SFDP) mode y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID Speed Package Comments F25D08QA –104PIG 104MHz 8-lead SOIC 150 mil Pb-free F25D08QA –104PAIG 104MHz 8-lead SOIC 200 mil Pb-free F25D08QA –104VIG 104MHz 8-lead VSOP 150 mil Pb-free F25D08QA –104HIG 104MHz 8-contact WSON 6x5 mm Pb-free

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 2/69 GENERAL DESCRIPTION The F25D08QA is a 8 Megabit, 1.8V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), a Dual/Quad SPI and QPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 4,096 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device features sector erase architecture. The memory array is divided into 256 uniform sectors with 4K byte each; 32 uniform blocks with 32K byte each; 16 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feat ure disables both program and erase operations in any combin ation of the sectors of the memory. FUNCTIONAL BLOCK DIAGRAM Memory Array Serial Interface CE SCK SI (SIO0) WP (SIO2) SO (SIO1) HOLD (SIO3) Command and Conrol Logic Page Buffer Y-Decoder Byte Address Latch / Counter Status Register High Voltage Generator Page Address Latch / Counter

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 3/69 PIN CONFIGURATIONS 8-Lead SOIC / 8-Lead VSOP (SOIC 8L, 150mil Body, 1.27mm Pin Pitch) (SOIC 8L, 208mil Body, 1.27mm Pin Pitch) (SOIC 8L, 150mil Body with thickness 0.88mm, 1.27mm Pin Pitch) CE SO / SIO1 WP / SIO2 VSS VDD HOLD / SIO3 SCK S I/S I O0 8- Contact WSON (WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch) CE SO / SIO1 VSS WP / SIO2 VDD HOLD / SIO3 SCK S I/S I O0

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 4/69 PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing for serial input and output operations SI / SIO0 Serial Data Input / Serial Data Input Output 0 To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK(for Dual/Quad mode). SO / SIO1 Serial Data Output / Serial Data Input Output 1 To transfer data serially out of the device. Data is shifted out on the falling edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Dual/Quad mode). CE Chip Enable To activate the device when CE is low. WP / SIO2 Write Protect / Serial Data Input Output 2 The Write Protect ( WP ) pin is used to enable/disable BPL bit in the Status Register. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). HOLD / SIO 3 H o l d / Serial Data Input Output 3 To temporality stop serial communication with SPI flash memory without resetting the device. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). VDD Power Supply To provide power. VSS Ground

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 5/69 SECTOR STRUCTURE Table 1: Sector Address Table 64KB Block 32KB Block Sector Sector Size (Kbytes) Address range 255 4KB 0FF000h – 0FFFFFh : : : 248 4KB 0F8000h – 0F8FFFh 247 4KB 0F7000h – 0F7FFFh : : : 240 4KB 0F0000h – 0F0FFFh individual 16 sectors unit: 4KB 239 4KB 0EF000h – 0EFFFFh : : : 29 232 4KB 0E8000h – 0E8FFFh 231 4KB 0E7000h – 0E7FFFh : : : 224 4KB 0E0000h – 0E0FFFh 223 4KB 0DF000h – 0DFFFFh : : : 27 216 4KB 0D8000h – 0D8FFFh 215 4KB 0D7000h – 0D7FFFh : : : 208 4KB 0D0000h – 0D0FFFh individual block unit: 64KB 47 4KB 02F000h – 02FFFFh : : : 5 40 4KB 028000h – 028FFFh 39 4KB 027000h – 027FFFh : : : 32 4KB 020000h – 020FFFh 31 4KB 01F000h – 01FFFFh : : : 3 24 4KB 018000h – 018FFFh 23 4KB 017000h – 017FFFh : : : 16 4KB 010000h – 010FFFh 15 4KB 00F000h – 00FFFFh : : : 8 4KB 008000h – 008FFFh 7 4KB 007000h – 007FFFh : : : 0 4KB 000000h – 000FFFh individual 16 sectors unit: 4KB

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 6/69 STATUS REGISTER The Software Status Register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an inter nal Erase or Program operation, the Status Register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the Software Status Register. Table 2: Software Status Register Bit Name Function Default at Power-up Read/Write Status Register

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress 0 R

1 WEL 1 = Device is memory Write enabled

0 = Device is not memory Write enabled 0 R

2 BP0 Indicate current level of block write protection (See Table 3) 0 R/W

3 BP1 Indicate current level of block write protection (See Table 3) 0 R/W

4 BP2 Indicate current level of block write protection (See Table 3) 0 R/W

5 BP3 Indicate current level of block write protection (See Table 3) 0 R/W

6 QE 1 = Quad enabled

0 = Quad disabled 0 R/W

7 BPL 1 = BP3, BP2,BP1,BP0 are read-only bits

0 = BP3, BP2,BP1,BP0 are read/writable 0 R/W Note: 1. BUSY and WEL are read only. 2. BP0~3, QE and BPL bits are non-volatile. Write Enable Latch (WEL) The Write-Enable-Latch bit indicate s the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions:

Power-up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Status Register instruction completion
Signal Block Lock (SBLK) instruction completion
Signal Block Unlock (SBULK) instruction completion
Gang Block Lock (GBLK) instruction completion
Gang Block Unlock (GBULK) instruction completion
Write Security Register (WRSCUR) instruction completion
Write Protect Selection (WPSEL) instruction completion BUSY The BUSY bit determines whether there is an internal Erase or Program operation in progress. A “1” for the BUSY bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Quad Enable (QE) When the Quad Enable bit is reset to “0” (factory default), WP and HOLD pins are enabled. When QE pin is set to “1”, Quad SIO2 and SIO3 are enabled. (The QE should never be set to “1” during standard and Dual SPI operation if the WP and HOLD pins are tied directly to the V DD or VSS.). When in QPI mode, QE bit is not required for setting.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 7/69 Table 3: Block Protection Table Status Register Bit Protected Memory Area Protection Level BP3 BP2 BP1 BP0 64KB Block Range 0 0 0 0 0 None Upper 1/16 0 0 0 1 Block 15 Upper 1/8 0 0 1 0 Block 14~15 Upper 1/4 0 0 1 1 Block 12~15 Upper 1/2 0 1 0 0 Block 8~15 All Blocks 0 1 0 1 Block 0~15 All Blocks 0 1 1 0 Block 0~15 All Blocks 0 1 1 1 Block 0~15 All Blocks 1 0 0 0 Block 0~15 All Blocks 1 0 0 1 Block 0~15 All Blocks 1 0 1 0 Block 0~15 Bottom 1/2 1 0 1 1 Block 0~7 Bottom 3/4 1 1 0 0 Block 0~11 Bottom 7/8 1 1 0 1 Block 0~13 Bottom 15/16 1 1 1 0 Block 0~14 All Blocks 1 1 1 1 Block 0~15 Block Protection (BP3, BP2, BP1, BP0) The Block-Protection (BP3, BP2, BP1, BP0) bits define the memory area, as defined in Tabl e 3, to be software protected against any memory Write (Progr am or Erase) operations. The Write Status Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP is high or the Block- Protection-Look (BPL) bit is 0. Chip Erase can only be executed if BP3, BP2, BP1 and BP0 bits are all 0. The factory default setting for Block Protection Bit (BP3 ~ BP0) is 0. Block Protection Lock-Down (BPL) WP pin driven low (V IL), enables the Block-Protection- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When the WP pin is driven high (V IH), the BPL bit has no effect and its value is “Don’t Care”. Table 4: 512 bytes Secured OTP Definition Address range Size Standard Factory Lock Customer Lock XXX000 ~ XXX00F 16-byte ESN (electrical serial number) XXX010 ~ XXX1FF 496-byte N/A Determined by customer Additional 512K bytes secured OTP for unique identifier: to provide 512K bytes one-time program area for setting device unique serial number - Which may be set by factory or system customer. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 512K bytes secured OTP by entering 512K bytes secured OTP mode (with Enter Security OTP (ENSO) command), and going through normal program procedure, and then exiting 512K bytes secured OTP mode by writing Exit Security OTP (EXSO) command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR (write security register) command to set customer lock-down bit1 as "1". Please refer to Table 9 of "security regist er definition" for security register bit definition and Table 4 of "512K bytes secured OTP definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512K bytes secured OTP mode, array access is not allowed.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 9/69 Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode By issuing 35H command, the QPI mode is enable. Quad Peripheral Interface (QPI) operation To use QPI protocol, the host drives CE low then sends the Fast Read command, 0BH, followed by 6 address cycles and 4 dummy cycles. Most significant bit (MSB) comes first (Please refer to Figure 8-2). After the dummy cycle, the Quad Peripher al Interface (QPI) Flash Memory outputs data on the falling edge of the SCK signal star ting from the specified address location. The device continually streams data output through all addresses until terminated by a low -to-high transition on CE . The internal address pointer automatically increases until the highest memory address is reached. When reached the highest memory address, the address pointer returns to the beginning of the address space. Reset QPI mode By issuing F5H command, the device is reset to 1-I/O SPI mode. Fast Read Quad I/O mode (4READ) To increase the code transmission speed, the device provides a "Fast Read Quad I/O Mode" (4READ). By issuing command code EBH, the 4READ mode is enabled. The number of dummy cycle increase fr om 4 to 6 cycles. The read cycle frequency will increase from 84MHz to 104MHz. (Please refer to Figure 10-2) CE SCK SIO3~S I O0 MODE3 MODE0 CE SCK SI 01234567 MSB HIGH IMPEDANCESO MODE3 MODE0

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 10/69 INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25D08QA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Writ e Status Register, Sector Erase, Block Erase, or Chip Er ase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 6. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. Table 6-1: Device Operation Instruction (SPI) SPI Bus Cycle 1~3 1 2 3 4 5 6 N Operation Max. Freq SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT Read 33 MHz 03H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X DOUT0 X DOUT1 X cont. Fast Read 0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X X X DOUT0 X cont. Fast Read Dual Output12, 104MHz 3BH A 23-A16 A 15-A8 A 7-A0 X D OUT0~1 cont. Fast Read Dual I/O12, 13 (2READ) 84MHz BBH A23-A8 A7-A0, X DOUT0~1 cont. - - Fast Read Quad Output12, 18 104MHz 6BH A 23-A16 A 15-A8 A 7-A0 X D OUT0~3 cont. Fast Read Quad I/O14 (4 dummy cycles) (W4READ) 84MHz E7H A 23-A0, M7-M0 X, D OUT 0~2 Cont. - - - Fast Read Quad I/O12, 14 (4READ) EBH A 23-A0, M7-M0 X, D OUT0~1 DOUT2~6 cont. - - Sector Erase4 - 4KB (SE) 20H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Block Erase 32KB 5 (BE32K) 52H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Block Erase5 (BE) D8H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Chip Erase (CE) 60H / Program / Erase Suspend B0H Hi-Z - - - - - - - - - - - - Program / Erase Resume 30H Hi-Z - - - - - - - - - - - - Page Program (PP) 02H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z D IN0 Hi-Z D IN1 Hi-Z Up to 256 bytes Hi-Z Dual Input Fast Program A2H A 23-A16 A 15-A8 A 7-A0 D IN0~1 D IN2~3 Up to 256 byte Quad Page Program (single address) 19 32H A 23-A16 A 15-A8 A 7-A0 D IN0~3 D IN4~7 Up to 256 byte Quad Page Program (4PP)15 38h A 23~A0, DIN 0 D IN 1~4 D IN 5~8 D IN 9~12 D IN 13~16 Up to 256 byte Mode Bit Reset16 FFH Hi-Z - - - - - - - - - - - - Read Status Register RDSR) 7 05H Hi-Z X DOUT Write Status Register (WRSR) 10 01H Hi-Z DIN Write Enable (WREN) 10 06H Hi-Z - - - - - - - - - - - - Write Disable (WRDI) 104MHz

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 11/69 Table 6-1: Device Operation Instruction (SPI) - Continued SPI Bus Cycle 1~3 1 2 3 4 5 6 N Operation Max. Freq SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT Read Electronic Signature (RES) 8 ABH Hi-Z X X X X X X X 34H - - - - RES in secured OTP mode & not lock down ABH Hi-Z X X X X X X X 74H - - - - RES in secured OTP mode & lock down ABH Hi-Z X X X X X X X F4H - - - - Read ID (RDID) 9 9FH Hi-Z X 8CH X 25H X 34H - - - - - - 00H Hi-Z X 8CH X 34H - - Read Electronic ID (REMS)11 104MHz 90H Hi-Z 00H Hi-Z 00H Hi-Z 01H Hi-Z X 34H X 8CH - - Read SFDP (RDSFDP) 33MHz 5AH Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z X X X D OUT0 X cont. Deep Power Down (DP) B9H Hi-Z - - - - - - - - - - - - Release from Deep Power Down (RDP) ABH Hi-Z - - - - - - - - - - - - Enter secured OTP mode (ENSO) B1H Hi-Z - - - - -. - - - - - - - Exit OTP (EXSO) C1H Hi-Z - - - - - - - - - - - - Read Security Register (RDSCUR) 2BH Hi-Z X D OUT - - - - - - - - - - Write Security Register (WRSCUR) 2FH Hi-Z - - - - - - - - - - - - Reset Enable (RSTEN) 66H Hi-Z - - - - - - - - - - - - Reset Memory (RST) 6 99H Hi-Z - - - - - - - - - - - - Signal Block Lock (SBLK) 36H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Signal Block Unlock (SBULK) 39H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Block Protect Read (RDBLOCK) 3CH Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - - - - - Gang Block Lock (GBLK) 7EH Hi-Z - - - - - - - - - - - - Gang Block Unlock Write Protect Selection Set Burst Length (SBL) C0H Hi-Z D IN Hi-Z - - - - - - - - - - Enable Quad I/O (EQIO) 35H Hi-Z - - - - - - - - - - - - NOP 104MHz

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 12/69 Table 6-2: Device Operation Instruction (QPI) QPI Bus Cycle 1~3 1 2 3 4 5 6 7 8 N Operation Max. Freq SIO SIO SIO SIO SIO SIO SIO SIO SIO Fast Read 84MHz 0BH A23-A16 A15-A8 A7-A0 M7-M0 X DOUT0 DOUT1 cont. Fast Read Quad I/O12, 14 (4READ) EBH A23-A16 A15-A8 A7-A0 M7-M0 X X DOUT0 cont. Sector Erase4 - 4KB (SE) 20H A23-A16 A15-A8 A7-A0 - - - - - Block Erase 32KB 5 (BE32K) 52H A23-A16 A15-A8 A7-A0 - - - - - Block Erase5 (BE) D8H A23-A16 A15-A8 A7-A0 - - - - - Chip Erase (CE) 60H / Program / Erase Suspend B0H - - - - - - - - Program / Erase Resume 30H - - - - - - - - Page Program (PP) 02H A23-A16 A15-A8 A7-A0 DIN0 DIN1 DIN2 DIN3 Up to 256 bytes Mode Bit Reset16 FFH FFH FFH FFH - - - - - Read Status Register (RDSR) 7 05H DOUT Write Status Register (WRSR) 10 01H DIN Write Enable (WREN) 10 06H - - - - - - - - Write Disable (WRDI) 04H - - - - - - - - Read Electronic Signature (RES) 8 ABH X X X 34H - - - - RES in secured OTP mode & not lock down ABH X X X 74H - - - - RES in secured OTP mode & lock down ABH X X X F4H - - - - Deep Power Down (DP) B9H - - - - - - - - Release from Deep Power Down (RDP) ABH - - - - - - - - Exit OTP (EXSO) C1H - - - - - - - - Enter secured OTP mode Read Security Register (RDSCUR) 2BH DOUT - - - - - - - Write Security Register (WRSCUR) 2FH - - - - - - - - Reset Enable (RSTEN) 66H - - - - - - - - Reset Memory (RST) 6 99H - - - - - - - - Signal Block Lock (SBLK) 36H A23-A16 A15-A8 A7-A0 - - - - - Signal Block Unlock (SBULK) 39H A23-A16 A15-A8 A7-A0 - - - - - Block Protect Read (RDBLOCK) 3CH A23-A16 A15-A8 A7-A0 - - - - - Gang Block Lock (GBLK) 7EH - - - - - - - - Gang Block Unlock (GBULK) 98H - - - - - - - - Write Protect Selection Set Burst Length (SBL) C0H DIN - - - - - - - QPI ID Read (QPIID) 9 AFH 8CH 25H 34H - - - - - Reset Quad I/O (RSTQIQ) F5H - - - - - - - - NOP 104MHz Notes: 1. Operation: S IN = Serial In, SOUT = Serial Out, SIO = Serial In/Out. 2. X = Dummy Input Cycles (V IL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous 3. One SPI bus cycle is eight clock periods; one QPI bus cycle is two clock periods. 4. 4K byte Sector Earse addresses: use A MS -A12, remaining addresses can be VIL or VIH.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 13/69 5. 32K byte Block Earse addresses: use A MS -A15, remaining addresses can be VIL or VIH 64K byte Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH 6. RST command only executed if RSTE N command is executed first. Any intervening command will disable Reset. 7. The Read-Status-Register is continuo us with ongoing clock cycles until terminated by a low to high transition on CE . 8. The Read-Electronic-Signature is contin uous with on going clock cycles until terminated by a low to high transition on CE . 9. The Read ID is output first byte 8CH as manufacture ID; second byte 25H as memory type; third byte 34H as memory capacity. 10. The Write-Enable (WREN) instruction an d the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. A successful WRSR can reset WREN. 11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 12. Dual and Quad commands use bidirectional IO pins. D OUT and cont. are serial data out; others are serial data in. 13. M 7-M0: Mode bits. Dual input address: IO0 =( A22,A 20,A 18,A 16,A 14,A 12,A 10,A 8)( A 6,A 4,A 2,A 0,M 6,M 4,M 2,M 0) IO1 =( A23,A 21,A 19,A 17,A 15,A 13,A 11,A 9)( A 7,A 5,A 3,A 1,M 7,M 5,M 3,M 1) Bus Cycle-2 Bus C ycle-3 14. M 7-M0: Mode bits. Quad input address: IO0 =( A20,A 16,A 12,A 8,A 4,A 0,M 4,M 0) IO1 =( A21,A 17,A 13,A 9,A 5,A 1,M 5,M 1) IO2 =( A22,A 18,A 14,A 10,A 6,A 2,M 6,M 2) IO3 =( A23,A 19,A 15,A 11,A 7,A 3,M 7,M 3) Bus Cycle-2 Fast Read Quad I/O data: Bus Cycle-3 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 Bus Cycle-4 15. The instruction is initiated by executing command co de, and then input data to bidirectional IO pins (SIO0 ~ SIO3). Quad input address and data: IO0 =( A20,A 16,A 12,A 8,A 4,A 0,D 4,D 0) IO1 =( A21,A 17,A 13,A 9,A 5,A 1,D 5,D 1) IO2 =( A22,A 18,A 14,A 10,A 6,A 2,D 6,D 2) IO3 =( A23,A 19,A 15,A 11,A 7,A 3,D 7,D 3) SPI Bus Cycle 16. This instruction is recommended when us ing the Dual or Quad Mode bit feature. 17. Dual output data: IO0 =( D6,D 4,D 2,D 0), (D6,D 4,D 2,D 0) IO1 =( D7,D 5,D 3,D 1), (D7,D 5,D 3,D 1) DOUT0 DOUT1 18. Quad output data: DOUT0 DOUT1 DOUT2 DOUT3

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 14/69 19. The instruction is initiated by executing comm and code, followed by address bits into SI (SIO0) before DIN, and then input data to bidirectional IO pins (SIO0 ~ SIO3). Quad input data: DIN0 DIN1 DIN2 DIN3

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 15/69 (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, WRSR, SBLK, SBULK, GBLK, GBULK, WRSCUR and WPSEL, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CE goes low → sending WREN instruction code → CE goes high. (Please refer to Figure 2-1 and Figure 2-2) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CE goes low → sending WRDI instruction code → CE goes high. (Please refer to Figure 3-1 and Figure 3-2) The WEL bit is reset by following situations: - Power-up - Completion of Write Disable (WRDI) instruction - Completion of Write Status Register (WRSR) instruction - Completion of Page Program (PP) instruction - Completion of Quad Page Program (4PP) instruction - Completion of Quad Page Program (single address) instruction - Completion of Dual Input Fast Program instruction - Completion of Sector Erase (SE) instruction - Completion of Block Erase 32KB (BE32K) instruction - Completion of Block Erase (BE) instruction - Completion of Chip Erase (CE) instruction - Program/Erase Suspend - Signal Block Lock (SBLK) instruction - Signal Block Unlock (SBULK) instruction - Gang Block Lock (GBLK) instruction - Gang Block Unlock (GBULK) instruction - Write Security Register (WRSCUR) instruction - Write Protect Selection (WPSEL) instruction (3) Read Identification (RDID) The RDID instruction is to read t he manufacturer ID of 1-byte and followed by Devi ce ID of 2-byte. The ESMT Manufacturer ID is 8CH, the memory type ID is 25H as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 8) The sequence of issuing RDID instruction is: CE goes low → sending RDID instruction code → 24-bits ID data out on SO → to end RDID operation can drive CE to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CE goes high, the device is at st andby stage. (Please refer Figure 4) (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. T he Read Status Register can be read at any time (even in Program/Erase/Write Status Register condition). It is recommended to check the BU SY bit before sending a new instruction when a Program, Erase, or Write Status Register operation is in progress. The sequence of issuing RDSR instruction is: CE goes low → sending RDSR instruction code → Status Register data out on SO. (Please refer to Figure 5-1 and Figure 5-2)

executed once the Hardware Protected Mode (HPM) is entered. and the Write Enable Latch (WEL) bit is reset. Table 7. Protection Modes Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 3. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). BP3, BP2, BP1, BP0. The protected area, which is defined by BP 3, BP2, BP1, BP0, is at software protected mode (SPM). BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). rejected to write the Status Register and not be executed.

When BPL bit=1, and then WP /SIO2 is low (or WP /SIO2 is low before BPL bit=1), it enters the hardware protected mode (HPM).

WP /SIO2 to against data modification. protected mode via BP3, BP2, BP1, BP0. If the system enter QPI or set QE=1, the feature of HPM will be disabled.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 17/69 (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCK, and data shifts out on the falling edge of SCK at a maximum frequency FRSCLK. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS goes low → sending READ instruction code → 3-byte address on SI → data out on SO → to end READ operation can use CS to high at any time during data out. (Please refer to Figure 7) (7) Read Data Bytes at Higher Speed (FAST_READ) The Fast Read instruction is for quickly reading data out. The address is latched on rising edge of SCK, and data of each bit shifts out on the falling edge of SCK at a maximum frequency F SCLK. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is sh ifted out, so the whole memory can be read out at a single Fast Read instruction. The address counter rolls over to 0 when the highest address has been reached. SPI mode The sequence of issuing Fast Read instruction is: CE goes low → sending Fast Read instruction code → 3-byte address on SI → 1-dummy byte (default) address on SI → data out on SO → to end Fast Read operation can use CE to high at any time during data out. (Please refer to Figure 8-1) QPI mode The sequence of issuing Fast Read instruction is: CE goes low → sending Fast Read instruction code, 2 cycle → 24-bit address on SIO3~SIO0 → 4 dummy cycle → data out interleave on SIO 3~SIO0 → to end QPI Fast Read operation can use CE to high at any time during data out. (Please refer to Figure 8-2) In the performance-enhancing mode, M[ 7:4] must be toggling with M[3: 0] ; likewise M[7:0]=A5h, 5Ah, F0h or 0Fh can make this mod e continue and reduce the next 4READ instruction. Once M[7:4] is no longer toggling with M[3:0] ; likewise M[7:0]=FFh, 00h, AAh or 55h and afterwards CE is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, Fast Read instruct ion is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Fast Read Dual I/O (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCK at a maximum frequency F TSCLK1. The first address byte can be at any location. The address is autom atically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2R EAD instruction. The address counter rolls over to 0 when the highest address has be en reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CE goes low → sending 2READ instruction → 24-bit address interleave on SIO 1 & SIO0 → 4 dummy cycles on SIO 1 & SIO0 → data out interleave on SIO 1 & SIO0 → to end 2READ operation can use CE to high at any time during data out (Please refer to Figure 9). While Program/Erase/Write Status Register cycle is in progress, 2READ instructi on is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 18/69 (9) Fast Read Quad I/O (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of Status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCK at a maximum frequency FTSCLK2. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when t he highest address has been reached. Once writing 4READ instructio n, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. SPI mode The sequence of issuing 4READ instruction is: CE goes low → sending 4READ instruction → 24-bit address interleave on SIO3,~SIO0 → 2+4 dummy cycles → data out interleave on SIO 3, SIO2, SIO1 & SIO 0 → to end 4READ operation can use CE to high at any time during data out. (Please refer to Figure 10-1) W4READ instruction (E7) is also available is SPI mode for 4 I/O read. The sequence is similar to 4READ, but with only 4 dummy cycles. The clock rate runs at 84MHz. QPI mode The sequence of issuing 4READ instruction is: CE goes low → sending 4READ instruction → 24-bit address interleave on SIO 3~SIO0 → 2+4 dummy cycles → data out interleave on SIO 3~SIO0 → to end 4READ operation can use CE to high at any time during data out. (Please refer to Figure 10-2) Another sequence of issuing 4 READ instructi on especially useful in random access is : CE goes low → sending 4READ instruction → 3-bytes address interleave on SIO 3, SIO2, SIO1 & SIO 0 → performance enhance toggling bit M[7:0] → 4 dummy cycles → data out still CE goes high → CE goes low (reduce 4 Read instruction) → 24-bit random access address (Please refer to Figure 22). In the performance-enhancing mode, M[ 7:4] must be toggling with M[3: 0] ; likewise M[7:0]=A5h, 5Ah, F0h or 0Fh can make this mod e continue and reduce the next 4READ instruction. Once M[7:4] is no longer toggling with M[3:0] ; likewise M[7:0]=FFh, 00h, AAh or 55h and afterwards CE is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instructi on is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 19/69 (10) Burst Read The device supports Burst Read in both SPI and QPI mode. To set the Burst length, following command operation is required Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and disable with“1h”. Next 4 clocks is to define wrap around depth. Definition as following table: Data Wrap Around Wrap Depth Data Wrap Around Wrap Depth 1xh No X 00h Yes 8-byte 1xh No X 01h Yes 16-byte 1xh No X 02h Yes 32-byte 1xh No X 03h Yes 64-byte The wrap around unit is defined within the 256-byte page, with random initial address. It’s defined as “wrap-around mode disable” for the default state of the devic e. To exit wrap around, it is required to issue another “C0” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is required to issue another “C0” command in which data=“0xh”. QPI “0Bh” “EBh” and SPI “EBh” “E7h” support wrap around feature after wrap around enable. The device id default without Burst read. SPI Mode CE SCK SIO MODE3 MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 0 0 0000 HH HH LLLL QPI Mode CE SCK SIO3~S I O0 MODE3 MODE0 012 3 H0 L0C0 MSB LSB MSB = Most Significant Bit LSB = Least Significant Bit

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 20/69 (11) Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note Figure 11-1 and F igure 11-2) Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EBh” “0Bh” and SPI “EBh” “E7h” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CE go high, the device will stay in the read mode and treat CE go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” command to exit enhance mode. (12) Mode Bit Reset (FFh) To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh command code, 8 clocks, should be issued in Signal I/O sequence. In QPI mode, FFFFFFFFh command code, 8 clocks, in 4 I/O should be issue (Please refer to Figure 23) (13) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execut e to set the Write Enable Latch (WEL) bit bef ore sending the Sector Erase (SE). Any address of the sector (see table of memory organization) is a valid address for Sector Erase (SE) instruction. The CE must go high exactly at the byte boundary (the latest ei ghth of address byte been latched-in); othe rwise, the instruction will be rejected a nd not executed. Address bits [AMS-A12] (AMS is the most significant address) select the sector address. The sequence of issuing SE instruction is: CE goes low → sending SE instruction code → 3-byte address on SI → CE goes high. (Please refer to Figure 14-1 and Figure 14-2) The self-timed Sector Erase Cycle time (T SE) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Sector Erase cycle is in progress. The BUSY sets 1 during the T SE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 21/69 (14) 32K Byte Block Erase (BE32K) The 32K Byte Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WRE N) instruction must execute to set the Write Enable Latch (WEL) bit before sending th e Block Erase (BE32K). Any address of the bl ock (see table of memory organization) is a valid address for Block Erase (BE32K) instruction. The CE must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CE goes low → sending BE32K instruction code → 3-byte address on SI → CE goes high. (Please refer to Figure 15-1 and Figure 15-2) The self-timed Block Erase Cycle time (TBE1) is initiated as soon as Chip Enable ( CE ) goes high. The BUSY bit still can be check out during the Block Erase cycle is in progress. The BUSY sets 1 during the T BE1 timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE32K) instruction will not be executed on the block. (15) 64K Byte Block Erase (BE) The 64K Byte Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) inst ruction must execute to set the Write Enab le Latch (WEL) bit before sending the Bloc k Erase (BE). Any address of the block (Please refer to table of memory organization) is a valid address for Block Erase (BE) instruction. The CE must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CE goes low → sending BE instruction code → 3-byte address on SI → CE goes high. (Please refer to Figure 16-1 and Figure 16-2) The self-timed Block Erase Cycle time (T BE2) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Block Erase cycle is in progress. The BUSY sets 1 during the T BE2 timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction w ill not be executed on the block. (16) Chip Erase (CE) The Chip Erase (CE) instruction is for eras ing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CE must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CE goes low → sending CE instruction code → CE goes high. (Please refer to Figure 17-1 and Figure 17-2) The self-timed Chip Erase Cycle time (TCE) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Chip Erase cycle is in progress. The BUSY sets 1 during the T CE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0".

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 22/69 (17) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP) . The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A 7-A0) are not all 0, all transmitted data going beyon d the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CE goes low → sending PP instruction code → 3-byte address on SI → at least 1-byte on data on SI → CE goes high. (Please refer to Figure 12-1 and Figure 12-2) The CE must be kept to low during the whole Page Program cycle; The CE must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (T PP) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Page Program cycle is in progress. The BUSY sets 1 during the T PP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (18) Quad Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). T he Quad Page Programming takes four pins: SIO 0, SIO 1, SIO 2, and SIO 3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad Page Program cannot provide more actual favors, because t he required internal page program time is far more than the time data flows in. The refore, we suggest that while executing this comm and (especially during sending data), user ca n slow the clock speed down to 33MHz belo w. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CE goes low → sending 4PP instruction code → 3-byte address on SIO[3:0] → at least 1-byte on data on SIO[3:0] → CE goes high. (19) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Powe r-down mode, the device is not active and all Write/Program/Erase instruction are ign ored. When CE goes high, it's only in deep power-down mode not standby mode. It's different from Standby mode. The sequence of issuing DP instruction is: CE goes low → sending DP instruction code → CE goes high. (Please refer to Figure 18-1 and Figure 18-2) Once the DP instruction is set, all instruction will be igno red except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction and software reset comm and. (those instructions allow t he ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction, the CE must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as CE goes high, a delay of T DP is required before entering the Deep Power-down mode.

not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. program/erase/write cycle in progress. receive, decode, and execute instruction. manufacturer ID and the specific device ID. alternating from one to the other. The instruction is completed by driving CE high. CE goes low → sending QPI ID instruction → Data out on SO → CE goes high. Most significant bit (MSB) first. Table 8. ID Definitions

down, only read related commands are valid. The EXSO instruction is for exiting the additional 512 bytes secured OTP mode. The sequence of issuing EXSO instruction is: CE goes low → sending EXSO instruction to exit Secured OTP mode→ CE goes high. Program/Erase/Write Status Register/Write Security Register condition) and continuously. indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. is in 512 bytes secured OTP mode, main array access is not allowed. Table 9. Security Register Definition

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 25/69 (26) Write Security Register (WRSCUR) The WRSCUR instruction is for setting the values of Security Regi ster Bits. The WREN (Write Enable) instruction is required bef ore issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 512 bytes Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The LDSO bit is an OTP bit. Once the LDSO bit is set, the value of LDSO bit can not be altered any more. The sequence of issuing WRSCUR instruction is: CE goes low → sending WRSCUR instruction → CE goes high. The CE must go high exactly at the boundary; otherwise , the instruction will be rejected and not executed. (27) Write Protection Selection (WPSEL) When the system accepts and execut es WPSEL instruction, the bit 7 in security register will be set. The WREN (Write Enable) instruction is required be fore issuing WPSEL instruction. It will activate SBLK, SBULK, RDBLOCK , GBLK, GBULK etc instructions t o conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods. The sequence of issuing WPSEL instruction is: CE goes low → sending WPSEL instruct ion to enter the individual block protect mode → CE goes high. Every time after the system is powered-on, and the Security Register bit 7 is che cked to be WPSEL=1, all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instru ction. Program or erase functi ons can only be operated after the Unlock instruction is conducted. Once WPSEL is set, it cannot be changed.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 26/69 WPSEL instruction function flow is as follows: WPSEL Flow

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 27/69 (28) Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block (or sector) of memory, using A MS-A16 or (A MS-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protec tion state. This feature allows user to stop protecting the ent ire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CE goes low → send SBLK/SBULK (36h/39h) instruction → send 3 address bytes assign one block (or sector) to be protected on SI pin → CE goes high. The CE must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. SBLK/SBULK instruction function flow is as follows: Block Lock Flow

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 28/69 Block Unlock Flow

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 29/69 (29) Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using AMS-A16 (or AMS-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has been protected, th at user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, an d user can read and write this block. The sequence of issuing RDB LOCK instruction is: CE goes low → send RDBLOCK (3Ch) instruction → send 3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CE goes high. (30) Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only e ffective after WPSEL was executed. The GBLK/GBUL K instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CE goes low → send GBLK/GBULK (7Eh/98h) instruction → CE goes high. The CE must go high exactly at the byte boundary, otherwis e, the instruction will be rejected and not be executed. (31) Program/ Erase Suspend/ Resume The device allow the interruption of Sector-Erase, Block-Eras e or Page-Program operations and conduct other operations. Details as follows. To enter the suspend / resume mode: issuing B0h for suspend; 30h for resume (SPI/QPI all acceptable). Read security register bit2 (PSB) and bit3 (ESB) (please refer to Table 9) to check suspend ready information. Suspend to suspend ready timing: 20us. Resume to another suspend timing: 1ms. ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. When issue a suspend command during erase operation ESB=1, when erase operation resumes, ESB will be reset to "0". (31-1) Erase Suspend Erase suspend allow the interruption of all erase operations. After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, 90h, 05h, 2Bh, B1h, C1h, 3Ch, 30h, 66h, 99h, C0h, 00h, ABh ) After issue erase suspend command, latency time 20us is neede d before issue another command. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note Figure 26-1, Figure 26-2 and Figure 26-3. ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. When issue a suspend command during program operation ESB=1, when erase operation resumes, ESB will be reset to "0". When ESB bit is issued, the Write Enable Latch (WEL) bit will be reset. See Figure 26-1 for Suspend to Read latency.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 30/69 (31-2) Program Suspend Program suspend allows the interruption of all program operations. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, 90h, 05h, 2Bh, B1h, C1h,3Ch, 30h, 66h, 99h, C0h, 00h, ABh ) After issue program suspend command, latency time 20us is needed before issue another command. For "Suspend to Read", "Resume to Read", "Resume to Suspe nd" timing specification please note Figure 26-1, Figure 26-2 and Figure 26-3. PSB bit (Program Suspend Bit) indicates the status of Program suspend operation. When issue a suspend command during program operation PSB=1, when program operation resumes, PSB will be reset to "0". (32) Write-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status Register will be changed back to “0” The operation of Write-Resume is as follows: CE drives low → send write resume command cycle (30h) → drive CE high. By polling Busy Bit in Status Register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of T SE, TBE, TPP for Sector-erase, Block-erase or Page-programming. WREN (command "06" is not required to issue before resume. Resume to another suspend operation requires latency time of 1ms. When Erase Suspend is being resumed, the WEL bit need to be set again if user desire to conduct the program or erase operation. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. To restart the write command, disable the "performance enhance mode" is requir ed. After the "performance enhance mode" is disable, the write-resume command is effective. (33) No Operation (NOP) The No Operation command only cancels a Reset Enable command. NOP has no impact on any other command. (34) Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). To reset the F25D08QA the host drives CE low, sends the Reset-Enable command (66h), and drives CE high. Next, the host drives CE low again, sends the Reset command (99h), and drives CE high. The Reset operation requires the Reset-Enable command follo wed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the Reset-Enable. A successful command execution will reset the device to SPI stand-by read mode, which are their respective default states, see Figure 27. A device reset during an active Program or Erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. Depending on t he prior operation, the reset timing may va ry. Recovery from a Write operation req uires more latency time than recovery from other operations.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 31/69 (35) Fast Read Dual Output The Fast Read Dual Output instruction enable double data output in read mode. The address is latched on rising edge of SCK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCK at a maximum frequency F TSCLK1. The first address byte can be at any location. The address is autom atically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Fast Read Dual Output in struction. The address counter ro lls over to 0 when the highes t address has been reached. Once writing Fast Read Dual Output instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing Fast Read Dual Output instruction is: CE goes low → sending Fast Read Dual Output instruction → 24-bit address interleave on SIO0 → 8 dummy cycles → data out interleave on SIO 1 & SIO0 → to end Fast Read Dual Output operation can use CE to high at any time during data out (Please refer to Figure 28). While Program/Erase/Write Status Register cycle is in progress, Fast Read Dual Output instruction is rejected without any impac t on the Program/Erase/Write Status Register current cycle. (36) Fast Read Quad Output The Fast Read Quad Output instruction enable quad data output in read mode. A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad Out put instruction. The address is latched on rising edge of SCK, and data of every four bits (interleave on 4 I/O pins) shift out on the fa lling edge of SCK at a maximum frequency F TSCLK1. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Fast Read Quad Ou tput instruction. The address counter rolls over to 0 when the highest address has bee n reached. Once writing Fast Read Quad Output instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing Fast Read Quad Output instruction is: CE goes low → sending Fast Read Quad Output instruction → 24-bit address interleave on SIO0 → 8 dummy cycles → data out interleave on SIO 3, SIO2, SIO1 & SIO0 → to end Fast Read Quad Output operation can use CE to high at any time during data out. (Please refer to Figure 29) While Program/Erase/Write Status Register cycle is in progress, Fa st Read Quad Output instructio n is rejected without any impac t on the Program/Erase/Write Status Register current cycle. (37) Quad Page Program (single address) The Quad Page Program (single address) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (W EL) bit and Quad Enable (QE) bit must be se t to "1" before sending the Quad Page Progra m (single address). The Quad Page Program (single address) takes four pins: SIO 0, SIO1, SIO2, and SIO 3 as data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad Page Program (single address) cannot provide more actual favo rs, because the required internal page program time is far mo re than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing Quad Page Pr ogram (single address) instruction is: CE goes low → sending Quad Page Program (single address) instruction code → 24-bit address interleave on SIO 0 → at least 1-byte on data on SIO[3:0] → CE goes high.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 32/69 (38) Daul Input Fast Program The Dual Input Fast Program instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit must be set to "1" before se nding the Dual Input Fast Program. The Dual Input Fast Progra m takes two pins: SIO0, SIO1 as data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Dual Input Fa st Program cannot provide more actual favors, because the requi red internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standar d page program. The sequence of issuing Dual Input Fast Program instruction is: CE goes low → sending Dual Input Fast Program instruction code → 24-bit address interleave on SIO 0 → at least 1-byte on data on SIO[1:0] → CE goes high. (39) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describi ng the functional and feature capabilities of serial flash devices in a standard set of inte rnal parameter tables. These par ameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SPI mode The sequence of issuing RDSFDP instruction is same as FAST_READ: CE goes low → send RDSFDP instruction (5Ah) → send 3-byte address on SI pin → send 1 dummy byte on SI pin → read SFDP code on SO → to end RDSFDP operation can use CE to high at any time during data out. (Please refer to Figure 32) SFDP is a standard of JEDEC. JESD216. v1.0.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 33/69 Table 10: Signature and Parameter Identification Data Values Description Comment Add (Byte) DW Add (Bit) Data1 (h/b) Data (h) 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h SFDP Signature Fixed: 50444653h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h Number of Parameter Headers Start from 00h 06h 23:16 01h 01h Unused Contains 0xFFh and can never be changed 07h 31:24 FFh FFh ID number (JEDEC) 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Parameter Table Minor Revision Number Start from 0x00h 09h 15:08 00h 00h Parameter Table Major Revision Number Start from 0x01h 0Ah 23:16 01h 01h Parameter Table Length (in double word) How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table 0Eh 23:16 00h 00h Unused Contains 0xFFh and can never be changed 0Fh 31:24 FFh FFh ID number ( manufacturer ID) it indicates manufacturer ID 10h 07:00 8Ch 8Ch Parameter Table Minor Revision Number Start from 0x00h 11h 15:08 00h 00h Parameter Table Major Revision Number Start from 0x01h 12h 23:16 01h 01h Parameter Table Length (in double word) How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h Parameter Table Pointer (PTP) First address of Flash Parameter table 16h 23:16 00h 00h Unused Contains 0xFFh and can never be changed 17h 31:24 FFh FFh

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 34/69 Table 11: Parameter Table (0): JEDEC Flash Parameter Table Description Comment Add (Byte) DW Add (Bit) Data1 (h/b) Data (h) Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase 01:00 01b Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b Write Enable Instruction Requested for Writing to Volatile Status Registers 0: Nonvolatile status bit 1: Volatile status bit (BP status register bit) 03 0b Write Enable Opcode Select for Writing to Volatile Status Registers 0: use 50h opcode, 1: use 06h opcode Note: If target flash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b Unused Contains 111b and can never be changed 30h 07:05 111b E5h 4KB Erase Opcode 31h 15:08 20h 20h (1-1-2) Fast Read 2 0=not support, 1=support 16 0b Address Bytes Number used in addressing flash array 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 18:17 00b Double Transfer Rate (DTR) Clocking 0=not support, 1=support 19 0b (1-2-2) Fast Read 0=not support, 1=support 20 1b (1-4-4) Fast Read 0=not support, 1=support 21 1b (1-1-4) Fast Read 0=not support, 1=support 22 1b Unused 32h 23 1b F0h Unused 33h 31:24 FFh FFh Flash Memory Density 37h:34h 31: 00 007FFFFFh (1-4-4) Fast Read Number of Wait states 3 0 0000b: Wait states (Dummy Clocks) not support 04:00 0 0100b (1-4-4) Fast Read Number of Mode Bits 4 000b: Mode Bits not support 38h 07:05 010b 44h (1-4-4) Fast Read Opcode 39h 15:08 EBh EBh (1-1-4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 20:16 0 1000b (1-1-4) Fast Read Number of Mode Bits 000b: Mode Bits not support 3Ah 23:21 010b 48h (1-1-4) Fast Read Opcode 3Bh 31:24 6Bh 6Bh

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 35/69 Table 11: Parameter Table (0): JEDEC Flash Parameter Table - Continued Description Comment Add (Byte) DW Add (Bit) Data1 (h/b) Data (h) (1-1-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 04:00 0 1000b (1-1-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 3Ch 07:05 010b 48h (1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh (1-2-2) Fast Read Number of Wait states 0 0000b: Wait states(Dummy Clocks) not support 20:16 0 0100b (1-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 3Eh 23:21 000b 04h (1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh (2-2-2) Fast Read 0=not support, 1=support 00 0b Unused 03:01 111b (4-4-4) Fast Read 0=not support, 1=support 04 1b Unused 40h 07:05 111b FEh Unused 43h:41h 31:08 0xFFh 0xFFh Unused 45h:44h 15:00 0xFFh 0xFFh (2-2-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 20:16 0 0000b (2-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 46h 23:21 000b 00h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh Unused 49h:48h 15:00 0xFFh 0xFFh (4-4-4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 20:16 0 0100b (4-4-4) Fast Read Number of Mode Bits 000b: Mode Bits not support 4Ah 23:21 010b 44h (4-4-4) Fast Read Opcode 4Bh 31:24 EBh EBh Sector Type 1 Size Sector/block size = 2^N bytes 5 0x00b: this sector type don't exist 4Ch 07:00 0Ch 0Ch Sector Type 1 erase Opcode 4Dh 15:08 20h 20h Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist 4Eh 23:16 0Fh 0Fh Sector Type 2 erase Opcode 4Fh 31:24 52h 52h Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist 50h 07:00 10h 10h Sector Type 3 erase Opcode 51h 15:08 D8h D8h Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist 52h 23:16 00h 00h Sector Type 4 erase Opcode 53h 31:24 FFh FFh

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 36/69 Table 12: Parameter Table (1): Flash Parameter Table Description Comment Add (Byte) DW Add (Bit) Data1 (h/b) Data (h) VCC Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 20h 00h 20h VCC Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 50h 16h 50h 16h HW RESET pin 0=not support, 1=support 00 1b HW HOLD pin 0=not support, 1=support 01 1b Deep Power Down Mode 0=not support, 1=support 02 1b SW Reset 0=not support, 1=support 03 1b SW Reset Opcode Should be issue Reset Enable (66h) before Reset cmd. 11:04 1001 1001b (99h) Program Suspend/Resume 0=not support, 1=support 12 1b Erase Suspend/Resume 0=not support, 1=support 13 1b Unused 14 1b Wrap-Around Read mode 0=not support, 1=support 65h:64h 15 1b F99Dh Wrap-Around Read mode Opcode 66h 23:16 C0h C0h Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B 67h 31:24 64h 64h Individual block lock 0=not support, 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile, 1=Nonvolatile 01 0b Individual block lock Opcode 09:02 0011 0110b (36h) Individual block lock Volatile protect bit default protect status 0=protect, 1=unprotect 10 0b Secured OTP 0=not support, 1=support 11 1b Read Lock 0=not support, 1=support 12 0b Permanent Lock 0=not support, 1=support 13 0b Unused 15:14 11b C8D9h Unused 6Bh:68h 31:16 FFh FFh Notes: 1. h/b is hexadecimal or binary. 2. (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4). 3. Wait States is required dummy clock cycles after the address bits or optional mode bits. 4. Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg, read performance enhance toggling bits) 5. 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h 6. Memory within the SFDP address space that has not yet been defined or used, default to all 0xFFh. 7. The maximum clock rate=33MHz when reading SFDP area.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 37/69 POWER-ON STATE The device is at below states when power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VDD achieves below correct level: - VDD minimum at power-up stage and then after a delay of TVSL - GND at power-down Please note that a pull-up resistor on CE may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadver tent data change during power u p state. When VDD is lower than V WI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, after VDD reaching the VWI level, a TPUW time delay is required before the device is fully accessible for commands like Write Enable (WREN), Page Program (PP), Quad Page Program (4PP), Quad P age Program (single address), Dual Input Fast Program, Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE), Ch ip Erase (CE), WRSCUR and Write Status Register (WRSR). If the V DD does not reach the V DD minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - TPUW after VDD reached VWI level - TVSL after VDD reached VDD minimum level The device can accept read command after VDD reached VDD minimum and a time delay of TVSL, even time of TPUW has not passed. Please refer to the figure of "power-up timing". Note: - To stabilize the VDD level, the VDD rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VDD drops below VWI level, all operations are disabled and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 45/69 Figure 14-2: Sector Erase (SE) Sequence (QPI Mode) CE SCK SI MSB HIGH IMPEDANCESO MODE3 MODE0 012345678 15 16 23 24 31 ADD. MSB ADD. ADD. Figure 15-1: 32K-byte Block Erase (BE32K) Sequence (SPI Mode) Figure 15-2: 32K-byte Block Erase (BE32K) Sequence (QPI Mode) SCK 01234567MODE3 MODE0 SIO3~SIO0 CE

52 A5 A4 A3 A2 A1 A0

SIO3~SIO0 CE

20 A5 A4 A3 A2 A1 A0

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 55/69 CE SCK SI 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 80 N+4 DOU T N+3 DOU T N+2 D OUT N+1 D OUT N DOU T MSB MSBMSB HIGH IMPENANCESO 5A ADD. ADD. A DD. MODE3 MODE0 71 72 X Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 32: Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 56/69 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those define d in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) TABLE 13: AC CONDITIONS OF TEST TABLE 14: OPERATING RANGE Parameter Symbol Value Unit Operating Supply Voltage VDD 1.65~2 V Ambient Operating Temperature T A -40 ~ +85 ℃ TABLE 15: DC OPERATING CHARACTERISTICS Limits Symbol Parameter Min Typ. Max Unit Test Condition IDDR1 Read Current @ 84MHz 10 15 mA CE =0.1 VDD/0.9 VDD, SO=open IDDR2 Read Current @ 104MHz 15 20 mA CE =0.1 VDD/0.9 VDD, SO=open IDDW Program and Write Status Register Current 15 20 mA CE =VDD Sector and Block Erase Current 15 20 mA CE =VDD IDDE Chip Erase Current 15 20 mA CE =VDD ISB1 Standby Current 25 30 50 µA CE =VDD, VIN =VDD or VSS ISB2 Deep Power Down Current 5 15 µA CE =VDD, VIN =VDD or VSS ILI Input Leakage Current ±2 µA V IN=GND to VDD, VDD=VDD Max ILO Output Leakage Current ±2 µA V OUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage -0.5 0.2 x V DD V VIH Input High Voltage 0.8 x V DD V DD +0.4 V VOL Output Low Voltage 0.2 V I OL=100uA VOH Output High Voltage V DD-0.2 V I OH=-100 µA See Figures 38 and 39

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 57/69 TABLE 16: LATCH UP CHARACTERISTIC Symbol Parameter Minimum Unit Test Method ILTH

1 Latch Up 100 + I DD mA JEDEC Standard 78

Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 17: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open) Parameter Description Test Condition Maximum COUT

1 Output Pin Capacitance V OUT = 0V 8 pF

1 Input Capacitance V IN = 0V 6 pF

Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 18: AC OPERATING CHARACTERISTICS Symbol Parameter Min. Typ. Max. Unit FSCLK Serial Clock Frequency for FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR instruction 104 MHz FRSCLK Serial Clock Frequency for READ instruction 33 MHz FTSCLK1 Serial Clock Frequency for 2READ instruction 84 MHz FTSCLK2

5 Serial Clock Frequency for 4READ instruction 84/ 104 MHz

Serial (FSCLK) 4.5 ns TSCKH Serial Clock High Time Normal Read (FRSCLK) 12 ns Serial (FSCLK) 4.5 ns TSCKL Serial Clock Low Time Normal Read (FRSCLK) 12 ns TCLCH2 Clock Rise Time (peak to peak) 0.1 V/ns TCHCL2 Clock Fall Time (peak to peak) 0.1 V/ns TCES

1 CE Active Setup Time 5 ns

1 CE Active Hold Time 5 ns

1 CE Not Active Setup Time 5 ns

1 CE Not Active Hold Time 5 ns

Write / Erase / Program 30 ns TCHZ CE High to High-Z Output 8 ns TCLZ SCK Low to Low-Z Output 0 ns TDS Data In Setup Time 2 ns TDH Data In Hold Time 5 ns THLS HOLD Low Setup Time 5 ns THHS HOLD High Setup Time 5 ns

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 58/69 TABLE 18: AC OPERATING CHARACTERISTICS - Continued Symbol Parameter Min. Typ. Max. Unit THLH HOLD Low Hold Time 5 ns THHH HOLD High Hold Time 5 ns THZ

3 HOLD Low to High-Z Output 8 ns

3 HOLD High to Low-Z Output 8 ns

TOH Output Hold from SCK Change 0 ns Loading: 30pF 8 ns TV Output Valid from SCK Loading: 15pF 6 ns TWHSL

4 Write Protect Setup Time before CE Low 20 ns

4 Write Protect Hold Time after CE High 100 ns

3 CE High to Deep Power Down Mode 10 us

3 CE High to Standby Mode ( for DP) 10 us

3 CE High to Standby Mode (for RES) 10 us

3 CE High to next Instruction after Suspend 20 us

TRCR Recovery time to read 20 us TRCP Recovery time to program 20 us TRCE Recovery time to erase 12 ms Note: 1. Relative to SCK. 2. T SCKH + TSCKL must be less than or equal to 1/ FCLK. 3. Value guaranteed by characterization, not 100% tested in production. 4. Only applicable as a constraint for a Write Status Register instruction when Block- Protection-Look (BPL) bit is set at 1. 5. When dummy cycle = 4, clock rate = 84 MHz; when dummy cycle = 6, clock rate =104 MHz

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 59/69 TABLE 19: ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Symbol Typ2 Max3 Unit Sector Erase Time (4KB) TSE 30 200 ms Block Erase Time (32KB) TBE1 100 200 ms Block Erase Time (64KB) T BE2 130 250 ms Chip Erase Time TCE 2 6 s Write Status Register Time T W 40 ms Page Programming Time TPP 0.4 0.8 ms Erase/Program Cycles1 100,000 - Cycles Data Retention 20 - Years Notes: 1. Not 100% Tested, Excludes external system level over head. 2. Typical values measured at 25°C, 1.8V. 3. Maximum values measured at 85°C, 1.65V.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 62/69 Time VDD VDD (max) VDD (min) VWI TPUW TVSLReset State Read command is allowed Device is fully accessible Program, Erase and Write command is ignored CE must track VDD Figure 37: Power-Up Timing Diagram Table 20: Power-Up Timing and VWI Threshold Parameter Symbol Min. Max. Unit VDD(min) to CE low TVSL 300 us Time Delay before Write instruction TPUW 1 10 ms Write Inhibit Threshold Voltage VWI 1 1.4 V Note: These parameters are characterized only.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 64/69 PACKING DIMENSIONS 8-LEAD SOIC ( 150 mil ) b e L DETAIL "X" A SEATING PLANE D L1 "X" C 1 4 E H 0.25 GAUGE PLANE Dimension in mm Dimension in inch Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max Controlling dimension : millimenter

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 65/69 PACKING DIMENSIONS 8-LEAD SOIC 200 mil ( o fficial name – 208 mil ) SEATING PLANE D b e E 1 4 8 5 DETAIL "X" θ L A E1 Dimension in mm Dimension in inch Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max Controlling dimension : millimenter

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 66/69 PACKING DIMENSIONS 8-LEAD VSOP (150 mil) c1b1 b c Base metal with plating Detail "B"-"B" E1 E D Pin 1 identifier -C- e bY Seating plane A See Detail "A" L B B Detail "A" Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max b1 0.35 - 0.46 0.014 - 0.018 c 0.09 - 0.16 0.004 - 0.006 c1 0.09 - 0.16 0.004 - 0.006 e 1.27 BSC 0.050 BSC (Revision date : Jan 03 2013)

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 67/69 PACKING DIMENSIONS 8-CONTACT WSON ( 6x5 mm ) PIN# 1 PIN# 1 D E e AA1 b L "A" "B" DETAIL : "B" DETAIL : "A" Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max e 1.27 BSC 0.050 BSC Controlling dimension : millimeter

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 68/69

Revision History

0.1 2012.03.26 Original 0.2 2012.06.05 1. Modify speed from 104MHz to 100MHz 2. Correct WRSCUR command 3. Correct D2(Min), D2(Max), E2(Min) and E2(Max) value of WSON packing dimensions 0.3 2012.07.27 1. Return speed to 104MHz 2. Modify product ID and ambient operating temperature 3. Add 8 lead SOIC (150 mil) package 0.4 2012.08.08 Modify data retention 0.5 2012.09.05 Add VVSOP package 0.6 2012.09.27 Modify the specification of TBE1 and TBE2 0.7 2012.10.30 1. Modify VVSOP to VSOP and the thickness 2. Correct the description of Block Protection, Block Protection Lock-Down 0.8 2013.01.09 Modify Product ID of VSOP (150mil) 1.0 2013.03.11 Delete "Preliminary" 1.1 2013.07.30 1. Add typical value of current 2. Modify the specification of ISB2, TSCKH and TSCKL 3. Add SBLK, SBULK, GBLK, GBULK, WRSCUR and WPSEL into the description of WEL, WREN and WRDI 4. Correct the command of 2READ for SPI mode and of Fast Read for QPI mode 5. Correct features 6. Correct the unit of TRCP 7. Add secured OTP definition

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 69/69 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this docum ent are believed to be accurate at the time of publication. ESMT assu mes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of o ur products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for us e in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.

Product Information

F25D08QA specifications and overview.

Summary

Fast Read for SPI mode

Description

Fast Read for SPI mode

Source title F25D08QA_1 Datasheet(PDF) - Elite Semiconductor Memory Technology Inc.

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