F2480 IDT | Alldatasheet
Document overview
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Technical content
Features
/square4 400 to 3000 MHz (Amplifier Range) /square4 50 to 6000 MHz (Attenuator Range) /square4 12dB typical cascaded max gain /square4 36dB continuous gain range /square4 Excellent linearity +41.5dBm OIP3 /square4 Noise Figure 4.3dB /square4 ICC = 106mA /square4 1.2mA Amplifier Standby Current /square4 BiEdirectional attenuator RF ports /square4 Positive amplifier gain slope vs. frequency to counteract system PCB loss. /square4 VMODE pin allows either positive or negative attenuation control response /square4 LinearEinEdB attenuation characteristic /square4 4 RF Port pinout supporting multiple lineup configurations /square4 50Ω input and output impedances /square4 Broadband, Internally Matched /square4 5 x 5 mm, 32Epin TQFN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 5 x 5 x 0.75 mm - TQFN Package – Top View
Table 1. Pin Descriptions 2, 4, 29, 31 GND Ground these pins. These pins are internally connected to the exposed paddle. 3 RFAMP_IN Amplifier input internally matched to 50 xglyphNjN. Must use external DC block. Application Circuit for details.
10 Band_Select
down resistor of approximately 1MxglyphNjN connects between this pin and GND. 12 RSET Connect external resistor to G ND to optimize amplifier bias. Used in conjunction with pin 13. 13 RDSET Connect external resistor to G ND to optimize amplifier bias. Used in c onjunction with pin 12. 20 V CTRL Attenuator control voltage. Apply a voltage in the range as specified in the General Specifica tions Table. See application section for details about V CTRL . This pin has an internal pull down resistor. Application Circuit for details.
22 V MODE
30 RFAMP_OUT Amplifier output internally matched to 50 xglyphNjN. Must use external DC block as close to the pin as possible. vias are also required to achieve the noted RF performance.
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Table 2. Absolute Maximum Ratings
Table 3. Recommended Operating Conditions Figure 3. Attenuator Maximum RF Input Power vs. Frequency
© 2017 Integrated Device Technology, Inc . 6 March 23 , 2017
Electrical Characteristics
Table 4. General Electrical Characteristics a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns that are not bold/italics are guaranteed by design characterization.
Table 5. Stand Alone Amplifier Electrical Characteristics connector losses are deEembedded, unless otherwise noted.
2700 MHz Wide Band Bias 39
2700 MHz High Band Bias 18
a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns that are not bold/italics are guaranteed by design characterization.
Table 6. Stand Alone Voltage Variable Attenuator Electrical Characteristics and RF load impedances = 50 Ω , PCB board traces and connector losses are deEembedded, unless otherwise noted.
50 MHz [a] 29
6000 MHz 37
50 MHz [a] 16
700 MHz 17
2000 MHz 17
2700 MHz 17
6000 MHz 15
50 MHz [a] 14
700 MHz 15
2000 MHz 16
6000 MHz 13
a. Set blocking capacitors C2 and C9 to 0.01µF to achi eve best return loss performance at 50MHz. b. The input 1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power.
Table 7. Package Thermal Characteristics Amplifier E Junction to Case Thermal Resistance. Attenuator E Junction to Case Thermal Resistance. /square4 TEP = +25°C (T EP is defined as the exposed paddle temperature). /square4 Amplifier components configured for operation per Table 8 for each indicated band. /square4 POUT = 0dBm/tone for all amplifier linearity tests. /square4 1MHz tone spacing for all amplifier linearity tests. /square4 PIN = +20dBm/tone applied to ATTEN_RF1 for all attenuator linearity tests. /square4 50MHz tone spacing for all attenuator linearity tests. /square4 VCTRL setting = minimum attenuation setting. /square4 STBY = Logic HIGH (or open). /square4 VMODE = Logic LOW = Negative Slope. /square4 Evaluation kit trace and connector losses are fully deEembedded. the Amplifier Wide Band section.
© 2017 Integrated Device Technology, Inc . 25 March 23 , 2017 Device Usage Table 8. Suggested Components for Optimum Linearity Performance of the Amplifier Note: Mid Band and Wide Band use the same setting and component values. Table 9. Control Pins Usage for the TX VGA
Application Information
The F2480 has been optimized for use in high performance RF applications from 400 to 3000 MHz. STBY The STBY control pin allows for power saving when the device is not in use. Setting the STBY pin as a logic low or b y leaving the pin open will produce a full current operation mode. The STBY pin has an internal 1 M Ω resistor to ground. Applying logic high to this pin will put the part in the power savings mode. Band_Select The Band_Select control pin can be used to boost the current in the device. This is typical done in the High Band and Wide Band frequency applications by grounding the Band_Select pin. Internally there is a 1.5 M Ω pullEup resistor to set this pin high if no connection is made to it. RSET and RDSET RSET (pin 12) and RDSET (pin 13) use external resistors to ground to set the DC current in the device and to optimize the linearity performance of the amplifier stage. The resistor values in Table 8 can be used as a guide for the RF band of inter est. By decreasing the resistor value to ground on the RSET pin will increase the DC current in the amplifier stage. The maximum operating DC current through RSET should never be higher than 1.5mA at T EP = 105 ºC. The resistor to ground on RDSET is used to optimize the linearity performance in conjunction with the resistor on RSET.
© 2017 Integrated Device Technology, Inc . 26 March 23 , 2017 Application Information (Cont.) Amplifier Stability The standalone amplifier is not unconditionally stable. Set RS = 5xglyphNjN and R1 = 500xglyphNjN to makes the circuit unconditionally stable. By increasing ATTEN_RF1 and ATTEN_RF2 Ports The attenuator stage is biEdirectional thus allowing ATTEN_R F1 or ATTEN_RF2 to be used as the RF input. As displayed in the Typical Operating Conditions curves, ATTEN_RF1 shows enhanced line arity. VCC must be applied prior to the application of RF power to en sure reliability. DC blocking capacitors are required on the RF pins and should be set to a value that results in a low reactance over the frequency range of interest. Attenuator Default Start-up The V CTRL pin has an internal pullEdown resistor while V MODE does not have an internal pullEup or pullEdown resistor and thus needs to be set externally. If V MODE is set to a logic LOW and V CTRL = 0V, the part will power up in the insertion loss state. If V MODE is set to a logic HIGH and VCTRL = 0V the part will power up in the maximum attenuation state. It is recommended that the user tie V MODE to either ground or logic HIGH. Ensure the V MODE and V CTRL pin voltages meet the dependencies to V CC as noted in the General Specifications Table during power up or under operation. VCTRL The V CTRL pin is used to control the attenuation of the attenuat or stage. With V MODE set to a logic LOW (HIGH), this places the device in a negative (positive) slope mode where increasing (decreasing) the V CTRL voltage produces an increasing (a decreasing) attenuation from min attenuation (max attenuation) to max attenuation (min attenuation) respectively. See the General Specifications Table for the allowed control voltage range and its dependence on V CC . Apply V CC before applying voltage to the V CTRL pin to prevent damage to the onEchip pullEup ESD diode. If this sequencing is not possible, then set resistor R6 to 1kxglyphNjN to limit the current into the V CTRL pin. VMODE The V MODE pin is used to set the attenuation vs. V CTRL slope. With V MODE set to logic LOW (HIGH) this will set the attenuation slo pe to be negative (positive). A negative (positive) slope is defined as increasing (decreasing) attenuation with increasing (d ecreasing) V CTRL voltage. The EVKit provides an onEboard jumper to manually set the V MODE . Installing a jumper on header J4 from V MODE to GND (V IH ) to set the device for a negative (positive) slope. Resistors R2 and R3 on the evaluation board form a voltage divider to establish a compatible logic HIGH level using the VCC supply as a source. The V MODE does not have an internal pullEup or pullEdown resistor so it must be set externally. Power Supplies A common 5V power supply should be used for all pins requir ing DC power. All supply pins should be bypassed with ex ternal capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at 0V (± 0.3V) while the supply voltage ramps or while it returns to zero.
by a single control line, values will need to be adjusted accordingly so as to not load the control line. Figure 83. Control Pin Components for Signal Integrity
Figure 86. Electrical Schematic Note: RS and R1 are used to produce unconditional stability for the amplifier and are not included in the performance stated in this datasheet. See applications information section above.
Table 10. Bill of Material (BOM)
1 Printed Circuit Board F2480 PCB IDT
RS and R1 must be installed. See the Applications Section for more details.
© 2017 Integrated Device Technology, Inc . 31 March 23 , 2017 Evaluation Kit Operation Below is a basic setup procedure for configuring and testing the F2480 EVKit. Pre-Configure EVKit: The section is a guide to setup the EVKit for testing. Re move the J8 header shunt if the application is for low ban d operation. All other operating bands require the J8 shunt to be installed. Re move any shorting shunt from header J9 which will allow th e part to be in the operating mode when powered up. Verify that there is a shunt between pins 1, 2 of J11 and pins 1, 2 of J10. These pins configure the PCB to use the installed bias resistors to support Mid Band and W ide Band (see Table 8). Alternate resistors can be inst alled on the unpopulated resistor slots on J11 and J10 to support the other op erating bands (see Additional EVKit Information section). I f a negative (positive) attenuator control slope is desired, connect a shunt between pins 1 and 2 (2 and 3) of header J4. Power Supply Setup: Without making any connections to the EVKit, setup one fixed power supply for 5V with a current limit of 160mA and one variable supply set to 0V with a current limit of 10mA. Disable both power supplies. RF Test Setup: Set up the RF test set to the desired frequency and power ranges within the specified operating limits noted in this datasheet. Disable the output power of all the RF sources. Connect EVKit to Test setup: With the RF sources and power supplies disabled connect the fixed 5V power supply to connector J3, the variab le supply to J6 and the RF connections to the desired RF ports. Terminate any unused RF ports (J1, J2, J5, J7) into 50xglyphNjN. Powering Up the EVkit: Enable the 5V supply and observe a DC current of approx. 120mA. Enable the variable supply. Enable the RF sources. Verify that the DC current stays about 120mA to verify that the amplifier is not being over driven by RF input power. If the J4 connection is set for a negative (positive) at tenuation slope then increasing the variable supply with produce increased (decreased) attenuation for the attenuator path (J2 to J7). Powering Down the EVkit: Disable the RF power being applied to the device. Adjust the variable supply down to 0V and disable it. Disable the 5V supply. Disconnect EVKit from the RF test stand. Additional EVKIT Information EVKit modification to support additional Table 8 bias settings: The standard EVKit is setup for only one RSET / RDSET bias setting (pins 12/ 13 on the F2480) noted in Table 8. Additional Table 8 values (R12/R10, R15/R14, R17/ R16) can be installed on the board to allow for different jumper settings. Never have two shunts installed at the same time on header J11 since this may produce excessive bias current and damage the pa rt. As the resistance to ground decreases on pin 12 of the device, the DC current will increase. The DC current of the EVKIT should never exceed 250mA.
Figure 87. Package Outline Drawing (5 x 5 x 0.75 mm 32-pin TQFN), NBG32
Figure 88. Recommended Land Pattern
© 2017 Integrated Device Technology, Inc . 34 March 23 , 2017
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F2480NBGI 5 x 5 x 0.75 mm 32 ETQFN 1 Tray E40 to +105 °C F2480NBGI8 5 x 5 x 0.75 mm 32 ETQFN 1 Tape and Reel E40 to +105 °C F2480EVBI Evaluation B oard Marking Diagram IDT F2480NBGI Z1503L Q32A016Y Line 1 E Company. Line 2 E Product Number. Line 3 E “Z” the initial alpha characters are the ASM Test Step. Line 3 E “1503” is two digits for the year and week that the part was assembled (2015, Week 3). Line 3 E “L” or last alpha characters are the Assembler Code. Line 4 E Near Dot – Lot Code.
Revision History
Revision Date Description of Change Ma rch 23 , 201 7 Initial release . Corporate Headquarters
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