F1978 IDT | Alldatasheet
Document overview
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Technical content
Features
Frequency: 5MHz to 3000MHz Serial and 6-bit parallel interface 31.5dB control range 0.5dB step Glitch-FreeTM technology, low transient overshoot 3.0V to 5.25V supply 1.8V or 3.3V control logic Attenuator step error: 0.1dB at 1GHz Low insertion loss: 1.2dB at 1GHz Ultra-linear IIP3: +64dBm IIP2: +125dBm typical Stable integral non-linearity over temperature Low current consumption: 550µA typical Bi-directional Operating temperature: -40°C to +105°C 4mm 4mm, 20-TQFN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 4mm 4mm 0.75mm, 20-TQFN Package – Top View (Through Package)
Table 1. Pin Descriptions 2 RF1 Device RF input or output (bi-directional). 3 DATA Serial interface data input. 4 CLK Serial interface clock input. 13 VMODE Pull this pin HIGH for Serial Control Mode. Ground this pin for Parallel Control Mode. 14 RF2 Device RF input or output (bi-directional). ground planes. These multiple ground vias are also required to achieve the specified RF performance. [a] There is a 100kΩ pull-up resistor to the internally regulated 2.5V power supply.
The absolute maximum ratings are stress ratings only . Stresses greater than those listed below can cause permanent damage to the device . Table 2. Absolute Maximum Ratings
Table 3. Recommended Operating Conditions Figure 3. Maximum Continuous Operating RF Input Power versus Input Frequency (+25 C)
© 2017 Integrated Device Technology, Inc. 6 Rev O August 28, 2017
Electrical Characteristics
The specifications in Table 4 apply at V DD = +3.3V, TEP = +25°C, fRF = 1000MHz, PIN = 0dBm, Serial Mode, ZS = ZL = 75Ω, Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Table 4. Electrical Characteristics that are not shown in bold italics are guaranteed by design characterization. [b] Current is tested using the Serial Mode with parallel pins floating. If parallel pins are grounded, add 25µA per pin.
(EVKit) trace and connector losses are de-embedded, unless otherwise noted. Table 5. Electrical Characteristics power. This specification is measured in a 50Ω system. [d] Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz. [e] Speeds are measured after SPI programming is completed (data latched with LE = HIGH).
Table 6. Package Thermal Characteristics Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.
Figure 4. Insertion Loss vs. Frequency Figure 5. Insertion Loss vs. Attenuation State Figure 6. RF1 Return Loss vs. Frequency Figure 7. RF1 Return Loss vs. Attenuation Figure 8. RF2 Return Loss vs. Frequency Figure 9. RF2 Return Loss vs. Attenuation
1 GHz, -40 C
1 GHz, +25 C
1 GHz, +105 C
by floating VMODE or pulling it to a logic HIGH, and Parallel Mode is selected by setting VMODE to a logic LOW. in the most significant bit (MSB) (D5 bit) first. described in the following sections. Table 7. 6 Bit SPI DATA Word Sequence Table 8. Truth Table for Serial Control Word Bits
Figure 18. Conventional Serial Register Timing Diagram Table 9. Conventional Serial Mode Timing Table
device attenuation state will be set immediately based on the contents of the shift register as illustrated in Figure 19. Figure 19. Direct Serial Register Timing Diagram clocked into the shift register, therefore as the serial word is moving through the device, the attenuator can swing over a 16dB range. Table 10. Direct Serial Programming Mode Timing Table When the device is first powered up, it will default to the maximum attenuation of 31.5dB independent of the parallel pin [D5:D0] conditions. Table 11. Default Control Word for the Serial Mode
For the F1978, the user has the option of programming in one of two parallel modes: Direct Parallel Mode or Latched Parallel Mode. The Latched Parallel Mode is selected when VMODE is set to a logic LOW and LE (pin 5) is toggled from a logic LOW to a logic HIGH. Set the LE pin to a logic LOW. Toggle LE to a logic HIGH. The device will then transition to the attenuation settings reflected by pins D5 through D0. The Latched Parallel Mode establishes a default attenuation state when the device is first powered up which is the maximum attenuation. Table 12. Truth Table for the Parallel Pins
Figure 20. Latched Parallel Mode Timing Diagram Table 13. Latched Parallel Mode Timing these pins will exhibit a voltage to ground as indicated. Table 14. Voltage and Resistance to Ground for the Logic Pins 13 VMODE 2.5V 100kΩ pull-up resistor to internally regulated 2.5V. 3, 4, 5 DATA, CLK, LE 2.5V 100kΩ pull-up resistor to internally regulated 2.5V. D2, D1, D0 2.5V 100kΩ pull-up resistor to internally regulated 2.5V.
Figure 21. F1978EVBI Evaluation Board – Top View
Figure 22. F1978EVBI Evaluation Board – Back View
Figure 23. Electrical Schematic
Table 15. Evaluation Kit Bill of Material
1 Printed Circuit Board F1975 EVKit Rev 02 IDT
shown in Figure 25. To use the Serial Mode, set U2 switch 7 to the “+” or “O” position. The attenuation setting can be programmed according to Table 8. Figure 25. Serial Logic Connections or “Serial Logic Control Setup” sections above. Enable the proper attenuation setting according to Figure 21 and Table 8 for Serial Mode or Table 12 for the Parallel Mode. Set the logic control pins to a logic LOW.
Figure 26. Package Outline Drawing NCG20 PSC-4445
Figure 27. Recommended Land Pattern for NCG20 PSC-4445
© 2017 Integrated Device Technology, Inc. 25 Rev O August 28, 2017 Marking Diagram IDTF19 78NCGK Z715BEG 1. Line 1 and 2 are the part number. 2. Line 3: “Z” is for die version. 3. Line 3: “yww” = “715” = one digit year and two digit week that the part was assembled. 4. Line 3: “BEG” denotes assembly site.
Ordering Information
Orderable Part Number Description and Package MSL Rating Shipping Packaging Temperature F1978NCGK 4mm x 4mm x 0.75mm TQFN 1 Tray -40°C to +105°C F1978NCGK8 4mm x 4mm x 0.75mm TQFN 1 Reel -40°C to +105°C F1978EVBI Evaluation Board F1978EVSI Evaluation Solution including the Evaluation Board, Controller Board, and cable. The Evaluation Software is available for download on the product page on the IDT website: www.IDT.com/F1978
© 2017 Integrated Device Technology, Inc. 26 Rev O August 28, 2017
Revision History
Revision Revision Date Description of Change O August 28, 2017 Initial release of the datasheet. Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) a nd its affiliated companies (herein referred to as “IDT”) reserve the right to modify t he products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spe cifications and operating parameters of the described p roducts are d etermined in an independent state and a re not guaranteed to perform the same way when installed in customer products. The informati on contained herein is provided without representation or warranty of a ny kind, whether express or implied , including, but not limited to, the suitability of IDT's products for any particular purpose, an implie d warranty of merchantability, or non -infringement of t he intellectual property rights of others. This docume nt is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applicati ons involving extreme environmental conditions or in life support systems or similar devices where the failu re or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other count ries. Other trademarks used herein are the property of IDT or their respective third party owners. For d atasheet type definitions and a glossary of common terms, vi sit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.