F1977

F1977 IDT | Alldatasheet

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72Bit, 75 Ω , Digital Step Attenuator 5 to 3000 MHz F1977, Rev 1, 04/21/2016 1 © 2016 Integrated Device Technology, Inc. G ENERAL DESCRIPTION This document describes the specification for the F1977 Digital Step Attenuator. The F1977 is part of a family of Glitch2Free TM DSAs optimized for the demanding requirements of CATV and Satellite systems. These devices are offered in a compact 5 mm x 5 mm 32 pin QFN package with 75 Ω impedances for ease of integration. COMPETITIVE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The F1977 is a 72bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss, low distortion (+64 dBm IIP3) and pinpoint attenuation accuracy. Most importantly, the F1977 includes IDT’s Glitch2Free TM technology which results in low overshoot & ringing during MSB transitions. /checkbld Lowest insertion loss for best SNR /checkbld Extremely accurate attenuation levels. /checkbld Ultra low distortion. /checkbld Glitch2Free TM technology to protect PA or ADC during transitions between attenuation states.

APPLICATIONS

• CATV Infrastructure
• CATV Set2Top Boxes
• CATV Satellite Modems
• Data Network Equipment
• Fiber Networks

Ordering Information

FEATURES

• Serial & 7 bit Parallel Interface
• 31.75 dB Control Range
• 0.25 dB step
• Glitch2Free TM for low transient overshoot
• Low Insertion Loss: 1.4 dB @ 1 GHz
• Ultra linear IIP3: +64 dBm
• Attenuation Error: 20.1 dB @ 1 GHz
• Stable Attenuator Accuracy over temperature
• Bi2directional RF use
• 3.00 V to 5.25 V supply
• 1.8 V or 3.3 V control logic
• Low Current Consumption: 325 µA typical
• 240 °C to +105 °C operating temperature
• 5 mm x 5 mm Thin QFN 32 pin package FUNCTIONAL B LOCK DIAGRAM Glitch-Free TM Glitch-Free TM F1977NBGI8 Tape & Reel Green

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 2 Rev 1, 04/21/2016 A BSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units VDD to GND V DD 20.3 +5.5 V D[6:0], DATA, CLK, LE, A0, A1, A2, V MODE V CNTL 20.3 Minimum DC Voltage RF1, RF2 V RF 20.3 +0.3 V Maximum Input Power applied to RF1 or RF2 (>100 MHz) P RF +34 dBm Maximum Junction Temperature T Jmax +150 °C Storage Temperature Range T ST 265 +150 °C Lead Temperature (soldering, 10 s) T LEAD +260 °C Electrostatic Discharge – HBM (JEDEC/ESDA JS200122012) V ESDHBM 1000 (Class 1C) V ESD Voltage – CDM (Per JESD222C101F) V ESDCDM 500 (Class C2) V Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD. Please use proper ESD precautions when handling to avoid damage or loss of performance. P ACKAGE THERMAL AND MOISTURE CHARACTERISTICS θJA (Junction – Ambient) 40 °C/W θJC (Junction – Case) [The Case is defined as the exposed paddle] 4 °C/W Moisture Sensitivity Rating (Per J2STD202 MSL1

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 4 Rev 1, 04/21/2016 F1977 SPECIFICATION Specifications apply at V DD = +3.3 V, T CASE = +25°C, F RF = 1 GHz, Pin = 210 dBm unless otherwise noted. Serial Mode. ZRF1 = Z RF2 = 75 Ω . EVkit losses are de2embedded unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Logic Input High V IH CLK, LE, DATA, D[6:0], A0, A1, A2, V MODE Logic Input Low V IL CLK, LE, DATA, D[6:0], A0, A1, A2, V MODE 0.63 V Logic Current I IH, IIL Individual Pins -40 +40 µA Supply Current I DD VDD = 3.3 V 322 365 µA VDD = 5.0 V 375 Attenuation Range ATT RNG 31.75 dB Minimum Gain Step LSB Monotonic for F RF ≤ 3 GHz 0.25 dB Insertion Loss IL FRF = 1 GHz 1.4 1.9 dB FRF = 2 GHz to 3 GHz 2.2 Relative Insertion Phase min vs. A max ) Φ∆ FRF = 1 GHz 18 deg FRF = 2 GHz 36 Step Error (Differential Non2Linearity) DNL Max error between adjacent steps 0.10 dB Absolute Attenuation Error (Integral Non2Linearity) INL Max Error for state 19.75 dB, F RF = 1 GHz -0.4 0.1 +0.5 dB Max Error, over all states F RF = 1 GHz 20.8 +0.5 Input Return Loss S11 5 MHz ≤ FRF ≤ 1.5 GHz 18 dB 1.5 GHz < F RF ≤ 3.0 GHz 15 Output Return Loss S22 5 MHz ≤ FRF ≤ 1.5 GHz 17 dB 1.5 GHz < F RF ≤ 3.0 GHz 15 Specification Notes: Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/ italics are Guaranteed by Design Characterization. Note 3. The input 0.1dB compression point is used a s a linearity figure of merit. The recommended maximum input power is specified as the lesser of the two values from Figure 1 and Figure 2 above. Note 4: Spurious due to on2chip negative voltage ge nerator. Typical generator fundamental frequency is 2.2 MHz. Note 5: Minimum time required between switching of attenuations states = 1 / (Maximum Switching Rate).

Rev 1, 04/21/2016 5 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator F1977 SPECIFICATION Specifications apply at V DD = +3.3 V, T CASE = +25°C, F RF = 1 GHz, Pin = 210 dBm unless otherwise noted. Serial Mode. Z RF1 = Z RF2 = 75 Ω . EVkit losses are de2embedded unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Input IP3 IIP3 PIN = +10 dBm per tone

50 MHz Tone Separation

Attn State = 0.00 dB 64 dBm Attn State = 15.75 dB 64 Attn State = 31.75 dB 64 Input 0.1dB Compression 3 P 0.1dB FRF = 1 GHz Attn = 10 dB Measured in 50 ohms 32 dBm DSA Settling Time τ SET Max to Min Attenuation to settle to within 0.5 dB of final value 0.9 µ s Min to Max Attenuation to settle to within 0.5 dB of final value 1.8 Video Feedthrough RF1, RF2 ports VID FT Measured at RF ports with 2.5 ns risetime, 0 to 3.3 V control pulse 10 mV pp Maximum spurious level on any RF port 4 Spur MAX Spur Freq ~ 2.2 MHz 2119 dBm Serial Clock Speed F CLK SPI 3 wire bus 25 MHz Parallel to Serial Setup A SPI 3 wire bus 100 ns Serial Data Hold Time B SPI 3 wire bus 10 ns LE Delay C SPI 3 wire bus Time from final serial clock rising edge 10 ns Maximum Switching Rate 5 SW RATE 25 kHz Specification Notes: Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/ italics are Guaranteed by Design Characterization. Note 3. The input 0.1dB compression point is used a s a linearity figure of merit. The recommended maximum input power is specified as the lesser of the two values from Figure 1 and Figure 2 above. Note 4: Spurious due to on2chip negative voltage ge nerator. Typical generator fundamental frequency is 2.2 MHz. Note 5: Minimum time required between switching of attenuations states = 1 / (Maximum Switching Rate).

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 6 Rev 1, 04/21/2016 PROGRAMMING OPTIONS F1977 can be programmed using either the parallel or serial interface; selectable via V MODE (pin 3). Serial mode is selected by floating V MODE or pulling VMODE to a logic high and parallel mode is selected by setting VMODE to logic low. SERIAL CONTROL MODE F1977 Serial mode is selected by floating V MODE (pin 3) or pulling it to logic high. The serial interface is a 162bit shift register made up of two words. The first 82bit word is the Attenuation word, which controls the DSA state. The second word is the address word, which uses only 3 of 82bits that must match the hard wired A02A2 programming in order to change the DSA state. If no external connections are made to A0 – A2 then internally they will default to 000 due to internal pull down resistors. If these 3 external preset address bits are not matched with the SPI loaded address bits then the current attenuator state will remain unchanged. This allows up to 8 serial2controlled devices to be used on a single board, which share a common DATA, CLK and LE. When serial programming is used, all the parallel control input pins 26 – 32 can be left open or grounded. If a pin is grounded than an additional 25 µA will be drawn from the voltage supply per pin. Set to either Logic High or Low Set to Logic Low MSB (Last In) LSB (First In) Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 82Bit Address Word 82Bit Attenuation Word Figure 2 - Two 8-bit words are comprised of 16-bit serial in, parallel out shift register Table 1 - Truth Table for the Serial Address Word (MSB) A6 A5 A4 A3 A2 A1 A0 Address Setting X X X X X 0 0 0 000 X X X X X 0 0 1 001 X X X X X 0 1 0 010 X X X X X 0 1 1 011 X X X X X 1 0 0 100 X X X X X 1 0 1 101 X X X X X 1 1 0 110 X X X X X 1 1 1 111

Rev 1, 04/21/2016 7 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator Table 2 - Truth Table for the Serial Control Word D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Attenuation State (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 0 1 0 0.5 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 2 0 0 0 1 0 0 0 0 4 0 0 1 0 0 0 0 0 8 0 1 0 0 0 0 0 0 16 0 1 1 1 1 1 1 1 31.75 SERIAL MODE DEFAULT CONDITION When the device is first powered up it will default to the Maximum Attenuation setting as described below: Note that for the F1977 in all cases logic high (1) = Attenuation Stepped IN, while logic Low (0) = Attenuation Stepped OUT. MSB (Last In) LSB (First In) Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X 0 0 0 0 1 1 1 1 1 1 1 82Bit Address Word 82Bit Attenuation Word Figure 3 -Default register settings set for Max Attenuation and 000 Address Word REGISTER TIMING DIAGRAM : (N OTE THE TIMING SPEC INTERVALS IN B LUE ) With serial control, the F1977 can be programmed via the serial port on the rising edge of Latch Enable (LE) which loads the last 8 DATA line bits [formatted LSB (D0) first] resident in the SHIFT register followed by the Address Word into the ACTIVE register.

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 8 Rev 1, 04/21/2016 Vmode tp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK Spec tps tdht tds tcls Interval tdst tlew LE DATA D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 0.25 dB 0.5 dB 2 dB 2 dB 4 dB 8 dB 16 dB LOW Bit 1 B it 2 Bit 3 Bit 4 DC DC DC DC LSB MSB LSB MSB Time Data Word Latched into the Active Register Figure 4 - Serial Timing Diagram Note 2 When Latch Enable (LE) is high, the shift register is disabled and DATA is NOT continuously clocked into the shift register which minimizes noise. It is recommended that Latch enable be left high when the device is not being programmed. Table 3 - Serial Mode Timing Table Interval Symbol Description Min Spec Max Spec Units tps Parallel to Serial Setup Time 2 From rising edge of Vmode to rising edge of CLK for D5 100 ns tp Clock high pulse width 10 ns tcls LE Setup Time 2 From the rising edge of CLK pulse for D0 to LE rising edge minus half the clock period. 10 ns tlew LE pulse width 30 ns tdst Data Setup Time 2 From the starting edge of Data bit to rising edge of CLK 10 ns tdht Data Hold Time 2 From rising edge of CLK to falling edge of the Data bit. 10 ns PARALLEL CONTROL MODE For the F1977 the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode. Direct Parallel Mode: Direct Parallel Mode is selected when V MODE is a logic low and LE is a logic high. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins 26 – 32]. Use direct parallel mode for the fastest settling time.

Rev 1, 04/21/2016 Latched Parallel Mode: Latched Parallel Mode is selected when V Latched Parallel Mode:

• Set VMODE is logic low.
• Set LE to logic low.
• Adjust pins [26, 27, 28, 29, 30, 31, 32] to the desired attenuation setting. low, the attenuation state will not change.
• Pull LE to a logic high. The device will then transition to the attenuation settings reflected by pins D6 2 D0. Latched Parallel Default Startup Condition: Latched Parallel Mode implies a default state for when the device is first powered up with V low and LE logic low . In this case the default setting is MAXIMUM Attenuation. Table 4 - Truth Table for the Parallel Control Word D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 Figure 5 - 9 7- Bit, 75 Latched Parallel Mode is selected when V MODE is logic low and LE is toggled from logic low to h Adjust pins [26, 27, 28, 29, 30, 31, 32] to the desired attenuation setting. (W low, the attenuation state will not change. ) The device will then transition to the attenuation settings reflected by pins Latched Parallel Default Startup Condition: Latched Parallel Mode implies a default state for when the device is first powered up with V . In this case the default setting is MAXIMUM Attenuation. Truth Table for the Parallel Control Word D3 D2 D1 D0 Attenuation (dB) 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 31.75 - Latched Parallel Mode Timing Diagram F1977 75 ΩΩ ΩΩ , Digital Step Attenuator logic low to h igh. To utilize While LE is set to a logic The device will then transition to the attenuation settings reflected by pins Latched Parallel Mode implies a default state for when the device is first powered up with V MODE set for logic Attenuation (dB) 0.25 0.5 31.75

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 10 Rev 1, 04/21/2016 Table 5 - Latched Parallel Mode Timing Interval Symbol Description Min Spec Max Spec Units tsps Serial to Parallel Mode Setup Time 100 ns tpdh Parallel Data Hold Time 10 ns tle LE minimum pulse width 10 ns tpds Parallel Data Setup Time 10 ns TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.

• V DD = +3.30 V
• TCASE = +25 °C
• PIN = 0 dBm for single tone measurements
• PIN = +15 dBm/tone for multi-tone measurements
• 50 MHz Tone Space
• Serial Control
• RF1 Port is the input port
• Attenuation Setting = 0 dB
• Measured in a 75 ohm system
• EVKit losses (traces and connectors) are fully de-embedded

Rev 1, 04/21/2016 11 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator TYPICAL OPERATING CONDITIONS (- 1 -) Insertion Loss vs Frequency RF1 Return Loss vs Frequency [All States] RF2 Return Loss vs Frequency [All States] Insertion Loss vs Attenuation State RF1 Return Loss vs Attenuation State RF2 Return Loss vs Attenuation State -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Insertion Loss (dB) Frequency (GHz) -40 C +25 C +105 C -40 -35 -30 -25 -20 -15 -10 Match (dB) Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 Match (dB) Frequency (GHz) -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Insertion Loss (dB) Attenuation (dB)

1 GHz, -40 C

1 GHz, +25 C

1 GHz, +105 C

-40 -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match(dB) Attenuation (dB) 0.01 GHz 0.25 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 2.25 GHz 2.50 GHz 2.75 GHz -40 -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match (dB) Attenuation (dB) 0.01 GHz 0.25 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 2.25 GHz 2.50 GHz 2.75 GHz

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 12 Rev 1, 04/21/2016 TYPICAL OPERATING CONDITIONS (- 2 -) Relative Insertion Phase vs Frequency Worst Case Absolute Accuracy vs Frequency Worst Case Step Accuracy vs Frequency Relative Insertion Phase vs Attenuation Absolute Accuracy vs Attenuation Step Accuracy vs Attenuation Phase (degrees) Frequency (GHz) -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Phase (degrees) Attenuation (dB) 0.01 GHz 0.25 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 2.25 GHz 2.50 GHz 2.75 GHz -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 0.01 GHz 0.25 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 2.25 GHz 2.50 GHz 2.75 GHz -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 0.01 GHz 0.25 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 2.25 GHz 2.50 GHz 2.75 GHz

Rev 1, 04/21/2016 13 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator TYPICAL OPERATING CONDITIONS (- 3 -) Input Compression at 50 MHz Input Compression 1.0 GHz Input Compression 2.0 GHz Input Compression 500 MHz Input Compression 1.5 GHz Input IP3 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) 0.00 dB 1.00 dB 2.00 dB 4.00 dB Measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) 0.00 dB 1.00 dB 2.00 dB 4.00 dB Measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) 0.00 dB 1.00 dB 2.00 dB 4.00 dB Measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) 0.00 dB 1.00 dB 2.00 dB 4.00 dB Measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) 0.00 dB 1.00 dB 2.00 dB 4.00 dB Measured in a 50 ohm system Input IP3 (dBm) Frequency (GHz)

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 14 Rev 1, 04/21/2016 PACKAGE DRAWING (5 mm x 5 mm 322pin TQFN), Use Exposed PAD (EPAD) Option P1

Rev 1, 04/21/2016 15 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator LAND PATTERN DIMENSION PIN DIAGRAM Exposed pad (GND) DNC VDD VMODE GND GND RF1 GND CLK LE NC GND RF2 GND GND GND GND GND GND GND GND GND DATA 32 9 TOP View (looking through the top of the package)

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 16 Rev 1, 04/21/2016 PIN DESCRIPTION Pin Name Function 1 DNC This pin must be left open. 2 V DD Main Supply. Use 3.3 V or 5 V. Bypass capacitor as close to pin as possible.

3 V MODE

1 Logic low for parallel mode. Logic high or NC for serial mode. 4 A0 2 Address bit A0 connection.

5 GND Connect directly to paddle ground or as close as possible to pin with

thru via. This pin is not internally connected.

6 GND Connect directly to paddle ground or as close as possible to pin with

thru via. 7 RF1 3 Device RF input or output (bi2directional). 8 – 17 GND Connect each pin directly to paddle ground or as close as possible to pin with thru vias. 18 RF2 3 Device RF input or output (bi2directional).

19 GND Connect directly to paddle ground or as close as possible to pin with

thru via. 20 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended).

21 A2 2 Address bit A2 connection

22 A1 2 Address bit A1 connection. 23 LE 1 Serial interface latch enable input. 24 CLK 1 Serial interface clock input. 25 DATA 1 Serial interface data input. 26 D6 1 Parallel control bit, 16 dB. 27 D5 1 Parallel control bit, 8 dB. 28 D4 1 Parallel control bit, 4 dB. 29 D3 1 Parallel control bit, 2 dB. 30 D2 1 Parallel control bit, 1 dB. 31 D1 1 Parallel control bit, 0.5 dB. 32 D0 1 Parallel control bit, 0.25 dB. EP Exposed Paddle Connect to Ground with multiple vias for good thermal and RF performance. Pin Description Notes: Note 1: Includes an internal 100 kΩ pullup resisto r to an internal regulated 2.5V supply. If pin is grounded then there is an additional 25 µA per pin for the supply current. Note 2: Includes an internal 100 kΩ pull2down resi stor to GND. Note 3: RF pins 7 and 18 do not require DC blockin g capacitors for operation if they are at 0 V DC. If they are not at 0V DC, then they require DC blocking capacitors.

Rev 1, 04/21/2016 17 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator EVKIT PICTURE

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 18 Rev 1, 04/21/2016 EV KIT / A PPLICATIONS CIRCUIT

Rev 1, 04/21/2016 19 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator EVK IT BOM Item # Part Reference QTY DESCRIPTION Mfr. Part # Mfr.

1 C1, C11, C15 3 100 nF ±10%, 16 V, X7R Ceramic Capacitor

(0402) GRM155R71C104K MURATA

2 C2, C10 2 10 nF ±5%, 50 V, X7R Ceramic Capacitor (0603) GRM188R71H103J MURATA

3 C3 2 C9, C12, C13,

C14, C31 2 C34 14 100 pF ±5%, 50 V, C0G Ceramic Capacitor (0402) GRM1555C1H101J MURATA

4 R3 2 R9,

R31 2 R34 11 100 Ω ±1%, 1/10W, Resistor (0402) ERJ22RKF1000X PANASONIC R10 2R13, R152R18, R242R30, R35, R36 17 0 Ω Resistors (0402) ERJ22GE0R00X PANASONIC

6 R21, R22, R23 3 3 kΩ ±1%, 1/10W, Resistor (0402) ERJ 22RKF3001X PANASONIC

7 R1 1 8.2 kΩ ±1%, 1/10W, Resistor (0402) ERJ 22RKF8201X PANASONIC

8 R2 1 10 kΩ ±1%, 1/10W, Resistor (0402) ERJ 22RKF1002X PANASONIC

9 J2, J3, J5 3 CONN HEADER VERT SGL 2 X 1 POS GOLD 961102 26404 2AR 3M

10 J14, J15 1 CONN HEADER VERT DBL 4 X 2 POS GOLD 67997 2108HLF FCI

11 J4 1 CONN HEADER VERT SGL 12 X 1 POS GOLD 961112 26404 2AR 3M

12 J1, J8 2 Edge Launch SMA

(0.250 inch pitch ground, round) 142207112821 Emerson Johnson

13 J6, J7 2 Edge Launch F TYPE 75 ohm SMA 222181 Amphenol

14 U2 1 SWITCH 10 POSITION DIP SWITCH KAT1110E E2Switch

15 U1 1 DSA F1977NCGI IDT

16 1 Printed Circuit Board F1977 Evkit Rev 01 IDT TOP MARKINGS IDT F1977NBGI Z1535G Part Number Date Code [YYWW] (Week 35 of 2015) ASM Test Step Assembler Code Q61A003MY Lot Code

7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 20 Rev 1, 04/21/2016 A PPLICATIONS INFORMATION Power Supplies A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1 V / 20 µS. In addition, all control pins should remain at 0 V (+/20.3 V) while the supply voltage ramps or while it returns to zero. Digital Pin Voltage & Resistance Values The following table provides open2circuit DC voltage referenced to ground and resistance values for each of the control pins listed. Pin Name Open Circuit DC Voltage Internal Connection 3 V MODE 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V 4, 21, 22 A0, A2, A1 0 V 100 kΩ resistor to GND 23, 24, 25 LE, CLK, DATA 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V 26232 D[6:0] 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V

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San Jose, CA 95138 USA Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or sp ecifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provi ded without representation or warranty of any kind, whether express or implied, including, but not lim ited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non2infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved. Rev 1, 04/21/2016 21 7-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator REVISION H ISTORY SHEET Rev Date Page Description of Change O 20162Feb219 Initial Release 1 20162Apr221 2 Typo on V HBM rating. Voltage changed from 1.5kV to 1kV. No chng. to Class