F1975

F1975 IDT | Alldatasheet

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6vBit, 75 Ω , Digital Step Attenuator 5 to 3000 MHz F1975, Rev O 01/15/2016 1 © 2016 Integrated Device Technology, Inc. General Description This document describes the specification for the IDT F1975 Digital Step Attenuator. The F1975 is part of a family of GlitchvFree TM DSAs optimized for the demanding requirements of CATV and Satellite systems. This device is offered in a compact 4 mm x 4 mm 20 pin Thin QFN package with 75 Ω impedance for ease of integration. COMPETITIVE A DVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The F1975 is a 6vbit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (+64 dBm IIP3). The device has pinpoint attenuation accuracy. Most importantly, the F1975 includes IDT’s GlitchvFree TM technology which results in low overshoot & ringing during MSB transitions. /checkbld GlitchvFree TM Technology protects PA or ADC from damage during transitions between attenuation states. /checkbld Extremely accurate attenuation levels /checkbld Ultra low distortion /checkbld Lowest insertion loss for best SNR A PPLICATIONS

• CATV Infrastructure
• CATV SetvTop Boxes
• CATV Satellite Modems
• Data Network Equipment
• Fiber Networks

ORDERING INFORMATION

FEATURES

• Serial & 6vBit Parallel Interface
• 31.5 dB Control Range
• 0.5 dB step
• GlitchvFree TM , low transient overshoot
• 3.0 V to 5.25 V supply
• 1.8 V or 3.3 V control logic
• Attenuator Step Error: 0.1 dB @ 1 GHz
• Low Insertion Loss: 1.2 dB @ 1 GHz
• Ultra linear IIP3: +64 dBm
• IIP2: +125 dBm typical
• Stable Integral NonvLinearity over temperature
• Low Current Consumption: 550 µA typical
• BivDirectional
• v40 °C to +105 °C Operating Temperature
• 4 mm x 4 mm Thin QFN 20 pin package FUNCTIONAL B LOCK DIAGRAM F1975NCGI8 Green Tape & Reel

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 2 Rev O 01/15/2016 A BSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units VDD to GND V DD v0.3 +5.5 V DATA, LE, CLK, D[5:0] V Logic v0.3 Min (V DD +0.3, 3.6) V RF1, RF2 VRF v0.3 +0.3 V Maximum Input Power applied to RF1 or RF2 (>100 MHz) P RF +34 dBm Maximum Junction Temperature T Jmax +140 °C Storage Temperature Range T st v65 150 °C Lead Temperature (soldering, 10 s) 260 °C Electrostatic Discharge – HBM (JEDEC/ESDA JSv001v2012) V ESDHBM 2000 (Class 2) Volts ESD Voltage – CDM (Per JESD22vC101F) V ESDCDM 250 (Class C1) Volts Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD. Please use proper ESD precautions when handling to avoid damage or loss of performance. PACKAGE THERMAL AND MOISTURE CHARACTERISTICS θJA (Junction – Ambient) 50 °C/W θJC (Junction – Case) [The Case is defined as the exposed paddle] 3 °C/W Moisture Sensitivity Rating (Per JvSTDv020) MSL1

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 4 Rev O 01/15/2016 F1975 SPECIFICATION Specifications apply at V DD = +3.3 V, T CASE = +25 °C, F RF = 1000 MHz, P in = 0 dBm, Serial Mode, ZRF1 = Z RF2 = 75 Ω, unless otherwise noted. EvKit losses are devembedded. Parameter Symbol Conditions Min Typ Max Units Logic Input High V IH All Control Pins VDD > 3.6 V 1.17 3.6 V 3.0 ≤ VDD ≤ 3.6 V 1.17 V DD V Logic Input Low V IL All Control Pins 0.63 V Logic Current I IH, IIL All Control Pins -35 +35 µA Supply Current I DD VDD = 3.3 V 550 830 1 µA VDD = 5.0 V 620 900 RF1 Return Loss S 11 18 dB RF2 Return Loss S 22 18 dB Attenuation Step LSB Least Significant Bit 0.5 dB Insertion Loss (Minimum Attenuation) A MIN D[5:0]=[000000] (IL State) 1.2 2.0 dB Attenuation Range A RANGE D[5:0]=[111111]=31.5 dB 30.5 2 31.1 31.7 dB Step Error DNL 0.1 dB Absolute Error INL D[5:0]=[100111]= 19.5 dB -0.7 +0.5 dB Insertion Phase Delta Φ ∆ At 0.5 GHz (AMAX to AMIN ) 10 degrees At 1.0 GHz (AMAX to AMIN ) 20 Input IP3 IIP3 PIN = +10 dBm/tone, F1 = 900 MHz, F2 = 950 MHz dBm Attn = 0.0 dB, RF IN = RF1 60 64 Attn =15.5 dB, RF IN = RF1 59 62 Input IP2 IIP2 PIN = +12 dBm/tone, F1= 945 MHz, F2 = 949 MHz F1+F2 = 1894 MHz RF IN = RF1 125 dBm Second Harmonic H2 PIN = +15 dBm, RF IN = 945 MHz RF OUT = 1890 MHz RF IN Port = RF1 108 dBc 0.1dB Compression 3 P 0.1 D[5:0] = [000000] = A MIN , RF IN = RF1 30.5 dBm Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/ italics are Guaranteed by Design Characterization. Note 3: The input 0.1dB compression point is a line arity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. Measured in a 50 ohm system. Note 4: Spurious due to onvchip negative voltage ge nerator. Typical generator fundamental frequency is 2.2 MHz. Note 5: Speeds are measured after SPI programming i s completed (data latched with LE = HIGH).

Rev O 01/15/2016 5 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator F1975 SPECIFICATION (CONTINUED ) Specifications apply at V DD = +3.3 V, T CASE = +25 °C, F RF = 1000 MHz, P in = 0 dBm, Serial Mode, ZRF1 = Z RF2 = 75 Ω, unless otherwise noted. EvKit losses are devembedded. Parameter Symbol Conditions Min Typ Max Units MSB Step Time T LSB Start at LE rising edge End ±0.10 dB Pout settling for 15.5 dB to 16.0 dB transition 500 ns Maximum spurious level on any RF port

4 Spur MAX v130 dBm

Maximum Switching Rate SW RATE 25 kHz DSA Settling time 5 τSET Max to Min Attenuation to settle to within 0.5 dB of final value 0.9 µs Min to Max Attenuation to settle to within 0.5 dB of final value 1.8 Control Interface SPI BIT 6 bit Serial Clock Speed SPI CLK 10 25 MHz Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/ italics are Guaranteed by Design Characterization. Note 3: The input 0.1dB compression point is a line arity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. Note 4: Spurious due to onvchip negative voltage ge nerator. Typical generator fundamental frequency is 2.2 MHz. Note 5: Speeds are measured after SPI programming i s completed (data latched with LE = HIGH).

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 6 Rev O 01/15/2016 PROGRAMMING OPTIONS F1975 can be programmed using either the parallel or serial interface which is selectable via V MODE (pin 13). Serial Mode is selected by floating VMODE or pulling it to a logic high and parallel mode is selected by setting VMODE to a logic low. SERIAL CONTROL MODE F1975 Serial Mode is selected by floating VMODE (pin 13) or pulling it to a logic high. The serial interface is a 6v bit shift register and shifts in the MSB (D5) first. When serial programming is used, all the parallel control input pins (1, 15, 16, 17, 19, 20) must be grounded. Table 1 - 6 Bit SPI Word Sequence D5 Attenuation 16 dB Control Bit D4 Attenuator 8 dB Control Bit D3 Attenuator 4 dB Control Bit D2 Attenuator 2 dB Control Bit D1 Attenuator 1 dB Control Bit D0 Attenuator 0.5 dB Control Bit Table 2 - Truth Table for Serial Control Word (MSB) D4 D3 D2 D1 D0 (LSB) Attenuation (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5

Rev O 01/15/2016 7 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator Serial Mode Register Timing Diagram: (Note the Timing Spec Intervals in Blue ) The F1975 can be programmed via the serial port on the rising edge of Latch Enable (LE). Refer to Figure 2. Figure 2 - Serial Register Timing Diagram Note v When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the shift register which minimizes noise. It is recommended that Latch Enable be left high when the device is not being programmed. Table 3 - Serial Mode Timing Table Interval Symbol Description Min Spec Max Spec Units tmc Parallel to Serial Setup Time v From rising edge of V MODE to rising edge of CLK for D5 100 ns tds Clock high pulse width 10 ns tcls LE Setup Time v From the rising edge of CLK pulse for D0 to LE rising edge minus half the clock period. 10 ns tlew LE pulse width 30 ns tdsc Data Setup Time v From the starting edge of Data bit to rising edge of CLK 10 ns Tdht Data Hold Time v From rising edge of CLK to falling edge of the Data bit. 10 ns

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 8 Rev O 01/15/2016 Serial Mode Default Startup Condition: When the device is first powered up it will default to the Maximum Attenuation of 31.5 dB independent of the VMODE and parallel pin [D5:D0] conditions. Table 4 - Default Control Word for the Serial Mode (MSB) D4 D3 D2 D1 D0 (LSB) Attenuation (dB) 1 1 1 1 1 1 31.5 PARALLEL CONTROL MODE For the F1975 the user has the option of running in one of two parallel modes: Direct Parallel Mode or Latched Parallel Mode. Direct Parallel Mode: Direct Parallel Mode is selected when V MODE (pin 13) is set to a logic low and LE (pin 5) is set to a logic high. In this mode the device will immediately react to any voltage changes to the parallel control pins (1, 15, 16, 17, 19, 20). Use direct parallel mode for the fastest settling time. Direct Parallel Default Startup Condition: Attenuation value using Direct Parallel Mode is determined by logic condition of the parallel pins (1, 15, 16, 17, 19, 20) at the time of start up. Latched Parallel Mode: Latched Parallel Mode is selected when VMODE is set to a logic low and LE (pin 5) is toggled from a logic low to a logic high. To utilize Latched Parallel Mode:

• Set LE to a logic low.
• Set pins (1, 15, 16, 17, 19, 20) for desired attenuation setting. (While LE is set to a logic low, the attenuation state will not change.)
• Toggle LE to a logic high. The device will then transition to the attenuation settings reflected by pins D5 – D0. Latched Parallel Default Startup Condition: Latched Parallel Mode establishes a default attenuation state when the device is first powered up. The default setting is MAXIMUM Attenuation. Table 5 - Truth Table for the Parallel Pins D5 D4 D3 D2 D1 D0 Attenuation (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5

Rev O 01/15/2016 9 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator Figure 3 - Latched Parallel Mode Timing Diagram Table 6 - Latched Parallel Mode Timing Interval Symbol Description Min Spec Max Spec Units tsps Serial to Parallel Mode Setup Time 100 ns tpdh Parallel Data Hold Time 10 ns tpds LE minimum pulse width 10 ns tle Parallel Data Setup Time 10 ns

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 10 Rev O 01/15/2016 TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.

• V DD = +3.30 V
• TCASE = +25 °C
• FRF = 1 GHz
• PIN = 0 dBm for single tone measurements
• PIN = +10 dBm/tone for multi-tone measurements
• Tone Spacing = 50 MHz
• EVKit connector and board losses are de-embedded
• Measured in a 75 ohm system unless otherwise specified

Rev O 01/15/2016 11 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator TYPICAL OPERATING CONDITIONS (- 1 -) Insertion Loss vs Frequency RF1 Return Loss vs Frequency (All States) RF2 Return Loss vs Frequency (All States) Insertion Loss vs Attenuation State RF1 Return Loss vs Attenuation State RF2 Return Loss vs Attenuation State -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Insertion Loss (dB) Frequency (GHz) -40 C +25 C +105 C -40 -35 -30 -25 -20 -15 -10 Match (dB) Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 Match (dB) Frequency (GHz) -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Insertion Loss (dB) Attenuation (dB)

1 GHz, -40 C

1 GHz, +25 C

1 GHz, +105 C

-40 -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match(dB) Attenuation (dB) 0.01 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz -40 -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match (dB) Attenuation (dB) 0.01 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 12 Rev O 01/15/2016 TYPICAL OPERATING CONDITIONS (- 2 -) Relative Insertion Phase vs Frequency (All States) Worst Case Absolute Accuracy Error Worst Case Step Accuracy Relative Insertion Phase vs Attenuation Accuracy Error vs Attenuation Step Error vs Attenuation Phase (degrees) Frequency (GHz) -2.0 -1.5 -1.0 -0.5 0.0 0.5 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Phase (degrees) Attenuation (dB) 0.01 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz -2.0 -1.5 -1.0 -0.5 0.0 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 0.01 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 0.01 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz

Rev O 01/15/2016 13 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator TYPICAL OPERATING CONDITIONS (- 3 -) Compression [Attenuation = 0.0 dB] Input IP3 -2.0 -1.5 -1.0 -0.5 0.0 0.5 16 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) 0.005 GHz 0.050 GHz 0.100 GHz 0.500 GHz 1.000 GHz 1.500 GHz 2.000 GHz Measured in a 50 ohm system 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Input IP3 (dBm) Attenuation Setting (dB) 0.035 GHz 0.065 GHz 0.130 GHz 0.500 GHz 0.920 GHz 1.400 GHz 2.000 GHz

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 14 Rev O 01/15/2016 PACKAGE DRAWING (4 mm x 4 mm 24vpin TQFN), NCG20 LAND PATTERN DIMENSION

Rev O 01/15/2016 15 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator PIN DIAGRAM CLK DATA NC VMODE GND LE NC *RF2*RF1 VDD NC GND 4 12 6 7 98 10 16 17 19 18 20 NC NC Exposed Pad TOP View (looking through the top of the package) * Device is RF Bi-Directional

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 16 Rev O 01/15/2016 PIN DESCRIPTION PIN NAME FUNCTION 1 D5 16 dB Attenuation Control Bit. Activated by L ogic High (see page 8) 2 RF1 Device RF input or output (bivdirectional).

3 DATA Serial interface Data Input

4 CLK Serial interface Clock Input

5 LE Serial interface Latch Enable Input. Internal pullup (100 kohm)

6 VDD Power supply pin

7 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) 8 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) 9 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) 10 GND Connect to Ground. This pin is internally c onnected to the exposed paddle 11 GND Connect to Ground. This pin is internally c onnected to the exposed paddle 12 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) 13 VMODE Pull high for serial control mode. Ground for parallel control mode. 14 RF2 Device RF input or output (bivdirectional). 15 D4 8 dB Attenuation Control Bit. Activated by L ogic High (see page 8) 16 D3 4 dB Attenuation Control Bit. Activated by L ogic High (see page 8) 17 D2 2 dB Attenuation Control Bit. Activated by L ogic High (see page 8) 18 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 19 D1 1 dB Attenuation Control Bit. Activated by L ogic High (see page 8) 20 D0 0.5 dB Attenuation Control Bit. Activated by Logic High (see page 8) EP Exposed Paddle Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance.

Rev O 01/15/2016 17 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator EVKIT PICTURE

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 18 Rev O 01/15/2016 EV KIT / A PPLICATIONS CIRCUIT

Rev O 01/15/2016 19 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator EVK IT BOM (R EV 1) Item # Part Reference QTY DESCRIPTION Mfr. Part # Mfr.

1 C1, C11, C15 3 100nF ±10%, 16V, X7R Ceramic Capacitor

(0402) GRM155R71C104K MURATA

2 C2, C10 2 10nF ±5%, 50V, X7R Ceramic Capacitor (0603) GRM188R71H103J MURATA

C3, C4, C5, C6, C7, C8, C9, C12, C13, C14 10 100pF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H101J MURATA

4 R3, R4, R5, R6,

R7, R8, R9 7 100Ω ±1%, 1/10W, Resistor (0402) ERJv2RKF1000X PANASONIC R10 vR13, R15vR18, R24vR27 12 0Ω Resistors (0402) ERJv2GE0R00X PANASONIC

6 R21, R22, R23 3 3kΩ ±1%, 1/10W, Resistor (0402) ERJ v2RKF3001X PANASONIC

7 R1 1 100 kΩ ±1%, 1/10W, Resistor (0402) ERJ v2RKF1003X PANASONIC

8 R2 1 267k Ω ±1%, 1/10W, Resistor (0402) ERJ v2RKF2673X PANASONIC

9 J2, J3, J5 3 CONN HEADER VERT SGL 2 X 1 POS GOLD 961102 v6404 vAR 3M

10 J11 1 CONN HEADER VERT DBL 4 X 2 POS GOLD 67997 v108HLF FCI

11 J4 1 CONN HEADER VERT SGL 9 X 1 POS GOLD 961109 v6404 vAR 3M

12 J1, J8 2 Edge Launch SMA (0.250 inch pitch ground, round) 142v0711v821 Emerson Johnson

13 J6, J7 2 Edge Launch F TYPE 75 ohm 222181 Amphenol

14 U2 1 SWITCH 8 POSITION DIP SWITCH KAT1108E EvSwitch

15 U1 1 DSA F1975 IDT

16 1 Printed Circuit Board F1975 Evkit Rev 01 IDT TOP MARKINGS IDTF19 75NCGI ZA515BEG Part Number Date Code [YWW] (Week 5 of 2015) ASM Test Step Assembler Code

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 20 Rev O 01/15/2016 A PPLICATIONS INFORMATION F1975 Digital Pin Voltage & Resistance Values (pins not connected) The following table lists the resistance between various pins and ground when no DC power is applied. When the device is powered up with +5 Volts DC, these pins will exhibit a voltage to ground as indicated. Pin Name DC voltage (volts) Resistance (ohms) 13 V MODE 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V 3, 4, 5 DATA, CLK, LE 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V

Rev O 01/15/2016 21 6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator REVISION H ISTORY SHEET Rev Date Page Description of Change O 2016v01v15 Initial Release

6-Bit, 75 ΩΩ ΩΩ , Digital Step Attenuator 22 Rev O 01/15/2016 Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or sp ecifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provi ded without representation or warranty of any kind, whether express or implied, including, but not lim ited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or nonvinfringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.