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Technical content
Features
Serial and 7-bit parallel interface 31.75dB range 0.25dB steps Glitch-FreeTM: low transient overshoot 500ns settling time for 0.25dB steps Ultra linear > 63dBm IIP3 Low insertion loss < 1.7dB at 4GHz Attenuation error < ±0.2dB at 4GHz Bi-directional RF use 3.3V or 5V supply -40°C to +105°C operating temperature 4mm x 4mm Thin QFN 24-pin package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 4mm x 4mm x 0.75mm TQFN Package – Top View
1 DATA
Table 1. Pin Descriptions 1 D0 Parallel control pin – 0.25dB. Pull high for attenuation. 2 VDD Power supply input. Bypass to ground with capacitors as close as possible to pin. 4, 6 - 13, 15 GND Internally grounded. These pins must be grounded as close to the device as possible. external AC coupling capacitor must be used if there is a DC voltage present. external AC coupling capacitor must be used if there is a DC voltage present. planes. These multiple ground vias are also required to achieve the specified RF performance. [a] There is a 500kΩ pull-down resistor to ground.
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Table 2. Absolute Maximum Ratings
Table 3. Recommended Operating Conditions Figure 3. Maximum Operating CW Input Power vs. Input Frequency
Table 4. Electrical Characteristics de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111]. these columns that are not shown in bold italics are guaranteed by design characterization. [b] Speeds are measured after SPI programming is completed (data latched with LE = LOW to HIGH transition). [c] Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
Table 5. Electrical Characteristics de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111]. these columns that are not shown in bold italics are guaranteed by design characterization.
Table 6. Electrical Characteristics de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111]. these columns that are not shown in bold italics are guaranteed by design characterization. Figure 3 for the maximum operating power levels.
Table 7. Package Thermal Characteristics
by pulling VMODE to a logic HIGH, and the parallel mode is selected by floating VMODE or setting it to logic LOW. shifted in LSB (D0) first. When serial programming is used, all the parallel control input pins (1, 19 - 24) must be grounded. Table 8. 7- Bit SPI Word Sequence Table 9. Truth Table for Serial Control Word register. Refer to Figure 33.
Figure 33. Serial Register Timing Diagram Table 10. SPI Timing Diagram Values for the Serial Mode Table 11. Default Setting Truth Table for Serial Control Word
For the F1958, the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode. DATA, can be either grounded or left opened in the Parallel Mode. Set VMODE to logic LOW or leave floating. Adjust pins (1, 19 - 24) to the desired attenuation setting. (Note the device will not react to these pins while LE is a logic LOW). Set LE to a logic HIGH. The device will then transition to the attenuation settings reflected by pins D6 - D0. If LE is set to a logic LOW then the attenuator will not change state. truth table for the Parallel Mode is identical for bits D6 to D0 as shown in the Serial Mode truth table; see Table 9. Figure 34. Latch Parallel Timing Diagram Table 12. Latched Parallel Timing Diagram Values
Figure 37. Electrical Schematic
10 Pin Header
1 SW1
8 Pin DP Switch
25 PAD
Table 13. Bill of Material (BOM)
1 Printed Circuit Board F1958 EVKit Rev 01 IDT
Figure 38. Power Supply Connections voltage that is supplied to the switch. Apply a voltage through a SMA connector (J9). This connector is not supplied. Apply a voltage on pin 2 of the J7 header connector. Evaluation Board. The logic voltage will be VDD.
© 2019 Integrated Device Technology, Inc. 22 November 13, 2019 F1958 Datasheet
Application Information
Digital Pin Voltage and Resistance Values Table 14 provides the open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed. Table 14. Digital Pin Voltages and Resistance the supply voltage ramps or while it returns to zero. below. Note the recommended resistor and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity. Figure 41. Control Pin Interface for Signal Integrity
© 2019 Integrated Device Technology, Inc. 23 November 13, 2019 F1958 Datasheet Package Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/nbnbg24-package-outline-40-x-40-mm-bodyepad-270mm-sq-050-mm-pitch-qfn
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F1958NBGK 4mm x 4mm x 0.75mm 24 pin QFN 1 Tray -40°C to +105°C F1958NBGK8 4mm x 4mm x 0.75mm 24 pin QFN 1 Reel -40°C to +105°C F1958EVB Evaluation Board F1958EVS Evaluation Solution including the Evaluation Board, Controller Board, and cable. The Evaluation Software is available for download on the product page on the IDT website: http://www.idt.com/F1958 Marking Diagram F1958 NBGK Z1716AAG 1. Line 1 and 2 are the part number. 2. Line 3 “ Z” is for die version. 3. Li ne 3 “yyww” = 1716 has two digits for the year and week that the part was assembled. 4. Li ne 3 “NG” denotes Assembly Lot number.
© 2019 Integrated Device Technology, Inc. 24 November 13, 2019 F1958 Datasheet
Revision History
Revision Date Description of Change November 13, 2019 Updated J10 connector on Evaluation Schematic to show all 8 pins (previously only 4 were displayed). August 22, 2018 Absolute Attenuator Error minimum value changed from -0.4 dB to -0.5 dB. March 26, 2018 Initial release Corporate Headquarters
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San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support D ISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non- infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. I DT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. I ntegrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.
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