F1956

F1956 IDT | Alldatasheet

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7-Bit 0.25 dB Wideband Digital Step Attenuator 1 to 6000 MHz F1956, Rev 2 04/08/2016 1 © 2016 Integrated Device Technology, Inc. GENERAL DESCRIPTION This document describes the specification for the F1956 Digital Step Attenuator. The F1956 is part of IDT’s Glitch-FreeTM family of DSAs optimized for the demanding requirements of Base Station (BTS) radio cards and numerous other non-BTS applications. This device is offered in compact 5 mm x 5 mm 32-pin package with 50  input and output impedance for ease of integration into the radio or RF system. COMPETITIVE ADVANTAGE The F1956 offers very high reliability due to its construction from a monolithic silicon die in a QFN package. The insertion loss is very low with minimal distortion. Additionally the device is designed to have extremely accurate attenuations levels. These accurate attenuation level improves system SNR and/or ACLR by ensuring system gain is as close to targeted level as possible. Also, the very fast settling time in parallel mode is ideal for fast switching systems. Finally, the device is Glitch-FreeTM with less than 2 dB of ringing across the attenuation range in stark contrast to competing DSAs that glitch as much as 10 dB during MSB state changes.  Lowest insertion loss for best SNR  Glitch-FreeTM technology to protect PA or ADC during transitions between attenuation states.  Extremely accurate attenuation levels  Ultra low distortion  MSL1 and 2000 V HBM ESD

ORDERING INFORMATION

FEATURES

 Serial & 7-bit Parallel Interface  31.75 dB Range  0.25 dB steps  Glitch-FreeTM: low transient overshoot  500 ns settling time  Ultra linear > 64 dBm IIP3  Low Insertion Loss < 1.7 dB @ 4 GHz  Attenuation error < ±0.2 dB @ 4 GHz  Bi-directional RF use  3.3 V or 5 V Supply  1.8 V or 3.3 V control logic  Low Current Consumption: 350 μA typical  -40 °C to +105 °C operating temperature  5 mm x 5 mm Thin QFN 32 pin package FUNCTIONAL BLOCK DIAGRAM Decoder RF1 RF2 D[6:0] SPIBias A[2:0] CLK DATA LEVMODE Glitch-FreeTM Glitch-FreeTM Part# Details Part# Freq Range (MHz) Resolution / Range (dB) Control IL (dB) Pinout F1950 150 - 4000 0.25 / 31.75 Parallel & Serial 1.3 PE43702 PE43701 F1951 100 - 4000 0.50 / 31.5 Serial Only 1.2 HMC305 F1952 100 – 4000 0.50 / 15.5 Serial Only 0.9 HMC305 F1953 400 – 4000 0.50 / 31.5 Parallel & Serial 1.3 PE4302 DAT-31R5 F1956 1 - 4000 0.25 / 31.75 Parallel & Serial 1.4 PE43705, PE43712, RFSA3715 F1912 1 – 4000 0.50 / 31.5 Parallel & Serial 1.6 PE4312 PE4302 F1956NBGI8 Green Tape & Reel

7-Bit 0.25 dB Wideband Digital Step Attenuator 2 Rev 2 04/08/2016 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units VDD to GND VDD -0.3 +5.5 V D[6:0], DATA, CLK, LE, A0, A1, A2, VMODE VCNTL -0.3 Min (VDD + 0.3, 3.9) V RF1, RF2 VRF -0.3 +0.3 V Maximum Input Power applied to RF1 or RF2 (>100 MHz) PRF +34 dBm Operating Case Temperature 105 °C Continuous Power Dissipation 1.5 W Maximum Junction Temperature TJmax +150 °C Storage Temperature Range TST -65 +150 °C Lead Temperature (soldering, 10s) TLEAD +260 °C Electrostatic Discharge – HBM (JEDEC/ESDA JS-001-2012) VESDHBM 1500 (Class 1C) V ESD Voltage – CDM (Per JESD22-C101F) VESDCDM 500 (Class C2) V Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD. Please use proper ESD precautions when handling to avoid damage or loss of performance . PACKAGE THERMAL AND MOISTURE CHARACTERISTICS θJA (Junction – Ambient) 40 °C/W θJC (Junction – Case) [The Case is defined as the exposed paddle] 4 °C/W Moisture Sensitivity Rating (Per J-STD-020) MSL1

7-Bit 0.25 dB Wideband Digital Step Attenuator 4 Rev 2 04/08/2016 F1956 SPECIFICATION Specifications apply at VDD = +3.3 V, TCASE = +25 °C, FRF = 2 GHz, 0.25 dB steps unless otherwise noted. Minimum Attenuation D[6:0] = [0000000], Maximum Attenuation D[6:0] = [1111111], EVKit losses are de -embedded unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Logic Input High VIH CLK, LE, DATA, D[6:0], A0, A1, A2, VMODE Logic Input Low VIL CLK, LE, DATA, D[6:0], A0, A1, A2, VMODE 0.63 V Logic Current IIH, IIL Individual Pins -40 +20 μA Supply Current IDD 350 800 μA Attenuation Range ATTRNG No missing codes 31.75 dB Minimum Gain Step LSB FRF  4.5 GHz 0.25 dB FRF  6.5 GHz 0.50 FRF  8.5 GHz 1.00 DSA Settling time SET Max to Min Attenuation to settle to within 0.5 dB of final value 0.9 s Min to Max Attenuation to settle to within 0.5 dB of final value 1.8 Video Feedthrough RF1, RF2 ports VIDFT Measured at RF ports with 2.5 ns risetime, 0 to 3.3 V control pulse 10 mVpp Maximum spurious level on any RF port4 SpurMAX Spur Freq ~ 2.2 MHz -140 dBm Serial Clock Speed FCLK SPI 3 wire bus 25 MHz Parallel to Serial Setup A SPI 3 wire bus 100 ns Serial Data Hold Time B SPI 3 wire bus 10 ns LE Delay C SPI 3 wire bus Time from final serial clock rising edge 10 ns Maximum Switching Rate SWRATE 25 kHz Specification Notes: Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Note 3. The input 0.1 dB compression point is used as a linearity figure of merit. The recommended maximum input power is specified as the lesser of the two values from RF CW Power (Figure 1) and the RF Average Power (Recommended Operating Conditions Table).. Note 4: Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz.

Rev 2 04/08/2016 5 7-Bit 0.25 dB Wideband Digital Step Attenuator F1956 SPECIFICATION (CONTINUED) Specifications apply at VDD = +3.3 V, TCASE = +25°C, FRF = 2 GHz, 0.25 dB steps unless otherwise noted. Minimum Attenuation D[6:0] = [0000000], Maximum Attenuation D[6:0] = [1111111], EVKit losses are de-embedded unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Insertion Loss IL 1 MHz < FRF ≤ 2 GHz 1.3 1.8 dB 2 GHz < FRF ≤ 3 GHz 1.3 1.9 3 GHz < FRF ≤ 4 GHz 1.6 2.2 4 GHz < FRF ≤ 5 GHz 2.1 2.6 5 GHz < FRF ≤ 6 GHz 2.6 3.0 Relative Phase (Amin vs. Amax) ΦΔ FRF = 1 GHz 12 deg FRF = 2 GHz 25 FRF = 4 GHz 55 FRF = 6 GHz 90 Step Error (Differential Non-Linearity) DNL Max error between adjacent steps 0.10 0.19 dB Absolute Attenuation Error (Integral Non-Linearity) INL Max Error for state 19.75 dB, FRF = 2 GHz -0.4 0.1 +0.5 dB Max Error, over all states FRF = 2 GHz -0.8 +0.5 Input Return Loss S11

1 MHz < FRF ≤ 2 GHz 20 15

dB 2 GHz < FRF ≤ 4 GHz 20 15

4 GHz < FRF ≤ 6 GHz 14 7

1 MHz < FRF ≤ 2 GHz 18 14

dB 2 GHz < FRF ≤ 4 GHz 16 12

4 GHz < FRF ≤ 6 GHz 11 7

PIN = +10 dBm per tone

50 MHz Tone Separation

Attn = 0.00 dB 64 dBm Attn = 15.75 dB 64 Attn = 31.75 dB 64 Attn = 0.00 dB PIN = +22 dBm per tone

1 MHz Tone Separation

FRF = 0.7 GHz 60 63.4 dBm FRF = 1.8 GHz 60 63.4 FRF = 2.2 GHz 60 64.1 FRF = 2.6 GHz 60 63.3 Input 0.1dB Compression3 P0.1dB FRF = 2 GHz, Attn = 10 dB 34.5 dBm Specification Notes: Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Note 3. The input 0.1 dB compression point is used as a linearity figure of merit. The recommended maximum input power is specified as the lesser of the two values from RF CW Power (Figure 1) and the RF Average Power (Recommended Operating Conditions Table).. Note 4: Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz.

7-Bit 0.25 dB Wideband Digital Step Attenuator 6 Rev 2 04/08/2016 PROGRAMMING OPTIONS F1956 can be programmed using either the parallel or serial interface; selectable via VMODE (pin 3). Serial mode is selected by floating VMODE or pulling VMODE to a logic high and parallel mode is selected by setting VMODE to logic low. SERIAL CONTROL MODE F1956 Serial mode is selected by floating VMODE (pin 3) or pulling it to logic high. The serial interface is a 16-bit shift register made up of two words. The first 8-bit word is the Attenuation word, which controls the DSA state. The second word is the address word, which uses only 3 of 8-bits that must match the hard wired A0-A2 programming in order to change the DSA state. If no external connections are made to A0 – A2 then internally they will default to 000 due to internal pull down resistors. If these 3 external preset address bits are not matched with the SPI loaded address bits then the current attenuator state will remain unchanged. This allows up to 8 serial-controlled devices to be used on a single board, which share a common DATA, CLK and LE. When serial programming is used, all the parallel control input pins 26 – 32 can be left open or grounded. If a pin is grounded then an additional 25 µA will be drawn from the voltage supply per pin. Set to either Logic High or Low Set to Logic Low MSB (Last In) LSB (First In) Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit Address Word 8-Bit Attenuation Word Figure 2 -Two 8-bit words are comprised of 16bit serial in, parallel out shift register Table 1 -Truth Table for the Serial Address Word (MSB) A6 A5 A4 A3 A2 A1 A0 Address Setting X X X X X 0 0 0 000 X X X X X 0 0 1 001 X X X X X 0 1 0 010 X X X X X 0 1 1 011 X X X X X 1 0 0 100 X X X X X 1 0 1 101 X X X X X 1 1 0 110 X X X X X 1 1 1 111

Rev 2 04/08/2016 7 7-Bit 0.25 dB Wideband Digital Step Attenuator Table 2 - Truth Table for the Serial Control Word D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Attenuation (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 0 1 0 0.5 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 2 0 0 0 1 0 0 0 0 4 0 0 1 0 0 0 0 0 8 0 1 0 0 0 0 0 0 16 0 1 1 1 1 1 1 1 31.75 SERIAL MODE DEFAULT CONDITION When the device is first powered up it will default to the Maximum Attenuation setting as described below: Note that for the F1956 in all cases logic high (1) has the attenuation stepped IN, while logic low (0) has the attenuation stepped OUT. MSB (Last In) LSB (First In) Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X 0 0 0 0 1 1 1 1 1 1 1 8-Bit Address Word 8-Bit Attenuation Word Figure 3 -Default register settings set for max attenuation and 000 Address Word REGISTER TIMING DIAGRAM: (NOTE THE TIMING SPEC INTERVALS IN BLUE) With serial control, the F1956 can be programmed via the serial port on the rising edge of Latch Enable (LE) which loads the last 8 DATA line bits [formatted LSB (D0) first] resident in the SHIFT register followed by the Address Word into the ACTIVE register.

7-Bit 0.25 dB Wideband Digital Step Attenuator 8 Rev 2 04/08/2016 Reinsert Figure 4 - Serial Timing Diagram Note - When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the shift register which minimizes noise. It is recommended that Latch enable be left high when the device is not being programmed. Table 3 - Serial Mode Timing Table Interval Symbol Description Min Spec Max Spec Units tps Parallel to Serial Setup Time - From rising edge of Vmode to rising edge of CLK for D5 100 ns tp Clock high pulse width 10 ns tcls LE Setup Time - From the rising edge of CLK pulse for D0 to LE rising edge minus half the clock period. 10 ns tlew LE pulse width 30 ns tdst Data Setup Time - From the starting edge of Data bit to rising edge of CLK 10 ns tdht Data Hold Time - From rising edge of CLK to falling edge of the Data bit. 10 ns PARALLEL CONTROL MODE For the F1956 the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode. Direct Parallel Mode: Direct Parallel Mode is selected when VMODE is a logic low and LE is a logic high. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins 26 – 32]. Use direct parallel mode for the fastest settling time.

Rev 2 04/08/2016 9 7-Bit 0.25 dB Wideband Digital Step Attenuator Latched Parallel Mode: Latched Parallel Mode is selected when VMODE is logic low and LE is toggled from logic low to high. To utilize Latched Parallel Mode:  Set VMODE is logic low.  Set LE to logic low.  Adjust pins [26, 27, 28, 29, 30, 31, 32] to the desired attenuation setting. (Note the device will not react to these pins while LE is a logic low).  Pull LE to a logic high. The device will then transition to the attenuation settings reflected by pins D6 - D0.  IF LE is pulled to a logic low then the attenuator will not change state. Latched Parallel Mode implies a default state for when the device is first powered up with V MODE set for logic low and LE logic low. In this case the default setting is MAXIMUM Attenuation. Table 4 - Truth Table for the Parallel Control Word D6 D5 D4 D3 D2 D1 D0 Attenuation (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 1 0 0.5 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 4 0 1 0 0 0 0 0 8 1 0 0 0 0 0 0 16 1 1 1 1 1 1 1 31.75 Figure 5 - Latched Parallel Mode Timing Diagram

7-Bit 0.25 dB Wideband Digital Step Attenuator 10 Rev 2 04/08/2016 Table 5 - Latched Parallel Mode Timing Interval Symbol Description Min Spec Max Spec Units tsps Serial to Parallel Mode Setup Time 100 ns tpdh Parallel Data Hold Time 10 ns tle LE minimum pulse width 10 ns tpds Parallel Data Setup Time 10 ns TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply. 1. VDD = +3.30 V 2. TCASE = +25 °C 3. 50 MHz Tone Space 4. Serial Control 5. PIN = 0 dBm 6. RF1 is the input port 7. Attenuation Setting = 0 dB 8. EVKit losses (traces and connectors) are fully de-embedded

Rev 2 04/08/2016 11 7-Bit 0.25 dB Wideband Digital Step Attenuator TYPICAL OPERATING CONDITIONS (- 1 -) Insertion Loss vs Frequency Input Return Loss vs Frequency [All States] Output Return Loss vs Frequency [All States] Insertion Loss vs Attenuation Input Return Loss vs Attenuation Output Return Loss vs Attenuation 0 1 2 3 4 5 6 7 8 Insertion Loss (dB) Frequency (GHz) -40 C +25 C +105 C -40 -35 -30 -25 -20 -15 -10 0 1 2 3 4 5 6 7 8 Match (dB) Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 0 1 2 3 4 5 6 7 8 Match (dB) Frequency (GHz) -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Insertion Loss (dB) Attenuation (dB)

3.0 GHz, -40 C

3.0 GHz, +25 C

3.0 GHz, +105 C

-40 -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match(dB) Attenuation (dB) -40 -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match (dB) Attenuation (dB)

7-Bit 0.25 dB Wideband Digital Step Attenuator 12 Rev 2 04/08/2016 TYPICAL OPERATING CONDITIONS (- 2 -) Worst Case Absolute Accuracy (LSB=0.25 dB) Worst Case Absolute Accuracy (LSB=0.50 dB) Worst Case Absolute Accuracy (LSB=1.00 dB) Absolute Accuracy (LSB=0.25 dB) Absolute Accuracy (LSB=0.50 dB) Absolute Accuracy (LSB=1.00 dB) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0 1 2 3 4 5 6 7 8 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0 1 2 3 4 5 6 7 8 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0 1 2 3 4 5 6 7 8 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 3.00 GHz 3.50 GHz 4.00 GHz 4.50 GHz -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB)

Rev 2 04/08/2016 13 7-Bit 0.25 dB Wideband Digital Step Attenuator TYPICAL OPERATING CONDITIONS (- 3 -) Worst Case Step Accuracy (LSB=0.25 dB) Worst Case Step Accuracy (LSB=0.50 dB) Worst Case Step Accuracy (LSB=1.00 dB) Step Accuracy (LSB=0.25 dB) Step Accuracy (LSB=0.50 dB) Step Accuracy (LSB=1.00 dB) -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 5 6 7 8 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 5 6 7 8 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 5 6 7 8 Error (dB) Frequency (GHz) -40 C Min -40 C Max +25 C Min +25 C Max +105 C Min +105 C Max -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 3.00 GHz 3.50 GHz 4.00 GHz 4.50 GHz -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB)

7-Bit 0.25 dB Wideband Digital Step Attenuator 14 Rev 2 04/08/2016 TYPICAL OPERATING CONDITIONS (- 4 -) Relative Insertion Phase vs Frequency [All States] Input Compression (at 2 GHz, Attn=0 dB) Input Compression (at 2 GHz, Attn=4 dB) Relative Insertion Phase vs Attenuation Input Compression (at 2 GHz, Attn=16 dB) Input Compression (at 2 GHz, Attn=31.75 dB) -10 100 110 0 1 2 3 4 5 6 7 8 Phase (degrees) Frequency (GHz) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) -40 C +25 C +105 C -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) -40 C +25 C +105 C -10 100 110 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Phase (degrees) Attenuation (dB) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) -40 C +25 C +105 C -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) -40 C +25 C +105 C

Rev 2 04/08/2016 15 7-Bit 0.25 dB Wideband Digital Step Attenuator TYPICAL OPERATING CONDITIONS (- 5 -) Input Compression (+25 °C, 4 GHz) Input IP3 vs Attenuation [2 GHz] Input IP3 vs Frequency [Attn=0 dB, Pin=+22 dBm] Input Compression (+25 °C, 6 GHz) Input IP3 vs Attenuation [3.92 GHz] -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 24 25 26 27 28 29 30 31 32 33 34 Compression (dB) Input Power (dBm)

4 GHz 0 dB

4 GHz 4 dB

4 GHz 8 dB

4 GHz 16 dB

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Input IP3 (dBm) Attenuation (dB) -40 C / Pin = 10 dBm/Tone -40 C / Pin = 15 dBm/Tone +25 C / Pin = 10 dBm/Tone +25 C / Pin = 15 dBm/Tone +105 C / Pin = 10 dBm/Tone +105 C / Pin = 15 dBm/Tone Input IP3 (dBm) Frequency (GHz) IIP3-HS IIP3-LS -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 24 25 26 27 28 29 30 31 32 33 34 Compression (dB) Input Power (dBm)

6 GHz 0 dB

6 GHz 4 dB

6 GHz 8 dB

6 GHz 16 dB

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Input IP3 (dBm) Attenuation (dB)

7-Bit 0.25 dB Wideband Digital Step Attenuator 16 Rev 2 04/08/2016 PACKAGE DRAWING 5mm x 5mm 32-pin TQFN), Use Exposed PAD (EPAD) Option P1

Rev 2 04/08/2016 17 7-Bit 0.25 dB Wideband Digital Step Attenuator LAND PATTERN DIMENSION PIN DIAGRAM F1956 Exposed pad (GND) NC VDD V_MODE GND GND RF1 GND CLK LE NC GND RF2 GND GND GND GND GND GND GND GND GND DATA25 329 TOP View (looking through the top of the package)

7-Bit 0.25 dB Wideband Digital Step Attenuator 18 Rev 2 04/08/2016 PIN DESCRIPTION Pin Name Function 1 DNC This pin must be left open. 2 VDD Main Supply. Use 3.3 V or 5 V. Bypass capacitor as close to pin as possible.

3 VMODE

1 Logic low for parallel mode. Logic high or NC for serial mode. 4 A02 Address bit A0 connection.

5 GND Connect directly to paddle ground or as close as possible to pin with thru

via. This pin is not internally connected

6 GND Connect directly to paddle ground or as close as possible to pin with thru

via. 7 RF13 Device RF input or output (bi-directional). AC couple to this pin unless 0V DC. 8 – 17 GND Connect each pin directly to paddle ground or as close as possible to pin with thru vias. 18 RF23 Device RF input or output (bi-directional). AC couple to this pin unless 0V DC.

19 GND Connect directly to paddle ground or as close as possible to pin with thru

via. 20 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended).

21 A22 Address bit A2 connection

22 A12 Address bit A1 connection. 23 LE1 Serial interface latch enable input. 24 CLK1 Serial interface clock input. 25 DATA1 Serial interface data input. 26 D61 Parallel control bit, 16 dB. Ground pin if not used. 27 D51 Parallel control bit, 8 dB. Ground pin if not used. 28 D41 Parallel control bit, 4 dB. Ground pin if not used. 29 D31 Parallel control bit, 2 dB. Ground pin if not used. 30 D21 Parallel control bit, 1 dB. Ground pin if not used. 31 D11 Parallel control bit, 0.5 dB. Ground pin if not used. 32 D01 Parallel control bit, 0.25 dB. Ground pin if not used. EP Exposed Paddle Connect to Ground with multiple vias for good thermal and RF performance.

Rev 2 04/08/2016 19 7-Bit 0.25 dB Wideband Digital Step Attenuator EVKIT PICTURE

7-Bit 0.25 dB Wideband Digital Step Attenuator 20 Rev 2 04/08/2016 EVKIT / APPLICATIONS CIRCUIT C15 C14 R15 R16 VDD 1345

2 C17 C18

V_MODE3 A04 GND5 GND6 RF17 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 CLK 24 LE 23 A1 22 A2 21 NC 20 GND 19 RF2 18 GND 17 D0 32 D1 31 D2 30 D3 29 D4 28 D5 27 D6 26 DATA 25 PAD33 1345 R17 R10 C10 R15 - 6 kohms 1% R16 - 10 kohms 1% R11 C11 J11 HEADER 1x21 2 SW1 10 pin DIP Swtich 10987654321 12 HEADER 1x2 1 2 1 345 C21C22 HEADER 4 1234 J12 1345 HEADER 1x2 J13 1 345 Thru Cal R12 R13 R14 C16

Rev 2 04/08/2016 21 7-Bit 0.25 dB Wideband Digital Step Attenuator EVKIT BOM (REV 2) Item # Part Reference QTY DESCRIPTION Mfr. Part # Mfr.

1 C1 - C11, C14,

C15, C16 14 100 pF ±5%, 50 V, C0G Ceramic Capacitor (0402) GRM1555C1H101J MURATA

2 C18, C20, C22 3 1000 pF ±5%, 50 V, C0G Ceramic Capacitor

(0402) GRM1555C1H102J MURATA

3 C17, C19, C21 3 10 nF ±5%, 50 V, X7R Ceramic Capacitor (0603) GRM188R71H103J MURATA

4 R17 1 0 Ω Resistors (0402) ERJ-2GE0R00X PANASONIC

5 R1 - R14 14 100 Ω ±1%, 1/10 W, Resistor (0402) ERJ-2RKF1000X PANASONIC

6 R15 1 6.98 kΩ ±5%, 1/10 W, Resistor (0402) ERJ-2RKF6981X PANASONIC

7 R16 1 10 kΩ ±1%, 1/10 W, Resistor (0402) ERJ-2RKF1002X PANASONIC

8 J3, J7, J9,

J10, J11

5 CONN HEADER VERT SGL 2 X 1 POS GOLD 961102-6404-AR 3M

9 J5 1 CONN HEADER VERT SGL 4 X 1 POS GOLD 961104-6404-AR 3M

10 J1 1 CONN HEADER VERT SGL 12 X 1 POS GOLD 961112-6404-AR 3M

11 J2, J4, J6, J8,

J12, J13

6 Edge Launch SMA

(0.375 inch pitch ground, tab) 142-0701-851 Emerson Johnson

12 SW1 1 SWITCH 10 POSITION DIP SWITCH KAT1110E E-Switch

13 U1 1 DSA F1956 IDT

14 1 Printed Circuit Board F1955 EVKit Rev 02 IDT TOP MARKINGS IDT F1956NBGI ZA1515G Part Number Date Code [YYWW] (Week 15 of 2015) ASM Test Step Assembler Code Q20A006MY Lot Code

7-Bit 0.25 dB Wideband Digital Step Attenuator 22 Rev 2 04/08/2016 APPLICATIONS INFORMATION Power Supplies A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V/20uS. In addition, all control pins should remain at 0V (+/-0.3V) while the supply voltage ramps or while it returns to zero. Digital Pin Voltage & Resistance Values The following table provides open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed. Pin Name Open Circuit DC Voltage Internal Connection 3 VMODE 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V 4, 21, 22 A0, A2, A1 0 V 100 kΩ resistor to GND 23, 24, 25 LE, CLK, DATA 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V 26 – 32 D6 – D0 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V

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San Jose, CA 95138 USA Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. The information contained herein is provided without representati on or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Copyright ©2016. Integrated Device Technology, Inc. All rights reserved. 7-Bit 0.25 dB Wideband Digital Step Attenuator 23 Rev 2 04/08/2016 REVISION HISTORY SHEET Rev Date Page Description of Change O 2015-May-22 Initial Release 1 2015-Sep-29 Datasheet Format Update Added Maximum Average Power Rating 2 2016-Apr-01 Maximum operating frequency changed to 6 GHz. Added curves showing performance at higher frequencies.