F1953 IDT | Alldatasheet
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6-bit Digital Step Attenuator 400 to 4000 MHz F1953 Datasheet © 2018 Integrated Device Technology, Inc. 1 September 5, 2018 G ENERAL D ESCRI PTI ON This document describes the specification for the IDTF1953 Digital Step Attenuator. The F1953 is part of a family of Glitch-FreeTM DSAs optimized for the demanding requirements of communications Infrastructure. These devices are offered in a compact 4x4 QFN package with 50 Ω impedances for ease of integration. COMPETI TI VE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The IDTF1953 is a 6-bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (> +60 dBm IP3 I.) The device has pinpoint accuracy and settles to final attenuation value within 400 ns. Most importantly, the F1953 includes IDT’s Glitch-FreeTM technology which results in less than 0.5 dB of overshoot ringing during MSB transitions. This is in stark contrast to competing DSAs that glitch as much as 10 dB (see p. 10.) Lowest insertion loss for best SNR Glitch-FreeTM when transitioning – won’t damage PA or ADC Extremely accurate with low distortion APPLI CATI ONS Base Station 2G, 3G, 4G, TDD radio-cards Repeaters and E911 systems Digital Pre-Distortion Point to Point Infrastructure Public Safety Infrastructure WIMAX Receivers and Transmitters Military Systems, JTRS radios RFID handheld and portable readers Cable Infrastructure PART # M ATRI X Part# Freq range Resolution / Range Control IL Pinout F1950 150 - 4000 0.25 / 31.75 Parallel & Serial -1.3 PE43702 PE43701 F1951 100 - 4000 0.50 / 31.5 Serial Only -1.2 HMC305 F1952 100 – 4000 0.50 / 15.5 Serial Only -0.9 HMC305 F1953 400 - 4000 0.50 / 31.5 Parallel & Serial -1.3 PE4302 DAT-31R5
FEATURES
Glitch-FreeTM, < 0.6 dB transient overshoot Spurious Free Design 2.7 to 3.6 V supply Attenuation Error < 0.5 dB @ 2 GHz Low Insertion Loss < 1.4 dB @ 2 GHz Excellent Linearity >+60 dBm IP3I Fast settling time, < 400 ns Serial or Parallel Interface 31.5 dB Range Stable Integral Non-Linearity over temperature Low Power Consumption < 200 uA Integrated DC blocking capacitors Drop-In replacement 4x4 mm Thin QFN 20 pin package D EVI CE BLOCK D I AGRAM O RDERI NG I NFORMATI ON RF 1 Bias VDDVMODE DEC D[5:0] CLK SPI LEDATA RF 2 I DTF1953NCGI 8 0.8 mm height package Green I ndustrial Temp range Tape & Reel Omit I DT prefix RF product Line Glitch-FreeTM Glitch-FreeTM
© 2018 Integrated Device Technology, Inc. 2 September 5, 2018 ABSOLUTE M AXI MUM R ATI NGS VDD to GND -0.3 V to +4.0 V D[5:0], DATA, CLK,LE,VMODE -0.3 V to 3.6 V RF Input Power (RF1, RF2) calibration and testing +29 dBm RF Input Power (RF1, RF2) continuous RF operation +23 dBm θJA (Junction – Ambient) +50 °C/W θJC (Junction – Case) The Case is defined as the exposed paddle +3 °C/W Operating Temperature Range (Case Temperature) T C = -40 °C to +100 °C Maximum Junction Temperature 140 °C Storage Temperature Range -65 °C to +150 °C Lead Temperature (soldering, 10s) +260 °C Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD Caution This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD. Please use proper ESD precautions when handling to avoid damage or loss of performance. I DTF1953 R ECOMMENDED O PERATI NG CONDI TI ONS Parameter Comment Sym Min Typ Max Units Supply Voltage Main Supply VDD 2.7 3.0 3.6 V Temperature Range Operating Range (Case) TC -40 +100 °C Frequency Range Operating Range FRF 400 4000 MHz RF1 Impedance Single Ended ZRF1 50 RF2 Impedance Single Ended ZRF2 50
© 2018 Integrated Device Technology, Inc. 3 September 5, 2018 I DTF1953 SPECI FI CATI ON (31.5 dB Range) Specifications apply at VDD = +3.0 V, fRF = 2000 MHz, TC= +25°C, VMODE > VIH (Serial Mode) EVkit losses are de-embedded (see p. 17) Parameter Comment Sym Min Typ Max Units Logic Input High CLK, DATA, LE, VMODE, D[5:0] VIH 0.7xVDD VDD V Logic Input Low CLK, DATA, LE, VMODE, D[5:0] VIL 0.3xVDD V Logic Current VMODE, D[5:0] IIH, IIL -5 +5 μA Logic Current LE IIH, IIL -35 +35 μA Supply Current Total V DD = 3V IDD 0.16 0.251 mA RF1,RF2 Return Loss 20*log( S11), 20*log(S22) S11,S22 -23 dB Minimum Attenuation D[5:0] = [000000] AMIN 1.35 1.90 dB Maximum Attenuation D[5:0] = [111111] AMAX 32.0 32.4 dB Minimum Gain Step Least Significant Bit LSB 0.50 dB Phase Delta Phase change AMIN vs. AMAX Φ∆ 39 deg Differential ATTN Error Between adjacent steps DNL 0.09 dB Integral ATTN Error Error vs. line (AMIN ref) to 13.5dB ATTN INL1 0.20 0.60 dB Integral ATTN Error Error vs. line (AMIN ref) to 31.5dB ATTN INL2 0.47 0.75 dB Input IP3 P IN = +10 dBm per tone 50 MHz Tone Separation IP3I1 IP3I2 IP3I3 +572 +53 +53 +66 +60 +60 dBm 0.1 dB Compression Please note ABS MAX PIN on Page 2 Baseline PIN = 20 dBm P0.1 28.5 dBm Settling Time (parallel mode) Start LE rising edge > VIH End +/-0.10 dB Pout settling 15.5 – 16.0 transition TLSB 400 ns Serial Clock Speed SPI 3 wire bus FCLK 10 50 MHz Serial Setup Time From rising edge of Vmode to rising edge of CLK for D5 A 20 ns Clock width Clock high pulse width B 10 ns LE setup time From rising edge of CLK pulse for D0 to LE rising edge C 10 ns LE pulse LE minimum pulse width D 30 ns SPECI FI CATI ON N OTES : 1 – Items in min/max columns in bold italics are Guaranteed by Test 2 – All other Items in min/max columns are Guaranteed by Design Characterization
© 2018 Integrated Device Technology, Inc. 4 September 5, 2018 SERI AL CONTROL Serial mode is selected when VMODE is pulled high (> VIH), In serial mode the F1953 attenuation setting is programmed via the 3 wire bus (LE, CLK, DATA). In serial mode data is clocked in MSB first. Note the timing diagram below. Note – The IDTF1953 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being programmed. When Latch enable is high (> VIH), the CLK input is disabled and DATA will not be clocked into the shift register. It is recommended that LE be pulled high (> VIH) when the device is not being programmed. SERI AL R EGI STER D EFAULT CONDI TI ON If the device is powered up in Serial Mode, the device will default to whatever attenuation state is defined by the six parallel data input pins D5,D4,D3,D2,D1,D0 thus allowing any attenuation setting to be specified as the power up state. SERI AL R EGI STER TI MI NG D I AGRAM : (Note the Timing Spec Intervals in Blue) SERI AL R EGI STER TI MI NG TABLE Interval Symbol Description Min Spec Max Spec Units A From rising edge of Vmode to rising edge of CLK for D5 20 ns B Clock high pulse width 10 ns C From rising edge of CLK pulse for D0 to LE rising edge 10 ns D LE minimum pulse width 30 ns E Serial data set-up time before clock rising edge 10 ns F Serial data hold time after clock rising edge 10 ns
© 2018 Integrated Device Technology, Inc. 5 September 5, 2018 PARALLEL CONTROL M ODE The user has the option of running in one of two parallel modes: Direct Parallel Mode or Latched Parallel Mode. D I RECT-PARALLEL M ODE : Direct-parallel mode is selected when VMODE (pin 13) is < VIL and LE (pin 5) is > VIH. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17, 19, 20]. Use direct-parallel mode for the fastest settling time. LATCHED -PARALLEL M ODE : Latched-parallel mode is selected when VMODE (pin 13) is < VIL and LE (pin 5) is toggled from < VIL to > VIH To utilize latched-parallel mode: Set LE < V IL Adjust pins [1, 15, 16, 17, 19, 20] to the desired attenuation setting. (Note the device will not react to these pins while LE < VIL.) Pull LE > V IH. The device will then transition to the attenuation settings reflected by these pins. When the device is powered up In Latched Parallel Mode [VMODE < VIL and LE > VIH] the attenuation setting defaults to the state defined by the six parallel data pins [pins 1, 15, 16, 17, 19, 20] LATCHED PARALLEL M ODE TI MI NG D I AGRAM : (Note the Timing Spec Intervals in Blue) LATCHED PARALLEL M ODE TI MI NG TABLE : Interval Symbol Description Min Spec Max Spec Units A Serial to Parallel Mode Setup Time 100 ns B Parallel Data Hold Time 10 ns C LE minimum pulse width 10 ns D Parallel Data Setup Time 10 ns D [ 5 : 0 ] Data Word Latched into Active RegisterLE V MODE Spec Interval A D C B
© 2018 Integrated Device Technology, Inc. 6 September 5, 2018 TYPI CAL O PERATI NG PARAMETRI C CURVES (EVKit loss de-embedded, 3.0V unless otherwise noted) I nsertion Loss vs. Frequency [AMI N] S11 vs. Frequency [TCASE = + 25C, 0.5 dB steps] S11 vs. Attenuation State Attenuation vs. Freq [TCASE = + 25C, 0.5 dB steps] S22 vs. Frequency [TCASE = + 25C, 0.5 dB steps] S22 vs. Attenuation State -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V RF Frequency (MHz) Insertion Loss (dB) -40 -35 -30 -25 -20 -15 -10 400 800 1200 1600 2000 2400 2800 3200 3600 4000 RF Frequency (MHz) RF1 Return Loss (dB) -40 -35 -30 -25 -20 -15 -10 0 4 8 12 16 20 24 28 -40 degC - 3.0 V - 900 MHz -40 degC - 3.0 V - 2000 MHz 25 degC - 3.0 V - 900 MHz 25 degC - 3.0 V - 2000 MHz 100 degC - 3.0 V - 900 MHz 100 degC - 3.0 V - 2000 MHz Attenuation Setting (dB) RF1 Return Loss (dB) -35 -30 -25 -20 -15 -10 400 800 1200 1600 2000 2400 2800 3200 3600 4000 RF Frequency (MHz) DSA Loss (dB) -40 -35 -30 -25 -20 -15 -10 400 800 1200 1600 2000 2400 2800 3200 3600 4000 RF Frequency (MHz) RF2 Return Loss (dB) -40 -35 -30 -25 -20 -15 -10 0 4 8 12 16 20 24 28 -40 degC - 3.0 V - 900 MHz -40 degC - 3.0 V - 2000 MHz 25 degC - 3.0 V - 900 MHz 25 degC - 3.0 V - 2000 MHz 100 degC - 3.0 V - 900 MHz 100 degC - 3.0 V - 2000 MHz Attenuation Setting (dB) RF2 Return Loss (dB)
© 2018 Integrated Device Technology, Inc. 7 September 5, 2018 TOC S CONTI NUED (-2-) Phase vs. Frequency Supply Current I DD [vs. Temp] I nput I P3 [fRF = 1900 MHz, VDD = 3.0 V] Phase vs. Attenuation Setting Supply Current I DD [vs. VDD ] Compression [fRF = 2000 MHz, ATTN = 2.5 dB] -130 -110 -90 -70 -50 -30 -10 500 800 1100 1400 1700 2000 2300 2600 2900 3200 3500 -40 degC - 3.0 V - 0 -40 degC - 3.0 V - 31.5 25 degC - 3.0 V - 0 25 degC - 3.0 V - 31.5 100 degC - 3.0 V - 0 100 degC - 3.0 V - 31.5 RF Frequency (MHz) S21 Phase (degrees) 0.0 0.1 0.2 0.3 0.4 0.5 0 4 8 12 16 20 24 28 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Total IDD (mA) Attenuation Setting (dB) 0 4 8 1 21 62 02 42 83 2 Input IP3 (dBm) Attenuation Setting (dB) -40C 25C 100C -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 4 8 12 16 20 24 28
400 MHz
900 MHz
1400 MHz
1900 MHz
2400 MHz
2900 MHz
3400 MHz
3900 MHz
S21 Phase (degrees) Attenuation Setting (dB) 0.00 0.10 0.20 0.30 0.40 0.50 0 4 8 1 21 62 02 42 8 25 degC - 3.3 V 25 degC - 3.0 V 25 degC - 2.7 V Total IDD (mA) Attenuation Setting (dB) 0.0 0.1 0.2 0.3 0.4 0.5 22 23 24 25 26 27 28 Loss Compression (dB) Input Power (dBm) -40degC 2.5 dB ATTN 25degC 2.5 dB ATTN 100degC 2.5 dB ATTN
© 2018 Integrated Device Technology, Inc. 8 September 5, 2018 TOC S CONTI NUED (-3-) DNL [400 MHz] DNL [900 MHz] DNL [2800 MHz] DNL [700 MHz] DNL [1900 MHz] Worst Setting DNL -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Step Error (dB) -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Step Error (dB) -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Step Error (dB) -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Step Error (dB) -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Step Error (dB) 0.00 0.25 0.50 0.75 1.00 400 800 1200 1600 2000 2400 2800 3200 3600 4000 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Worst Setting Step Error (dB) RF Frequency (MHz)
© 2018 Integrated Device Technology, Inc. 9 September 5, 2018 TOC S CONTI NUED (-4-) I NL [400 MHz] I NL [900 MHz] I NL [2900 MHz] I NL [700 MHz] I NL [1900 MHz] Worst Setting I NL -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Absolute Error (dB) -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Absolute Error (dB) -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Absolute Error (dB) -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Absolute Error (dB) -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0 4 8 1 21 62 02 42 8 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Attenuation Setting (dB) Absolute Error (dB) -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 -40 degC - 3.0 V 25 degC - 3.0 V 100 degC - 3.0 V Worst Setting Absolute Error (dB) RF Frequency (MHz)
© 2018 Integrated Device Technology, Inc. 10 September 5, 2018 TOC S CONTI NUED (-5-) [fRF = 900 MHz] Transient [ 15.5 to 16.0 (MSB+ ) 3.3V F1953 ] The graphs ABOVE show the transient overshoot and settling time performance for both the MSB+ and MSB- cases for the F1953. The device settles very quickly (~400) ns with benign (~0.5) dB overshoot. Transient [ 15.75 to 16.00 (MSB+ ) Standard DSA ] Transient [ 16.0 to 15.5 (MSB-) 5.0V F1953 ] The graphs BELOW show the transient overshoot and settling time performance for a popular competing DSA. Note the overshoot/undershoot excursion of almost 10 dB and the very long settling time. For the MSB- case, the settling time is off the scale, ~ 3 μsec. Transient [ 16.00 to 15.75 (MSB-) Standard DSA ] -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -10.9 -9.9 -8.9 -7.9 -6.9 -5.9 -4.9 -3.9 -2.9 -1.9 -0.9 0 100 200 300 400 500 600 700 800 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Glitch ~ 0.5 dB Pwr (dBm) Trigger Settling Time = 400 nsec (+/- 0.1 dB) -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -15.20 -14.20 -13.20 -12.20 -11.20 -10.20 -9.20 -8.20 -7.20 -6.20 -5.20 -100 0 100 200 300 400 500 600 700 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Pwr (dBm) Trigger Settling Time = 600nsec (+/- 0.1 dB) -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -11.0 -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0 100 200 300 400 500 600 700 800 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Glitch ~ 0.3 dB Pwr (dBm) Trigger Settling Time = 370 nsec (+/- 0.1 dB) -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -13.57 -12.57 -11.57 -10.57 -9.57 -8.57 -7.57 -6.57 -5.57 -4.57 -3.57 -100 0 100 200 300 400 500 600 700 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Pwr (dBm) Trigger Settling Time >> 1 usec
© 2018 Integrated Device Technology, Inc. 11 September 5, 2018 PI N D I AGRAM CLK DATA GND [internal NC] VMODE GND [internal NC] LE GND [internal NC] *RF2*RF1 Exposed Pad VDD NC GND [internal NC] Package Drawing 4 mm x 4 mm package dimension 2.06 mm x 2.06 mm exposed pad 0.5 mm pitch 20 pins 0.75 mm height 0.25 mm pad width 0.55 mm pad length 6 7 98 10 161719 1820 NC NC CO 0.3 5 m m TOP View (looking through the top of the package) * Device is RF Bi-Directional
© 2018 Integrated Device Technology, Inc. 12 September 5, 2018 PACKAGE D RAWI NGS The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/20-qfn-package-outline-drawing-40-x-40-x-075-mm-body-05mm-pitch-epad-206-x-206- mm-ncg20p1
© 2018 Integrated Device Technology, Inc. 13 September 5, 2018 PI N D ESCRI PTI ONS Pin # Pin Name Pin Function 1 D5 16 dB Attenuation Control Bit. Pull high for 16 dB ATTN. 2 RF1 Device RF input or output (bi-directional). Internally DC blocked. 3 DATA Serial interface Data Input. 4 CLK Serial interface Clock Input. 5 LE Serial interface Latch Enable Input. Internal pullup (100K ohm). 6 VDD Power supply pin. 7 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 8 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 9 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 10 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 11 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 12 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 13 VMODE Pull high for serial mode. Ground for Parallel control mode. 14 RF2 Device RF input or output (bi-directional). Internally DC blocked. 15 D4 8 dB Attenuation Control Bit. Pull high for 8 dB ATTN. 16 D3 4 dB Attenuation Control Bit. Pull high for 4 dB ATTN. 17 D2 2 dB Attenuation Control Bit. Pull high for 2 dB ATTN. 18 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 19 D1 1 dB Attenuation Control Bit. Pull high for 1 dB ATTN. 20 D0 0.5 dB Attenuation Control Bit. Pull high for 0.5 dB ATTN. EP Exposed Paddle Connect to Ground with multiple vias for good thermal relief.
© 2018 Integrated Device Technology, Inc. 14 September 5, 2018 EV KI T SCHEMATI C The diagram below describes the recommended applications / EVkit circuit:
© 2018 Integrated Device Technology, Inc. 15 September 5, 2018 EVK I T O PERATI ON (Email: RFsupport@I DT.com to request an EVkit and Controller) The picture and graphic below describe how to operate the EVkit RF1 DC Power Serial Control Port Unused RF2 DATA Clock Latch Enable Set to ‘-‘ to use DIP switch Set to ‘+’ to use Serial Port 0.5 dB LSB 16 dB MSB
© 2018 Integrated Device Technology, Inc. 16 September 5, 2018 EVK I T BOM (F1953) TOP M ARKI NGS F1953 BOM Rev 01 PCB Rev 01 Item # Value Size Desc Mfr. Part # Mfr. Part Reference Qt y 1 10nF 0402 CAP CER 10000PF 16V 10% X7R 0402 GRM155R71C103KA01D MURATA C2,12 2 2 0.1uF 0402 CAP CER 0.1UF 16V 10% X7R 0402 GRM155R71C104KA88D MURATA C1,11 2
3 Header 2 Pin TH 2 CONN HEADER VERT SGL 2POS GOLD 961102-6404-AR 3M J5,7 2
4 Header 4 Pin TH 4 CONN HEADER VERT SGL 4POS GOLD 961104-6404-AR 3M J8 1
5 Header 8 Pin TH 8 CONN HEADER VERT SGL 8POS GOLD 961108-6404-AR 3M J6 1
6 SMA_END_LAUNCH .062 SMA_END_LAUNCH (Small) 142-0711-821 Emerson Johnson J2,3,4 3 7 0 0402 RES 0.0 OHM 1/10W 0402 SMD ERJ-2GE0R00X Panasonic R1-7,12,C13,C14 10 8 3K 0402 RES 3.00K OHM 1/10W 1% 0402 SMD ERJ-2RKF3001X Panasonic R9-11 3 9 10K 0402 RES 10K OHM 1/10W 1% 0402 SMD ERJ-2RKF1002X Panasonic R8,15-17 4 10 100K 0402 RES 100KOHM 1/10W 1% 0402 SMD ERJ-2RKF104X Panasonic R13 1 11 267K 0402 RES 267K OHM 1/10W 1% 0402 SMD ERJ-2RKF2673X Panasonic R14 1
12 DIPSwitch TH 10 8 POSITION DIP SWITCH KAT1108E E-Switch U1 1
13 Digital Step Attenuator F1953Z F1953Z IDT U2 1
14 PCB PCB Rev 01 F1953S Evkit Rev 01 SBC 1
15 100pF 0402 CAP CER 100PF 16V 10% X7R 0402 GRM155R71C103KA01D MURATA C3-10,15-20 DNP 16 SMA_END_LAUNCH .062 SMA_END_LAUNCH (Small) 142-0711-821 Emerson Johnson J1 DNP Total 33 11/15/2012
© 2018 Integrated Device Technology, Inc. 17 September 5, 2018 EVK I T THROUGH -REFLECT -LI NE (TRL) CALI BRATI ON The “Through-Reflect-Line” (TRL) method [1] is used to de-embed the evaluation board losses from the S-parameter measurements of the F1953. This method requires the use of three standards: a through, a reflection, and a line. The TRL method has the advantage over other calibration methods in that it requires only one of these three standards to be well defined. The TRL through which is used for the F1953 TRL calibration was constructed identically to the evaluation board, minus the DUT and its corresponding length. Therefore, the through corresponds to a precise zero length connection between the input and output reference planes of the DUT. This through satisfies the requirement of the TRL method that one of the three standards be precisely specified. The TRL reflection standard used is constructed identically to the input and output lines of the evaluation board, with a short placed at the reference plane of the DUT. In accordance with the TRL method’s requirements, the actual magnitude and phase were not accurately specified, but the phase was known to within 90 degrees and the TRL reflection standard has a magnitude close to one. The TRL line standard is identical to the TRL through, but with an additional length of 0.8 inches (2 cm). This satisfies the TRL method’s requirement that the TRL be a different length than the TRL through, that it have the same impedance and propagation constant as the through, and that the phase difference between the through and the line be between 20 degrees and 160 degrees. The difference in length yields a phase difference of approximately 20 degrees at 500 MHz, and a phase difference of 160 degrees at 4 GHz. Standards used for F195x TRL calibration F1953 evaluation circuit Engen, G.F.; Hoer, C.A.; “Thru-Reflect-Line: An Improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer,” IEEE Transactions on Microwave Theory and Techniques, Volume: 27 Issue:12, pp. 987 – 993, Dec 1979.
© 2018 Integrated Device Technology, Inc. 18 September 5, 2018
Revision History
Revision Date Description of Change September 5, 2018 Updated document template. Updated Package Outline Drawings section. Now references the latest official drawing. No changes to dimensions. Added disclaimer paragraph. December 3, 2015 Corrected logic voltage. Add recommended operating conditions table. Updated serial timing figure. Updated pin description table. Updated evaluation board schematic. April 10, 2014 Correct top marking drawing. March 30, 2013 Initial release. Corporate Headquarters
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San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its af filiated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specif ications described herein at any time, without notice, at IDT's sole di scretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of t he intellectual p roperty rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For dat asheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.
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,QWHJUDWHG'HYLFH7HFKQRORJ\\,QF NCG20P1, PSC-4445-01, Rev 01, Page 2 Package Revision History Rev No.Date Created Description Sept 11, 2017 Rev 00 Initial Release Sept 12, 2017 Rev 01 Correct Title