F1951

IDTF1951 IDT | Alldatasheet

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6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 1 Rev2 April 2013 IDT F195 1 DATASHEET G ENERAL D ESCRIPTION This document describes the specification for the IDTF1951 Digital Step Attenuator. The F1951 is part of a family of Glitch6Free TM DSAs optimized for the demanding requirements of communications Infrastructure. These devices are offered in a compact 4x4 QFN package with 50 Ω impedances for ease of integration into the radio system. COMPETITIVE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The IDTF1951 is a 66bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (+65 dBm IP3 I.) The device has pinpoint accuracy and settles to final attenuation value within 400 nsec. Most importantly, the F1951 includes IDT’s GG lliittcchh--FFrreeeeTTMM technology which results in less than 0.6 dB of overshoot ringing during MSB transitions. This is in stark contrast to competing DSAs that glitch as much as 10 dB during MSB transitions (see p.10) /checkbld/checkbld LLoowweesstt iinnsseerrttiioonn lloossss ffoorr bbeesstt SSNNRR /checkbld/checkbld GGlliittcchh66FFrreeeeTTMM wwhheenn ttrraannssiittiioonniinngg –– wwoonn’’tt ddaammaaggee PPAA oorr AADDCC /checkbld/checkbld EExxttrreemmeellyy aaccccuurraattee wwiitthh llooww ddiissttoorrttiioonn

APPLICATIONS

• Base Station 2G, 3G, 4G, TDD radiocards
• Repeaters and E911 systems
• Digital Pre6Distortion
• Point to Point Infrastructure
• Public Safety Infrastructure
• WIMAX Receivers and Transmitters
• Military Systems, JTRS radios
• RFID handheld and portable readers
• Cable Infrastructure P ART # MATRIX Part# Freq range Resolution / Range Control IL Pinout F1950 150 I 4000 0.25 / 31.5 Serial Only I1.3 PE F1952 100 – 4000 0.50 / 15.5 Serial Only I0.9 HITT

FEATURES

• Glitch6Free TM , < 0.6 dB transient overshoot
• Spurious Free Design
• 3V to 5V supply
• Attenuation Error < 0.2 dB @ 2 GHz
• Low Insertion Loss < 1.2 dB @ 2 GHz
• Excellent Linearity +65 dBm IP3 I
• Fast settling time, < 450 nsec
• Class 2 JEDEC ESD (> 2kV HBM)
• Serial Interface 31.5 dB Range
• Stable Integral Non6Linearity over temperature
• 4x4 mm Thin QFN 24 pin package D EVICE BLOCK D IAGRAM O RDERING INFORMATION RF 1 Bias VDD DEC SPI RF 2 RST CLK CS SDI SDO IDT F1951NBGI8 0.8 mm height package Green Industrial Temp range Tape & Reel Omit IDT prefix RF product Line Glitch-Free TM Glitch-Free TM

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 2 Rev2 April 2013 IDT F195 1 DATASHEET ABSOLUTE MAXIMUM RATINGS VDD to GND 60.3V to +5.25V D[5:0], DATA, CLK,CSb,SDO, RSTb 60.3V to 3.6V RF Input Power (RF1, RF2) calibration and testing + 29 dBm RF Input Power (RF1, RF2) continuous RF operation + 23 dBm θJA (Junction – Ambient) +50°C/W θJC (Junction – Case) The Case is defined as the exposed paddle +3°C/W Operating Temperature Range (Case Temperature) T C = 640°C to +100°C Maximum Junction Temperature 140°C Storage Temperature Range 665°C to +150°C Lead Temperature (soldering, 10s) . +260°C

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 3 Rev2 April 2013 IDT F195 1 DATASHEET IDTF1951 SPECIFICATION (31.5 dB Range) Specifications apply at VDD = +3.3V, fRF = 2000MHz , TC= +25°C unless otherwise noted, EVkit losses are deIembedded (see p. 17) Parameter Comment Sym. min typ ical max units Logic Input High CLK, CSb, DATA, D[5:0], RSTb VIH 2.3 3.6 V Logic Input Low CLK, CSb, DATA, D[5:0], RSTb VIL 0.7 V Logic Current V MODE IIH, IIL -5 +5 µA Supply Voltage(s) Main Supply VDD 3.0 to 5.25 V Supply Current Total IDD 1.1 2 1 mA Temperature Range Operating Range (Case) TC I40 to +100 degC Frequency Range Operating Range fRF 100 to 4000 MHz RF1, RF2 Return Loss dB(s11), dB(s22) S11 , S 22 I22 dB Minimum Attenuation D[5:0] = [111111] AMIN or IL 1.2 1.9 dB Maximum Attenuation • D[5:0] = [000000]

• VDD = 3.3V AMAX 32.2 32.5 dB Minimum Gain Step Least Significant Bit LSB 0.50 dB Phase Delta Phase change A MIN vs. AMAX Φ∆ 33 deg Differential NonILinearity Error: adjacent steps DNL 0.08 dB Integral NonILinearity Error: absolute to 14 dB ATTN INL 1 0.03 0.34 dB Integral NonILinearity Max Error vs. line (A MIN ref) to 31.5 dB ATTN [V DD = 3.3V] INL 2 0.21 0.38 dB Input IP3 /square4 P IN = +10 dBm per tone /square4 50 MHz Tone Separation /square4 VDD = 3.3V IP3I1 IP3I2 IP3I3 +612 +59 +57 +64 +61 +61 dBm 0.1 dB Compression Please note ABS MAX /square4 Baseline PIN = 20 dBm P0.1 29 dBm Settling Time /square4 Start LE rising edge > V IH /square4 End +/I0.10 dB Pout settling /square4 15.5 – 16.0 transition TLSB 400 nsec Serial Clock Speed SPI 4 wire bus FCL K 20 50 MHz Reset to Serial Setup SPI 4 wire bus A 20 nsec Serial Data Hold Time SPI 4 wire bus B 5 nsec CSb setup delay SPI 4 wire bus C 40 100 nsec Serial Data Out Delay SPI 4 wire bus D 8 8 8 Cycles S PECIFICATION NOTES : 1 – Items in min/max columns in bold italics are Guaranteed by Test 2 – All other Items in min/max columns are Guaranteed by Design Characterization

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 4 Rev2 April 2013 IDT F195 1 DATASHEET S ERIAL CONTROL MODE Data is clocked in LSB first via serial mode. Note the timing diagram below. An RSTb pulse resets the shift register to [00000000]. If the RSTb pulse is followed immediately by a CSb pulse the device will be set to Maximum Attenuation . Note – The IDTF1951 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being programmed. When CSb is high (> VIH ), the CLK input is disabled and serial data (SDI) will not be clocked into the shift register. It is recommended that CSb be pulled high (>V IH ) when the device is not being programmed SERIAL REGISTER TIMING D IAGRAM [S INGLE D EVICE ]: (Note the Timing Spec Intervals in Blue ) S ERIAL REGISTER TIMING D IAGRAM [TWO OR MORE DEVICES ]: The contents of the shift register is delayed by 8 clock cycles while CSb is low. This feature allows one to program multiple DSAs (in a MIMO transceiver for instance) with a single common CSb line by daisyIchaining the SDO of the 2nd DSA to the SDI of the 1st DSA and so forth:

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 5 Rev2 April 2013 IDT F195 1 DATASHEET S ERIAL REGISTER D EFAULT CONDITION [F1951]: When the device is first powered up, it will default to the Maximum Attenuation setting as described below: Note that for the F1951 (High or 1) = Attenuation Stepped OUT . (0 or Low) = Attenuation Stepped IN . S ERIAL REGISTER TIMING TABLE [F1951]: Interval Symbol Description Min Spec Max Spec Units A Reset to Serial Setup Time 20 nsec B Serial Data Hold Time 5 nsec C CSb setup delay 40 100 nsec D Serial Data Out Delay 8 8 Cycles Default Register Settings 00 0 0 0 0 0 0 R0 R1 D3D0 D2D1 LSB MSB RSV RSV

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 6 Rev2 April 2013 IDT F195 1 DATASHEET T YPICAL OPERATING PARAMETRIC CURVES (EVKit loss de-embedded, 3.3V unless otherwise noted) Insertion Loss vs. Frequency [A MIN ] S11 vs. Frequency [T CASE = +25C, 0.5 dB steps] S11 vs. Attenuation State Attenuation vs. Freq [T CASE = +25C, 0.5 dB steps] S22 vs. Frequency [T CASE = +25C, 0.5 dB steps] S22 vs. Attenuation State I4.0 I3.5 I3.0 I2.5 I2.0 I1.5 I1.0 I0.5 0.0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 I40 degC I 3.3 V 25 degC I 3.3 V 100 degC I 3.3 V RF Frequency (MHz) Insertion Loss (dB) I40 I35 I30 I25 I20 I15 I10 200 600 1000 1400 1800 2200 2600 3000 3400 3800 RF Frequency (MHz) RF Frequency (MHz) RF Frequency (MHz) RF Frequency (MHz) RF1 Return Loss (dB) I40 I35 I30 I25 I20 I15 I10 0 4 8 12 16 20 24 28 I40 degC I 900 MHz I40 degC I 2000 MHz 25 degC I 900 MHz 25 degC I 2000 MHz 100 degC I 900 MHz 100 degC I 2000 MHz Attenuation Setting (dB) RF1 Return Loss (dB) I35 I30 I25 I20 I15 I10 200 600 1000 1400 1800 2200 2600 3000 3400 3800 RF Frequency (MHz) RF Frequency (MHz) RF Frequency (MHz) RF Frequency (MHz) DSA Loss (dB) I40 I35 I30 I25 I20 I15 I10 200 600 1000 1400 1800 2200 2600 3000 3400 3800 RF Frequency (MHz) RF Frequency (MHz) RF Frequency (MHz) RF Frequency (MHz) RF2 Return Loss (dB) I40 I35 I30 I25 I20 I15 I10 0 4 8 12 16 20 24 28 I40 degC I 900 MHz I40 degC I 2000 MHz 25 degC I 900 MHz 25 degC I 2000 MHz 100 degC I 900 MHz 100 degC I 2000 MHz Attenuation Setting (dB) RF2 Return Loss (dB) Attenuation Setting (dB) RF1 Return Loss (dB)

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 7 Rev2 April 2013 IDT F195 1 DATASHEET TOC S CONTINUED (-2-) Phase vs. Frequency Supply Current I DD Input IP3 [f RF = 1900 MHz] Phase vs. Attenuation Setting Input IP3 [f RF = 900 MHz] Compression [f RF = 2000 MHz, ATTN = 2.5 dB] I110 I100 I90 I80 I70 I60 I50 I40 I30 I20 I10 200 600 1000 1400 1800 2200 2600 3000 3400 3800 I40 degC I31.5 dB I40 degC I0.0 dB 25 degC I 31.5 dB 25 degC I 0.0 dB 100 degC I 31.5 dB 100 degC I 0.0 dB RF Frequency (MHz) S21 Phase (degrees) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 0 4 8 12 16 20 24 28 I40 degC I 3.3 V 25 degC I 3.3 V 100 degC I 3.3 V Total IDD (mA) Attenuation Setting (dB) 0 4 8 12 16 20 24 28 I40 degC I5.0 V I40 degC I3.3 V 25 degC I 5.0 V 25 degC I 3.3 V 100 degC I 5.0 V 100 degC I 3.3 V Attenuation Setting (dB) Input IP3 (dBm) I100 I90 I80 I70 I60 I50 I40 I30 I20 I10 0 4 8 12 16 20 24 28

100 MHz

400 MHz

900 MHz

1400 MHz

1900 MHz

2400 MHz

2900 MHz

3400 MHz

3900 MHz

Attenuation Setting (dB) S21 Phase (degrees) 0 4 8 12 16 20 24 28 I40 degC I5.0 V I40 degC I3.3 V 25 degC I 5.0 V 25 degC I 3.3 V 100 degC I 5.0 V 100 degC I 3.3 V Attenuation Setting (dB) Input IP3 (dBm) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 20 21 22 23 24 25 26 27 28 29 I40 degC I5.0 V I40 degC I3.3 V 25 degC I 5.0 V 25 degC I 3.3 V 100 degC I 5.0 V 100 degC I 3.3 V Loss Compression (dB) Attenuation Setting (dB)

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 8 Rev2 April 2013 IDT F195 1 DATASHEET TOC S CONTINUED (-3-) DNL [150 MHz] DNL [900 MHz] DNL [2800 MHz] DNL [400 MHz] DNL [1900 MHz] Worst Setting DNL I0.75 I0.50 I0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Step Error (dB) I0.75 I0.50 I0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Step Error (dB) I0.75 I0.50 I0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Step Error (dB) I0.75 I0.50 I0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Step Error (dB) I0.75 I0.50 I0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Step Error (dB) I1.00 I0.75 I0.50 I0.25 0.00 0.25 0.50 0.75 1.00 100 500 900 1300 1700 2100 2500 2900 3300 3700 I40 degC IMin of DNL (dB) I40 degC IMax of DNL (dB) 25 degC I Min of DNL (dB) 25 degC I Max of DNL (dB) 100 degC I Min of DNL (dB) 100 degC I Max of DNL (dB) RF Frequency (MHz) Worst Setting Step Error (dB)

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 9 Rev2 April 2013 IDT F195 1 DATASHEET TOC S CONTINUED (-4-) INL [150 MHz] INL [900 MHz] INL [2900 MHz] INL [400 MHz] INL [1900 MHz] Worst Setting INL I1.50 I1.25 I1.00 I0.75 I0.50 I0.25 0.00 0.25 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Absolute Error (dB) Attenuation Setting (dB) I1.50 I1.25 I1.00 I0.75 I0.50 I0.25 0.00 0.25 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Absolute Error (dB) Attenuation Setting (dB) I1.50 I1.25 I1.00 I0.75 I0.50 I0.25 0.00 0.25 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Absolute Error (dB) Attenuation Setting (dB) I1.50 I1.25 I1.00 I0.75 I0.50 I0.25 0.00 0.25 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Absolute Error (dB) Attenuation Setting (dB) I1.50 I1.25 I1.00 I0.75 I0.50 I0.25 0.00 0.25 0 4 8 12 16 20 24 28 I40 degC 25 degC 100 degC Attenuation Setting (dB) Attenuation Setting (dB) Absolute Error (dB) Attenuation Setting (dB) I4.0 I3.5 I3.0 I2.5 I2.0 I1.5 I1.0 I0.5 0.0 0.5 1.0 100 500 900 1300 1700 2100 2500 2900 3300 3700 I40 degC 25 degC 100 degC RF Frequency (MHz) Worst Setting Absolute Error (dB) RF Frequency (MHz)

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 10 Rev2 April 2013 IDT F195 1 DATASHEET TOC S CONTINUED (-5-) [f RF = 900 MHz] Transient [ 15.5 to 16.0 (MSB+) 3.3V F1951 ] The graphs ABOVE show the transient overshoot and settling time performance for both the MSB+ and MSB6 cases for the F1951. The device settles very quickly (~400) nsec with benign (~0.5) dB overshoot. Transient [ 15.75 to 16.00 (MSB+) Standard DSA ] Transient [ 16.0 to 15.5 (MSB-) 5.0V F1951 ] The graphs BELOW show the transient overshoot and settling time performance for a popular competing DSA. NNoottee tthhee oovveerrsshhoooott//uunnddeerrsshhoooott eexxccuurrssiioonn ooff aallmmoosstt 1100 ddBB and the very long settling time. For the MSB6 case, the settling time is off the scale, ~ 3 usec. Transient [ 16.00 to 15.75 (MSB-) Standard DSA ] I1.0 I0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I20.0 I19.0 I18.0 I17.0 I16.0 I15.0 I14.0 I13.0 I12.0 I11.0 I10.0 I100 0 100 200 300 400 500 600 700 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Glitch~ 0.5 dB Pwr (dBm) Trigger Settling Time = 400 nsec (+/- 0.1 dB) I1.0 I0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I15.20 I14.20 I13.20 I12.20 I11.20 I10.20 I9.20 I8.20 I7.20 I6.20 I5.20 I100 0 100 200 300 400 500 600 700 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Pwr (dBm) Trigger Settling Time = 600nsec (+/- 0.1 dB) I1.0 I0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I20.0 I19.0 I18.0 I17.0 I16.0 I15.0 I14.0 I13.0 I12.0 I11.0 I10.0 I100 0 100 200 300 400 500 600 700 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Glitch~ 0.5 dB Pwr (dBm) Trigger Settling Time = 390 nsec (+/- 0.1 dB) I1.0 I0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I13.57 I12.57 I11.57 I10.57 I9.57 I8.57 I7.57 I6.57 I5.57 I4.57 I3.57 I100 0 100 200 300 400 500 600 700 LE Trigger (volts) Envelope Power (dBm) Time (nsec) Pwr (dBm) Trigger Settling Time >> 1 usec

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 11 Rev2 April 2013 IDT F195 1 DATASHEET PIN D IAGRAM (F1951) NC GND [internal NC] NC NC *RF2 SDO NC V DD GND [internal NC] *RF1 NC Exposed Pad Package Drawing 4 mm x 4 mm package dimension 2.80 mm x 2.80 mm exposed pad 0.5 mm pitch 24 pins 0.75 mm height 0.25 mm pad width 0.40 mm pad length 87 9 11 10 12 20 19 21 23 22 24 NC CO 0.35 m m TOP View (looking through the top of the package) * Device is RF Bi-Directional

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 12 Rev2 April 2013 IDT F195 1 DATASHEET PACKAGE D RAWING (4X4 24 PIN )

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 13 Rev2 April 2013 IDT F195 1 DATASHEET PIN D ESCRIPTIONS Pin Pin Name Pin Function 1 NC Internally unconnected. Recommended connection is GND. 2 RF1 Device RF input or output (biIdirectional). Must AC couple to this pin. 3 GND Connect directly to paddle ground or as close as possible to pin with thru via. 4 NC Internally unconnected. Recommended connection is GND. 5 SDO Serial Data OutKelipsisDelayed 8 clock cycles from Serial Data In. 6 NC Internally unconnected. Recommended connection is GND. 7 RSTb Reset BAR. Falling Edge resets the device to Max Attenuation [D5:D0] = [000000]. 8 CLK Serial Clock. 9 CSb Chip Select Bar. Serial Data latched into active register on Rising Edge. 10 NC Internally unconnected. Recommended connection is GND. 11 SDI Serial Data Input. 12 NC Internally unconnected. Recommended connection is GND. 13 NC Internally unconnected. 14 VDD Main Supply. Use 3.3V or 5V. Current is < 1 mA. 15 NC Internally unconnected. Recommended connection is GND. 16 GND Connect directly to paddle ground or as close as possible to pin with thru via. 17 RF2 Device RF output or input (biIdirectional). Must AC couple to this pin. 18 NC Internally unconnected. Recommended connection is GND. 19 GND Connect directly to paddle ground or as close as possible to pin with thru via. 20 GND Connect directly to paddle ground or as close as possible to pin with thru via. 21 GND Connect directly to paddle ground or as close as possible to pin with thru via. 22 GND Connect directly to paddle ground or as close as possible to pin with thru via. 23 GND Connect directly to paddle ground or as close as possible to pin with thru via. 24 GND Connect directly to paddle ground or as close as possible to pin with thru via. EP Exposed Paddle Connect to Ground with multiple vias for good thermal relief.

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 14 Rev2 April 2013 IDT F195 1 DATASHEET EV KIT SCHEMATIC The diagram below describes the recommended applications / EVkit circuit: GND NC GND RF1 SDO NC RF2 NC NC VDD NC C13 C14 20 19 21 23 22 24 8 7911 10 12 RF1 VDD NC VDD C12 C11 RF2 I+ o I+ o I+ o I+ o I+ o I+ o I+ o I+ o C1 C2 R3 R4 R5 R6 R7 R8 4 pin Header Parallel Control Switch (not placed)VLH 8 pin Header C4 C5 C7 C8 C9 R1 C10 C15 C16 C17 R10 R11 R12 TP1 IDTF1951

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 15 Rev2 April 2013 IDT F195 1 DATASHEET EVK IT OPERATION (Email: RFsupport@IDT.com to request an EVkit, Serial Control HW/SW, or TRL cal board) The picture and graphic below describe how to operate the EVkit RF2 DC Power Unused RF1 SDO SDI CSb CLK RSTb

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 16 Rev2 April 2013 IDT F195 1 DATASHEET EVK IT BOM T OP MARKINGS F1951 BOM Rev 02 PCB Rev 01 Item # Value Size Description Mfr. Part # Mfr. Ref Des Qty 1 1000pF 0402 CAP CER 1000PF 50V C0G 0402 GRM1555C1H102JA01D MURATA C13,14 2 2 10nF 0402 CAP CER 10000PF 16V 10% X7R 0402 GRM155R71C103KA01D MURATA C12 1 3 0.1uF 0402 CAP CER 0.1UF 16V 10% X7R 0402 GRM155R71C104KA88D MURATA C11 1

4 Header 2 Pin TH 2 CONN HEADER VERT SGL 2POS GOLD 961102I6404IAR 3M J5 1

5 Header 4 Pin TH 4 CONN HEADER VERT SGL 4POS GOLD 961104I6404IAR 3M J8 1

6 Header 8 Pin TH 8 CONN HEADER VERT SGL 8POS GOLD 961108I6404IAR 3M J6 1

7 SMA_END_LAUNCH .062 SMA_END_LAUNCH (Small) 142I0711I821 Emerson Johnson J2,3,4 3 8 0 0402 RES 0.0 OHM 1/10W 0402 SMD ERJI2GE0R00X Panasonic R7,8,10 3 9 3K 0402 RES 3.00K OHM 1/10W 1% 0402 SMD ERJI2RKF3001X Panasonic R3,5,6 3

10 Digital Step Attenuator F1951 F1951 IDT U2 1

11 PCB PCB Rev 01 F195XS Evkit Rev 01 1

6Ibit 0.5 dB Digital Step Attenuator 100 MHz to 4000 MHz GlitchIFree TM Digital Step Attenuator 17 Rev2 April 2013 IDT F195 1 DATASHEET EVK IT THROUGH -REFLECT -LINE (TRL) CALIBRATION The “ThroughIReflectILine” (TRL) method [1] is used to deIembed the evaluation board losses from the SIparameter measurements of the F1951. This method requires the use of three standards: a through, a reflection, and a line. The TRL method has the advantage over other calibration methods in that it requires only one of these three standards to be well defined. The TRL through which is used for the F1951 TRL calibration was constructed identically to the evaluation board, minus the DUT and its corresponding length. Therefore, the through corresponds to a precise zero length connection between the input and output reference planes of the DUT. This through satisfies the requirement of the TRL method that one of the three standards be precisely specified. The TRL reflection standard used is constructed identically to the input and output lines of the evaluation board, with a short placed at the reference plane of the DUT. In accordance with the TRL method’s requirements, the actual magnitude and phase were not accurately specified, but the phase was known to within 90 degrees and the TRL reflection standard has a magnitude close to one. The TRL line standard is identical to the TRL through, but with an additional length of 0.8 inches (2 cm). This satisfies the TRL method’s requirement that the TRL be a different length than the TRL through, that it have the same impedance and propagation constant as the through, and that the phase difference between the through and the line be between 20 degrees and 160 degrees. The difference in length yields a phase difference of approximately 20 degrees at 500 MHz, and a phase difference of 160 degrees at 4 GHz. For characterization of performance from 150 to 500 MHz a separate TRL board with different “Line” length is used. Standards used for F195x TRL calibration F1951 evaluation circuit Engen, G.F.; Hoer, C.A.; “ThruIReflectILine: An Improved Technique for Calibrating the Dual SixIPort Automatic Network Analyzer,” IEEE Transactions on Microwave Theory and Techniques , Volume: 27 Issue:12, pp. 987 – 993, Dec 1979.