IDTF1912NCGI_17 IDT | Alldatasheet
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6 Bit Digital Step Attenuator 1 MHz to 4000 MHz
Glitch-FreeTM, Digital Step Attenuator 1 Rev 1, May 2017 IDTF1912NCGI Datasheet GENERAL DESCRIPTION This document describes the specification for the IDT F1912 Digital Step Attenuator. The F1912 is part of a family of Glitch-FreeTM DSAs optimized for the demanding requirements of Base Station (BTS) radio cards and numerous other non-BTS applications. These devices are offered in a compact 4mm x 4mm 20 pin QFN package with 50Ω impedances for ease of integration. COMPETITIVE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The F1912 is a 6-bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (> +60 dBm IIP3.) The device has pinpoint accuracy. Most importantly, the F1912 includes IDT’s Glitch-FreeTM technology which results in low overshoot & ringing during MSB transitions. Glitch-FreeTM Technology so PA or ADC will not be damaged during when transitions. Extremely accurate with low distortion. Lowest insertion loss for best SNR
APPLICATIONS
Base Station 2G, 3G, 4G, TDD radio cards Repeaters and E911 systems Digital Pre-Distortion Point to Point Infrastructure Public Safety Infrastructure WIMAX Receivers and Transmitters Military Systems, JTRS radios RFID handheld and portable readers Cable Infrastructure
ORDERING INFORMATION
FEATURES
Serial & 6 bit Parallel Interface 31.5 dB Control Range 0.5 dB step Glitch-FreeTM, low transient overshoot 3.0 V to 5.25 V supply 1.8 V or 3.3 V control logic Attenuation Error < 0.22 dB @ 2 GHz Low Insertion Loss < 1.6 dB @ 2 GHz Ultra linear IIP3 >+59.5 dBm IIP2 = +110 dBm typical Stable Integral Non-Linearity over temperature Low Current Consumption 550 µA typical -40 °C to +105 °C operating temperature 4mm x 4mm Thin QFN 20 pin package FUNCTIONAL BLOCK DIAGRAM Part# Details Part# Freq Range (MHz) Resolution / Range (dB) Control IL (dB) Pinout F1950 150 - 4000 0.25 / 31.75 Parallel & Serial 1.3 PE43702 PE43701 F1951 100 - 4000 0.50 / 31.5 Serial Only 1.2 HMC305 F1952 100 – 4000 0.50 / 15.5 Serial Only 0.9 HMC305 F1953 400 – 4000 0.50 / 31.5 Parallel & Serial 1.3 PE4302 DAT-31R5 F1956 1 - 4000 0.25 / 31.75 Parallel & Serial 1.4 PE43705, RFSA3715 F1912 1 – 4000 0.50 / 31.5 Parallel & Serial 1.4 PE4312 PE4302 Decoder RF1 RF2 D[5:0] SPIBias CLK DATA LEVMODE Glitch-FreeTM Glitch-FreeTM IDTF1912NCGI8 0.8 mm height package Green Tape & Reel Omit IDT prefix RF product Line
Glitch-FreeTM, Digital Step Attenuator 2 Rev 1, May 2017 IDTF1912NCGI Datasheet ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units VDD to GND VDD -0.3 +5.5 V DATA, LE, CLK, D[5:0] VLogic -0.3 Min (VDD-0.3, 3.6) V RF1, RF2 VRF -0.3 +0.3 V Maximum Input Power applied to RF1 or RF2 (>100 MHz) PRF +34 dBm Operating Case Temperature +105 °C Maximum Junction Temperature TJmax +140 °C Junction Temperature Tjmax 140 °C Continuous Power Dissipation 1.5 W Storage Temperature Range Tst -65 150 °C Lead Temperature (soldering, 10s) 260 °C Electrostatic Discharge – HBM (JEDEC/ESDA JS-001-2012) VESDHBM 2000 (Class 2) Volts ESD Voltage – CDM (Per JESD22-C101F) VESDCDM 500 (Class C2) Volts Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD. Please use proper ESD precautions when handling to avoid damage or loss of performance. PACKAGE THERMAL AND MOISTURE CHARACTERISTICS θJA (Junction – Ambient) 50 °C/W θJC (Junction – Case) [The Case is defined as the exposed paddle] 3 °C/W Moisture Sensitivity Rating (Per J-STD-020) MSL1
Glitch-FreeTM, Digital Step Attenuator 3 Rev 1, May 2017 IDTF1912NCGI Datasheet F1912 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Min Typ Max Units Supply Voltage(s) VDD 3 5.25 V Frequency Range FRF 1 4000 MHz Operating Temperature Range TCASE Exposed Paddle -40 105 °C RF CW Input Power PCW RF1 or RF2 See Figure 1 dBm Source Impedance ZSource Single Ended 50 Ω Load Impedance ZLoad Single Ended 50 Ω Figure 1 Maximum Continuous Operating RF input power versus Input Frequency Max CW PIN (dBm) Frequency (MHz)
Glitch-FreeTM, Digital Step Attenuator 4 Rev 1, May 2017 IDTF1912NCGI Datasheet F1912 SPECIFICATION Specifications apply at VDD = +3.3 V, TCASE = +25 °C, FRF = 2000 MHz, Pin = 0 dBm, Serial Mode (Vmode > VIH), Zsource = ZLoad = 50 Ω unless otherwise noted. EvKit losses are de-embedded. Parameter Symbol Conditions Min Typ Max Units Logic Input High VIH All Control Pins VDD > 3.9 V 1.17 3.6 V 3.0 ≤ VDD ≤ 3.9 V 1.17 VDD-0.3 V Logic Input Low VIL All Control Pins 0.63 V Logic Current IIH, IIL All Control Pins -35 +35 μA Supply Current IDD VDD = 3.3 V 550 8301 μA VDD = 5.0 V 620 900 RF1 Return Loss S11 18 dB RF2 Return Loss S22 18 dB Attenuation Step LSB Least Significant Bit 0.5 dB Insertion Loss (Minimum Attenuation) AMIN D[5:0]=[000000] (IL State) 1.4 2.0 dB Insertion Loss (Maximum Attenuation) AMAX D[5:0]=[111111]=31.5 dB 322 33.0 dB Step Error DNL 0.10 dB Absolute Error INL D[5:0]=[100111]= 19.5 dB -0.7 +0.5 dB Insertion Phase Delta ΦΔ At 2 GHz 27 degrees At 4 GHz 55 Input IP3 IIP3 PIN = +10 dBm/tone, Tone Spacing = 50 MHz Attn = 0.0 dB, RFin = RF1 60 64.0 dBm Attn = 0.0 dB, RFin = RF2 56 60.5 Attn =15.5 dB, RFin = RF1 56 61.0 Attn =15.5 dB, RFin = RF2 57 61.5 Attn = 0.00 dB, RFin = RF1 PIN = +22 dBm per tone
1 MHz Tone Separation
FRF = 0.7 GHz 60 62.5 FRF = 1.8 GHz 58 61.5 FRF = 2.2 GHz 58 61.0 FRF = 2.6 GHz 57 60.5 Input IP2 IIP2 PIN = +12dBm/tone, VDD=5.0V F1=945 MHz, F2= 949 MHz F1+F2 = 1894 MHz RFIN= RF1 110 dBm 0.1dB Compression3 P0.1 D[5:0] = [000000] = 0 dB 31 dBm Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Note 3: The input 0.1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. Note 4: Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz. Note 5: Speeds are measured after SPI programming is completed (data latched with LE = HIGH).
Glitch-FreeTM, Digital Step Attenuator 5 Rev 1, May 2017 IDTF1912NCGI Datasheet F1912 SPECIFICATION (CONTINUED) Specifications apply at VDD = +3.3 V, TCASE = +25 °C, FRF = 2000 MHz, Pin = 0 dBm, Serial Mode (Vmode > VIH), Zsource = ZLoad = 50 Ω unless otherwise noted. EvKit losses are de-embedded. Parameter Symbol Conditions Min Typ Max Units MSB Step Time TLSB Start LE rising edge > VIH End ±0.10 dB Pout settling for 15.5 dB to 16.0 dB transition 500 ns Maximum spurious level on any RF port4 SpurMAX -140 dBm Maximum Switching Frequency SWFREQ 25 kHz DSA Settling time SET Max to Min Attenuation to settle to within 0.5 dB of final value 0.9 s Min to Max Attenuation to settle to within 0.5 dB of final value 1.8 Control Interface SPIBIT 6 bit Serial Clock Speed SPICLK 25 MHz Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Note 3: The input 0.1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. Note 4: Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz. Note 5: Speeds are measured after SPI programming is completed (data latched with LE = HIGH).
Glitch-FreeTM, Digital Step Attenuator 6 Rev 1, May 2017 IDTF1912NCGI Datasheet PROGRAMMING OPTIONS F1912 can be programmed using either the parallel or serial interface which is selectable via VMODE (pin 13). Serial mode is selected by floating VMODE or pulling it to a voltage logic high (greater than VIH) and parallel mode is selected by setting VMODE to logic low (less than VIL). SERIAL CONTROL MODE F1912 Serial mode is selected by floating VMODE (pin 13) or pulling it to a voltage > VIH. The serial interface is a 6 bit shift register to shift in the data MSB (D5) first. When serial programming is used, all the parallel control input pins (1, 15, 16, 17, 19, 20) must be grounded. Table 1 - 6 Bit SPI Word Sequence D5 Attenuation 16 dB Control Bit D4 Attenuator 8 dB Control Bit D3 Attenuator 4 dB Control Bit D2 Attenuator 2 dB Control Bit D1 Attenuator 1 dB Control Bit D0 Attenuator 0.5 dB Control Bit Table 2 - Truth Table for Serial Control Word (MSB) D4 D3 D2 D1 D0 (LSB) Attenuation (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5 Serial Mode REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue) With serial control, the F1912 can be programmed via the serial port on the rising edge of Latch Enable (LE) which loads the last 6 DATA line bits [formatted MSB (D5) first] resident in the SHIFT register followed by the next 5 bits.
Glitch-FreeTM, Digital Step Attenuator 7 Rev 1, May 2017 IDTF1912NCGI Datasheet Figure 2 - Serial Register Timing Diagram Note - When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the shift register which minimizes noise. It is recommended that Latch enable be left high when the device is not being programmed. Table 3 - Serial Mode Timing Table Interval Symbol Description Min Spec Max Spec Units tmc Parallel to Serial Setup Time - From rising edge of VMODE to rising edge of CLK for D5 100 ns tds Clock high pulse width 10 ns tcls LE Setup Time - From the rising edge of CLK pulse for D0 to LE rising edge minus half the clock period. 10 ns tlew LE pulse width 30 ns tdsc Data Setup Time - From the starting edge of Data bit to rising edge of CLK 10 ns Tdht Data Hold Time - From rising edge of CLK to falling edge of the Data bit. 10 ns
Glitch-FreeTM, Digital Step Attenuator 8 Rev 1, May 2017 IDTF1912NCGI Datasheet Serial Mode Default Startup Condition: When the device is first powered up it will default to the Maximum Attenuation of 31.5 dB independent of the VMODE and parallel pin [D5:D0] conditions. Table 4 - Default Control Word for the Serial Mode (MSB) D4 D3 D2 D1 D0 (LSB) Attenuation (dB) 1 1 1 1 1 1 31.5 PARALLEL CONTROL MODE For the F1912 the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode. Direct Parallel Mode: Direct Parallel Mode is selected when VMODE (pin 13) is less than VIL and LE (pin 5) is greater than VIH. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17, 19, 20]. Use direct parallel mode for the fastest settling time. Latched Parallel Mode: Latched Parallel Mode is selected when VMODE is less than VIL and LE (pin 5) is toggled from less than VIL to greater than VIH. To utilize Latched Parallel Mode: Set LE < VIL Adjust pins [pins 1, 15, 16, 17, 19, 20] to the desired attenuation setting. (Note the device will not react to these pins while LE < VIL.) Pull LE > VIH. The device will then transition to the attenuation settings reflected by pins D5 – D0. Latched Parallel Mode implies a default state for when the device is first powered up with VMODE < VIL and LE < VIL. In this case the default setting is MAXIMUM Attenuation. Table 5 - Truth Table for the Parallel Control Word D5 D4 D3 D2 D1 D0 Attenuation (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5
Glitch-FreeTM, Digital Step Attenuator 9 Rev 1, May 2017 IDTF1912NCGI Datasheet Figure 3 - Latched Parallel Mode Timing Diagram Table 6 - Latched Parallel Mode Timing Interval Symbol Description Min Spec Max Spec Units tsps Serial to Parallel Mode Setup Time 100 ns tpdh Parallel Data Hold Time 10 ns tpds LE minimum pulse width 10 ns tle Parallel Data Setup Time 10 ns
Glitch-FreeTM, Digital Step Attenuator 10 Rev 1, May 2017 IDTF1912NCGI Datasheet TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply. VDD = +3.30 V TCASE = +25 °C FRF = 2 GHz PIN = 0 dBm for single tone measurements PIN = +10 dBm/tone for multi-tone measurements Tone Spacing = 50 MHz EVKit connector and board losses are de-embedded
Glitch-FreeTM, Digital Step Attenuator 11 Rev 1, May 2017 IDTF1912NCGI Datasheet TYPICAL OPERATING CONDITIONS (- 1 -) Insertion Loss vs Frequency RF1 (Input) Return Loss vs Frequency [All States] RF2 (Output) Return Loss vs Frequency [All States] Insertion Loss vs Attenuation State RF1 (Input) Return Loss vs Attenuation State RF2 (Output) Return Loss vs Attenuation State -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Insertion Loss (dB) Frequency (GHz) -30 -25 -20 -15 -10 Match (dB) Frequency (GHz) -30 -25 -20 -15 -10 Match (dB) Frequency (GHz) -35 -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Insertion Loss (dB) Attenuator State (dB) -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match (dB) Attenuation (dB) 0.5 GHz 1.0 GHz 1.5 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 4.0 GHz -30 -25 -20 -15 -10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Match (dB) Attenuation (dB) 0.5 GHz 1.0 GHz 1.5 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 4.0 GHz
Glitch-FreeTM, Digital Step Attenuator 12 Rev 1, May 2017 IDTF1912NCGI Datasheet TYPICAL OPERATING CONDITIONS (- 2 -) Relative Insertion Phase vs Frequency Worst Case Absolute Accuracy vs Frequency Worst Case Step Accuracy vs Frequency Relative Insertion Phase vs Attenuation Absolute Accuracy vs Attenuation Step Accuracy vs Attenuation Relative Phase (degrees) Frequency (GHz) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 Error (dB) Frequency (GHz) -40 C / Min -40 C / Max +25 C / Min +25 C / Max +105 C / Min +105 C / Max -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 Error (dB) Frequency (GHz) -40 C / Min -40 C / Max +25 C / Min +25 C / Max +105 C / Min +105 C / Max 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Phase (degrees) Attenuation (dB) 0.5 GHz 1.0 GHz 1.5 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 4.0 GHz -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 0.5 GHz 1.0 GHz 1.5 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 4.0 GHz -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Error (dB) Attenuation (dB) 0.5 GHz 1.0 GHz 1.5 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 4.0 GHz
Glitch-FreeTM, Digital Step Attenuator 13 Rev 1, May 2017 IDTF1912NCGI Datasheet TYPICAL OPERATING CONDITIONS (- 3 -) Compression at 0 dB and 2 GHz Compression at 15.5 dB and 2 GHz Compression at 31.5 dB and 2 GHz Input IP3 - 0 dB, +22 dBm, 1 MHz Tone Delta, RF1 Input IP3 (Low Side) vs attenuation at 2GHz Input IP3 (High Side) vs attenuation at 2GHz -0.3 -0.2 -0.1 0.0 0.1 0.2 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) -40 C +25 C +105 C -0.3 -0.2 -0.1 0.0 0.1 0.2 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) -40 C +25 C +105 C -0.3 -0.2 -0.1 0.0 0.1 0.2 18 20 22 24 26 28 30 32 34 Compression (dB) Input Power (dBm) -40 C +25 C +105 C Input IP3 (dBm) Frequency (GHz) IIP3-LS IIP3-HS 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Input IP3 (dBm) Attenuation (dB) -40 C / Pin = 10 dBm/Tone -40 C / Pin = 15 dBm/Tone +25 C / Pin = 10 dBm/Tone +25 C / Pin = 15 dBm/Tone +105 C / Pin = 10 dBm/Tone +105 C / Pin = 15 dBm/Tone 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Input IP3 (dBm) Attenuation (dB) -40 C / Pin = 10 dBm/Tone -40 C / Pin = 15 dBm/Tone +25 C / Pin = 10 dBm/Tone +25 C / Pin = 15 dBm/Tone +105 C / Pin = 10 dBm/Tone +105 C / Pin = 15 dBm/Tone
Glitch-FreeTM, Digital Step Attenuator 14 Rev 1, May 2017 IDTF1912NCGI Datasheet PACKAGE DRAWING (4 mm x 4 mm 20-pin TQFN), NCG20
Glitch-FreeTM, Digital Step Attenuator 15 Rev 1, May 2017 IDTF1912NCGI Datasheet LAND PATTERN DIMENSION
Glitch-FreeTM, Digital Step Attenuator 16 Rev 1, May 2017 IDTF1912NCGI Datasheet PIN DIAGRAM CLK DATA GND VMODE GND LE GND *RF2*RF1 VDD NC GND 4 12 6 7 98 10 161719 1820 NC NC Exposed Pad TOP View (looking through the top of the package) * Device is RF Bi-Directional
Glitch-FreeTM, Digital Step Attenuator 17 Rev 1, May 2017 IDTF1912NCGI Datasheet PIN DESCRIPTION PIN NAME FUNCTION 1 D5 16 dB Attenuation Control Bit. Pull high for 16 dB ATTN. 2 RF1 Device RF input or output (bi-directional). Internally DC blocked. 3 DATA Serial interface Data Input. 4 CLK Serial interface Clock Input. 5 LE Serial interface Latch Enable Input. Internal pullup (100K ohm). 6 VDD Power supply pin. 7 NC Internally unconnected. 8 NC Internally unconnected. 9 NC Internally unconnected. 10 GND Connect to Ground. This pin is internally connected to the exposed paddle. 11 GND Connect to Ground. This pin is internally connected to the exposed paddle. 12 GND Connect to Ground. This pin is internally unconnected. 13 VMODE Pull high for serial control mode. Ground for parallel control mode. 14 RF2 Device RF input or output (bi-directional). Internally DC blocked. 15 D4 8 dB Attenuation Control Bit. Pull high for 8 dB ATTN. 16 D3 4 dB Attenuation Control Bit. Pull high for 4 dB ATTN. 17 D2 2 dB Attenuation Control Bit. Pull high for 2 dB ATTN. 18 GND Connect to Ground. This pin is internally unconnected. 19 D1 1 dB Attenuation Control Bit. Pull high for 1 dB ATTN. 20 D0 0.5 dB Attenuation Control Bit. Pull high for 0.5 dB ATTN. EP Exposed Paddle Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple via grounds are also required to achieve the specified RF performance.
Glitch-FreeTM, Digital Step Attenuator 18 Rev 1, May 2017 IDTF1912NCGI Datasheet EVKIT PICTURE
Glitch-FreeTM, Digital Step Attenuator 19 Rev 1, May 2017 IDTF1912NCGI Datasheet EVKIT / APPLICATIONS CIRCUIT
Glitch-FreeTM, Digital Step Attenuator 20 Rev 1, May 2017 IDTF1912NCGI Datasheet EVKIT BOM Item # Part Reference QTY DESCRIPTION Mfr. Part # Mfr.
1 C1, C11 2
100nF ±10%, 50V, X7R Ceramic Capacitor (0402) GRM155R71H104K MURATA
2 C2, C12 2 10nF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM155R71H103J MURATA
3 R12, C13, C14 3 0Ω Resistors (0402) ERJ-2GE0R00X PANASONIC
4 R1-R7 7 100Ω ±1%, 1/10W, Resistor (0402) ERJ-2RKF1000X PANASONIC
5 R9, R10, R11 3 3kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF3001X PANASONIC
6 R8, R15, R16, R17 4 10kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1002X PANASONIC
7 R13 1 100KΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1003X PANASONIC
8 R14 1 267KΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF2673X PANASONIC
9 J5, J7 2 CONN HEADER VERT SGL 2 X 1 POS GOLD 961102-6404-AR 3M
10 J8 1 CONN HEADER VERT SGL 4 X 1 POS GOLD 961104-6404-AR 3M
11 J6 1 CONN HEADER VERT SGL 8 X 1 POS GOLD 961108-6404-AR 3M
12 J2, J3, J4 3
Edge Launch SMA (0.250 inch pitch ground, round) 142-0711-821 Emerson Johnson
13 U1 1 SWITCH 8 POSITION DIP SWITCH KAT1108E E-Switch
14 U2 1 DSA F1912Z IDT
15 1 Printed Circuit Board (Rev 01) F1953S Evkit Rev 01 IDT
16 Bill Of Material (Rev 01)
Date Code [YWW] (Week 5 of 2015) ASM Test Step Assembler Code
Glitch-FreeTM, Digital Step Attenuator 21 Rev 1, May 2017 IDTF1912NCGI Datasheet APPLICATIONS INFORMATION F1912 Digital Pin Voltage & Resistance Values (pins not connected) The following table lists the resistance between various pins and ground when no DC power is applied. When the device is powered up with +5 Volts DC these same pins to should have the measured voltage to ground. Pin Name DC voltage (volts) Resistance (ohms) 13 VMODE 2.5V 100 kΩ pullup resistor to internally regulated 2.5 V 3, 4, 5 DATA, CLK, LE 2.5V 100 kΩ pullup resistor to internally regulated 2.5 V
Glitch-FreeTM, Digital Step Attenuator 22 Rev 1, May 2017 IDTF1912NCGI Datasheet
Revision History
Revision Revision Date Description of Change 1 2017-May-26 Corrected pin label on Page 16. O 2015-June-06 Initial release of the datasheet Corporate Headquarters
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San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are d etermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of a ny kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT o r any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signific antly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Fo r datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.