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Technical content
Features
RF range: 400MHz to 3800MHz LO range: 400MHz to 3600MHz IF Range: 50MHz to 600MHz 4 Gain Settings; 11dB, 8dB, 5dB, 2dB 2 bit gain step control Ideal for Multi-Carrier Systems +35dBm OIP3 Low Noise Figure at any gain setting via Renesas’ FlatNoiseTM technology Z = 200Ω IF balanced, 50Ω RF, 50Ω LO single-ended All internally matched. Single BOM for all RF, LO and IF frequencies 4 x 4 mm, 24-VFQFPN package Independent Path Standby mode 75 nsec settling for gain adjustment VCC = 3.3V, 462mW, 373mW (low power mode) Band Performance Summary RF Frequency (MHz) 900 1900 2600 3500 Gain (dB, max G11 setting) 11.0 10.8 10.3 9.0 Gain (dB, min G2 setting) 2.5 2.3 1.8 0.5 NF at max gain (dB) 8.9 8.7 10.0 10.9 IIP3 at min gain (dBm) 28 27 29 30 OIP3 at G8 (dBm) 37 34 35 35 IP1dB at min gain (dBm) 13.6 14.7 14.6 15.8 Pdiss (mW) 442 462 485 520
Figure 2. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View
Table 1. F1792 Pin Descriptions 1 RF_IN RF input. Matched to 50 ohms. DO NOT apply DC to this pin. 2 RF_IN_rtn RF input transformer ground return. Ground this pin. 15 LO_IN_rtn LO input transformer ground return. Ground this pin. 16 LO_IN Local Oscillator (LO) input. Matched to 50 ohms. DO NOT apply DC to this pin.
17 LO_ADJ Connect zero ohm resistor to ground here for best performance
Table 2. Absolute Maximum Ratings Table 3. Recommended Operating Conditions
© 2022 Renesas Electronics Corporation 5 February 9, 2022
Electrical Characteristics
Table 4. F1792 Specification (General) all gain settings unless otherwise stated, STBY = LOW. EVkit IF transformer losses are de-embedded unless otherwise noted. NOTE 1: Items in min/max columns in bold italics are Guaranteed by Test. NOTE 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic.
Table 5. F1792 Specification (Low Band) NOTE 1: Items in min/max columns in bold italics are confirmed by Test. NOTE 2: Items in min/max columns that are not bold/italics are confirmed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic. NOTE 5: Max limit at Tcase = +105°C.
Table 6. F1792 Specification (Low Band) Continued NOTE 1: Items in min/max columns in bold italics are confirmed by Test. NOTE 2: Items in min/max columns that are not bold/italics are confirmed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic. NOTE 4: Specification limits over voltage and temperature. NOTE 5: Max limit at Tcase = +105°C.
Table 7. F1792 Specification (Mid Band) NOTE 1: Items in min/max columns in bold italics are confirmed by Test. NOTE 2: Items in min/max columns that are not bold/italics are confirmed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic. NOTE 4: Specification limits over voltage and temperature. NOTE 5: Max limit at Tcase = +105°C.
Table 8. F1792 Specification (Mid Band) Continued NOTE 1: Items in min/max columns in bold italics are confirmed by Test. NOTE 2: Items in min/max columns that are not bold/italics are confirmed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic. NOTE 4: Specification limits over voltage and temperature. NOTE 5: Max limit at Tcase = +105°C.
Table 9. F1792 Specification (High Band) NOTE 1: Items in min/max columns in bold italics are confirmed by Test. NOTE 2: Items in min/max columns that are not bold/italics are confirmed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic. NOTE 4: Specification limits over voltage and temperature. NOTE 5: Max limit at Tcase = +105°C.
Table 10. F1792 Specification (High Band) Continued (-1-) NOTE 1: Items in min/max columns in bold italics are confirmed by Test. NOTE 2: Items in min/max columns that are not bold/italics are confirmed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic. NOTE 4: Specification limits over voltage and temperature. NOTE 5: Max limit at Tcase = +105°C.
Table 11. F1792 Specification (High Band) Continued (-2-) NOTE 1: Items in min/max columns in bold italics are confirmed by Test. NOTE 2: Items in min/max columns that are not bold/italics are confirmed by Design Characterization. NOTE 3: JEDEC 3.3V and JEDEC 1.8V logic. NOTE 4: Specification limits over voltage and temperature. NOTE 5: Max limit at Tcase = +105°C.
Table 12. Package Thermal and Moisture Characteristics
© 2022 Renesas Electronics Corporation 14 February 9, 2022 NxM (dBc, Gset=5 dB, LO=1700 MHz, IF=200 MHz, RFfund=0 dBm at 1900 MHz, RFspur(MHz)=(N*LO(MHz)+IF(MHz))/M ) N (LO) 1 2 3 4 5 6 7 8 9 10 M (RF) NxM (dBc, Gset=5 dB, LO=1700 MHz, IF=200 MHz, RFfund=0 dBm at 1500 MHz, RFspur(MHz)=(N*LO(MHz)+IF(MHz))/M ) N (LO) 1 2 3 4 5 6 7 8 9 10 M (RF)
© 2022 Renesas Electronics Corporation 26 February 9, 2022 Applications Information EvKit Picture
© 2022 Renesas Electronics Corporation 27 February 9, 2022 EvKit / Applications Circuit R3 R4 VCC1 VCC2 VCC3 F1792 RF_IN GND NC NC GND NC Vcc LO_ADJ LO_IN GND NC IFRefBias Vcc IF_BiasA IF_OUT+ IF_OUT- Vcc STBY NC NC Gain_Sel2 Vcc NC Gain_Sel1 PAD VCC4 VCC3 TP11 TP21 VCC5 TP31 4x2 Header C3C4 G_SET1 G_SET2 SD_2 SD_1 VCC VCC1 C7 C8 C11C12 L1 L2 VCC5 Balun Center Tap 4 3 6 1 Balun Center Tap C5C6 C9C10 VCC4 G_SET1 G_SET2 C13 C14 R11 R12 C21 SD_2 R13 C15 SD_1R14 C16 L3 L4 R10 C20 C19 R15 VCC2 C18 C17 R16 VCC TP41 VCC TP51 C22C23 R1 R2 Pin 20 must be connected to Vcc for proper operation
© 2022 Renesas Electronics Corporation 28 February 9, 2022 EvKit BOM Part Reference QTY Description Mfr. Part # Mfr. C3, C7, C9, C11, C22 6 1000pF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H102J Murata C4, C8, C10, C12, C19, C20, C23 10 10,000pF ±10%, 50V, X7R Ceramic Capacitor (0603) GRM188R71H103KA01D Murata C21 1 1000pF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H102J Murata C1, 2 39pF ±5%. 5V, C0G Ceramic Capacitor (0402) GRM1555C1H390J Murata R1, R3-R5, R8, R9, R12, R13, R14, R15 13 0 Ohm, 1/10W, Resistor (0402) ERJ-2GE0R00X Panasonic R16 2 390 Ohm ±1%, 1/10W, Resistor (0402) ERJ-2RKF3900X Panasonic R10 1 1.74 kOhm ±1%, 1/10W, Resistor (0402) ERJ-2RKF1741X Panasonic L3, L4 4 390nH ±5%, 0.29 A, Ceramic Chip Inductor (0805) 0805CS-391XJL Coilcraft T2 2 4:1 Center Tap Balun TC4-6TG2+ Mini-Circuits J7 1 CONN HEADER VERT DBL 4POS GOLD 67997-108HLF FCI J1, J4, J9 3 Edge Launch SMA Connector (Big) 142-0701-851 Emerson Johnson J8 1 Edge Launch SMA Connector (Small) 142-0711-821 Emerson Johnson U1 1 RF Dual Wideband Gain-Settable Downconverting Mixer 4x4 TQFN24 F1192NLGI Renesas
1 Printed Circuit Board F1192 EVKIT REV 01 Renesas
A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V/20µ s. In addition, all control pins should remain at 0V ( ±0.3V) while the supply voltage ramps or while it returns to zero.
© 2022 Renesas Electronics Corporation 29 February 9, 2022 Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., provisions for an R- C circuit at the input of each control pin is recommended. This applies to pins 11, 12, and 19 as shown below. Gain Select F1792 provides a gain select feature requiring 2 pins for logic control. The following table summarizes the required pin logic to achieve the desired gain setting. Internal pull down resistors are included requiring no control to set both channels to maximum gain. Desired Power Gain (dB) Gain Select1 (Pin 11) # Gain Select2 (Pin 12) 11 0 0 8 0 1 5 1 0 2 1 1 Default Start-up Upon start-up, the device gain will be whatever the gain select pins are set for as defined in the table above. Gain_Select1 Gain_Select2 192021222324 STBY 7 8 9 10 11 12 IDTF1792 Exposed pad (GND) 5Kohm 2pf 5Kohm 2pf 5Kohm 2pf
© 2022 Renesas Electronics Corporation 30 February 9, 2022 Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revis ion of this document.
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F1792NLGI 4 x 4 x 0.9 mm 24-VFQFPN MSL1 Tray -40° to +85°C F1792NLGI8 4 x 4 x 0.9 mm 24-VFQFPN MSL1 Tape and Reel -40° to +85°C Marking Diagram Q40A017Y F1792GI YD1536G Part Number Date Code [YYWW] (Week 36 of 2015) Lot Code ASM Test Step Assembler Code
Revision History
Revision Date Description of Change February 9, 2022 Rebranded to Renesas. December 13, 2019 Corrected a typo in logic current unit in Table 4. Updated the package outline drawings; however, no mechanical changes April 5, 2016 First release (Rev O) of the F1792 datasheet.
© Integrated Device Technology, Inc.
© Integrated Device Technology, Inc. Package Revision HistoryRev No.Date CreatedDescriptionRev 02New Format, Recalculate Land Pattern Change QFN to VFQFPNSept 13, 2018Rev 01Add Chamfer on EpadSept 9, 2016
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