F159V

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Features

 Independent dual-path operation  RF output frequency: 450MHz to 2800MHz  18.3dB typical maximum gain (no attenuation)  +31dBm OIP3 (no attenuation)  +14dBm Output P1dB (no attenuation)  13dB NF corresponds to -142.5dBm/Hz output noise floor (no attenuation)  Output noise floor -152.3dBm/Hz (VVA=14dB, DSA=1dB)  Channel Isolation: 47dB  DSA with 31dB total gain range in 1dB steps  Multiple VVAs with 32dB gain range controlled by on-chip SPI controlled 11-bit DAC  Variable Gain amplifier (VGA) is comprised of DSAs, VVAs, and a fixed-gain amplifier  I lead Q by 90 degrees for high side LO injection  Supports ZIF or CIF architectures  Common-mode voltage range: +0.1V to +0.8V  Integer-N and Fractional-N Synthesizer  Direct 110Ω differential driven from I/Q DAC  50Ω single-ended RF output impedance  Internal or external LO select  +3.3V supply voltage at 685mA (LO_Out not turned on)  Specified Case Temperature; -20°C to +115°C  10mm x 10mm, 68-pin QFN package Block Diagram Figure 1. Block Diagram

© 2020 Renesas Electronics Corporation 3 May 15, 2020 F159V Datasheet

© 2020 Renesas Electronics Corporation 4 May 15, 2020 F159V Datasheet

Figure 2. Pin Assignments for 10mm x 10mm x 0.9mm QFN Package – Top View

Table 1. Pin Descriptions close to this pin as possible. 2 CH0_RDIST_AMP Channel 0 VGA amplifier distortion bias. 3 CH0_RBIAS Channel 0 VGA amplifier current bias. 5 GND Internally grounded. This pin must be grounded as close to the device as possible. 6 GND Internally grounded. This pin must be grounded as close to the device as possible. 7 CH0_RFOUT Channel 0 RF output. Must be AC-coupled. 8 GND Internally grounded. This pin must be grounded as close to the device as possible. 9 GND Internally grounded. This pin must be grounded as close to the device as possible. 10 GND Internally grounded. This pin must be grounded as close to the device as possible. 11 CH1_RFOUT Channel 1 RF output. Must be AC-coupled. 12 GND Internally grounded. This pin must be grounded as close to the device as possible. 13 GND Internally grounded. This pin must be grounded as close to the device as possible. 15 CH1_RBIAS Channel 1 VGA amplifier current bias. 16 CH1_RDIST_AMP Channel 1 VGA amplifier distortion bias. close to this pin as possible. 19 CH1_MODCOUPLE Channel 1 modulator coupled output.

21 CH1_RDIST_MOD Channel 1 modulator amplifier bias

22 CH1_QBB+

Channel 1 Quadrature differential baseband input. Internally matched to 110Ω.

23 CH1_QBB-

25 CH1_IBB+

Channel 1 In-Phase differential baseband input. Internally matched to 110Ω.

26 CH1_IBB-

Table 2. Pin Descriptions (Cont.) 27 CH1_MODEN Enable or disable Channel 1 modulator output. Logic LOW will enable the output (normal operation). Logic HIGH or NC will disable the output (power down). 30 GND_LO Internally grounded. This pin must be grounded as close to the device as possible.

31 LO_IN+

Local oscillator (LO) 100Ω differential input. Pins must be AC-coupled.

32 LO_IN-

33 LO_OUT+

Local oscillator (LO) 100Ω differential output. Pins must be AC-coupled.

34 LO_OUT-

35 Vdd_LO Power supply pin. Place bypass capacitors to GND as close as possible to the pin. 36 VCOM Requires a capacitor from this pin to Vdd_VCO or to VREF_VCO for noise reduction. 37 Vdd_VCO Power Supply Voltage. Place bypass capacitors to GND as close as possible to the pin. voltage 2.8V when part is turned on. 39 VTUNE Voltage control input to tune the VCO. 40 GND_VCO Internally grounded. This pin must be grounded as close to the device as possible. output of the loop filter is connected to VTUNE to drive the internal VCO. 42 GND_CP Internally grounded. This pin must be grounded as close to the device as possible. 43 DNC Do not connect anything to this pin. capacitors to the ground plane as close to this pin as possible. 45 GND_REF Internally grounded. This pin must be grounded as close to the device as possible.

47 REF_IN

48 Vdd_REF Power supply for reference path. Place bypass capacitors to GND as close as possible to the pin. 49 RESET HIGH: Reset PLL. Resets all settings to default. 50 GND_SPI Internally grounded. This pin must be grounded as close to the device as possible. 51 Vdd_SPI SPI power supply pin. Place bypass capacitors to GND as close to this pin as possible. 52 SPI_CSN Serial chip Select. CSN pin can be pulled up to Vdd and down to GND. 53 SPI_CLK Serial Clock Input. 54 SPI_DIO Data write/read of 3-wire serial interface.

Table 3. Pin Descriptions (Cont.) 55 SPI_DO Data read of 4-wire serial interface. 56 LO_LD LO Lock Detect output. Logic HIGH indicates PLL lock. Logic LOW indicates loss of PLL lock. 57 Vdd_DAC Power supply for DACs. Place bypass capacitors to GND as close as possible to the pin.

60 CH0_IBB-

Channel 0 In-Phase differential baseband input. Internally matched to 110Ω.

61 CH0_IBB+

63 CH0_QBB-

Channel 0 Quadrature differential baseband input. Internally matched to 110Ω.

64 CH0_QBB+

65 CH0_RDIST_MOD Channel 0 modulator amplifier bias. 67 CH0_MODCOUPLE Channel 0 modulator coupled output. 68 CH0_AMPEN Enable or disable Channel 0 modulator output. Logic LOW will enable the output (normal operation). Logic HIGH or NC will disable the output (power down). multiple ground vias are also required to achieve the noted RF performance.

The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Table 4. Absolute Maximum Ratings

1. Recommended Operating Conditions

Table 5. Recommended Operating Conditions warms up. Device functions normally but not specified for temperatures below -20°C. [b] Expect a slight performance degradation from 600MHz to 450MHz.

1. Electrical Characteristics

Table 6. General Characteristics parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization. [b] Values valid for CP current set to 0.94mA, LO_SW_OUT = 0dBm.

Table 7. Electrical Characteristics parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization.

Table 8. Electrical Characteristics (Cont.) parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization.

Table 9. Electrical Characteristics – Frequency Synthesizer parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. are de-embedded, unless otherwise noted. columns that are not shown in bold italics are guaranteed by design characterization. [b] When input reference frequency is between 10MHz and 20MHz, the reference doubler must be turned on.

Table 10. Electrical Characteristics – Frequency Synthesizer (Cont.) parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. losses are de-embedded, unless otherwise noted. Table 11. Electrical Characteristics – Signal Path Cascaded Performance parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization.

Table 12. Electrical Characteristics – Signal Path Cascaded Noise Figure Performance parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization.

Table 13. Electrical Characteristics – Signal Path Cascaded IP3 Performance parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization.

Table 14. Electrical Characteristics – Signal Path Cascaded IP3 Performance (Cont.) parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.

Table 15. Electrical Characteristics – Signal Path Cascaded P1dB Performance parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization.

Table 16. Electrical Characteristics – Signal Path Cascaded General Performance parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. columns that are not shown in bold italics are guaranteed by design characterization. turned off. Measure the difference in the RF power between CH0_RFOUT (CH1_RFOUT) and CH1_RFOUT (CH0_RFOUT). This difference is the channel isolation.

Table 17. Package Thermal Characteristics Junction to Case Thermal Resistance.

1. Typical Operating Conditions (TOC)

frequency generator. There are two modulators per device. digital step attenuator (DSA) and voltage variable attenuator (VVA). There are two variable gain amplifiers (VGA) per device. Controlling the F159V is done using fifty 8-bit registers. registers to generate the required frequency. The registers are described in the following section. Figure 91. Phase Lock Loop (PLL) Schematic

Each of the values is a 16-bit word that requires the programming of two registers. Table 18. Feedback Divider Values 16-bit word. The value is limited between 7 and 65,535. NFrac_0 is the lower 8 bits. NFrac_1 is the upper 8 bits. a 16-bit word. The value must be between 2 and 65,535. The Fractional-N PLL can be put into an integer N mode. This is accomplished by setting the fractional value, NFrac, to 0. a sine or square wave. This signal can be translated for various performance enhancements. mode, the upper frequency is limited to 105MHz.

Table 19. Reference Frequency Divider Values The default value is 1 (doubler is on). for 1. This is the first four bits of the word. The default value is 1 = 0000b. Table 20. Charge Pump the charge pump. This is the first four bits of the word. The default value is 0.94mA = 0010b. 849 for a general description for a loop filter design. frequency of the VCO can be divided by up to a factor of 8 using a 3-bit control word. frequency by a factor of 2. This divider can be used on either the internal signal or the external frequency supplied. quadrature divider must be disabled.

Table 21. LO Frequency Divider Values This is a 3-bit control word that divides the VCO signal. This is first three bits of the word. The default value is 1 = 001b (divide by 2). The default value is to divide by 1. Table 22. VCO setting recalibrate itself. The default value is to not relock (0b). and then the bit is self-clearing (reset to 0b). then the PLL is recalibrated with the default value of 0b. the PLL will allow auto-recalibration mode.

39 Band Select Divider BandSelect_0

BandSelect_0 is the lower 8 bits. BandSelect_1 has the upper 4 bits.

Table 23. LO Signal Power The default value is JEDEC 1.8V logic = 0b.

the power can be modified to adjust the performance. Table 24. LO Signal Power from -2dBm to +4dBm in 2dB steps. The default value is 0dBm = 01b. from -2dBm to +4dBm in 2dB steps. The default value is 0dBm = 01b. adding 9.6mA of current to the pre-driver. The default value is no extra power= 0b. Table 25. LO Signal Routing switch to route the LO from the PLL to the output LO port. The default has switch enabled (turned on). DAC. The default has this enabled (turned on). is the control for the switch shown in Figure 92.

input. There is a coupled output of the RF signal before the variable gain amplifier. There is no control of the modulator. Figure 94. Generic DAC Interface LPF: Differential Low Pass Filter for unwanted harmonics. can be set with a 12-bit word. Minimum attenuation is at the maximum digital word of 2047. Table 26. Digital Step Attenuator Setting for the DSA Channel 0. This is the first 5 bits of the word. The default value is 0dB = 0 0000b. for the DSA Channel 1. This is the first 5 bits of the word. The default value is 0dB = 0 0000b.

Table 27. Digital Step Attenuator Truth Table Table 28. Voltage Variable Attenuator Setting setting for the VVA in Channel 0. setting for the VVA in Channel 1. DAC1_1 has the upper 4 bits.  The reference frequency doubler is enabled.  The PLL is set for integer mode with a divider of 63.  The LO signal used for the modulator is set for half the frequency of the PLL frequency and 0dBm.  The LO is set for the 1.50GHz to 2.00GHz range.  The internal LO signal is used for the modulator.  Digital step attenuators are set for the minimum attenuation (0dB).  Voltage variable attenuators are set for the minimum attenuation (state 2047) and the DAC used to control them is turned on.

Table 29. Amplifier Enable Pin Truth Table LOW Amplifier in channel path has the DC power turned on. HIGH or No Connect Amplifier in channel path has the DC power turned off. Table 30. Coupled Modulator Output Enable Pin Truth Table LOW Coupled modulator output path has the DC power turned on. HIGH or No Connect Coupled modulator output path has the DC power turned off. Table 31. RESET Pin Truth Table RESET (pin 49) LOW Resets all registers to the default states. HIGH or No Connect Normal operation. Figure 95. Serial Timing Diagram Note: Falling edge of the last clock period is required in order to properly program the SPI.

Figure 96. Serial Timing Diagram for Multiple Bits Table 32. SPI Timing Parameters

parameters that require two registers to fulfill the functionality. Table 33. Register Definition 0 00h R/W 0000_0000b This register configures the Reset and bit definition. 1 01h R/W 0000_0000b This register configures the Single instruction. 2 02h R/W 0000_0000b This register configures the data transfer. 4 04h R 0000_0000b Chip ID – lower 8 bits (total 16 bits). 5 05h R 0000_0000b Chip ID – higher 8 bits (total 16 bits). 7 07h R/W 0000_0000b Unused at this time. 8 08h R/W 0000_0000b Unused at this time. 9 09h R/W 0000_0000b Unused at this time. 10 0Ah R/W 0000_0000b Unused at this time. 11 0Bh R/W 0000_0000b Unused at this time. 12 0Ch R 0010_0110b Vendor ID – lower 8 bits (total of 16 bits). 13 0Dh R 0000_0100b Vendor ID – higher 8 bits (total of 16 bits). 14 0Eh R/W 0000_0000b Unused at this time. 15 0Fh R/W 0000_0000b Unused at this time. 16 10h R/W 0001_0000b 5-bit word to control the Reference Divider and Reference Doubler. 17 11h R/W 0011_1111b FB divider integer part, lower 8 bits (total of 16 bits). Minimum divide ratio is 7. 18 12h R/W 0000_0000b FB divider integer part, higher 8 bits (total of 16-bits). 19 13h R/W 0000_0000b FB divider fractional numerator, lower 8 bits (total of 16 bits). Default = 31,232. 20 14h R/W 0111_1010b FB divider fractional numerator, higher 8 bits (total of 16-bits). 21 15h R/W 1111_1111b FB divider fractional denominator, lower 8 bits (total of 16 bits). Minimum modulus value is 2. 22 16h R/W 1111_1111b FB divider fractional denominator, higher 8 bits (total of 16 bits). 23 17h R/W 0000_0001b 1-bit for the Quadrature Divider, 3-bit for the output divider. 24 18h R/W 0000_0010b Charge pump current setting, 4 bits.

Table 34. Register Definition–(Cont.) additional pre-driver current (output power). 26 1Ah R/W 0001_1100b Set the various LO switch parameters, and if the PLL and DAC are enabled. 27 1Bh R/W 0000_0000b 5-bit word to control the DSA in Channel 0 (1dB LSB). 28 1Ch R/W 0000_0000b 5-bit word to control the DSA in Channel 1 (1dB LSB). 29 1Dh R/W 1111_1111b Lower 8 bits of 11-bit word to control the VVA in Channel 0. 30 1Eh R/W 0000_0111b Higher 3 bits of 11-bit word to control the VVA in Channel 0. 31 1Fh R/W 1111_1111b Lower 8-bits of 11-bit word to control the VVA in Channel 1. 32 20h R/W 0000_0111b Higher 3-bits of 11-bit word to control the VVA in Channel 1. 33 21h R/W 0000_0000b 1 bit for the RF Band, 1 bit for the LO Band. 34 22h R/W 0000_0000b 1 bit for Digital Output Logic. 35 23h R/W 0000_0000b 3 bits for Lock Detect Precision, 2 bits for Lock Detect. 1 bit for Automatic recalibration. 37 25h R/W 0000_0001b 1 bit for Lock Detection. 38 26h R/W 0000_0000b Lower 8 bits of a 12-bit word for the Band Select Divider. 39 27h R/W 0000_0001b Higher 4 bits of a 12-bit word for the Band Select Divider. 40 28h R/W 0000_0000b Reserved for Vendor Use. Use only the default value. 41 29h R/W 0000_0000b Reserved for Vendor Use. Use only the default value. 42 2Ah R/W 0000_0010b Reserved for Vendor Use. Use only the default value. 43 2Bh R/W 1100_1011b Reserved for Vendor Use. Use only the default value. 44 2Ch R/W 0000_0000b Reserved for Vendor Use. Use only the default value. 45 2Dh R/W 0000_0000b Reserved for Vendor Use. Use only the default value. 46 2Eh R N/A Reserved for Vendor Use. Use only the default value. 47 2Fh R N/A Reserved for Vendor Use. Use only the default value. 48 30h R N/A Reserved for Vendor Use. Use only the default value. 49 31h R/W N/A Reserved for Vendor Use. Use only the default value.

Table 35. Register 0: Bit Definition

0 SoftReset 0

Set to logic LOW is for normal operation. state. Registers 0 and 1 are not reset.

1 LSBFirst 0

Defines the bit transmitted first in SPIN transfers between the master and slave. If this bit is set to logic LOW, data is oriented as MSB first. If this bit is set to logic HIGH, data is oriented as LSB first.

2 AddressAscend 0

Defines how the addresses are incremented in streaming SPI mode. If this bit is set to logic LOW, addresses are auto-decremented. If this bit is set to logic HIGH, addresses are auto-incremented.

3 SDO Active 0

Selects the unidirectional or bidirectional data transfer mode for the SDIO pin. 4 SDO Active 0 Must be equal to bit 3 (Mirror image to be independent of MSB or LSB). 5 AddressAscend 0 Must be equal to bit 2 (Mirror image to be independent of MSB or LSB). 6 LSBFirst 0 Must be equal to bit 1 (Mirror image to be independent of MSB or LSB). 7 SoftReset 0 Must be equal to bit 0 (Mirror image to be independent of MSB or LSB). This register is used to determine how data is read back from the device. The default value is 0 = 00h = 0000_0000b. Table 36. Register 1: Bit Definition

5 BufferReadMode 0

Double Buffer. Vendor can choose to design in a secondary buffer for reading. obtained for the active register.

This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b. This register is used to define what type of Chip this is and is READ ONLY. It is 8 bits long. The default value is 1 = 01h = 0000_0001b. Table 37. Register 3: Bit Definition 0 ChipType[0] 1 Bit 0 of the value. 1 ChipType[1] 0 Bit 1 of the value. 2 ChipType[2] 0 Bit 2 of the value. 3 ChipType[3] 0 Bit 3 of the value. 4 ChipType[4] 0 Bit 4 of the value. 5 ChipType[5] 0 Bit 5 of the value. 6 ChipType[6] 0 Bit 6 of the value. 7 ChipType[7] 0 Bit 7 of the value. Register 5 and 4 define the value for the ChipID . The ChipID is a 16- bit word with a default value of 0 = 0000h = 0000_0000_0000_0000b. Register 4 is the lower 8 bits of the word and the default value is 0 = 00h = 0000_0000b. This register is READ ONLY. Table 38. Register 4: Bit Definition 0 ChipID[0] 0 Bit 0 of the value. 1 ChipID[1] 0 Bit 1 of the value. 2 ChipID[2] 0 Bit 2 of the value. 3 ChipID[3] 0 Bit 3 of the value. 4 ChipID[4] 0 Bit 4 of the value. 5 ChipID[5] 0 Bit 5 of the value. 6 ChipID[6] 0 Bit 6 of the value. 7 ChipID[7] 0 Bit 7 of the value.

Register 5 and 4 define the value for the ChipID. The ChipID is a 16- bit word with a default value of 0 = 0000h = 0000_0000_0000_0000b. Register 5 is the higher 8 bits of the word and the default value is 0 = 00h = 0000_0000b. This register is READ ONLY. Table 39. Register 5: Bit Definition 0 ChipID[8] 0 Bit 8 of the value. 1 ChipID[9] 0 Bit 9 of the value. 2 ChipID[10] 0 Bit 10 of the value. 3 ChipID[11] 0 Bit 11 of the value. 4 ChipID[12] 0 Bit 12 of the value. 5 ChipID[13] 0 Bit 13 of the value. 6 ChipID[14] 0 Bit 14 of the value. 7 ChipID[15] 0 Bit 15 of the value. This register is READ ONLY and contains the Chip Version value. The Chip Version is an 8-bit word. The default value is 3 = 03h= 0000_0011b. Table 40. Register 6: Bit Definition 0 ChipVersion[0] 1 Bit 0 of the value. 1 ChipVersion[1] 1 Bit 1 of the value. 2 ChipVersion[2] 0 Bit 2 of the value. 3 ChipVersion[3] 0 Bit 3 of the value. 4 ChipVersion[4] 0 Bit 4 of the value. 5 ChipVersion[5] 0 Bit 5 of the value. 6 ChipVersion[6] 0 Bit 6 of the value. 7 ChipVersion[7] 0 Bit 7 of the value. This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b. This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b. This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b. This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b. This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.

lower 8 bits of the word and the default value is 38 = 26h= 0010_0110b. This register is READ ONLY. Table 41. Register 12: Bit Definition 0 VendorID[0] 0 Bit 0 of the value. 1 VendorID[1] 1 Bit 1 of the value. 2 VendorID[2] 1 Bit 2 of the value. 3 VendorID[3] 0 Bit 3 of the value. 4 VendorID[4] 0 Bit 4 of the value. 5 VendorID[5] 1 Bit 5 of the value. 6 VendorID[6] 0 Bit 6 of the value. 7 VendorID[7] 0 Bit 7 of the value. higher 8 bits of the word and the default value is 4 = 04h= 0000_0100b. This register is READ ONLY. Table 42. Register 13: Bit Definition 0 VendorID[8] 0 Bit 8 of the value. 1 VendorID[9] 0 Bit 9 of the value. 2 VendorID[10] 1 Bit 10 of the value. 3 VendorID[11] 0 Bit 11 of the value. 4 VendorID[12] 0 Bit 12 of the value. 5 VendorID[13] 0 Bit 13 of the value. 6 VendorID[14] 0 Bit 14 of the value. 7 VendorID[15] 0 Bit 15 of the value. This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.

Table 43. Register 15: Bit Definition

0 TransferOn 0

If this is set to logic LOW, then there is no transfer. not affect the operation of the device. This bit is always reset to logic LOW 0 after the operation, and this is called Auto-Clear. Table 44. Register 16: Bit Definition 0 R[0] 0 Bit 0 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45). 1 R[1] 0 Bit 1 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45). 2 R[2] 0 Bit 2 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45). 3 R[3] 0 Bit 3 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45).

4 RefDoub 1

2). This is the default value.

Table 45. 4-bit Pre Divider Value (R) Description Registers 18 and 17 control the Feedback Frequency Divider within the PLL. This is a 16- bit word that gives the integer value of the divider. and has a default value 63 = 3Fh = 0011_1111b. Table 46. Register 17: Bit Definition 0 NInt[0] 1 Bit 0 of a 16-bit word to determine Integer value for the feedback divider. 1 NInt[1] 1 Bit 1 of a 16-bit word to determine Integer value for the feedback divider. 2 NInt[2] 1 Bit 2 of a 16-bit word to determine Integer value for the feedback divider. 3 NInt[3] 1 Bit 3 of a 16-bit word to determine Integer value for the feedback divider. 4 NInt[4] 1 Bit 4 of a 16-bit word to determine Integer value for the feedback divider. 5 NInt[5] 1 Bit 5 of a 16-bit word to determine Integer value for the feedback divider. 6 NInt[6] 0 Bit 6 of a 16-bit word to determine Integer value for the feedback divider. 7 NInt[7] 0 Bit 7 of a 16-bit word to determine Integer value for the feedback divider.

Registers 18 and 17 control the Feedback Frequency Divider within the PLL. This is a 16- bit word that gives the integer value of the divider. and has a default value of 0 = 00h = 0000_0000b. Table 47. Register 18: Bit Definition 0 NInt[8] 0 Bit 8 of a 16-bit word to determine integer value for the feedback divider. 1 NInt[9] 0 Bit 9 of a 16-bit word to determine integer value for the feedback divider. 2 NInt[10] 0 Bit 10 of a 16-bit word to determine integer value for the feedback divider. 3 NInt[11] 0 Bit 11 of a 16-bit word to determine integer value for the feedback divider. 4 NInt[12] 0 Bit 12 of a 16-bit word to determine integer value for the feedback divider. 5 NInt[13] 0 Bit 13 of a 16-bit word to determine integer value for the feedback divider. 6 NInt[14] 0 Bit 14 of a 16-bit word to determine integer value for the feedback divider. 7 NInt[15] 0 Bit 15 of a 16-bit word to determine integer value for the feedback divider. the lower 8 bits of NFrac, and its default value is 0 = 00h = 0000_0000b. Table 48. Register 19: Bit Definition 0 NFrac[0] 0 Bit 0 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 1 NFrac[1] 0 Bit 1 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 2 NFrac[2] 0 Bit 2 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 3 NFrac[3] 0 Bit 3 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 4 NFrac[4] 0 Bit 4 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 5 NFrac[5] 0 Bit 5 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 6 NFrac[6] 0 Bit 6 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 7 NFrac[7] 0 Bit 7 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.

the upper 8 bits of NFrac, and its default value is 122 = 7Ah = 0111_1010b. Table 49. Register 20: Bit Definition 0 NFrac[8] 0 Bit 8 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 1 NFrac[9] 1 Bit 9 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 2 NFrac[10] 0 Bit 10 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 3 NFrac[11] 1 Bit 11 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 4 NFrac[12] 1 Bit 12 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 5 NFrac[13] 1 Bit 13 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 6 NFrac[14] 1 Bit 14 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. 7 NFrac[15] 0 Bit 15 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation. lower 8 bits of NMod, and its default value is 255 = FFh = 1111_1111b. Table 50. Register 21: Bit Definition 0 NMod[0] 1 Bit 0 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 1 NMod[1] 1 Bit 1 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 2 NMod[2] 1 Bit 2 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 3 NMod[3] 1 Bit 3 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 4 NMod[4] 1 Bit 4 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 5 NMod[5] 1 Bit 5 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 6 NMod[6] 1 Bit 6 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 7 NMod[7] 1 Bit 7 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.

upper 8 bits of NMod, and its default value is 255 = FFh = 1111_1111b. Table 51. Register 22: Bit Definition 0 NMod[8] 1 Bit 8 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 1 NMod[9] 1 Bit 9 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 2 NMod[10] 1 Bit 10 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 3 NMod[11] 1 Bit 11 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 4 NMod[12] 1 Bit 12 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 5 NMod[13] 1 Bit 13 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 6 NMod[14] 1 Bit 14 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. 7 NMod[15] 1 Bit 15 in the 16-bit NMod denominator in the fraction term in the feedback divider equation. not used. The default value is 1 = 01h = 0000_0001b. Table 52. Register 23: Bit Definition 0 MDiv[0] 1 Bit 0 of 3-bit word for divider (see Table 53). 1 MDiv[1] 0 Bit 1 of 3-bit word for divider (see Table 53). 2 MDiv[2] 0 Bit 2 of 3-bit word for divider (see Table 53).

3 Quad_Divider 0

Set for logic LOW for divide by 1. This is the default value. Set for logic HIGH for divide by 2.

Table 53. 3-Bit Divider Value (MDiv) Description current is 0.94mA. Bits 4 to 7 are not used. The default value is 2 = 02h = 0000_0010b. Table 54. Register 24: Bit Definition 0 ChrgPmp[0] 0 Bit 0 of 4-bit word for charge pump current (see Table 55). 1 ChrgPmp[1] 1 Bit 1 of 4-bit word for charge pump current (see Table 55). 2 ChrgPmp[2] 0 Bit 2 of 4-bit word for charge pump current (see Table 55). 3 ChrgPmp[3] 0 Bit 3 of 4-bit word for charge pump current (see Table 55).

Table 55. 4-Bit Charge Pump Current LO power can be increased by setting a 1 bit word. Bits 5 to 7 are unused. The register default is 5 = 05h = 0000_0101b. Table 56. Register 25: Bit Definition 0 LO_Out_Pwr[0] 1 Bit 0 of a 2-bit word to set the LO power to the modulator (see Table 57). 1 LO_Out_Pwr[1] 0 Bit 1 of a 2-bit word to set the LO power to the modulator (see Table 57). 2 LO_SW_Out_Pwr[0] 1 Bit 0 of a 2-bit word to set LO power to the external port (see Table 58). 3 LO_SW_Out_Pwr[1] 0 Bit 1 of a 2-bit word to set LO power to the external port (see Table 58).

4 LO_Out_Pwr_extra 0

modulator. The addition power is different for each of the LO_Out_Pwr settings. If this bit is set for logic LOW (default), then the LO predriver will not increase the output power.

Table 57. 2-Bit Power Setting for the Modulator Signal Table 58. 2-Bit LO Power for the External LO Port (LO_OUT) Table 59. Register 26: Bit Definition

0 LO_IN_Enable 0

1 LO_Out_Enable 0

2 LO_SW_Out_Enable 1

disabled. If this bit is set for logic HIGH (default), then the DAC is enabled.

4 PLL_Enable 1

5 LO_SW_Out_Select 0

Table 60. Register 27: Bit Definition 0 DSA0[0] 0 Bit 0 of a 5-bit word to set the DSA for Channel 0 (see Table 61). 1 DSA0[1] 0 Bit 1 of a 5-bit word to set the DSA for Channel 0 (see Table 61). 2 DSA0[2] 0 Bit 2 of a 5-bit word to set the DSA for Channel 0 (see Table 61). 3 DSA0[3] 0 Bit 3 of a 5-bit word to set the DSA for Channel 0 (see Table 61). 4 DSA0[4] 0 Bit 4 of a 5-bit word to set the DSA for Channel 0 (see Table 61). Table 61. 5-Bit Digital Attenuator Setting used for both DSA0 and DSA1

Table 62. Register 28: Bit Definition 0 DSA1[0] 0 Bit 0 of a 5-bit word to set the DSA for Channel 1 (see Table 61). 1 DSA1[1] 0 Bit 1 of a 5-bit word to set the DSA for Channel 1 (see Table 61). 2 DSA1[2] 0 Bit 2 of a 5-bit word to set the DSA for Channel 1 (see Table 61). 3 DSA1[3] 0 Bit 3 of a 5-bit word to set the DSA for Channel 1 (see Table 61). 4 DSA1[4] 0 Bit 4 of a 5-bit word to set the DSA for Channel 1 (see Table 61). Table 63. Register 29: Bit Definition 0 DAC0[0] 1 Bit 0 of an 11-bit word to set the VVA for Channel 0. 1 DAC0[1] 1 Bit 1 of an 11-bit word to set the VVA for Channel 0. 2 DAC0[2] 1 Bit 2 of an 11-bit word to set the VVA for Channel 0. 3 DAC0[3] 1 Bit 3 of an 11-bit word to set the VVA for Channel 0. 4 DAC0[4] 1 Bit 4 of an 11-bit word to set the VVA for Channel 0. 5 DAC0[5] 1 Bit 5 of an 11-bit word to set the VVA for Channel 0. 6 DAC0[6] 1 Bit 6 of an 11-bit word to set the VVA for Channel 0. 7 DAC0[7] 1 Bit 7 of an 11-bit word to set the VVA for Channel 0.

3 bits of the word and the default is 7 = 7h = 0000_0111b. Table 64. Register 30: Bit Definition 0 DAC0[8] 1 Bit 8 of an 11-bit word to set the VVA for Channel 0. 1 DAC0[9] 1 Bit 9 of an 11-bit word to set the VVA for Channel 0. 2 DAC0[10] 1 Bit 10 of an 11-bit word to set the VVA for Channel 0. Table 65. Register 31: Bit Definition 0 DAC1[0] 1 Bit 0 of an 11-bit word to set the VVA for Channel 1. 1 DAC1[1] 1 Bit 1 of an 11-bit word to set the VVA for Channel 1. 2 DAC1[2] 1 Bit 2 of an 11-bit word to set the VVA for Channel 1. 3 DAC1[3] 1 Bit 3 of an 11-bit word to set the VVA for Channel 1. 4 DAC1[4] 1 Bit 4 of an 11-bit word to set the VVA for Channel 1. 5 DAC1[5] 1 Bit 5 of an 11-bit word to set the VVA for Channel 1. 6 DAC1[6] 1 Bit 6 of an 11-bit word to set the VVA for Channel 1. 7 DAC1[7] 1 Bit 7 of an 11-bit word to set the VVA for Channel 1.

3 bits of the word and the default is 7 = 7h = 0000_0111b. Table 66. Register 32: Bit Definition 0 DAC1[8] 1 Bit 8 of an 11-bit word to set the VVA for Channel 1. 1 DAC1[9] 1 Bit 9 of an 11-bit word to set the VVA for Channel 1. 2 DAC1[10] 1 Bit 10 of an 11-bit word to set the VVA for Channel 1. This register selects the RF and LO bands used for the device. Bits 2 to 7 are unused. The default is 0 = 0h = 0000_0000b. Table 67. Register 33: Bit Definition

0 LO_BAND 0

Set the LO band of operation. Set to logic LOW to select the 1.50GHz to 2.00GHz range for the LO band. This is the default.

1 RF_BAND 0

Set the RF band of operation. Set to logic LOW to select the 0.55GHz to 2.80GHz range for the RF band. This is the default. Set to logic HIGH to select the 0.45GHz to 0.55GHz range for the RF band.

This register selects the logic levels used for the digital output. Default is JEDEC 1.8 V logic and the default value is 0 = 00h = 0000_0000b. Table 68. Register 34: Bit Definition 0 Dig_Out_Level 0 Set for logic LOW for JEDEC 1.8 Volt logic (default). Set for logic HIGH for JEDEC 3.3 V logic. Table 69. Register 35: Bit Definition 0 LDP[0] 0 Bit 0 of a 3-bit word to set when the VCO precision lock detection is set (see Table 70). 1 LDP[1] 0 Bit 1 of a 3-bit word to set when the VCO precision lock detection is set (see Table 70). 2 LDP[2] 0 Bit 2 of a 3-bit word to set when the VCO precision lock detection is set (see Table 70). 4 LDPinMode[0] 0 Bit 0 of a 2-bit word to set the LD pin operation (see Table 71). 5 LDPinMode[1] 0 Bit 1 of a 2-bit word to set the LD pin operation (see Table 71). Table 70. 3-bit VCO Lock Precision Detection Description 0 0 0 0 Set for lock detection to within 11.5ns (default). 1 0 0 1 Set for lock detection to within 6.5ns. 2 0 1 0 Set for lock detection to within 6.5ns. 3 0 1 1 Set for lock detection to within 3.0ns. 4 1 0 0 Set for lock detection to within 5.0ns. 5 1 0 1 Set for lock detection to within 5.0ns. 6 1 1 0 Set for lock detection to within 1.5ns. 7 1 1 1 Set for lock detection to within 1.5ns.

Table 71. 2-bit Lock Detection Pin Description 0 0 0 Digital Lock (normal operation) (default). 1 0 1 VCO calibration is done. This register controls how the PLL locks the VCO frequency. The default value is 0 = 00h = 0000_0000b. Bits 3 to 7 are unused. Table 72. Register 36: Bit Definition 0 Force_Relock 0 0 = No VCO relocking (default). 1 = Force the VCO to recalibrate. This-bit is self-clearing. 1 Band_Sel_Disable 0 0 = If registers16-22 are written, then the VCO will recalibrate (default). 1 = No VCO recalibration is done. 2 Auto_Recal_Enable 0 0 = Disable Auto Recalibration (default). 1 = Enable Auto Recalibration. This register controls the lock detection of the PLL. The default value is 1 = 01h = 0000_0001b. Table 73. Register 37: Bit Definition 0 Vendor Supplied 1 Reserved for vendor use. Use only the default value. 1 Vendor Supplied 0 Reserved for vendor use. Use only the default value. 2 Vendor Supplied 0 Reserved for vendor use. Use only the default value. 3 Vendor Supplied 0 Reserved for vendor use. Use only the default value. 4 Vendor Supplied 0 Reserved for vendor use. Use only the default value. 5 Vendor Supplied 0 Reserved for vendor use. Use only the default value. 6 Vendor Supplied 0 Reserved for vendor use. Use only the default value.

0001_0000_0000b. Register 38 is the lower 8 bits of the word and the default value is 0 = 00h = 0000_0000b. Table 74. Register 38: Bit Definition 0 BndSelDiv[0] 0 Bit 0 of a 12-bit word to select the VCO Band. 1 BndSelDiv[1] 0 Bit 1 of a 12-bit word to select the VCO Band. 2 BndSelDiv[2] 0 Bit 2 of a 12-bit word to select the VCO Band. 3 BndSelDiv[3] 0 Bit 3 of a 12-bit word to select the VCO Band. 4 BndSelDiv[4] 0 Bit 4 of a 12-bit word to select the VCO Band. 5 BndSelDiv[5] 0 Bit 5 of a 12-bit word to select the VCO Band. 6 BndSelDiv[6] 0 Bit 6 of a 12-bit word to select the VCO Band. 7 BndSelDiv[7] 0 Bit 7 of a 12-bit word to select the VCO Band. 0001_0000_0000b. Register 39 is the higher 4 bits of the word and the default value is 1 = 01h = 0000_0001b. Table 75. Register 39: Bit Definition 0 BndSelDiv[8] 1 Bit 8 of a 12-bit word to select the VCO Band. 1 BndSelDiv[9] 0 Bit 9 of a 12-bit word to select the VCO Band. 2 BndSelDiv[10] 0 Bit 10 of a 12-bit word to select the VCO Band. 3 BndSelDiv[11] 0 Bit 11 of a 12-bit word to select the VCO Band. This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b. This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b. This register is reserved for internal use. The default value is 2 = 02h = 0000_0010b. This register is reserved for internal use. The default value is 203 = CBh = 1100_1011b. This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b.

© 2020 Renesas Electronics Corporation 69 May 15, 2020 F159V Datasheet 24.2.46. Register 45 (2Dh) This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b. 24.2.47. Register 46 (2Eh) This register is reserved for internal use and is READ ONLY. The default value does not apply. 24.2.48. Register 47 (2Fh) This register is reserved for internal use and is READ ONLY. The default value does not apply. 24.2.49. Register 48 (30h) This register is reserved for internal use and is READ ONLY. The default value does not apply. 24.2.50. Register 49 (31h) This register is reserved for internal use. The default value does not apply.

1. Evaluation Kit / Applications Circuit

Figure 99. Electrical Schematic for the Differential Evaluation Board All differential ports have transmission lines of equal length.

Figure 100. DC Electrical Schematic for the Differential Evaluation Board

Table 76. Bill of Material (BOM)

Table 77. Bill of Material (BOM) (Cont.)

1 Printed Circuit Board F159V EVKIT REV 02 IDT

Note: All other parts noted in the schematic that are not contained in this Bill of Material are not installed.

The F159V is optimized for use in high-performance RF applications from 450MHz to 2800MHz. minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. as to not load the control line. All power supply pins must be turned on simultaneously. The following table provides open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed. Table 78. Digital Pin Voltages and Resistance

49 RESET 0 51

52 SPI_CSN 0 51

53 SPI_CLK 0 51

When BBI leads BBQ by 90 degrees, HS LO injection is used. When BBQ leads BBI by 90 degrees, LS LO injection is used. and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity.

Figure 101. Control Pin Interface

© 2020 Renesas Electronics Corporation 77 May 15, 2020 F159V Datasheet 28. Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package inf ormation is the most current data available. www.idt.com/us/en/document/psc/nlnlg68-package-outline-100-x-100-mm-epad-770-mm-sq-vfqfp-n 29. Ordering Information Orderable Part Number Package MSL Rating Shipping Packaging Temperature F159VNLGN 10 x 10 x 0.9 mm 68-VFQFPN 3 Tray -20° to +115°C F159VNLGN8 10 x 10 x 0.9 mm 68-VFQFPN 3 Reel -20° to +115°C F159VEVBN Evaluation Board 30. Marking Diagram IDT F159VNLGN ZK1729L Q57BO12PY THA  Line 1 and 2 are the part number.  Line 3 “ZK” is for die version.  Line 3 “yyww” = 1729 has two digits for the year and week that the part was assembled.  Line 3 “L” denotes assembly site.  Line 4 “Q57BO12PY THA” is the assembly lot number.

Revision History

Revision Date Description of Change May 15, 2020 Rebranded/reformatted document. November 10, 2017 Updated for format, theory of operation, and register definition. December 23, 2016 Initial release.

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