F1471

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 23

Technical content

Datasheet sections

Features

• RF range: 400MHz to 4200MHz
• 15dB typical gain at 3600MHz
• 3.8dB NF at 3600MHz
• +29dBm output P1dB at 3600MHz
• 5V power supply
• Adjustable DC bias
• Bias control compatible for 3.3V and 5V VREF operation allowing power-down mode for power savings
• 50Ω single-ended input and output impedances
• Internal DC overvoltage protection
• Internal RF overdrive protection
• On-chip ESD protection
• Operating temperature (TEP) range: -40°C to +115°C
• 3 × 3 mm, 16-VFQFPN package

Applications

• 4G/5G cellular base stations
• Multi-mode, multi-carrier transmitters
• Active antenna systems
• General purpose wireless RFIN RFOUT Bias VCC I_REF

Figure 1. Block Diagram

Rev.1.0 Oct.16.20 Page 4 1. Pin Information Pin Configuration

16 Ld 3 x 3 mm VFQFPN Package

I_REF VCC NC Pin Descriptions Number Name Description 1, 4, 5, 6, 7, 8, 9, 12, 13, 16 NC No internal connection. Renesas highly recommends connecting these pins to a ground via, which is located as close to the pin as possible. 2, 3 RFIN RF input internally matched to 50Ω. Must use an external DC block. 10, 11 RFOUT RF output. Pull up to VCC through inductor. Must use an external DC block. 14 VCC Connect pin directly to VCC. Renesas recommends placing a 1000pF decoupling capacitor as close to this pin as possible. 15 I_REF Reference current and STBY pin. Connect an external resistor (reference BOM) to VREF to set the quiescent current of the device. Setting VREF < 2V disables the amplifier. EPAD Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance.

Rev.1.0 Oct.16.20 Page 5 2. Specifications Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the F1471 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Parameter Symbol Minimum Maximum Units VCC to GND VCC 0 8.0 V VREF to GND VREF[b] 0 5.5 V RFIN Externally Applied DC Voltage VRFIN 8.0 V RFOUT Externally Applied DC Voltage VRFOUT 8.0 V Maximum CW input power applied for 24 hours f = 2.6GHz, TEP = +115°C, input/output VSWR < 2:1 based on 50Ω system [a] PMAXIN 18 dBm Junction Temperature TJMAX +175 °C Storage Temperature Range TSTOR -65 +150 °C Lead Temperature (soldering, 10s) TLEAD +260 °C Electrostatic Discharge – HBM (JEDEC/ESDA JS-001-2012) VESDHBM 1500 V Electrostatic Discharge – CDM (JEDEC 22-C101F) VESDCDM 1000 V [a] Exposure to these maximum RF levels can result in significantly higher ICC current draw due to overdriving the amplifier stages. [b] VREF conditions apply when VCC is applied Recommended Operating Conditions Parameter Symbol Condition Minimum Typical Maximum Units Power Supply Voltage VCC 4.75 5.25 V Reference Voltage VREF Powered On 3.3 or 5 [a] V Powered Off 0 1.8 2 Operating Temperature Range TEPAD Exposed Paddle -40 +115 °C RF Frequency Range fRF 400 4200 MHz RFIN Port Impedance ZRFI Single-ended 50 Ω RFOUT Port Impedance ZRFO Single-ended 50 Ω [a] Refer to R5 value in the BOM.

Rev.1.0 Oct.16.20 Page 6

Electrical Characteristics

See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for desired band of interest, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in the electrical schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. 2.3.1. General Parameter Symbol Condition Minimum Typical Maximum Units Quiescent Current [b] ICQ 130 160 [a] mA Reference Bias Current [b] IREF 2 mA IREF_STBY VREF < 2V 500 µA Standby Switching Time TON 50% STBY control to within 0.5dB of the on-state final gain value 200 ns TOFF 50% STBY control to ICC < 10mA 200 ns 2.3.2. 2300MHz to 2900MHz See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for the 2300MHz to 2900MHz band, fRF = 2600MHz, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in the electrical schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. Parameter Symbol Condition Minimum Typical Maximum Units Gain G 16 dB Gain Flatness GFLAT fRF = 2300MHz to 2900MHz 1 dB Gain Variation Over Temp GTEMP TEPAD = -40°C to +115°C, referenced to TEPAD = 25°C +0.5/-1 dB STBY Mode Gain GSTBY VREF < 2V -16 dB RF Input Return Loss RLRFIN 12 dB RF Output Return Loss RLRFOUT 12 dB Reverse Isolation ISOREV 27 dB Noise Figure NF 4 dB Output Third Order Intercept Point OIP3 POUT = +18dBm/tone 1MHz tone separation 38 dBm Output 1dB Compression Point OP1dB 28.5 dBm ACLR ACLR Pout = +18dBm, LTE 20MHz, 9dB PAR -48 dBc

Rev.1.0 Oct.16.20 Page 7 Parameter Symbol Condition Minimum Typical Maximum Units Stability K K-Factor [b] TEPAD = -40°C to +115°C VCC = 4.75V to 5.25V Up to 20GHz [a] Specifications in the minimum/maximum columns that are shown in bold italics are confirmed by test. Specifications in these columns that are not shown in bold italics are confirmed by design characterization. [b] K-Factor calculated taking the matching circuit into consideration, no de-embedding applied. 2.3.3. 3300MHz to 3900MHz See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for the 3300MHz to 3900MHz band, fRF = 3600MHz, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in the electrical schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. Parameter Symbol Condition Minimum Typical Maximum Units Gain G 13[a] 15 dB Gain Flatness GFLAT fRF = 3300MHz to 3900MHz 1 dB Gain Variation Over Temp GTEMP TEPAD = -40°C to +115°C, referenced to TEPAD = 25°C +0.5/-1 dB STBY Mode Gain GSTBY VREF < 2V -14 dB RF Input Return Loss RLRFIN 14 dB RF Output Return Loss RLRFOUT 12 dB Reverse Isolation ISOREV 25 dB Noise Figure NF 3.8 dB Output Third Order Intercept Point OIP3 POUT = +18dBm/tone 1MHz tone separation 38 dBm POUT = +18dBm/tone 1MHz tone separation VCC = 4.75V to 5.25V TEPAD = -40°C to +115°C 32 dBm Output 1dB Compression Point OP1dB 29 dBm VCC = 4.75V to 5.25V TEPAD = -40°C to +115°C 26 dBm ACLR ACLR Pout = +18dBm, LTE 20MHz, 9dB PAR -47 dBc Stability K K-Factor [b] TEPAD = -40°C to +115°C VCC = 4.75V to 5.25V Up to 20GHz [a] Specifications in the minimum/maximum columns that are shown in bold italics are confirmed by test. Specifications in these columns that are not shown in bold italics are confirmed by design characterization. [b] K-Factor calculated taking the matching circuit into consideration, no de-embedding applied.

Rev.1.0 Oct.16.20 Page 8 2.3.4. 3800MHz to 4200MHz See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for the 3800MHz to 4200MHz band, fRF = 4000MHz, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in the electrical schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated. Parameter Symbol Condition Minimum Typical Maximum Units Gain G 14 dB Gain Flatness GFLAT fRF = 3800MHz to 4200MHz 1.2 dB Gain Variation Over Temp GTEMP TEPAD = -40°C to +115°C, referenced to TEPAD = 25°C +0.5/-1 dB STBY Mode Gain GSTBY VREF < 2V -13 dB RF Input Return Loss RLRFIN 15 dB RF Output Return Loss RLRFOUT 9 dB Reverse Isolation ISOREV 25 dB Noise Figure NF 3.8 dB Output Third Order Intercept Point OIP3 POUT = +18dBm/tone 1MHz tone separation 37 dBm Output 1dB Compression Point OP1dB 28.5 dBm ACLR ACLR Pout = +18dBm, LTE 20MHz, 9dB PAR -44 dBc Stability K K-Factor [b] TEPAD = -40°C to +115°C VCC = 4.75V to 5.25V Up to 20GHz [a] Specifications in the minimum/maximum columns that are shown in bold italics are confirmed by test. Specifications in these columns that are not shown in bold italics are confirmed by design characterization. [b] K-Factor calculated taking the matching circuit into consideration, no de-embedding applied. Thermal Characteristics Parameter Symbol Value Units Junction to Ambient Thermal Resistance. θJA 48.6 °C/W Junction to Case Thermal Resistance. (Case is defined as the exposed paddle) θJC-BOT 4.3 °C/W Moisture Sensitivity Rating (Per J-STD-020) MSL 1

Rev.1.0 Oct.16.20 Page 9 3. Typical Operating Conditions (TOC) Unless otherwise noted, the following conditions apply for the TOC graphs on the following pages:

• Vcc = 5.0V
• ZL = ZS = 50Ω Single-ended
• fRF = 2600MHz (set 1)
• fRF = 3600MHz (set 2)
• fRF = 4000MHz (set 3)
• TEP = +25°C
• VREF = 3.3V
• 1MHz Tone Spacing
• All temperatures are referenced to the exposed paddle.
• ACLR measurements used with LTE signal, 20MHz, PAR = 9dB at 0.01% probability.
• Evaluation Kit traces and connector losses are de-embedded

The F1471 includes a STBY feature as defined in the following table. Table 1. STBY Truth Table The F1471 has been optimized for use in high performance RF applications from 400MHz to 4200MHz. addition, keep all control pins at 0V (±0.3V) while the supply voltage ramps or while it returns to zero.

1. Evaluation Kit Information

Figure 26. Evaluation Kit Photo

Figure 27. Electrical Schematic for the Evaluation Kit

Table 2. Evaluation Kit Bill of Material (BOM) – 2300MHz to 2900MHz Tune

Table 3. Evaluation Kit Bill of Material (BOM) – 3300MHz to 3900MHz Tune

Table 4. Evaluation Kit Bill of Material (BOM) – 3800MHz to 4200MHz Tune

Rev.1.0 Oct.16.20 Page 19 Evaluation Kit Operation 7.3.1. Power Supply Setup Set up a power supply in the voltage range of 4.75V to 5.25V with the power supply output disabled. The voltage is applied using the following connection (see Figure 26):

• Directly to the J2 SMA connector Set up a control supply of either 3.3V or 5V (Use the correct value of resistance (R5) based on the applied control voltage as indicated per the BOM). The voltage is applied using the following connection (see Figure 26):
• Directly to the J3 SMA connector 7.3.2. Shunt Jumper Setup
• J7 Header Pins o Always place the Shunt Jumper to bias the amplifier output (see Evaluation Schematic in Figure 27).
• J6 Header Pins o J6 Header pins provide the VCC and VREF voltages to the DUT. o Always place a shunt jumper on pins 5 and 6 to provide the supplied VCC to the DUT. o Place a shunt jumper on pins 3 and 4. In this configuration, VREF is set independent to the supply voltage, VCC. o Place a shunt jumper on pins 1 and 2. In this configuration, VREF is set to the same level as the supply voltage, VCC.
• Only place jumpers on Pins 3 and 4 or Pins 1 and 2 at any given time. Important: Do not place jumpers on all four pins (1, 2, 3, and 4) simultaneously. 7.3.3. Power-On Procedure 1. Set up the voltage supplies, and Evaluation Board as described in the Power Supply Setup section. 2. Enable the VCC supply. 3. Enable the VREF supply. 7.3.4. Power-Off Procedure Disable the VREF supply and then disable the VCC power supply.

Rev.1.0 Oct.16.20 Page 20 8. Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. https://www.idt.com/us/en/document/psc/16-vfqfpn-package-outline-drawing30x-30-x-075-mm-body050mm- pitchepad-160-x-160-mm-ntg16t1 9. Ordering Information Orderable Part Number Package MSL Rating Shipping Packaging Temperature F1471NTGI 3 × 3 × 0.75 mm 16-VFQFPN 1 Tray -40° to +115°C F1471NTGI8 3 × 3 × 0.75 mm 16-VFQFPN 1 Reel -40° to +115°C F1471EVB-2P6 Evaluation Board 2300MHz – 2900MHz Tune F1471EVB-3P6 Evaluation Board 3300MHz – 3900MHz Tune F1471EVB-4P0 Evaluation Board 3800MHz – 4200MHz Tune 10. Marking Diagram XXX YWW$ F1471

• “XXX” denotes the last 3 digits of the assembly lot number
• “Y” denotes the last digit of the year
• “WW” denotes the work week
• “$” denotes the mark location code
• F1471 Is the product name 11. Revision History Revision Revision Date Description of Change 1.0 Oct.16.20 Initial release.

© Integrated Device Technology, Inc.

© Integrated Device Technology, Inc. Package Revision HistoryRev No.Date CreatedDescriptionRev 02Add "K" Value 0.20 MinimumSept 5, 2018Rev 03Correct Typo Error MinimumJuly 8, 2019

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