F1456 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Renesas Electronics Corporation
- PDF pages: 30
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 ESD Ratings
- 2.3 Recommended Operating Conditions
- 2.4 Electrical Characteristics – General
- 2.5 Electrical Characteristics – RF
- 2.6 Package Thermal Characteristics
- 6.1 Power Up Attenuation Setting
- 6.2 Chip Select (CSb)
- 6.3 Standby Mode (/STBY)
- 6.4 Power Supplies
- 6.5 Control Pin Interface
- 7.1 Evaluation Kit Pictures
- 7.2 Evaluation Kit Schematic Circuit
- 7.3 Evaluation Kit Operation
Features
■ Broadband 1500MHz to 2950MHz ■ 32.1dB maximum gain ■ 3.9dB NF at maximum gain (2650MHz) ■ 31.5dB total gain control range, 0.5 dB step ■ < 2dB overshoot between gain transitions ■ Maintains flat +21.5dBm OP1dB for more than 13dB gain adjustment range ■ Maintains flat +38dBm OIP3 for more than 15dB gain adjustment range ■ SPI interface for DSA control ■ Single 5V supply voltage ■ ICC = 215mA ■ Up to +105°C TCASE operating temperature ■ 50Ω input and output impedance ■ Standby mode for power savings ■ Pin compatible 700MHz and 2100MHz versions ■ 6 x 6 mm, 28-VFQFPN package
Applications
■ Multi-mode, Multi-carrier Transmitters ■ WiMAX and LTE Base Stations ■ UMTS/WCDMA 3G Base Stations ■ PHS/PAS Base Stations ■ Public Safety Infrastructure Figure 1. Block Diagram
1.1 Pin Assignments
Figure 2. Pin Assignments – Top View
1.2 Pin Descriptions
Table 1. Pin Descriptions 1 CSb Chip Select Input: 1.8V or 3.3V logic compatible. 2 DATA Data Input: 1.8V or 3.3V logic compatible. 3 CLK Clock Input: 1.8V or 3.3V logic compatible. 4 [a] RSET Connect 2.2kΩ external resistor to GND to set amplifier bias. 21, 23, 27 GND Pins internally tied to exposed paddle. Connect to ground on PCB. 6 RFIN RF input internally matched to 50Ω. Must use external DC block. circuitry is still active. With a logic high applied to pin 14 the part is set to full operation mode. 16 RFOUT RF output internally matched to 50Ω. Must use external DC block. 28 VCC 5 V Power Supply. Connect to Vcc and use bypass capacitors as close to the pin as possible. multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the noted RF performance.
- External resistor on pin 4 used to optimize the overall device for DC current and linearity performance across the entire frequency
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.1 Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
- Exposure to these maximum RF levels can result in significantly higher Icc current draw due to overdriving the amplifier stages.
2.2 ESD Ratings
2.3 Recommended Operating Conditions
Table 3. Recommended Operating Conditions
- Device linearity is optimized over the range from 2100 MHz to 2700 MHz. Gain flatness is optimized up to 2950 MHz to account for
systems with extended DPD bandwidth requirements.
2.4 Electrical Characteristics – General
trace and connector losses are de-embedded. Table 4. Electrical Characteristics
- Items in min/max columns in bold italics are confirmed by Test.
- Items in min/max columns that are not bold/italics are confirmed by Design Characterization.
- SPI 3 wire bus (refer to serial Control Mode Timing diagram).
2.5 Electrical Characteristics – RF
trace and connector losses are de-embedded. Table 5. Electrical Characteristics
- Items in min/max columns in bold italics are confirmed by Test.
- Items in min/max columns that are not bold/italics are confirmed by Design Characterization.
- Includes a positive slope feature over the noted RF range to compensate for typical system roll-off.
2.6 Package Thermal Characteristics
Table 6. Package Thermal Characteristics Junction to Case Thermal Resistance.
- Typical Operating Conditions
Table 8. SPI Timing Diagram Values for Figure 63
- Once all desired DATA is clocked in, TLC represents the time a CSb high needs to occur before any subsequent CLK signals.
Table 9. Standby Truth Table
0 V Amplifier OFF with SPI powered ON
6.1 Power Up Attenuation Setting
When the part is initially powered up, the default VGA setting is the 31.5dB [000000] attenuation state.
6.2 Chip Select (CSb)
setting (see Standby Mode section below).
6.3 Standby Mode (/STBY)
programmed. Therefore, the device will present the desired attenuation when it is enabled.
6.4 Power Supplies
6.5 Control Pin Interface
line, the component values will need to be adjusted accordingly so as not to load down the control line. Figure 64. Control Pin Interface for Signal Integrity
7.1 Evaluation Kit Pictures
Figure 65. Top View Figure 66. Bottom View
7.2 Evaluation Kit Schematic Circuit
Figure 67. Evaluation Kit Schematic Diagram check the Bill of Material (BOM) table.
Table 10. Bill of Material (BOM)
1 Printed Circuit Board F145X EVKIT REV 02
7.3 Evaluation Kit Operation
Figure 68. J6 Connector for Standby Mode Control Connector J7 pins 1, 2, 4, 6, 8 are ground. Pin 3 is DATA, pin 5 is Clock (CLK), pin 7 is Chip Select (CSB). Figure 69. J7 Connector for SPI
R35DS0037EU0102 Rev.1.02 Feb 16, 2022 Page 27 8. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 9. Ordering Information Part Number Package MSL Rating Carrier Type Temp. Range F1456NKGK 6 x 6 x 0.9 mm 28-VFQFPN 1 Tray -40° to +105°C F1456NKGK8 6 x 6 x 0.9 mm 28-VFQFPN 1 Tape and Reel -40° to +105°C F1456EVBK Evaluation Board F1456EVSK Evaluation Solution 10. Marking Diagram Line 2 and 3 are the part number. Line 4 “ZW” is Assembly Stepping. Line 4 “yyww = 1629 has two digits for the year and week that the part was assembled. Line 4 “L” denotes Assembly Site. Line 5 “Q54E042PY” is the Assembly Lot number 11. Revision History Revision Date Description
1.02 Feb 16, 2022
Updated the operating range down to 1500MHz Added plots for 1800MHz performance Completed other minor changes 1.01 Feb 9, 2022 Rebranded as Renesas. 1.00 Nov 9, 2016 Initial release.
© Integrated Device Technology, Inc.
© Integrated Device Technology, Inc. May 14, 2019Rev 00Initial ReleasePackage Revision HistoryRev No.Date CreatedDescription
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