F1451 IDT | Alldatasheet
Document overview
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Technical content
Features
Broadband 700 MHz to 1100 MHz 32 dB max gain 3.6 dB NF @ max gain (900 MHz) 29.5 dB total gain control range, 0.5 dB step < 2 dB overshoot between gain transitions Maintains flat +23 dBm OP1dB for more than 13 dB gain adjustment range Maintains flat +41 dBm OIP3 for more than 15 dB gain adjustment range SPI interface for DSA control Single 5 V supply voltage ICC = 185 mA Up to +105 °C TCASE operating temperature 50 Ω input and output impedance Standby mode for power savings Pin compatible 2100 MHz and 2700 MHz versions 6 mm x 6 mm, 28-pin QFN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 6 mm x 6 mm x 0.9 mm QFN Package – Top View
Table 1. Pin Descriptions 1 CSb Chip Select Input: 1.8 V or 3.3 V logic compatible. 2 DATA Data Input: 1.8 V or 3.3 V logic compatible. 3 CLK Clock Input: 1.8 V or 3.3 V logic compatible. 4 [a] RSET Connect 2.0 kΩ external resistor to GND to set amplifier bias. 21, 23, 27 GND Pins internally tied to exposed paddle. Connect to ground on PCB. 6 RFIN RF input internally matched to 50 Ω. Must use external DC block. left floating (pulled low via internal high impedance to GND). In standby mode, SPI circuitry is still active. With a logic high applied to pin 14 the part is set to full operation mode. 16 RFOUT RF output internally matched to 50 Ω. Must use external DC block. 28 VCC 5 V Power Supply. Connect to Vcc and use bypass capacitors as close to the pin as possible. are also required to achieve the noted RF performance.
for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings overdriving the amplifier stages.
Table 3. Recommended Operating Conditions 1200 MHz to account for systems with extended DPD bandwidth requirements.
TCASE = +25 °C, /STBY = High, ZS = ZL = 50 , maximum gain setting. Evaluation Kit trace and connector losses are de-embedded. Table 4. Electrical Characteristics a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. d. SPI 3 wire bus (refer to serial Control Mode Timing diagram).
Table 5. Electrical Characteristics
5 MHz tone separation
a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. c. Includes a positive slope feature over the noted RF range to compensate for typical system roll-off.
Table 6. Package Thermal Characteristics
Serial data is formatted as a 6-bit word clocking data in MSB first. Table 7. Attenuation Word Truth Table Figure 52. Serial Register Timing Diagram
Figure 53. SPI Timing Diagram Table 8. SPI Timing Diagram Values for Figure 53 Table 9. Standby Truth Table
0 V Amplifier OFF with SPI powered ON
© 2016 Integrated Device Technology, Inc. 20 November 29, 2016
Application Information
The F1451 has been optimized for use in high performance RF applications from 700 MHz to 1100 MHz but in general has a much wider band which is shown in the Typical Performance Characteristics. Power Up Attenuation Setting When the part is initially powered up, the default VGA setting is the 29.5 dB [000000] attenuation state. Chip Select (CSb) When CSb is set to logic high, the CLK input is disabled. When CSb is set to logic low, the CLK input is enabled and the DATA word can be programmed into the shift registers. The programmed word is then latched into the F1451 on the CSb rising edge (refer to Figure 53). The operation of the SPI bus in independent of the /STBY pin setting (see Standby Mode section below). Standby Mode (/STBY) The F1451 has a power down feature for power savings which is on Pin 14. For normal operation pin 14 must be set to a logic high. When a logic low is applied to pin 14 the amplifier is placed in standby mode. The Standby mode is a high isolation state. The level of this isolation is not specified and is dependent on the device and attenuation state. In Standby mode the SPI bus is operational and the device attenuation setting can be programmed. Therefore, the device will present the desired attenuation when it is enabled. Power Supplies A common V CC power supply should be used for all power supply pins. To minimize noise and fast transients de -coupling capacitors to all supply pins. Supply noise can degrade noise figure and fast transients can trigger ESD clamps causing them to fail. Supply voltage change or transients should have a slew rate smaller than 1 V / 20 µs. In addition, all control pins should remain at 0 V (± 0.3 V) while the supply voltage ramps or while it returns to zero. Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to SPI and control pins 1, 2, 3 and 14 as shown below. Note the recommended resistor and capacitor values do not necessarily match the EV kit BOM for the case of poor control signal integrity. For multiple devices driven by a single control line, the component values will need to be adjusted accordingly so as not to load down the control line. Figure 54. Control Pin Interface for Signal Integrity
Figure 57. Electrical Schematic check the Bill of Material (BOM) table.
Table 10. Bill of Material (BOM)
1 Printed Circuit Board F145X EVKIT REV 02
Figure 60. Package Outline Drawing NKG28 PSC-4606
Figure 61. Recommended Land Pattern
© 2016 Integrated Device Technology, Inc. 27 November 29, 2016
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F1451NKGK 6 x 6 x 0.9 mm QFN 1 Tray -40° to +105°C F1451NKGK8 6 x 6 x 0.9 mm QFN 1 Tape and Reel -40° to +105°C F1451EVBK Evaluation Board F1451EVSK Evaluation Board with Controller Marking Diagram IDT F1451 NKGK ZB1635L XU65013PY 1. Line 1, 2 and 3 are the part number. 2. Line 4 “ZB” is Assembly Stepping. 3. Line 4 “yyww = “1635” is two digit for the year and week that the part was assembled. 4. Line 4 “L” denotes Assembly Site. 5. Line 5 “XU65013PY” is the Assembly Lot number.
6024 Silver Creek Valley Road
San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the r ight to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Per formance specifications and operating parameters of the described products are determined in an independent state and are not guara nteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an expre ss, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT an d its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their © 2016 Integrated Device Technology, Inc. 28 November 29, 2016
Revision History
Revision Revision Date Description of Change O 2016-November -29 Initial Release