DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 26
Technical content
Features
Broadband 450MHz to 1100MHz 32dB maximum gain 3.6dB NF at maximum gain (900MHz) 29.5dB total gain control range, 0.5dB step < 2dB overshoot between gain transitions Maintains flat +23dBm OP1dB for more than 13dB gain adjustment range Maintains flat +41dBm OIP3 for more than 15dB gain adjustment range SPI interface for DSA control Single 5V supply voltage ICC = 185mA Up to +105°C TCASE operating temperature 50Ω input and output impedance Standby mode for power savings Pin compatible 2100MHz and 2700MHz versions 6 × 6 mm, 28-VFQFPN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 6 × 6 × 0.9 mm QFN Package – Top View
Table 1. Pin Descriptions 1 CSb Chip select input: 1.8V or 3.3V logic compatible. 2 DATA Data input: 1.8V or 3.3V logic compatible. 3 CLK Clock input: 1.8V or 3.3V logic compatible. 4 [a] RSET Connect 2.0kΩ external resistor to GND to set amplifier bias. 21, 23, 27 GND Pins internally tied to exposed paddle. Connect to ground on PCB. 6 RFIN RF input internally matched to 50Ω. Must use external DC block. left floating (pulled low via internal high impedance to GND). In standby mode, SPI circuitry is still active. With a logic high applied to pin 14 the part is set to full operation mode. 16 RFOUT RF output internally matched to 50Ω. Must use external DC block. 28 VCC 5V Power Supply. Connect to Vcc and use bypass capacitors as close to the pin as possible. are also required to achieve the noted RF performance.
for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings overdriving the amplifier stages. Table 3. Recommended Operating Conditions to account for systems with extended DPD bandwidth requirements.
TCASE = +25°C, /STBY = High, ZS = ZL = 50Ω, maximum gain setting. Evaluation Kit trace and connector losses are de-embedded. Table 4. Electrical Characteristics a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns that are not bold/italics are guaranteed by design characterization. d. SPI 3 wire bus (refer to serial Control Mode Timing diagram).
Table 5. Electrical Characteristics a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns that are not bold/italics are guaranteed by design characterization. c. Includes a positive slope feature over the noted RF range to compensate for typical system roll-off.
Table 6. Package Thermal Characteristics
Serial data is formatted as a 6-bit word clocking data in MSB first. Table 7. Attenuation Word Truth Table Figure 46. Serial Register Timing Diagram
Figure 47. SPI Timing Diagram Table 8. SPI Timing Diagram Values for Figure 53 Table 9. Standby Truth Table
0 V Amplifier OFF with SPI powered ON
© 2020 Renesas Electronics Corporation. 18 January 15, 2020
Application Information
The F1451 has been optimized for use in high performance RF applications from 450MHz to 1100MHz but in general has a much wider band which is shown in the Typical Performance Characteristics. Power Up Attenuation Setting When the part is initially powered up, the default VGA setting is the 29.5dB [000000] attenuation state. Chip Select (CSb) When CSb is set to logic high, the CLK input is disabled. When CSb is set to logic low, the CLK input is enabled and the DATA word can be programmed into the shift re gisters. The programmed word is then latched into the F1451 on the CSb rising edge (refer to Figure 53). The operation of the SPI bus in independent of the /STBY pin setting (see Standby Mode section below). Standby Mode (/STBY) The F1451 has a power down feature for power savings which is on Pin 14. For normal operation pin 14 must be set to a logic high. When a logic low is applied to pin 14 the a mplifier is placed in standby mode. The Standby mode is a high isolation state. The level of this isolation is not specified and is dependent on the device and attenuation state. In Standby mode the SPI bus is operational and the device attenuation setting can be programmed. Therefore, the device will present the desired attenuation when it is enabled. Power Supplies A common V CC power supply should be used for all power supply pins. To minimize noise and fast transients de-coupling capacitors to all supply pins. Supply noise can degrade noise figure and fast transients can trigger ESD clamps causing them to fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at 0 V (±0.3V) while the supply voltage ramps or while it returns to zero. Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to SPI and control pins 1, 2, 3 and 14 as shown below. Note the recommended resistor and capacitor values do not necessarily match the EV kit BOM for the case of poor control signal integrity. For multiple devices driven by a single control line, the component values will need to be adjusted accordingly so as not to load down the control line. Figure 48. Control Pin Interface for Signal Integrity
Figure 51. Electrical Schematic check the Bill of Material (BOM) table.
Table 10. Bill of Material (BOM)
1 Printed Circuit Board F145X EVKIT REV 02
© 2020 Renesas Electronics Corporation. 23 January 15, 2020 Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/us/en/document/psc/28-vfqfpn-package-outline-drawing-60-x-60-x-090-mm-body-07mm-pitch-nkg28p1
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F1451NKGK 6 x 6 x 0.9 mm VFQFPN 1 Tray -40° to +105°C F1451NKGK8 6 x 6 x 0.9 mm VFQFPN 1 Tape and Reel -40° to +105°C F1451EVBK Evaluation Board F1451EVSK Evaluation Board with Controller Marking Diagram IDT F1451 NKGK ZB1635L XU65013PY Line 1, 2 and 3 are the part number. Line 4 “ZB” is assembly stepping. Line 4 “yyww” = “1635” is two digit for the year and week that the part was assembled. Line 4 “L” denotes assembly site. Line 5 “XU65013PY” is the assembly lot number.
Revision History
Revision Date Description of Change January 15, 2020 Extended coverage down to 450MHz. November 29, 2016 Initial release.
© Integrated Device Technology, Inc.
© Integrated Device Technology, Inc. May 14, 2019Rev 00Initial ReleasePackage Revision HistoryRev No.Date CreatedDescription
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2020 Renesas Electronics Corporation. All rights reserved.