F118BS

MB95110B_1 FUJITSU | Alldatasheet

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DS07-12615-1EaFUJITSU MICROELECTRONICS DATA SHEET “Check Sheet” is seen at the following support page URL : http://edevice.fujitsu.com/micom/en-support/ “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Be sure to refer to the “Check Sheet” for the latest cautions on development. Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2006.12 8-bit Proprietary Microcontrollers CMOS F2MC-8FX MB95110B Series MB95116B/F118BS/F118BW/FV100D-101 ■ DESCRIPTION The MB95110B series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES

F2MC-8FX CPU core Instruction set that is optimum to the controllers Multiplication and division instructions 16-bit arithmetic operation Bit test branch instruction Bit manipulation instructions etc.
Clock Main clock Main PLL clock Sub clock (for dual clock product) Sub PLL clock (for dual clock product) (Continued)

(Continued)

Timer 8/16-bit compound timer × 2 channels 8/16-bit PPG × 2 channels 16-bit PPG Time-base timer Watch prescaler (for dual clock product)
LIN-UART Full duplex double buffer Clock asynchronous (UART) or Clock synchronous (SIO) serial data transfer capable
UART/SIO Full duplex double buffer Clock asynchronous (UART) or Clock synchronous (SIO) serial data transfer capable
I2C* Built-in wake-up function
External interrupt Interrupt by edge detecti on (rising, falling, or both edges can be selected) Can be used to recover from low-power consumption (standby) modes.
8/10-bit A/D converter 8-bit or 10-bit resolution can be selected
Low-power consumption (standby) mode Stop mode Sleep mode Watch mode (for dual clock product) Time-base timer mode
I/O port: The number of maximum ports
Single clock product : 39 ports
Dual clock product : 37 ports Port configuration
General-purpose I/O ports (N-ch open drain) : 2 ports
General-purpose I/O ports (CMOS) : Single clock product : 37 ports Dual clock product : 35 ports
Flash memory security function Protects the content of Flash memory (Flash memory device only) * : Purchase of Fujitsu I 2C components conveys a license under the Philips I2C Patent Rights to use, these com- ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.

■ PRODUCT LINEUP (Continued) Part number Parameter MB95116B MB95F118BS MB95F118BW Type MASK ROM product Flash memory product ROM capacity 32 Kbytes 60 Kbytes RAM capacity 1 Kbyte 2 Kbytes Reset output No Option*1 Clock system Selectable single/dual clock*2 Single clock Dual clock Low voltage detection reset No CPU functions Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes Data bit length : 1, 8, and 16 bits Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25MHz) Interrupt processing time : 0.6 μs (at machine clock frequency 16.25 MHz) General-purpose I/O port

Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports)
Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports) Time-base timer Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Watchdog timer Reset generated cycle At main oscillation clock 10 MHz : Minimum 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Minimum 250 ms Wild register Capable of replacing 3 bytes of ROM data I Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function UART/SIO Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable. LIN-UART Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable. LIN functions available as the LIN master or LIN slave. 8/10-bit A/D converter (8 channels) 8-bit or 10-bit resolution can be selected. Peripheral functions

(Continued) *1 : For details of option, refer to “■ MASK OPTIONS”. *2 : Specify clock mode when ordering MASK ROM. *3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of the evaluation products in MB95110B series is MB95FV100D-101. When using it, the MCU board (MB2146-301A) is required. Part number Parameter MB95116B MB95F118BS MB95F118BW 8/16-bit compound timer (2 channels) Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1 channel”. Built-in timer function, PWC function, PWM function, capture function and square wave form output Count clock : 7 internal clocks and external clock can be selected. 16-bit PPG PWM mode or one-shot mode can be selected. Counter operating clock : 8 selectable clock sources Support for external trigger start 8/16-bit PPG (2 channels) Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”. Counter operating clock : Eight selectable clock sources Watch counter (for dual clock product) Count clock : Four selectable clock sources (125ms, 250ms, 500ms, or 1s) Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) Watch prescaler (for dual clock product) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) External interrupt (8 channels) Interrupt by edge detection (rising, falling, or both edges can be selected) Can be used to recover from standby modes. Flash memory Supports automatic programming, Embedded Algorithm TM *3 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Standby mode Sleep, stop, watch (for dual clock product) , and time-base timer Peripheral functions

■ SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY) For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value of main clock oscillation stabilization wait time from among the following four values. Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabilization wait time at the maximum value. ■ PACKAGES AND CORRESPONDING PRODUCTS : Available : Unavailable * : Under development Selection of oscillation stabilization wait time Remarks (22 − 2) /FCH 0.5 μs (at main oscillation clock 4 MHz) (212 − 2) /FCH Approx. 1.02 ms (at main oscillation clock 4 MHz) (213 − 2) /FCH Approx. 2.05 ms (at main oscillation clock 4 MHz) (214 − 2) /FCH Approx. 4.10 ms (at main oscillation clock 4 MHz) Part number Package MB95116B MB95F118BS/F118BW MB95FV100D-101 LCC-48P-M09 FPT-48P-M26 FPT-52P-M01 BGA-224P-M08

■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS

Notes on Using Evaluation Products The evaluation product has not only the functions of the MB95110B corresponding products series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95110B series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or written unexpectedly). Note that the values read from barred addresses are different between the evaluation product and the Flash memory product. Therefore, the value must not be used for program. The evaluation product do not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. The evaluation, Flash memory, and MASK ROM products are designed to behave completely the same way in terms of hardware and software.
Difference of Memory Spaces If the amount of memory on the evaluation product is different from that of the Flash memory or MASK ROM product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to “■ CPU CORE”.
Current Consumption The current consumption of Flash memory product is greater than for MASK ROM product. For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
Package For details of information on each package, refer to “■ PACKAGE DIMENSIONS”.
Operating voltage The operating voltage are different among the evaluation, Flash memory, and MASK ROM products. For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
Difference between RST and MOD pins The input type of RST and MOD pins is CMOS input on the Flash memory product. The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull - down resistor is provided for the MOD pin of the MASK ROM product.

■ PIN ASSIGNMENTS (Continued) (TOP VIEW) (LCC-48P-M09) * : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product. P65/SCK P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss P06/INT06 P05/INT05 P04/INT04 P03/INT03 P02/INT02 P01/INT01 P00/INT00 RST PG1/X0A* PG2/X1A* PG0 Vcc1413 15 16 17 18 19 20 21 22 23 24 25 48 47 46 45 44 43 42 41 40 39 38 AVcc P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P51/SDA0 P50/SCL0 MOD Vss P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P15 P14/PPG0 P13/TRG0/ADTG P12/UCK0 P11/UO0 P10/UI0 P07/INT07

(Continued) (TOP VIEW) (FPT-48P-M26) * : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product. 17 18 19 20 21 22 23 24 P65/SCK P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss AVcc P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P51/SDA0 P50/SCL0 MOD Vss P06/INT06 P05/INT05 P04/INT04 P03/INT03 P02/INT02 P01/INT01 P00/INT00 RST PG1/X0A* PG2/X1A* PG0 Vcc P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P15 P14/PPG0 P13/TRG0/ADTG P12/UCK0 P11/UO0 P10/UI0 P07/INT07

(Continued) (TOP VIEW) (FPT-52P-M01) * : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product. 52 51 50 49 48 47 46 45 44 43 42 41 14 15 16 17 18 19 20 21 22 23 24 25 P65/SCK P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 NC P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss AVcc P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 NC P51/SDA0 P50/SCL0 MOD Vss P06/INT06 P05/INT05 P04/INT04 P03/INT03 P02/INT02 P01/INT01 NC P00/INT00 RST PG1/X0A* PG2/X1A* PG0 Vcc P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P15 NC P14/PPG0 P13/TRG0/ADTG P12/UCK0 P11/UO0 P10/UI0 P07/INT07

■ PIN DESCRIPTION (Continued) Pin no. Pin name I/O Circuit type*3 Function LQFP*1 LQFP*2 1 1 P65/SCK K General-purpose I/O port. The pin is shared with LIN-UART clock I/O. 2 2 P66/SOT General-purpose I/O port. The pin is shared with LIN-UART data output. 33 P 6 7 / S I N L General-purpose I/O port. The pin is shared with LIN-UART data input. 4 4 P37/AN07 J General-purpose I/O port. The pins are shared with A/D converter analog input. 5 5 P36/AN06 6 6 P35/AN05 7 8 P34/AN04 8 9 P33/AN03 91 0 P 3 2 / A N 0 2 10 11 P31/AN01 11 12 P30/AN00 12 13 AVss ⎯ A/D converter power supply pin (GND) 13 14 AVcc ⎯ A/D converter power supply pin 14 15 P24/EC0 H General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 clock input. 15 16 P23/TO01 General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.0 output. 16 17 P22/TO00 17 18 P21/PPG01 General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.0 output. 18 19 P20/PPG00 19 21 P51/SDA0 I General-purpose I/O port. The pin is shared with I 2C ch.0 data I/O. 20 22 P50/SCL0 General-purpose I/O port. The pin is shared with I2C ch.0 clock I/O. 21 23 MOD B Operating mode designation pin 22 24 X0 A Main clock input oscillation pin 23 25 X1 Main clock input/output oscillation pin 24 26 Vss ⎯ Power supply pin (GND) 25 27 Vcc ⎯ Power supply pin 26 28 PG0 H General-purpose I/O port.

(Continued) *1 : FPT-48P-M26 *2 : FPT-52P-M01 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE” Pin no. Pin name I/O Circuit type* Function LQFP*1 LQFP*2 27 29 PG2/X1A H/A This pin is general-purpose port in single clock product (PG2) . This pin is sub clock oscillation pin in dual clock product (32 kHz) . 28 30 PG1/X0A This pin is general-purpose port in single clock product (PG1) . This pin is sub clock oscillation pin in dual clock product (32 kHz) . 29 31 RST B’ Reset pin 30 32 P00/INT00 C General-purpose I/O port. The pins are shared with external interrupt input. Large current port. 31 34 P01/INT01 32 35 P02/INT02 33 36 P03/INT03 34 37 P04/INT04 35 38 P05/INT05 36 39 P06/INT06 37 40 P07/INT07 38 41 P10/UI0 G General-purpose I/O port. The pin is shared with UART/SIO ch.0 data input. 39 42 P11/UO0 H General-purpose I/O port. The pin is shared with UART/SIO ch.0 data output. 40 43 P12/UCK0 General-purpose I/O port. The pin is shared with UART/SIO ch.0 clock I/O. 41 44 P13/TRG0/ ADTG General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter trigger input (ADTG). 42 45 P14/PPG0 General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 output. 43 47 P15 General-purpose I /O port. 44 48 P60/PPG10 K General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.1 output. 45 49 P61/PPG11 46 50 P62/TO10 General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.1 output. 47 51 P63/TO11 48 52 P64/EC1 General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.1 clock input. ⎯ 7, 20, 33, 46 NC ⎯ Internal connect pin. Be sure this pin is left open.

■ I/O CIRCUIT TYPE (Continued) Type Circuit Remarks A Oscillation circuit High-speed side Feedback resistance value : approx. 1 MΩ Low-speed side Feedback resistance : approx. 24 MΩ (Evaluation product : approx. 10 MΩ) Dumping resistance : approx. 144 kΩ (Evaluation product : without dumping resistance) B Only for input Hysteresis input only for MASK ROM product With pull-down resistor only for MASK ROM product Hysteresis input only for MASK ROM product C CMOS output Hysteresis input G CMOS output CMOS input Hysteresis input With pull-up control X0 (X0A) X1 (X1A) N-ch Standby control Clock input R Mode input Reset input P-ch N-ch Standby control External interrupt enable Digital output Digital output Hysteresis input R P-ch P-ch N-ch Pull-up control Standby control Digital output Digital output Hysteresis input CMOS input

(Continued) Type Circuit Remarks H CMOS output Hysteresis input With pull-up control I N-ch open drain output CMOS input Hysteresis input J CMOS output Hysteresis input Analog input With pull-up control K CMOS output Hysteresis input L CMOS output CMOS input Hysteresis input P-ch P-ch N-ch R Pull-up control Standby control Digital output Digital output Hysteresis input N-ch Standby control Digital output Hysteresis input CMOS input R P-ch P-ch N-ch Pull-up control Analog input A/D control Standby control Digital output Digital output Hysteresis input P-ch N-ch Standby control Digital output Digital output Hysteresis input P-ch N-ch Standby control Digital output Digital output Hysteresis input CMOS input

■ HANDLING DEVICES

Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AV CC) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the VCC power-supply voltage. For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range (50 Hz/60 Hz) not to exceed 10 % of the standard V CC value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode.

■ PIN CONNECTION

Treatment of Unused Input Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open.
Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
Power Supply Pins In products with multiple V CC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the V CC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between VCC and VSS pins near this device.
Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection.
Analog Power Supply Always set the same potential to AV CC and VCC . When VCC > AVCC, the current may flow through the AN00 to AN07 pins.

■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER

Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Note: For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380
Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: Package Applicable adapter model Parallel programmers FPT-48P-M26 TEF110-118F37AP AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more) FPT-52P-M01 TEF110-95F118PMC LCC-48P-M09 TEF100-118F41AP *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. Flash memory CPU address Writer address* SA1 (4 Kbytes) 1000H 71000H 1FFFH 71FFFH SA2 (4 Kbytes) 2000H 72000H 2FFFH 72FFFH SA3 (4 Kbytes) 3000H 73000H 3FFFH 73FFFH SA4 (16 Kbytes) 4000H 74000H 7FFFH 77FFFH SA5 (16 Kbytes) 8000H 78000H BFFFH 7BFFFH SA6 (4 Kbytes) C000H 7C000H CFFFH 7CFFFH SA7 (4 Kbytes) D000H 7D000H DFFFH 7DFFFH SA8 (4 Kbytes) E000H 7E000H EFFFH 7EFFFH SA9 (4 Kbytes) F000H 7F000H FFFFH 7FFFFH Lower bankUpper bank

Programming Method 1) Set the type code of the parallel programmer to “17226”. 2) Load program data to programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer.

■ BLOCK DIAGRAM P15 P65/SCK P67/SIN AVCC AVSS P50/SCL0 P51/SDA0 P30/AN00 to P37/AN07 P12/UCK0 P62/TO10 P61/PPG11 P60/PPG10 P63/TO11 P00/INT00 to P07/INT07 P10/UI0 P64/EC1 P66/SOT RST X0,X1 P14/PPG0 P13/TRG0/ADTG P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P11/UO0 UART/SIO 16-bit PPG 8/16-bit PPG ch.0 8/10-bit A/D converter I 2C 8/16-bit PPG ch.1 ROM RAM F2MC-8FX CPU Port Port 8/16-bit compound timer ch.0 8/16-bit compound timer ch.1 Interrupt control Wild register Reset control Clock control Watch prescaler Watch counter External interrupt Internal bus PG2/X1A* PG1/X0A* PG0 LIN-UART MOD, VCC, VSS Other pins * : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.

■ CPU CORE 1. Memory space Memory space of the MB95110B series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95110B series shown in below. 0000H 0080H 0100H 0200H 0880H 0F80H 1000H FFFFH Flash memory

60 Kbytes

RAM 3.75 Kbytes MB95FV100D-101 I/O 0000H 0080H 0100H 0200H 0480H 0F80H 8000H FFFFH MASK ROM

32 Kbytes

Register The MB95110B series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.) Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register PC A T IX EP SP PS 16-bit : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial Value FFFD H 0000H 0000H 0000H 0000H 0000H 0030H PS RP CCR bit15 bit14 bit13b it12 bit11 bit10 bit9 bit8 DP2 DP1 DP0 bit7 bit6 bit5 bit4 bit3b it2 bit1 bit0 R4 R 3 R2 R1 R0 H I IL1 IL0 N Z V C DP Structure of the program status

The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. The CCR consists of the bits indicating arithmetic operation results or trans fer data contents and the bits that control CPU operations at interrupt. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 0000 H to 007FH 0000H to 007FH (without mapping) 000B (initial value) 0080H to 00FFH 0080H to 00FFH (without mapping) 001B 0100H to 017FH 010B 0180H to 01FFH 011B 0200H to 027FH 100B 0280H to 02FFH 101B 0300H to 037FH 110B 0380H to 03FFH 111B 0400H to 047FH H flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”. The flag is set to “0” when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level Priority 00 0 High Low = no interruption 01 1 10 2 11 3 N flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is set to “0”. Z flag : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise. V flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise. C flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. A7 A6 A5 A4 A 3 A2 A1 A0A15 A14 A1 3 A12 A11 A10 A9 A 8

Rule for Conversion of Actual Addresses in the General-purpose Register Area Generated address RP upper OP code lower

The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB95110B series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). This address = 0100H + 8 × (RP) Address 100H 107H 1F8H 1FFH Bank 31 Bank 0 8-bit Register Bank Configuration 32 banks Memory area 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance.

■ I/O MAP (Continued) Address Register abbreviation Register name R/W Initial value 0000H PDR0 Port 0 data register R/W 00000000 B 0001H DDR0 Port 0 direction register R/W 00000000 B 0002H PDR1 Port 1 data register R/W 00000000 B 0003H DDR1 Port 1 direction register R/W 00000000 B 0004H ⎯ (Disabled) ⎯⎯ 0005H WATR Oscillation stabilization wait time setting register R/W 11111111 B 0006H PLLC PLL control register R/W 00000000 B 0007H SYCC System clock control register R/W 1010X011 B 0008H STBC Standby control register R/W 00000000 B 0009H RSRR Reset source register R XXXXXXXX B 000AH TBTC Time-base timer control register R/W 00000000 B 000BH WPCR Watch prescaler control register R/W 00000000 B 000CH WDTC Watchdog timer control register R/W 00000000 B 000DH ⎯ (Disabled) ⎯⎯ 000EH PDR2 Port 2 data register R/W 00000000 B 000FH DDR2 Port 2 direction register R/W 00000000 B 0010H PDR3 Port 3 data register R/W 00000000 B 0011H DDR3 Port 3 direction register R/W 00000000 B 0012H, 0013H ⎯ (Disabled) ⎯⎯ 0014H PDR5 Port 5 data register R/W 00000000 B 0015H DDR5 Port 5 direction register R/W 00000000 B 0016H PDR6 Port 6 data register R/W 00000000 B 0017H DDR6 Port 6 direction register R/W 00000000 B 0018H to 0029H ⎯ (Disabled) ⎯⎯ 002AH PDRG Port G data register R/W 00000000 B 002BH DDRG Port G direction register R/W 00000000 B 002CH ⎯ (Disabled) ⎯⎯ 002DH PUL1 Port 1 pull-up register R/W 00000000 B 002EH PUL2 Port 2 pull-up register R/W 00000000 B 002FH PUL3 Port 3 pull-up register R/W 00000000 B 0030H to 0034H ⎯ (Disabled) ⎯⎯

(Continued) Address Register abbreviation Register name R/W Initial value 0035H PULG Port G pull-up register R/W 00000000 B 0036H T01CR1 8/16-bit compound timer 01 control status register 1 ch.0 R/W 00000000 B 0037H T00CR1 8/16-bit compound timer 00 control status register 1 ch.0 R/W 00000000 B 0038H T11CR1 8/16-bit compound timer 11 control status register 1 ch.1 R/W 00000000 B 0039H T10CR1 8/16-bit compound timer 10 control status register 1 ch.1 R/W 00000000 B 003AH PC01 8/16-bit PPG1 control register ch.0 R/W 00000000 B 003BH PC00 8/16-bit PPG0 control register ch.0 R/W 00000000 B 003CH PC11 8/16-bit PPG1 control register ch.1 R/W 00000000 B 003DH PC10 8/16-bit PPG0 control register ch.1 R/W 00000000 B 003EH to 0041H ⎯ (Disabled) ⎯⎯ 0042H PCNTH0 16-bit PPG status control register (Upper byte) ch.0 R/W 00000000 B 0043H PCNTL0 16-bit PPG status control register (Lower byte) ch.0 R/W 00000000 B 0044H to 0047H ⎯ (Disabled) ⎯⎯ 0048H EIC00 External interrupt circuit control register ch.0/ch.1 R/W 00000000 B 0049H EIC10 External interrupt circuit control register ch.2/ch.3 R/W 00000000 B 004AH EIC20 External interrupt circuit control register ch.4/ch.5 R/W 00000000 B 004BH EIC30 External interrupt circuit control register ch.6/ch.7 R/W 00000000 B 004CH to 004FH ⎯ (Disabled) ⎯⎯ 0050H SCR LIN-UART serial control register R/W 00000000 B 0051H SMR LIN-UART serial mode register R/W 00000000 B 0052H SSR LIN-UART serial status register R/W 00001000 B 0053H RDR/TDR LIN-UART reception/transmission data register R/W 00000000 B 0054H ESCR LIN-UART extended status control register R/W 00000100 B 0055H ECCR LIN-UART extended communication control register R/W 000000XX B 0056H SMC10 UART/SIO serial mode control register 1 ch.0 R/W 00000000 B 0057H SMC20 UART/SIO serial mode control register 2 ch.0 R/W 00100000 B 0058H SSR0 UART/SIO serial status register ch.0 R/W 00000001 B 0059H TDR0 UART/SIO serial output data register ch.0 R/W 00000000 B 005AH RDR0 UART/SIO serial input data register ch.0 R 00000000 B 005BH to 005FH ⎯ (Disabled) ⎯⎯

(Continued) Address Register abbreviation Register name R/W Initial value 0060H IBCR00 I 2C bus control register 0 ch.0 R/W 00000000 B 0061H IBCR10 I 2C bus control register 1 ch.0 R/W 00000000 B 0062H IBSR0 I 2C bus status register ch.0 R 00000000 B 0063H IDDR0 I 2C data register ch.0 R/W 00000000 B 0064H IAAR0 I 2C address register ch.0 R/W 00000000 B 0065H ICCR0 I 2C clock control register ch.0 R/W 00000000 B 0066H to 006BH ⎯ (Disabled) ⎯⎯ 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000 B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000 B 006EH ADDH 8/10-bit A/D converter data register (Upper byte) R/W 00000000 B 006FH ADDL 8/10-bit A/D converter data register (Lower byte) R/W 00000000 B 0070H WCSR Watch counter status register R/W 00000000 B 0071H ⎯ (Disabled) ⎯⎯ 0072H FSR Flash memory status register R/W 000X0000 B 0073H SWRE0 Flash memory sector writing control register 0 R/W 00000000 B 0074H SWRE1 Flash memory sector writing control register 1 R/W 00000000 B 0075H ⎯ (Disabled) ⎯⎯ 0076H WREN Wild register address compare enable register R/W 00000000 B 0077H WROR Wild register data test setting register R/W 00000000 B 0078H ⎯ (Mirror of register bank pointer (RP) and direct bank pointer (DP) ) ⎯⎯ 0079H ILR0 Interrupt level setting register 0 R/W 11111111 B 007AH ILR1 Interrupt level setting register 1 R/W 11111111 B 007BH ILR2 Interrupt level setting register 2 R/W 11111111 B 007CH ILR3 Interrupt level setting register 3 R/W 11111111 B 007DH ILR4 Interrupt level setting register 4 R/W 11111111 B 007EH ILR5 Interrupt level setting register 5 R/W 11111111 B 007FH ⎯ (Disabled) ⎯⎯ 0F80H WRARH0 Wild register address setting register (Upper byte) ch.0 R/W 00000000 B 0F81H WRARL0 Wild register address setting register (Lower byte) ch.0 R/W 00000000 B 0F82H WRDR0 Wild register data setting register ch.0 R/W 00000000 B 0F83H WRARH1 Wild register address setting register (Upper byte) ch.1 R/W 00000000 B 0F84H WRARL1 Wild register address setting register (Lower byte) ch.1 R/W 00000000 B 0F85H WRDR1 Wild register data setting register ch.1 R/W 00000000 B

(Continued) Address Register abbreviation Register name R/W Initial value 0F86H WRARH2 Wild register address setting register (Upper byte) ch.2 R/W 00000000 B 0F87H WRARL2 Wild register address setting register (Lower byte) ch.2 R/W 00000000 B 0F88H WRDR2 Wild register data setting register ch.2 R/W 00000000 B 0F89H to 0F91H ⎯ (Disabled) ⎯⎯ 0F92H T01CR0 8/16-bit compound timer 01 control status register 0 ch.0 R/W 00000000 B 0F93H T00CR0 8/16-bit compound timer 00 control status register 0 ch.0 R/W 00000000 B 0F94H T01DR 8/16-bit compound timer 01 data register ch.0 R/W 00000000 B 0F95H T00DR 8/16-bit compound timer 00 data register ch.0 R/W 00000000 B 0F96H TMCR0 8/16-bit compound timer 00/01 timer mode control register ch.0 R/W 00000000 B 0F97H T11CR0 8/16-bit compound timer 11 control status register 0 ch.1 R/W 00000000 B 0F98H T10CR0 8/16-bit compound timer 10 control status register 0 ch.1 R/W 00000000 B 0F99H T11DR 8/16-bit compound timer 11 data register ch.1 R/W 00000000 B 0F9AH T10DR 8/16-bit compound timer 10 data register ch.1 R/W 00000000 B 0F9BH TMCR1 8/16-bit compound timer 10/11 timer mode control register ch.1 R/W 00000000 B 0F9CH PPS01 8/16-bit PPG1 cycle setting buffer register ch.0 R/W 11111111 B 0F9DH PPS00 8/16-bit PPG0 cycle setting buffer register ch.0 R/W 11111111 B 0F9EH PDS01 8/16-bit PPG1 duty setting buffer register ch.0 R/W 11111111 B 0F9FH PDS00 8/16-bit PPG0 duty setting buffer register ch.0 R/W 11111111 B 0FA0H PPS11 8/16-bit PPG1 cycle setting buffer register ch.1 R/W 11111111 B 0FA1H PPS10 8/16-bit PPG0 cycle setting buffer register ch.1 R/W 11111111 B 0FA2H PDS11 8/16-bit PPG1 duty setting buffer register ch.1 R/W 11111111 B 0FA3H PDS10 8/16-bit PPG0 duty setting buffer register ch.1 R/W 11111111 B 0FA4H PPGS 8/16-bit PPG starting register R/W 00000000 B 0FA5H REVC 8/16-bit PPG output inversion register R/W 00000000 B 0FA6H to 0FA9H ⎯ (Disabled) ⎯⎯ 0FAAH PDCRH0 16-bit PPG down counter register (Upper byte) ch.0 R 00000000 B 0FABH PDCRL0 16-bit PPG down counter register (Lower byte) ch.0 R 00000000 B 0FACH PCSRH0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 R/W 11111111 B 0FADH PCSRL0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 R/W 11111111 B 0FAEH PDUTH0 16-bit PPG duty setting buffer register (Upper byte) ch.0 R/W 11111111 B 0FAFH PDUTL0 16-bit PPG duty setting buffer register (Lower byte) ch.0 R/W 11111111 B

(Continued) R/W access symbols Initial value symbols Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value. Address Register abbreviation Register name R/W Initial value 0FB0H to 0FBBH ⎯ (Disabled) ⎯⎯ 0FBCH BGR1 LIN-UART baud rate generator register 1 R/W 00000000 B 0FBDH BGR0 LIN-UART baud rate generator register 0 R/W 00000000 B 0FBEH PSSR0 UART/SIO dedicated baud rate generator prescaler selection register ch.0 R/W 00000000 B 0FBFH BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 R/W 00000000 B 0FC0H to 0FC2H ⎯ (Disabled) ⎯⎯ 0FC3H AIDRL A/D input disable register (Lower byte) R/W 00000000 B 0FC4H to 0FE2H ⎯ (Disabled) ⎯⎯ 0FE3H WCDR Watch counter data register R/W 00111111 B 0FE4H to 0FEDH ⎯ (Disabled) ⎯⎯ 0FEEH ILSR Input level select register R/W 00000000 B 0FEFH WICR Interrupt pin control register R/W 01000000 B 0FF0H to 0FFFH ⎯ (Disabled) ⎯⎯ R/W : Readable/Writable R : Read only W : Write only 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined.

■ INTERRUPT SOURCE TABLE Interrupt source Interrupt request number Vector table address Bit name of interrupt level setting register Same level priority order (at simultaneous occurrence) Upper Lower External interrupt ch.0 IRQ0 FFFA H FFFBH L00 [1 : 0] High External interrupt ch.4 External interrupt ch.1 IRQ1 FFF8 H FFF9H L01 [1 : 0] External interrupt ch.5 External interrupt ch.2 IRQ2 FFF6 H FFF7H L02 [1 : 0] External interrupt ch.6 External interrupt ch.3 IRQ3 FFF4 H FFF5H L03 [1 : 0] External interrupt ch.7 UART/SIO ch.0 IRQ4 FFF2 H FFF3H L04 [1 : 0] 8/16-bit compound timer ch.0 (Lower) IRQ5 FFF0 H FFF1H L05 [1 : 0] 8/16-bit compound timer ch.0 (Upper) IRQ6 FFEE H FFEFH L06 [1 : 0] LIN-UART (reception) IRQ7 FFEC H FFEDH L07 [1 : 0] LIN-UART (transmission) IRQ8 FFEA H FFEBH L08 [1 : 0] 8/16-bit PPG ch.1 (Lower) IRQ9 FFE8 H FFE9H L09 [1 : 0] 8/16-bit PPG ch.1 (Upper) IRQ10 FFE6 H FFE7H L10 [1 : 0] (Unused) IRQ11 FFE4 H FFE5H L11 [1 : 0] 8/16-bit PPG ch.0 (Upper) IRQ12 FFE2 H FFE3H L12 [1 : 0] 8/16-bit PPG ch.0 (Lower) IRQ13 FFE0 H FFE1H L13 [1 : 0] 8/16-bit compound timer ch.1 (Upper) IRQ14 FFDE H FFDFH L14 [1 : 0] 16-bit PPG ch.0 IRQ15 FFDC H FFDDH L15 [1 : 0] I2C ch.0 IRQ16 FFDA H FFDBH L16 [1 : 0] (Unused) IRQ17 FFD8 H FFD9H L17 [1 : 0] 8/10-bit A/D converter IRQ18 FFD6 H FFD7H L18 [1 : 0] Time-base timer IRQ19 FFD4 H FFD5H L19 [1 : 0] Watch prescaler/watch counter IRQ20 FFD2 H FFD3H L20 [1 : 0] (Unused) IRQ21 FFD0 H FFD1H L21 [1 : 0] 8/16-bit compound timer ch.1 (Lower) IRQ22 FFCE H FFCFH L22 [1 : 0] Flash memory IRQ23 FFCC H FFCDH L23 [1 : 0] Low

■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (Continued) Parameter Symbol Rating Unit RemarksMin Max Power supply voltage*1 Vcc, AVcc Vss − 0.3 Vss + 4.0 V * 2 Input voltage*1 VI1 Vss − 0.3 Vss + 4.0 V Other than P50, P51*3 VI2 Vss − 0.3 Vss + 6.0 P50, P51 Output voltage*1 VO Vss − 0.3 Vss + 4.0 V * 3 Maximum clamp current I CLAMP − 2.0 + 2.0 mA Applicable to pins* 4 Total maximum clamp current Σ|ICLAMP| ⎯ 20 mA Applicable to pins* 4 “L” level maximum output current IOL1 ⎯ 15 mA Other than P00 to P07 IOL2 15 P00 to P07 “L” level average current IOLAV1 mA Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) IOLAV2 12 P00 to P07 Average output current = operating current × operating ratio (1 pin) “L” level total maximum output current ΣIOL ⎯ 100 mA “L” level total average output current ΣIOLAV ⎯ 50 mA Total average output current = operating current × operating ratio (total of pins) “H” level maximum output current IOH1 ⎯ − 15 mA Other than P00 to P07 IOH2 − 15 P00 to P07 “H” level average current IOHAV1 − 4 mA Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) IOHAV2 − 8 P00 to P07 Average output current = operating current × operating ratio (1 pin) “H” level total maximum output current ΣIOH ⎯ − 100 mA “H” level total average output current ΣIOHAV ⎯ − 50 mA Total average output current = operating current × operating ratio (total of pins) Power consumption Pd ⎯ 320 mW Operating temperature T A − 40 + 85 °C Storage temperature Tstg − 55 + 150 °C

(Continued) *1 : The parameter is based on AV CC = VSS = 0.0 V. *2 : Apply equal potential to AVcc and Vcc. *3 : V I1 and VO should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI1 rating. *4 : • Applicable to pins : P00 to P07, P10 to P15, P20 to P24, P30 to P37, PG0

Use within recommended operating conditions.
Use at DC voltage (current).
+ B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller.
The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result.
Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the + B input pin open.
Sample recommended circuits : WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. P-ch N-ch Vcc R Input/Output Equivalent Circuits + B input (0 V to 16 V) Limiting resistance Protective diode

Recommended Operating Conditions (AVSS = VSS = 0.0 V) * : The values vary with the operating frequency. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply voltage VCC, AVCC 1.8* ⎯ 3.3 V At normal operating, Flash memory product, T A = − 10 °C to + 85 °C 1.8* ⎯ 3.6 At normal operating, MASK ROM product, T A = − 10 °C to + 85 °C 2.0* ⎯ 3.3 At normal operating, Flash memory product, T A = − 40 °C to + 85 °C 2.0* ⎯ 3.6 At normal operating, MASK ROM product, T A = − 40 °C to + 85 °C 2.6 ⎯ 3.6 MB95FV100D-101, TA = + 5 °C to + 35 °C 1.5 ⎯ 3.3 Retain status of stop mode operation, Flash memory product 1.5 ⎯ 3.6 Retain status of stop mode operation, MASK ROM product Operating temperature T

DC Characteristics (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) (Continued) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max “H” level input voltage VIH1 P10, P67 *1 0.7 Vcc ⎯ Vcc + 0.3 V At selecting of CMOS input level (hysteresis input) V IH2 P50, P51 *1 0.7 Vcc ⎯ Vss + 5.5 V At selecting of CMOS input level (hysteresis input) V IHS1 P00 to P07, P10 to P15, P20 to P24, P30 to P37, P60 to P67, PG0, PG1* PG2*1 *1 0.8 Vcc ⎯ Vcc + 0.3 V Hysteresis input VIHS2 P50, P51 *1 0.8 Vcc ⎯ Vss + 5.5 V Hysteresis input VIHM RST, MOD ⎯ 0.7 Vcc ⎯ Vcc + 0.3 V CMOS input (Flash memory product) ⎯ 0.8 Vcc ⎯ Vcc + 0.3 V Hysteresis input (MASK ROM product) “L” level input voltage V IL P10, P50, P51, P67 *1 Vss − 0.3 ⎯ 0.3 Vcc V At selecting of CMOS input level (hysteresis input) V ILS P00 to P07, P10 to P15, P20 to P24, P30 to P37, P50, P51, P60 to P67, PG0, PG1* PG2*1 *1 Vss − 0.3 ⎯ 0.2 Vcc V Hysteresis input VILM RST, MOD ⎯ Vss − 0.3 ⎯ 0.3 Vcc V CMOS input (Flash memory product) ⎯ Vss − 0.3 ⎯ 0.2 Vcc V Hysteresis input (MASK ROM product) Open drain output application voltage V D P50, P51 ⎯ Vss − 0.3 ⎯ Vss + 5.5 V

(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) (Continued) Parameter Sym- bol Pin name Conditions Value Unit Remarks Min Typ Max “H” level output voltage VOH1 Output pin other than P00 to P07 I OH = − 4.0 mA 2.4 ⎯⎯ V MB95FV100D-101 a conditional : I OH = − 2.0 mA VOH2 P00 to P07 IOH = − 8.0 mA 2.4 ⎯⎯ V MB95FV100D-101 a conditional : I OH = − 5.0 mA “L” level output voltage VOL1 Output pin other than P00 to P07 I OL = 4.0 mA ⎯⎯ 0.4 V MB95FV100D-101 a conditional : I OL = 3.0 mA VOL2 P00 to P07 I OL = 12 mA ⎯⎯ 0.4 V MB95FV100D-101 a conditional : I OL = 8.0 mA Input leakage current (Hi-Z output leakage current) I LI Port other than P50, P51

0.0 V < V

I < Vcc − 5 ⎯ + 5 μA When no pull-up prohibition setting Open drain output leakage current I LIOD P50, P51 0.0 V < VI < Vss + 5.5 V ⎯⎯ 5 μA Pull-up resistor R PULL P10 to P15, P20 to P24, P30 to P37, PG0, PG1* PG2*2 VI = 0.0 V 25 50 100 k Ω When pull-up permission setting Pull-down resistor R MOD MOD V I = Vcc 50 100 200 k Ω MASK ROM product Power supply current*3 ICC VCC (external clock operation) F CH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) ⎯ 11 14 mA Flash memory product (at other than Flash memory writing and erasing) ⎯ 7.3 10 mA Flash memory product (at Flash memory writing and erasing) ⎯ 30 35 mA MASK ROM product

(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) (Continued) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply current*3 ICC VCC (external clock operation) F CH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) ⎯ 17.6 22.4 mA Flash memory product (at other than Flash memory writing and erasing) ⎯ 38.1 44.9 mA Flash memory product (at Flash memory writing and erasing) ⎯ 11.7 16.0 mA MASK ROM product I CCS FCH = 20 MHz FMP = 10 MHz Main sleep mode (divided by 2) ⎯ 4.5 6 mA F CH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) ⎯ 7.2 9.6 mA I CCL FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) , T A = + 25 °C ⎯ 25 35 μA ICCLS FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , T A = + 25 °C ⎯ 71 5 μA ICCT FCL = 32 kHz Watch mode Main stop mode T A = + 25 °C ⎯ 21 0 μA Flash memory product ⎯ 15 μA MASK ROM product ICCMPLL FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) ⎯ 10 14 mA Flash memory product ⎯ 6.7 10 mA MASK ROM product F CH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) ⎯ 16.0 22.4 mA Flash memory product ⎯ 10.8 16.0 mA MASK ROM product

(Continued) (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) *1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”. The switching of the input level can be set by the input level selection register (ILSR). *2 : Single clock products only *3 : The power-supply current is determined by the external clock.

Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL.
Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for fMP and fMPL. Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply current*3 ICCSPLL VCC (external clock operation) F CL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 °C ⎯ 190 250 μA ICTS FCH = 10 MHz Time-base timer mode T A = + 25 °C ⎯ 0.4 0.5 mA ICCH Sub stop mode TA = + 25 °C ⎯ 15 μA IA AVcc FCH = 10 MHz At A/D converting ⎯ 1.3 2.2 mA IAH FCH = 10 MHz At A/D converting stop T A = + 25 °C ⎯ 15 μA Input capacitance CIN Other than AVcc, AVss, Vcc, and Vss f = 1 MHz ⎯ 51 5 p F

AC Characteristics (1) Clock Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Sym- bol Pin Condi- tions Value Unit Remarks Min Typ Max Clock frequency FCH X0, X1 1.00 ⎯ 16.25 MHz When using main oscillation circuit 1.00 ⎯ 32.50 MHz When using external clock 3.00 ⎯ 10.00 MHz Main PLL multiplied by 1 3.00 ⎯ 8.13 MHz Main PLL multiplied by 2 3.00 ⎯ 6.50 MHz Main PLL multiplied by 2.5 3.00 ⎯ 4.06 MHz Main PLL multiplied by 4 FCL X0A, X1A ⎯ 32.768 ⎯ kHz When using sub oscillation circuit ⎯ 32.768 ⎯ kHz When using sub PLL Flash memory product : Vcc = 2.3 V to 3.3 V MASK ROM product : Vcc = 2.3 V to 3.6 V Clock cycle time t HCYL X0, X1 100 ⎯ 1000 ns When using main oscillation circuit 50 ⎯ 1000 ns When using external clock tLCYL X0A, X1A ⎯ 30.5 ⎯μ s When using sub oscillation circuit, When using external clock Input clock pulse width t WH1 tWL1 X0 10 ⎯⎯ ns When using external clock Duty ratio is about 30% to 70%.tWH2 tWL2 X0A ⎯ 15.2 ⎯μ s Input clock rise time and fall time tCR tCF X0, X0A ⎯⎯ 5 ns When using external clock

0.2 VCC

X0 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tCF tWL1

Input Wave form when using External Clock (Main clock) X0 X1 FCH FCH Microcontroller Microcontroller C1 C2
Figure of Main Clock Input Port External Connection When using a crystal or ceramic oscillator When using external clock Open tLCYL tWH2 tCR

0.1 VCC

X0A 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC tCF tWL2

Input Wave form when using External Clock (Sub clock) X0A X1A FCL X0A FCL X1A Microcontroller Microcontroller C1 C2
Figure of Sub clock Input Port External Connection When using a crystal or ceramic oscillator When using external clock Open

(2) Source Clock/Machine Clock (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follow.

Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5 4 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication) 2 : Operation clock of the microcontroller. Machine clock can be selected as follow.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16 Parameter Sym- bol Pin name Value Unit Remarks Min Typ Max Source clock*1 (Clock before setting division) tSCLK ⎯ 61.5 ⎯ 2000 ns When using Main clock Min : FCH = 8.125 MHz, PLL multiplied by 2 Max : FCH = 1 MHz, divided by 2 7.6 ⎯ 61.0 μs When using Sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2 Source clock frequency FSP ⎯ 0.5 ⎯ 16.25 MHz When using Main clock FSPL ⎯ 16.38 4 ⎯ 131.072 kHz When using Sub clock Machine clock*2 (Minimum instruction execution time) tMCLK ⎯ 100 ⎯ 32000 ns When using Main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 7.6 ⎯ 976.5 μs When using Sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16 Machine clock frequency FMP 0.031 ⎯ 16.250 MHz When using Main clock FMPL 1.024 ⎯ 131.072 kHz When using Sub clock

Outline of clock generation block FCH (main oscillation) FCL (sub oscillation) Divided by 2 Main PLL × 1 × 2 × 2.5 × 4 Divided by 2 Sub PLL × 2 × 3 × 4 SCLK ( source clock ) MCLK ( machine clock ) Clock mode select bit ( SYCC : SCS1, SCS0 ) Division circuit × 1 × 1/4 × 1/8 × 1/16

Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
MB95116B
MB95F118BS, MB95F118BW 131.072 kHz16.384 kHz 1.8 3.6 2.3 32 kHz 16.25 MHz0.5 MHz 3.6 1.8

5 MHz3 MHz

2.7 Sub PLL operation guarantee range Source clock frequency (FSP) Operating voltage (V) Sub clock mode and watch mode operation guarantee range PLL operation guarantee range Source clock frequency (FSP) Operating voltage (V) PLL operation guarantee range Main clock operation guarantee range Main clock mode and main PLL mode operation guarantee range 131.072 kHz16.384 kHz 1.8 3.3 2.3 32 kHz 16.25 MHz0.5 MHz 3.3 1.8

10 MHz3 MHz

2.7

5 MHz

Sub PLL operation guarantee range Source clock frequency (FSP) Operating voltage (V) Sub clock mode and watch mode operation guarantee range PLL operation guarantee range Source clock frequency (FSP) Operating voltage (V) PLL operation guarantee range Main clock operation guarantee range Main clock mode and main PLL mode operation guarantee range

Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C)
MB95116B
MB95F118BS, MB95F118BW 131.072 kHz16.384 kHz 2.0 3.6 2.3 32 kHz 16.25 MHz0.5 MHz 3.6 2.0

7.5 MHz3 MHz

Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
MB95FV100D-101 10 MHz 16.25 MHz0.5 MHz 2.6

3 MHz

3.6 3.3 131.072 kHz16.384 kHz 2.6 32 kHz 3.6 Operating voltage (V) Operating voltage (V) Source clock frequency (FSP) Main clock operation guarantee range PLL operation guarantee rangePLL operation guarantee range Source clock frequency (FSP) Sub PLL , Sub clock mode and watch mode operation guarantee range Main clock mode and main PLL mode operation guarantee range

Main PLL operation frequency [MHz] 16.25 7.5 0 3 4 4.062 5 6.4 6.5 8.125 10 [MHz] Main clock frequency (FMP) Source clock frequency (FSP) × 2.5 × 2 × 1 × 4

(3) External Reset (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) *1 : Refer to “ (2) Source Clock/Machine Clock” for t MCLK. *2 : Oscillation time of oscillator is th e time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of μs and several ms. In the external clock, the oscillation time is 0 ms. Parameter Symbol Value Unit Remarks Min Max RST “L” level pulse width tRSTL 2 tMCLK*1 ⎯ ns At normal operating Oscillation time of oscillator*2 + 2 tMCLK*1 ⎯ ns At stop mode, sub clock mode, sub sleep mode, and watch mode tRSTL 0.2 VCC 0.2 VCC 2 tMCLK RST Oscillation stabilization wait time Execute instruction Oscillation time of oscillator 90% of amplitude Internal operating clock Internal reset

At normal operating
At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on

(4) Power-on Reset (AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Note : The power supply must be turned on within the selected oscillation stabilization time. Note : Sudden change of power supply voltage may acti vate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 20 mV/ms as shown below. Parameter Symbol Conditions Value Unit Remarks Min Max Power supply rising time t R ⎯⎯ 36 ms Power supply cutoff time t OFF ⎯ 1 ⎯ ms Waiting time until power-on 0.2 V0.2 V tOFFtR 1.5 V

0.2 VVCC

1.5 V VSS Limiting the slope of rising within 20 mV/ms is recommended. Hold condition in stop mode

(5) Peripheral Input Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Symbol Pin name Value Unit Min Max Peripheral input “H” pulse width tILIH INT00 to INT07, EC0, EC1, TRG0/ADTG 2 tMCLK* ⎯ ns Peripheral input “L” pulse width tIHIL 2 tMCLK* ⎯ ns tILIH INT00 to INT07, EC0, EC1, TRG0/ADTG 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tIHIL

(6) UART/SIO, Serial I/O Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Symbol Pin name Conditions Value Unit Min Max Serial clock cycle time t SCYC UCK0 Internal clock operation output pin : CL = 80 pF + 1 TTL. 4 tMCLK* ⎯ ns UCK ↓ → UO time t SLOV UCK0, UO0 − 190 + 190 ns Valid UI → UCK ↑ tIVSH UCK0, UI0 2 t MCLK* ⎯ ns UCK ↑ → valid UI hold time t SHIX UCK0, UI0 2 t MCLK* ⎯ ns Serial clock “H” pulse width t SHSL UCK0 External clock operation output pin : CL = 80 pF + 1 TTL. 4 tMCLK* ⎯ ns Serial clock “L” pulse width t SLSH UCK0 4 t MCLK* ⎯ ns UCK ↓ → UO time t SLOV UCK0, UO0 ⎯ 190 ns Valid UI → UCK ↑ tIVSH UCK0, UI0 2 t MCLK* ⎯ ns UCK ↑ → valid UI hold time t SHIX UCK0, UI0 2 t MCLK* ⎯ ns tSCYC tIVSH

0.8 VCC

0.8 V 2.4 V 0.8 V 2.4 V UCK0 UO0 UI0 0.8 V tSLSH tIVSH tSHIX tSLOV 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC tSHSL 2.4 V UCK0 UO0 UI0 0.8 V

Internal shift clock mode
External shift clock mode

(7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Sym- bol Pin name Conditions Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operation output pin : CL = 80 pF + 1 TTL 5 tMCLK*3 ⎯ ns SCK ↑→ SOT delay time t SLOVI SCK, SOT − 95 + 95 ns Valid SIN→SCK↑ tIVSHI SCK, SIN t MCLK*3 + 190 ⎯ ns SCK↑→ valid SIN hold time t SHIXI SCK, SIN 0 ⎯ ns Serial clock “L” pulse width t SLSH SCK External clock operation output pin : CL = 80 pF + 1 TTL 3 tMCLK*3 − tR ⎯ ns Serial clock “H” pulse width t SHSL SCK t MCLK*3 + 95 ⎯ ns SCK ↓→SOT delay time t SLOVE SCK, SOT ⎯ 2 tMCLK*3 + 95 ns Valid SIN→SCK↑ tIVSHE SCK, SIN 190 ⎯ ns SCK↑→ valid SIN hold time t SHIXE SCK, SIN t MCLK*3 + 95 ⎯ ns SCK fall time t F SCK ⎯ 10 ns SCK rise time t R SCK ⎯ 10 ns

0.8 V0 . 8 V 2.4 V tSLOVI tIVSHI tSHIXI 2.4 V 0.8 V SCK SOT SIN tSCYC 2.4 V 0.8 V tRtF SCK SOT SIN tSLSH tSHSL 0.8 VCC 0.8 VCC0.8 VCC 0.2 VCC 0.2 VCC Internal shift clock mode External shift clock mode

Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Sym- bol Pin name Conditions Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operation output pin : CL = 80 pF + 1 TTL 5 tMCLK*3 ⎯ ns SCK↑→ SOT delay time t SHOVI SCK, SOT − 95 + 95 ns Valid SIN→SCK↓ tIVSLI SCK, SIN t MCLK*3 + 190 ⎯ ns SCK↓→ valid SIN hold time t SLIXI SCK, SIN 0 ⎯ ns Serial clock “H” pulse width t SHSL SCK External clock operation output pin : CL = 80 pF + 1 TTL 3 tMCLK*3 − tR ⎯ ns Serial clock “L” pulse width t SLSH SCK t MCLK*3 + 95 ⎯ ns SCK↑ →SOT delay time t SHOVE SCK, SOT ⎯ 2 tMCLK*3 + 95 ns Valid SIN→SCK↓ tIVSLE SCK, SIN 190 ⎯ ns SCK↓→ valid SIN hold time t SLIXE SCK, SIN t MCLK*3 + 95 ⎯ ns SCK fall time t F SCK ⎯ 10 ns SCK rise time t R SCK ⎯ 10 ns

0.8 V 2.4 V 2.4 V tSHOVI tIVSLI tSLIXI 2.4 V 0.8 V SCK SOT SIN tSCYC 0.2 VCC 0.2 VCC0.2 VCC tSHOVE tIVSLE tSLIXE 2.4 V 0.8 V tFtR SCK SOT SIN tSHSL tSLSH 0.8 VCC 0.8 VCC Internal shift clock mode External shift clock mode

Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Sym- bol Pin name Conditions Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operation output pin : CL = 80 pF + 1 TTL 5 tMCLK*3 ⎯ ns SCK↑→ SOT delay time t SHOVI SCK, SOT − 95 + 95 ns Valid SIN→SCK↓ tIVSLI SCK, SIN t MCLK*3 + 190 ⎯ ns SCK↓→ valid SIN hold time t SLIXI SCK, SIN 0 ⎯ ns SOT→SCK↓ delay time t SOVLI SCK, SOT ⎯ 4 tMCLK*3 ns SCK SOT SIN 2.4 V 0.8 V 0.8 VtSHOVI 2.4 V 0.8 V 2.4 V 0.8 V tSCYC tSOVLI tIVSLI tSLIXI

Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Sym- bol Pin name Conditions Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operating output pin : CL = 80 pF + 1 TTL 5 tMCLK*3 ⎯ ns SCK↓→SOT hold time t SLOVI SCK, SOT − 95 + 95 ns Valid SIN→SCK↑ tIVSHI SCK, SIN t MCLK*3 + 190 ⎯ ns SCK↑ → valid SIN hold time t SHIXI SCK, SIN 0 ⎯ ns SOT→SCK↑ delay time t SOVHI SCK, SOT ⎯ 4 tMCLK*3 ns SCK SOT SIN 2.4 V 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V 2.4 V 0.8 V tSCYC tSOVHI tIVSHI tSHIXI

(8) I2C Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum t HD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. Parameter Symbol Pin name Conditions Value UnitStandard- mode Fast-mode Min Max Min Max SCL clock frequency f SCL SCL0 R = 1.7 kΩ, C = 50 pF*1 01 0 004 0 0 k H z (Repeat) Start condition hold time SDA ↓ → SCL ↓ tHD;STA SCL0 SDA0 4.0 ⎯ 0.6 ⎯μ s SCL clock “L” width t LOW SCL0 4.7 ⎯ 1.3 ⎯μ s SCL clock “H” width t HIGH SCL0 4.0 ⎯ 0.6 ⎯μ s (Repeat) Start condition setup time SCL ↑ → SDA ↓ tSU;STA SCL0 SDA0 4.7 ⎯ 0.6 ⎯μ s Data hold time SCL ↓ → SDA ↓ ↑ tHD;DAT SCL0 SDA0 03 . 4 5 * 2 00 . 9 * 3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSU;DAT SCL0 SDA0 0.25 ⎯ 0.1 ⎯μ s Stop condition setup time SCL ↑ → SDA ↑ tSU;STO SCL0 SDA0 4 ⎯ 0.6 ⎯μ s Bus free time between stop condition and start condition tBUF SCL0 SDA0 4.7 ⎯ 1.3 ⎯μ s SDA0 SCL0 tWAKEUP tHD;STA tHD;DAT tHD;STA tSU;STA tLOW tSU;DAT tHIGH tSU;STO tBUF

(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) (Continued) Parameter Sym- bol Pin name Condition Value*2 Unit Remarks Min Max SCL clock “L” width t LOW SCL0 R = 1.7 kΩ, C = 50 pF*1 (2 + nm / 2) tMCLK − 20 ⎯ ns Master mode SCL clock “H” width t HIGH SCL0 (nm / 2) tMCLK − 20 (nm / 2 ) tMCLK + 20 ns Master mode Start condition hold time tHD;STA SCL0 SDA0 (−1 + nm / 2) tMCLK − 20 ( −1 + nm) tMCLK + 20 ns Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Stop condition setup time tSU;STO SCL0 SDA0 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode Start condition setup time tSU;STA SCL0 SDA0 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode Bus free time between stop condition and start condition tBUF SCL0 SDA0 (2 nm + 4) tMCLK − 20 ⎯ ns Data hold time t HD;DAT SCL0 SDA0 3 tMCLK − 20 ⎯ ns Master mode Data setup time t SU;DAT SCL0 SDA0 (−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Setup time between clearing interrupt and SCL rising t SU;INT SCL0 (nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to interrupt at 8th SCL↓. SCL clock “L” width t LOW SCL0 4 tMCLK − 20 ⎯ ns At reception SCL clock “H” width t HIGH SCL0 4 tMCLK − 20 ⎯ ns At reception Start condition detection tHD;STA SCL0 SDA0 2 tMCLK − 20 ⎯ ns Undetected when 1 tMCLK is used at reception Stop condition detection tSU;STO SCL0 SDA0 2 tMCLK − 20 ⎯ ns Undetected when 1 tMCLK is used at reception Restart condition detection condition tSU;STA SCL0 SDA0 2 tMCLK − 20 ⎯ ns Undetected when 1 tMCLK is used at reception Bus free time t BUF SCL0 SDA0 2 tMCLK − 20 ⎯ ns At reception Data hold time t HD;DAT SCL0 SDA0 2 tMCLK − 20 ⎯ ns At slave transmission mode Data setup time t SU;DAT SCL0 SDA0 tLOW − 3 tMCLK − 20 ⎯ ns At slave transmission mode

(Continued) *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.

m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register.
Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < t MCLK ≤ 1 MHz (m, n) = (1, 98) : 0.9 MHz < t MCLK ≤ 10 MHz
Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. MCLK ≤ 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < t MCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < t MCLK ≤ 10 MHz Parameter Sym- bol Pin name Condition Value*2 Unit Remarks Min Max Data hold time t HD;DAT SCL0 SDA0 R = 1.7 kΩ, C = 50 pF*1 0 ⎯ ns At reception Data setup time t SU;DAT SCL0 SDA0 tMCLK − 20 ⎯ ns At reception SDA↓→SCL↑ (at wake-up function) tWAKEUP SCL0 SDA0 Oscillation stabilization wait time + 2 tMCLK − 20 ⎯ ns

A/D Converter (1) A/D Converter Electrical Characteristics (AVcc = Vcc = 1.8 V to 3.3 V [Flash memory product], AVcc = Vcc = 1.8 V to 3.6 V [MASK ROM product], AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Sym- bol Value Unit Remarks Min Typ Max Resolution ⎯⎯ 10 bit Total error − 3.0 ⎯ + 3.0 LSB Linearity error − 2.5 ⎯ + 2.5 LSB Differential linear error − 1.9 ⎯ + 1.9 LSB Zero transition voltage VOT AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB V Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V Full-scale transition voltage V FST AVcc − 3.5 LSB AVcc − 1.5 LSB AVcc + 0.5 LSB V Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V Compare time ⎯ 1.3 ⎯ 140 μs Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V 20 ⎯ 140 μs 1.8 V ≤ AVcc < 2.7 V Sampling time ⎯ 0.4 ⎯ ∞ μs Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V external impedance < at 1.8 kΩ 30 ⎯ ∞ μs 1.8 V ≤ AVcc < 2.7 V external impedance < at 14.8 kΩ Analog input current I AIN −0.3 ⎯ + 0.3 μA Analog input voltage VAIN AVss ⎯ AVcc V Reference voltage ⎯ AVss + 1.8 ⎯ AVcc V AVcc pin Reference voltage supply current IR ⎯ 400 600 μA AVcc pin, During A/D operation IRH ⎯⎯ 5 μA AVcc pin, at stop mode

(2) Notes on Using A/D Converter

About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
About errors As |AV CC − AVSS| becomes smaller, values of relative errors grow larger. R C During sampling : ON Analog input pin Comparator Note : The values are reference values.
Analog input equivalent circuit RC 2.7 V ≤ AVcc ≤ 3.6 V 1.7 k Ω (Max) 14.5 pF (Max) 1.8 V ≤ AVcc < 2.7 V 84 k Ω (Max) 25.2 pF (Max) 0 5 10 15 20 25 30 35 40 100 01234 (External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ) Minimum sampling time [μs] External impedance [kΩ] Minimum sampling time [μs] External impedance [kΩ]
The relationship between external impedance and minimum sampling time AVcc ≥ 2.7 V AVcc ≥ 1.8 V AVcc ≥ 2.7 V

(3) Definition of A/D Converter Terms Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained. Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (Continued) VFST

1.5 LSB

1 LSB

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

1 LSB = AVCC − AVSS

[LSB]Total error of digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB} Ideal I/O characteristics Total error Digital output Digital output Analog input Analog input N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) to N. (V) Actual conversion characteristic Actual conversion characteristic Ideal characteristics

(Continued) AVSS AVCC 001H 002H 003H 004H AVSS AVCC 3FCH 3FDH 3FEH 3FFH AVSS AVCC 001H 002H 003H 004H 3FDH 3FEH 3FFH {1 LSB × N + VOT} VNT AVSS AVCC VNT N − 2H N − 1H NH N + 1H V (N + 1) T Full-scale transition error Digital output Analog input Zero transition error Digital output Analog input Differential linear errorLinearity error Digital output Digital output Analog inputAnalog input Linear error in digital output N = VNT − {1 LSB × N + VOT} N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVCC − 1.5 LSB [V] Differential linear error in digital output N = V (N + 1) T − VNT

1 LSB − 1

VOT (measurement value) Ideal characteristics Actual conversion characteristic Actual conversion characteristic Ideal characteristics VFST (measurement value) Actual conversion characteristic Actual conversion characteristic Ideal characteristics VFST (measurement value) VOT (measurement value) Actual conversion characteristic Actual conversion characteristic Ideal characteristics

Flash Memory Program/Erase Characteristics *1 : T A = +25 °C, Vcc = 3.0 V, 10000 cycles *2 : T A = +85 °C, Vcc = 2.7 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . Parameter Value Unit Remarks Min Typ Max Sector erase time (4 Kbytes sector) ⎯ 0.2*1 3.0*2 s Excludes 00 H programming prior erasure Sector erase time (16 Kbytes sector) ⎯ 0.5*1 12.0*2 s Excludes 00 H programming prior erasure Byte programming time ⎯ 32 3600 μs Excludes system-level overhead Erase/program cycle 10000 ⎯⎯ cycle Power supply voltage at erase/program 2.7 ⎯ 3.3 V Flash data retention time 20* 3 ⎯⎯ year Average T A = +85 °C

■ MASK OPTIONS * : Low voltage detection reset is options of 5-V products. ■ ORDERING INFORMATION No Part number MB95116B MB95F118BS MB95F118BW MB95FV100D-101 Specifying procedure Specify when ordering MASK Setting disabled Setting disabled Setting disabled Clock mode select

Single-system clock mode
Dual-system clock mode Selectable Single-system clock mode Dual-system clock mode Changing by the switch on MCU board Low voltage detection reset*
With low voltage detection reset
Without low voltage detection reset No No No No Selection of oscillation stabilization wait time
Selectable the initial value of main clock oscillation stabilization wait time Selectable 1 : ( 2 2 − 2) /FCH Fixed to oscillation stabilization wait time of 14-2) /FCH Fixed to oscillation stabilization wait time of 14-2) /FCH Fixed to oscillation stabilization wait time of 14-2) /FCH Part number Package MB95116BPV2 MB95F118BSPV2 MB95F118BWPV2 48-pin plastic BCC (LCC-48P-M09) MB95116BPMT MB95F118BSPMT MB95F118BWPMT 48-pin plastic LQFP (FPT-48P-M26) MB95116BPMC MB95F118BSPMC MB95F118BWPMC 52-pin plastic LQFP (FPT-52P-M01) MB2146-301A (MB95FV100D-101PBT) MCU board 224-pin plastic PFBGA (BGA-224P-M08)

■ PACKAGE DIMENSIONS Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 48-pin plastic BCC Le ad pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Sealing method Pl astic mold Mounting height 0. 80 mm Max Weight 0.06 g 48-pin plastic BCC (LCC-48P-M09) (LCC-48P-M09) C 2004 FUJITSU LIMITED C48062S-c-1-1 113 3725 5.00(.197) REF 6.25(.246) REF "C" "B" "A" 6.25(.246)REF 6.20(.244) TYP 0.50±0.10 TYP 5.00(.197)REF 6.20(.244)TYP 0.075±0.025 (.003±.001) 2537 (Stand off) 7.00±0.10 (.276±.004) 0.05(.002) Details of "C" part 0.55±0.06 (.022±.002) 0.55±0.06 (.022±.002) INDEX AREA Details of "A" part (.026±.002) 0.65±0.06 (.012±.002) 0.30±0.06 C0.2(.008) Details of "B" part 0.14(.006) MIN (Mount height) (.030±.002) 0.75±0.05 TYP 0.50(.020) 0.50±0.10 (.020±.004) 0.55±0.06 (.022±.002) 0.55±0.06 (.022±.002) (8-.024±.002) 8-0.60±0.06 6.15(.242)TYP 6.15(.242) TYP Dimensions in mm (inches). Note: The values in parentheses are reference values.

Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 48-pin plastic LQFP Le ad pitch 0.50 mm Package width × package length 7 × 7 mm Lead shape G ullwing Sealing method Pl astic mold Mounting height 1.70 mm MAX Weight 0.17 g Code (Reference) P-LFQFP48-7×7-0.50 48-pin plastic LQFP (FPT -48P-M26) (FPT-48P-M26) C 2003 FUJITSU LIMITED F48040S-c-2-2 362 5 INDEX SQ 0.145±0.055 (.006±.002) 0.08(.003) "A" 0˚~8˚ .059 –.004 +.008 –0.10 +0.20 1.50 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) Details of "A" part 1 12 0.08(.003) M (.008±.002) LEAD No. (Mounting height) .276 –.004 +.016 –0.10 +0.40 7.00* Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

(Continued) Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 52-pin plastic LQFP Le ad pitch 0.65 mm Package width × package length 10.0 × 10.0 mm Lead shape G ullwing Sealing method Pl astic mold Mounting height 1.70 mm Max Code (Reference) P-LQFP52-10×10-0.65 52-pin plastic LQFP (FPT-52P-M01) (FPT-52P-M01) LEAD No. Details of "A" part 0.25(.010) (Stand off) (.004±.004) 0.10±0.10 (.024±.006) 0.60±0.15 (.020±.008) 0.50±0.20 1.50 +0.20 –0.10 +.008 –.004.059 0˚~8˚ "A" 0.10(.004) (.006±.002) 0.145±0.055 0.13(.005) M 0.65(.026) INDEX 2739 131

2005 FUJITSU LIMITED F52001S-c-1-1C

(Mounting height) .012 –.0014 +.0027 –0.035 +0.065 0.30 Dimensions in mm (inches). Note: The values in parentheses are reference values Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

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Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD.

151 Lorong Chuan, #05-08 New Tech Park,

Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Y an An Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F ., World Commerce Centre, 11 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat- ing the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FU JITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic c ontrol, mass transport control, me dical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent ch ance of failure. You must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Strategic Business Development Dept.

Summary

8-bit Proprietary Microcontrollers

Description