F100363

F100363 NSC | Alldatasheet

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S National 3 Semiconductor ° Low Power Dual 8-Input Multiplexer General Description Features The F100163 is a dual 8-input multiplexer. The Data Select ™ 50% power reduction of the F100163 {Sp) inputs determine which bit (A, and B,) will be present- @ 2000V ESD protection ed at the outputs (Za and Zp respectively). The same bit Pin/function compatible with F100163 {0-7) will be selected for both the Zz and Zp output. All Voltage compensated operating range - —4.2V to inputs have 50 kQ. pulldown resistors. =5.7V ‘@ Tighter min to max propagation delay than F100163 Ordering Code: see sections Logic Symbol [_Pinmiames [Description | So-S2 Data Select Inputs gt At Az Aa Re Ae Ae Ar Bp Di Be Os Ba Be Os Or Ag-Az A Data Inputs ss Bo-B7 B Data Inputs i Boy Za Zp Data Outputs TUF No612-1 Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak I Mg As AaVers As Ap Ay By Sp Sy Vex Sp Ay ast 2a, {anf feafespeafesfes| J 42 23-85, 843 22-6, 4B [ony naa i ig aa ribs Ry] oy hoon Mig 7 rac) Veca as bay as abs, Pat ae ne a Veo“ 6 19s, 3, Boe Bas i) td Vecaq7 18 Vee 2@ Az, as 18h ay a8 17h s9 eB Bey 789 10 1112 roe 16h, Afio sha em eee fe Te Wecton te Aq thas Og Bs OyVersBs By 8 TL/F/10612-3 asf sha, TUF/10612-4 TUF/H0812-2 2-135

3 Logic Diagram

r Bo 8: Bz Bs Ba Bs Bs 87 So Si Sz Ao Ar Az As Aa As Ag Ar he ae a a , ee | Pe PA $d itl | 2 2 TUF /10612-5 Truth Table s[s[s(Slslelsfelelels| & Be Bo L L L L L L L L H H L L H L L L L H H H L H L L L L H L H H L H H L L L H H H H H L L L L H L L H H H L H L L H| LH H H H L L L H L H H H H L L H H H H H = HIGH Voltage Level L = LOW Voltage Level Blank = X = Don't Care 2-136

Absolute Maximum Ratings Recommended Operating 3 Above which the useful life may be impared (Note 1) Conditions 8 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Case Temperature ture) vot 108°C Office/Distributors for availability and specifications. Military —55°C to +125°C ‘Storage Temperature (Tstg) 65°C to + 150°C Supply Voltage (Vee) Maximum Junction Temperature (Ty) Commercial —5.7Vto ~4.2V Ceramic +175°C Military -5.7V to -4.2V Plastic +150°C Vee Pin Potential to Ground Pin —7.0V to +0.5V Input Voltage (DC) Veg to + 0.5V Output Current (DC Output HIGH) —50 mA ESD (Note 2) > 2000V Commercial Version Vee = —4.2V to -5.7V, Voc = Voca = GND, Tc = 0°C to +85°C (Note 3) symbol [Parameter | min | typ | Max | units | Conditions Vou Output HIGH Voltage | —1025 | 955 | -870 | mv_| Vin = Vin (Max) Loading with Vo. | Oupurrowvottage | —1e90 | 1705 | -1620 | mv | or vu iWin) 500 to =20¥ Vouc Output HIGH Voltage | ~—1035 re ee | Vin = Vin (Min) Loading with Vorc | Outputowvorage [| [| -1610 ori. (Man) S08 to ~20V Vin inputHIGH Voltage | -1165 | | _—870 | mV | Guaranteed HIGH Signal for All inputs Vi Input LOW Voltage | -1890 | | _—1475 | mv_| Guaranteed LOW Signal for All Inputs lin Input HIGH Current Vin = Vin (Max) Sp 265 An, Bn 340 HA tee | PowerSuppiycurent | ao [| | «0 | ma | inputs Open Note 1; Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. Ceramic Dual-In-Line Package AC Electrical Characteristics 2 | Veg = —4.2V to —5.7V, Voc = Voca = GND tPLH Propagation Delay teLH Propagation Delay ‘ teat Sp-Se to Output 1.40 2.70 1.40 2.70 Figures t and 2 tTLH Transition Time tHE 20% to 80%, B0% to 20% 045 1:30 0.45 1.30 2-137

o S| Commercial Version (continued) S PCC and Cerpak AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND teLH Propagation Delay tPLH Propagation Delay 5 tri Transition Time ts, Skew, Gate to Gate TaD Teo ep PCC Only (Note 1) Note 1: Gate to gate skew is defined as the difference in propagation delays between each of the outputs. Military Version—Preliminary Vee = -4.2V to —5.7V, Voc = Veca = GND, Tc = —55°C to + 125°C symbol | Parameter [min | Max | units| to | Conditions Note Vou Output HIGH Voltage _ oC to 870 | mV | is y25c VoL Output LOW Voltage | _ ipaq | 4620] mv Oto | Vi (Min) 500 to —2.0V a + 125°C Vorc | Output HIGH Voltage | _ OC to

1035 WV | 425°C

Voice Output LOW Voltage mV OCto | OF Vi (Max) 502 to —2.0V “™ +125°C [| -1555 Vin Input HIGH Voltage -1165 | —870 | mv | ~55°Cto | Guaranteed HIGH Signal for All Inputs 1.2.3.4 +125°C an Viv Input LOW Voltage —1475 | my | ~55°Cto | Guaranteed LOW Signal for All Inputs 1.2.3.4 +125°C on Ie Input LOW Current —S58°Cto | Veg = —4.2V BAT 425°C Vin = Vi (Min) 12,3 tid Input HIGH Current Sp 265 A OC to An, Bn 340 +125°C | Veg = —5.7V 12,3 Sp 385 A 55°C Vin = Vin (Max) An Bn 490 Ms lee Power Supply Current | _ —58°C to | Inputs Open 1.2.3 +125°C o Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals —55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at — 56°C, +25°C, and + 125°C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table f) on each manufactured lot at —55°C, + 25°C, and + 125°C, Subgroups A1, 2, 3, 7, and 8. Note 4; Guaranteed by applying specified input condition and testing Vou/Vou- 2-138

Military Version—Preliminary (Continued) 8 taal o Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Veca = GND. teLH Propagation Delay teHL Ao-A7, Bo-B7 to Output 2.30 | 0.70 3.00 12,3 tPLH Propagation Delay , 0.80 3.00 . 4 1 4 Fi ss Tand2 teu So-Sp to Output 0 0.90 2.80 00 3.40 ‘igures 7 ai try Transition Time Cerpak AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND tel Propagation Delay tPHL Ag-Az, 89-87 to Output 30 | 0.70 3.00 1.2.3 tPLH Propagation Delay 0.80 3.01 .! J . Fi 1 2 teu Sq-Sp to Output 10 0.90 2.80 1.00 3.40 ns ‘igures 1 and tTLH Transition Time tHE 20% to 80%, 80% to 20% 0.30 90 | 040 180 | 0.30 2.10 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals ~ 55°C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at + 25°C temperature only, Subgroup A9. Note 3: Sampie tested (Method 5005, Table |) on each manufactured lot at + 25°C, Subgroup AQ, and at + 125°C and — 55°C, temperatures, Subgroups A10 and AN Note 4: Not tested at + 25°C, + 125°C, and — 55°C temperature (design characterization data). Test Circuitry yy 0.1 WF +105 71 a ” (eas at 2 a8 GENERATOR we I 2 7 = 3 16 ut uw 4 15 Ha 2 — fat ‘SCOPE a i CHAN B I gm 25. T T 0.4 uF a Notes: = Veo = TLIF/10612-6 Voc: Voca = +2V. Veg = ~2.5V FIGURE 1. AC Test Circuit L1 and L2 = equal length 509 impedance lines Ay = 50M terminator internal to scope Decoupling 0.1 uF from GND to Voc and Vee All unused outputs are loaded with 509 to GND C, = Fixture and stray capacitance < 3 pF Pin numbers shown are for flatpak; for DIP see logic symbol 2-139

3 Switching Waveforms

FIGURE 2. Propagation Delay and Transition Times