F100336

F100336 NSC | Alldatasheet

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rx) Semiconductor ° Low Power 4-Stage Counter/Shift Register General Description The F100336 operates as either a modulo-16 up/down —_ multistage counting or shift-up operation. The individual Pre- counter or as a 4-bit bidirectional shift register. Three Select _ set (Pp) inputs are used to enter data in parailel or to preset (Sp) inputs determine the mode of operation, as shown in the counter in programmable counter applications. A HIGH the Function Select table. Two Count Enable (CEP, CET) signal on the Master Reset (MR) input overrides all other inputs are provided for ease of cascading in multistage inputs and asynchronously clears the flip-flops. In addition, counters. One Count Enable (CET) input also doubles as a_—_ a synchronous clear is Provided, as well as a complement Serial Data (Dg) input for shift-up operation. For shift-down function which synchronously inverts the contents of the operation, Dg is the Serial Data input. In counting operations __ flip-flops. All inputs have 50 k. pull-down resistors. the Terminal Count (TC) output goes LOW when the coun- ter reaches 45 in the count/up mode or 0 (zero) in the Features count/down mode. In the shift modes, the TC output re- w 30% power reduction of the F100136 Peats the Qg output. The dual nature of this TC/Qs output 2900V ESD protection and the Do/CET input means that one interconnection from Pin/function compatible with F100136 ‘one stage to the next higher stage serves as the link for : mpat § Voltage compensated operating range = —4.2N to —5.7V Ordering Code: see sections Logic Symbol [ PinNames | Description TEP DGCET Py Py Py Ps Ds cP Clock Pulse Input cr CEP Count Enable Parallel Input (Active LOW) ba tclo Do/CET Serial Data Input/Count Enable St Trickle Input (Active LOW) Stun Ge 0; So-S2 Select Inputs re) fe) fe) fe) MR Master Reset Input Po-P3 Preset Inputs TUF/I0584-1 | Dy Serial Data Input Te Terminal Count Output Qo-Q3 Data Outputs Qo-O3, Complementary Data Outputs 2 | Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak o ay, Moa Py Yor 5 0 8 St Sp MR Veg OF Pe e uber (o}ofa}afayoye eer 42 23 {OOOO 24 23 22 21 20 19 te Ed Res .@ ea Sot 18eP, ae abs, ol 7 2 WP, eB Be TH as 20F5) om eis Oy/Et 4s 1h Ps Yoo 19h aa ate con 15} Dy Veca]7 18 Ver “a wy 45 14 a5 48 17 aw a. as 13 0, a ‘sbr “om pa: Testi Gs-q10 she, " " a. 3 ais ube, SGoo0000r” 91 91 Vor Voca a Se relia me Bana we TUF/10584~3 Sy Wayans FE oy ay TUF /10564~2 TUF/10504~4 2-53

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o [ se [si | s | Function | 3 L L L Parallel Load L L H Complement L H L Shift Left L H H Shift Right H L L Count Down H L H Clear H H L Count Up H H H Hold Truth Table Qo = LSB Inputs [ outouts mn | 2 | s1 | so | CEP | porcer | ps | cp | as | a2 | a | a | Te | Mode cfefetet x | «x [x [os [re [es | Po |e | Preset (arate Loac) cfefetat x | x [xT [ee [ee [a Ge [eT inven cfetetet x | x [xT Fe Poe [as [bs | shiner a ed L tye L L xfs (Qo_) minus 1 Count Down L tye H L x {| x Q | Q Count Down with CEP not active L L L x H x x Q; | Qo Count Down with TET not active ttwfetHt xf ox [xfrte fete te Ta [ cear L H]L L L x la (Qo-3) plus 1 ® | Countup L H] uel oH L x | x Q, | Qo | @ | Count Up with CEP not active L HJ L x H x | x Q; | Qo | H_| Count Up with CET not active tfufatat x] « Tx] x fo [oe fo [oe] H | Hos Hype} ede x x x | x Lyefyure L H L L H x x x x L L L L L HJ eT AH] x x x | x Lpeyeure L HJ] LTH] H] x x x | x bypeyeude L | asynchronous H}H] LIL] x L x} x}eyete}el ec | eee HI}THT LIL x H x | xX Lye}eufeutyu H]HI] LH x x x | x Lye}efeutlr HTH} ATL x x x | x Ly e}ufyeudu H[H]HIH x x x | x Lfee}uef{eiu H if Qg-Qg # LLL After the clock, TC is Q2 ® = LilQo-Q3 = HHHH H if Qo-Qg # HHHH H = HIGH Voltage Level L= LOW Voltage Level X= Don't Care 7 = LOW-t0-HIGH Transition 2-55

S| Absolute Maximum Ratings Recommended Operating J Above which the useful life may be impairod (Note 0 , Conditions ary/Aerospace specified devices are required, please contact the National Semiconductor Sales Case Tomperature (To) oC to 488°C Siice/eietibutors for availability and specications. 6 Military —55°C to +125°C lorage Temperature (TsT@) io +4 Supply Voltage (Vee) Maximum Junction Temperature (Ty) Commercial —5.7V to -4.2V Ceramic +175°C Military -5.7V to —4.2V Plastic + 150°C Vee Pin Potential to Ground Pin 7.0V to +0.5V Input Voltage (DC) Veg to + 0.5V Output Current (DC Output HIGH) —50 mA ESD (Note 2) 22000V Commercial Version Vee = —4.2V to —5.7V, Voc = Voca = GND, Tc = 0°C to + 85°C (Note 3) Vou Output HIGH Vortage | —1028 | -o55 | -e70 | mv | Viv=Vinqway | Loading with Vou Output Low Vottage | —1e30 | -1705 | -1620 | my | oF Viki SOR to ~2.0N Vouc OuiputHiGHVotage | toss [|Tv | Vin = Vii Loading with Voc | Outputtowvorage | | | = 1610 oN a) S00 to 20 Vin Input HIGH Voltage 870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage _ Guaranteed LOW Signal 475 | MV | for All inputs tn InputHiGHurent [| |e Vin = Vin (Max) lee Power Supply Current Inputs Open -198 —100 Vee = —4.2V to —4.8V —220 100 Vee = —4.2Vto-5.7V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 2-56

s Commercial Version (continued) 3 a . . a Ceramic Dual-In-Line Package AC Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND forte | Shit Frequency [eso [aso a0 | iz | rieures zane tpLH Propagation Delay Figures 1 and 3 tei Propagation Delay Figures 1, 7,8 tPLH Propagation Delay Figures 1 and 9 toy CP to TC (Count) 160 460 60 4.60 1.60 (Note 1) tPLH Propagation Delay Figures 1 and 4 teat MR to Qn, On 1.10 2.50 1.10 2.50 (Note 1) tel Propagation Delay Figures 1,12 ter MR to TC (Count) 2.00 4,00 2.00 oo | 2.20 4.10 (Note 1) tPHL Propagation Delay Figures 1, 10, 11 MR to TC (Shift) 160 9.20 170 3.40 (Note 1) te Propagation Delay teHL Do/TET to TC 120 320) 140 3:70 Figures 1 and 5 ~ (Note 1) tPLH Propagation Delay 090 400 | 090 420] 1.00 4.80 tPHL Sp to TC tT Transition Time - tHe 20% to 80%, 80% to 20% 0.35 1.20 0.35 1.20 Figures 4 and 3 ts Setup Time D3 1.00 1,00 1.00 Ph 1.30 1.30 1.30 Do/CET 1.35 1.35 1.35 Figure 6 CEP 1.90 1.90 1.90 Sp 4.40 4.40 4.40 MR (Release Time) 2.60 2.60 2.60 th Hold Time Dg 0.40 0.40 0.40 P, 0.50 0.50 0.50 Figure 6 Do/CET 0.30 0.30 0.30 ba CEP 0.40 0.40 0.40 ‘Note 1: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 2-57

o

3 Commercial Version (Continued)

= scat PCC and Cerpak AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND fern | Shit Frequency | s00 | soo | a0 |e | Figures ean tPLH Propagation Delay Figures 1 and 3 ; : . : 0.80 1.80 tem CP 10 Gy, Gp 0.70 1.70 | 070 1.70 Bi (Note 2) tPLH Propagation Delay 1.40 3.70 Figures 1, 7,8 teHL GP to TC (Shift) : ° (Note 2) tPLH Propagation Delay Figures 1 and 9 tem GP to TC (Count) 160 440 | 160 440 | 160 4.80 (Note 2) tPLH Propagation Delay Figures 1 and 4 WA . 1a 40, tPHL MR to Qh, Gn o 280 2 2 (Note 2) tel Propagation Delay Figures 1 and 12 tom MR to TC (Count) 200 380] 200 380 | 220 390 (Nato 2) teHL Propagation Delay Figures 1, 10,11 MR to TC (Shift) 160 300] 160 300] 1.70 3.20 (Note 2) tpLH Propagation Delay te Do/CET to TC 120 3.00 Figures 1 and 5 , (Note 2) tPLH Propagation Delay ( tem gn toTC 090 380] 090 400] 1.00 460 ttLH Transition Time ; trHe 20% to 80%, 80% toz0% | 295 = 1.10 Figures 1 and 3 ts Setup Time Dg 0.90 0.90 0.90 Py 1.20 1.20 1.20 Do/CET 1.25 1.25 1.25 Figure 6 CEP 1.80 1.80 1.80 Sp 4.30 4,30 4.30 MR (Release Time) 2.50 2.50 2.50 th Hold Time Dg 0.30 0.30 0.30 Ph 0.40 0.40 0.40 ; Do/CET 0.20 0.20 0.20 Figure 6 CEP 0.30 0.30 0.30 tpw(H) Pulse Width HIGH cP.MR ns | Figures 3and 4 ts,a-.¢ | Skew, Gate to Gate TaD ep ap PCC Only (Note 1) Note 1: Gate to gate skew is defined as the difference in propagation delays between each of the outputs. Note 2: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 2-58

. =J Military Version—Preliminary 3 ao 5 taal. a Vee = —4.2V to —5.7V, Voc = Voca = GND, To = —55°C to + 125°C Symbol | Parameter [win [| wax [ units | to | Conditions Notes Vin = ViH (Max) | Loading with VoL Output LOW Voltage ~1830 | —1620 mv oCto +125°C =1555 Vorc | Output HIGH Voltage oC to m™ | + 125% Vin = Viti (Min) | Loading with Voic Output LOW Voltage _ 0° to 1610 | mv + 125°C |_| = 1555 Vin Input HIGH Voltage —55°C to | Guaranteed HIGH Signal 41 _ 85 | 870 | MY | 425 | for All inputs 1.2.3.4 Viv Input LOW Voltage _ —55°C to | Guaranteed LOW Signal 1475 | VY | oy 425%¢_ | for AllInputs 12,34 i Input LOW Current Foo | | =55°Cto | Veg = —4.2V 1,2,3 BA +125°C | Vin = Vit (min) im Input HIGH Current oC to __ HA | s1asr¢ | Vee = ~87V 1,23 Vin = ViH(Max) ee eee lee Power Supply Current 55°C | Inputs Open —208 —100 mA to Vee = —4.2V to —4.8V 1,2,3 230 —100 +125°C | Veg = —4.2Vto -5.7V Note 1: F100K 300 Series coki temperature testing is performed by temperature soaking (to guarantee junction temperature equals — 55°C), then testing immediately without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at — 55°C, + 25°C, and + 125°C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sampie tested (Method 5005, Table I) on each manufactured lot at — 55°C, + 25°C, + 125°C, Subgroups At, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input conditon and testing Vou/Vou- 2-59

o oa S| Military Version—Preliminary (continued) o Ceramic Dual-in-Line Package AC Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND fan _ [Shit Frequency [20 | oot Me [Figures 2anas | 4 tetn | Propagation Delay 060 210 | 060 210 | 070 2.20 Figures 1 and 3 teH, {CP toQn, On 1.2.35 tPLH Propagation Delay . i tPHL GP to TC (Shifty 1.20 4.00 1,20 00 1.30 4.10 Figures 1, 7,8 tpty _| Propagation Delay tpLH | Propagation Delay 1.00 270 | 100 270 | 110 280 Figures 1 and 4 tPHL MR to Qn, Qn 4.2.3.5 tPLH Propagation Delay , == J 4. ’ 4. 1 , tet |Man to TC (Count 1.90 20 | 1.90 20 | 210 4.30 Figures 1, 12 teu. | Propagation Delay ; MR to TG (Shit) 1.50 3.40 1.60 3.60 Figures 1, 10, 11|1,2,3,5 irl Delete Te 10 940 ue a0 [130300 | oe tea. [Do/GET to TC Figures 1 and 5 |1,2,3,5 tetn | Propagation Delay A 7 4.40 0. . teHL Sq to TC 0.80 4.20 0.80 90 5.00 ttn | Transition Time ; trae 20% to 80%, 80% to 20% 0.45 1.20 0.35 1.20 Figures 1 and 3 4 ts Setup Time Dg 1.20 1.20 1.20 Ph 1.50 1.50 1.50 Do/CET 1.55 1.55 1.55 Figure 6 4 CEP 2.10 2410 2.10 Sn 4.60 4.60 4.60 MR (Release Time) 2.80 2.80 2.80 th Hold Time Dg 0.60 0.60 0.60 Pa 0.70 0.70 0.70 Do/CET 0.50 0.50 0.50 Figure 6 4 CEP 0.60 0.60 0.60 Sn 0.30 0.90 0,90 Pulse Width HIGH tout) cP, MR ce few few [| Figures Jan 4 ‘ Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals —55°C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold tempertures. Note 2: Screen tested 100% on each device at +25°C temperature only, Subgroups Ag. Note 3: Sample tested (Method 5005, Table |) on each manufactured lot at + 25°C, Subgroups AQ, and at + 125°C and — 55°C temperatures, Subgroups A10 and Att Note 4: Not tested at +25°C, +125°C, and — 55°C temperature (design characterization data). Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 2-60

Military Version—Preliminary (continued) Fy . a Cerpak AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND “nee rome | Tee] “he Can as] “te Fe — | cma | ‘ee fern [Shift Frequency | 200 | a0 | a00 | ti [Figures 2and | 4 tpi __ | Propagation Delay 060 210 | 060 210 | 070 220 Figures 1 and 3 tpy_ _ |CP to Qn, On, 1,2,3,5 teLH | Propagation Delay teat lopto 7 (shit) 1.20 400 | 120 4.00 30 4.10 Figures 1, 7,8 tPLH Propagation Delay gat 150 4 : r Figures 1, 9 12,3, tor lopte TC (count go | 150 4.80 ‘igures 1,2,3,5 tpLH Propagation Delay 1.00 270 | 100 270 | 140 280 Figures 1 and 4 teu, [MR to Qp, Qn 1,2,3,5 tPLH Propagation Delay wt |an to TC (coun 1.90 4.20 90 420 | 210 4.30 Figures 4 and 12 tp. _ | Propagation Delay MA to TS (shit) 150 340 | 150 340 | 160 3.60 Figures 1, 10, 111, 2,3,5 Nal propagator 1.10 340 | 1.10 340 | 130 3.90 [| IPHL 0! Figures 1 and 5 |1,2,3,5 tet |Propagation Delay oso 420 | 080 440 | 090 5.00 teu, _|SntoTC trun | Transition Time 0.4! js F . . 14 tren [20% 10.80%. 80% to20%| O45 10 | 035 1.10 | 0.98 0 | ns |Figurestanda | 4 ts Setup Time Dg 1.20 1.20 1.20 Ph 1.50 1.50 1.50 Do/CET 1.55 1.55 1.55 Figure 6 4 CEP 2.10 2.10 2.10 Sq 4.60 4.60 4.60 MR (Release Time) 2.80 2.80 2.80 th Hold Time Dg 0.60 0.60 0.60 Pr 0.70 0.70 0.70 ; Do/CET 0.50 0.50 0.50 Figure 6 4 CEP 0.60 0.60 0.60 Sa -0.30 0.30 0.30 tpw(H) | Pulse Width HIGH ; ‘pws ¥ Fi oPMA 2.20 igures3and4| 4 ‘Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals ~55°C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold tempertures. Note 2: Screen tested 100% on each device at +25°C temperature only, Subgroup A. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at + 25°C, Subgroup AQ, and at + 125°C and --55°C temperatures, Subgroups A10 and AN Note 4: Not tested at +25°C, + 125°C, and —55°C temperature (design characterization data). ‘Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 2-61

3-Stage Divider, Preset Count Down Mode o PRESET N se) a) No=Na NeNy Nextt [it —t Lt Po-Pa LU Po-Pa & Po-Ps & & — ofcep nat O}CEP F100336 of cer F100336 100338 tcp of cet tw cp tcf cp rs Note: If So = S; = Sz = LOW, then Te = LOW TUF/10584~12 Slow Expansion Scheme COUNT gy cer a Oo CEP of CEP ENABLE cer 100338 «Tc fo—cer Fi00338 © Tc fo—of cer F100338 © Tcfo—oh cet F100338 = Tc fp r cp fi cp fi ce i cp cLock TUF/10584~13 Fast Expansion Scheme aounr cep Teo F cep u cEP LL cep ENABLE Ofcer F100336 Acer 100338 = tcfo—olcer #10038 © tcf>—al cer 100338 © tc cp rt cp fi cp fi cp 2 | cLock TUIF/10584-14 267