F100331

F100331 NSC | Alldatasheet

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APR & 1991 nu = —_ National Dsconon 80 | 4 f=] Semiconductor 2 F100331 c . . Q Low Power Triple D Flip-Flop = uv General Description Features 2 The F100331 contains three D-type, edge-triggered mas- 35% power reduction of the F100131 a ter/slave flip-flops with true and complement outputs, a ™ 2000V ESD protection = Common Clock (CPo), and Master Set (MS) and Master Re- Pin/function compatible with F100131 4 Set (MR) inputs. Each fip-lop has individual Clock (CPr), @ Voltage compensated operating range = —4.2V to | = Direct Set (SDp) and Direct Clear (CDp) inputs. Data enters 5.7 3 a master when both CP, and CP¢ are LOW and transfers to ry a slave when CP, or CPg (or both) go HIGH. The Master Set, Master Reset and individual CD, and SD, inputs over- o ride the Clock inputs. All inputs have 50 kQ. pull-down resis- on tors. = a . fe} Logic Symbol no] [_Pinwames [Description | [] [ er4 CPo-CP2 Individual Clock Inputs \\) \\) \\) CP Common Clock Input ©Pp_CP; CP; Dy Dy Dz Do-D2 Data Inputs Do CDp-CDp Individual Direct Clear Inputs oo SDp Individual Direct Set Inputs soo MR Master Reset Input 80, MS Master Set Input ‘Sz Qo-Q2 Data Outputs i) Q; a ts Q-O2 Complementary Data Outputs TUR/10262~1 Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak : co Tabs. $09 CD CPp Vers Dy Oy dp Dy $0, MR Veg CPe MS 1 4 ce asb-co, Ot GG) cee 3 nbc __ or 18F- 50) | a5 20-so, Ce GB] 9, 30,43 16h cry ' vee 4s rm vs Ve i Dee coe 50, | You? 18}-Vee Yas 3 Dvee os 14h oy | 4s 17hcPe we fis) BB Vee 46 13 Q ! a410 15} 509 ote Bo 0 Yor Veeads 8 ait 14f-co, ofi2 bop lelabelelels) TUF / 0282-8

1 PCy $0, Vz 6D CP Dp

| TLIF/10262-2 TUF /10262-4 (©1990 National Semiconductor Corporation TL/F/10262 : ARD-820M120/Pnnted in U.S. A.

SDo Do CPo Dp SD; Dy CP; CD; SDz Dz CP2CPc Dz Do ce ] I D ce | I Sp Co So Cp opt Lt nelle wa—p>— | Qo Q a, a Q a TUF 0262-5 Truth Tables (Each Flip-Flop) Synchronous Operation Asynchronous Operation L x L L L L x x x H L H H a L L L H x x x t H L L L a L L L x x x H H U H L a L L H x L L L L Qn(t) x H x L L Qni(t) x x H L L Qn(t) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care U = Undefined t = Time before CP Positive Transition t + 1 = Time after CP Positive Transition ~~ = LOW to HIGH Transition

Above which the useful life may be impaired (Note 1) Output Current If Military/Aerospace specified devices are required, (DC Output HIGH) —50 mA please contact the National Semiconductor Sales ESD (Note 2) < 2000V Office/Distributors for availability and specifications. Storage Temperature (Tstq) —65°C to + 150°C Recommended Operating Maximum Junction Temperature (Ty) iti Ceramic +175°C Conditions Plastic +150°C Case Temperature (Tc) Pin Potential to Commercial O°C to +85°C Mili ~55°C to +125" Ground Pin (Vee) 7.0V to +0.5V supply vol © Vex) 55°C to +125°C ly Input Voltage (DC) Veg to +0.5V Commercial -57V to -42V Military —5.7V to —4.2V Commercial Version Vee = ~4.2V to —5.7V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Symbol | Parameter [Min Typ Max | Units | Conditions Vou Output HIGH Voltage | —1025 955 -870 Vin = Vin (Max) | Loading with Vou Output LOW Voltage -1830 -1705 —1620 or Vi (Min) 500 to —2.0V Vouc OutputHIGH Voltage | -10395 || Vin = VmitMiny) | Loading with Voie Output LOW Voltage 1610 oF Vin (Max) 509 to —2.0V Vin Input HIGH Voltage 1165 _870 mv Guaranteed HIGH Signal for All Inputs. Vit Input LOW Voltage 1890 4475 mv Guaranteed LOW Signal for All Inputs in Inputowcurent | 05 || Viv = Va Mi rm ImputHiGH Curent [240A |My = Vin (a) lee Powersupply Curent | -12e 68 | mA | Inputs Open Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the “worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operate under “worst case” conditions. i

Commercial Version (continues) Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = ~4.2V to —5.7V, Voc = Voca = GND. tax | ToagleFrequency |-a75 [avs | ars | i | Fires Sand’ 075 200] 075 200] 075 2.00 {PHL oe fo oe Figures 1 and 3 tPLH ropagation Delay tPLH Propagation Delay CPp, CPe =L PLH 0.70 2.00 0.70 200 CP. CPo =H | teHL Figures tPLH Propagation Delay CPp, CPg = L tand4 teat MS, MR to Output 1.10 2.60 1.10 2.60 PHL tTLH Transition Time ts Setup Time ; Dn 0.40 0.40 0.40 Figure CDn, SDp (Release Time) | 1.30 1.30 1.30 MS, MR (Release Time) | 2.30 2.30 2.30 Figure 4 th Hold Time Dn [1.00 [4.00 [00 [ns | Figures tow) | Pulse Width HIGH Pp, CP¢, CDp, 2.00 2.00 Figures 3 and 4 SDp, MR, MS PCC and Cerpak AC Electrical Characteristics Vee = —4.2V to ~5.7V, Voc = Voca = GND fnax | ToasleFrequensy | 00 [400 | 400” | wir | Figures Pana'3 {PHL oe to caer Figures 1 and 3 tPLH ropagation Delay tPLH Propagation Delay CPp, CPg =L teu 070 1.80] 070 180 | 0.70 1.80 CP CPo =H | tPHL Figures tPLH Propagation Delay CPp, CPe = L tand4 tPLH 1140 280 CP, CP = H {PHL tH Transition Time t Setup Time ; . Dn 0.30 0.30 0.30 Figure 5 CDp, SDp (Release Time) | 1.20 1.20 1.20 - MS, MR (Release Time) | 2.20 2.20 2.20 Figure 4 ty | Wold Tine [oso [090 | 090 [ns | Figures tow) | Pulse Width HIGH CPp, CP, CDp, 2.00 Figures 3 and 4 SDp, MR, MS tsGug | Skew.GatetoGate | ___Ted | TaD | Tad | ps POCO Row Note 1: Gate to gate skew is defined as the difference in propagation delays between each of the outputs.

Military Version—Preliminary Vee = —4.2V to —5.7V, Voc = Voca = GND, To = —55°C to + 125°C symbol | Parameter [win wax [units [Te | Conaitions | Notes Vou Output HIGH Voltage | _ _ OC to 1025 870 mV +1250 VoL Output LOW Voltage | _ OC to or Vi. (Min) 502 to —2.0V ™ 1830-1620 | mv | occ = 1830-1555 Vouc | Output HIGH Voltage mv OC to +125°C Voic | Output LOW Voltage mv OCto | oF Vit (Max) 50nto-20v } *"* + 125°C [1585 [mv [ss | Vin InputHIGH Voltage | _ sig. a7 | my | ~S5°Cto | Guaranteed HIGH Signal 1.2.34 + 125°C for all inputs Vir Input LOW Voltage _ —55°C to | Guaranteed LOW Signal 1830 = 1475 | mV | 425°. | forall inputs 1.23,4 he Input LOW Current —55°Cto | Veg = ~4.2V HA +125°C | Vin = Vi (Min) 12.3 ha Input HIGH Current OCto _ pA +125 | Vee = ~5.7V 123 Vin = Vi (Max) re ee ee lee Power Supply Current ~55°C to +125°C Inputs Open 1,2,3 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature ‘equals — 55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” ‘specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at — 55°C, + 25°C, and + 125°C, Subgroups, 1, 2, 3, 7 and 8. Note 3: Sampled tested (Method 5005, Table !) on each manufactured jot at — 55°C, + 25°C, and + 125°C, Subgroups A1, 2, 3, 7 and 8. Note 4: Guaranteed by applying specified input condition and testing Vou/Vot.

Military Version—Preliminary (continued) Ceramic Dual-In-Line Package AC Electrical Characteristics Veg = —4.2V to —5.7V, Vcc = Veca = GND come] rer eam] cme fmax__| Toggle Frequency | 30 [380 350 | wiz | Figures 2and 3 4 tPLH Propagation Delay 060 2 0 . A ).50 4 teu. _| CPc to Output 00 2.40 Figures 1 and 3 tPLH Propagation Delay tore | CPs to Output 0.60 200 | 0.50 2.40 tPLH Propagation Delay _ tPLH 0.50 2.40 0.60 2.10 CP, CPt H teLH Propagation Delay _ tand4) '™ tere | MS MA to Output 0.70 270 | 0.80 260 | 0.80 290 CPp, CPo = L iH 0.70 290 | 080 280 | 080 3.10 CPh, CPo = H trun | Transition Time ts Setup Time ; Dn 1.00 0.80 0.90 Figure 5 4 CDp, SDp (Release Time) | 1.50 1.30 1.60 MS, MR (Release Time) 2.50 2.30 2.50 Figure 4 LT [Hold Tine a EY | tpw(H) | Pulse Width HIGH CP, CPc, CD, 2.00 Figures 3 and 4 SDn, MR, MS Cerpak AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Veca = GND Symbol | renee gare -_ Cin was] _" Lain "i te] conatone | Notes {max __| Toggle Frequency [ave a7 a5 | iz | Figures Band 3 4 teu Propagation Delay 050 200 | 0.60 .! . A 1.80 tpri.__| CP to Output Figures 1 and 3 tPLH Propagation Delay tein __ | Propagation Delay _ tPLH 050 220 | 0.60 1.90 cP, =H teHL : ° : nm CP Figures teLH Propagation Delay _ tand 4 heel 0.70 270 | 080 260 | 080 2.90 CPpy, CPo = H | ttt | Transition Time ; tre | 20% to 80%, 80% to20% | 0-20 1.20] 0.20 1.20] 020 1.20 Figures 1, 3 and 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals ~55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after Power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. i Note 2: Screen tested 100% on each device at + 25°C. Temperature only, Subgroup A9. | Note 3: Sample tested (Method 5008, Table |) on each Mfg. lot at + 25°C, Subgroup AQ, and at + 125°C, and - 55°C Temp., Subgroups A10 and A11 ' Note 4: Not tested at +25°C, + 125°C and —55*C Temperature (design characterization data). i i 6 i

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows:

100331 D C QR

Device Type ee = Special Variations (Basic) QR = Commercial grade device with burn-in QB = Military grade device with Package Code ‘ " D — Ceramic DIP environmental and burn-in processing. F = Quad Cerpak Temperature Range Q = Plastic Leaded Chip Carrier (PCC) C = Commercial (0°C to + 85°C) M = Military (— 55°C to + 125°C) Physical Dimensions inches (milimeters) 902s cn 0 0155 easy ‘areata Ll | Ba (23) fez) fer) feo} Fish re) (7) fie) fis) ffl fal ao YP a\\| Pate ass am cuss: I) - 4 rrerrrorrerer ew 070.08, e josaz0.77 a 1 ap ie sour inate gag-om ath fd fe i ar i ‘om-075 8125 vw ac 1° ve sam 0s sna veve 24-Lead Ceramic Dual-in-Line Package (0.400” Wide) (D) sce | im Te aan | = isi ll putin ae BO =a somes ES ass 1/2 OF Raananiy ase rie ng as! Le Po 2410-40 pane (Comme boio) [ aoe Soh ial oso. waco “a ne awe eel Femstoan t | ——+ wee le apron me ere on meses, | ute masa hee somos! vate ina une 28-Lead Plastic Chip Carrier (Q)

a 2 Physical Dimensions inches (millimeters) (Continued) Lit. # 114912 2 osm 0.004 0.006 16.350—0.144) MIN SQUARE (6.350 9.144) a TP TYP 1 2 PIN NO. 1 | = NENT EF \\ _ 1 24 23-22 21-20-19,» A o ———J, — a

4 Sr es wu '

° | I o 0.075 oO (1.905)

8 PLCS

b=4 0.016~0.018 | MAX 9.035 — 0.050 Le ve (1.270-20.127) 0.065 0.400 TP (2.159) (10.16) MAX SQUARE MAX GLASS 248 (REV C) 24-Lead Quad Cerpak (F) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL, SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to Perform can | into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance Support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury ie Le to the user. os . ee ! ZA National Semiconductor National Semiconductor National Semiconductor _ National Semiconductor National Semicondutores National Semiconductor Corporation ‘GmbH sapen Lie. Hong Kong Lid. Do Bra Lida, (Australia) PY, Lic. 2200 Semiconductor Dive _Indusiestrasse 10 Sansoido Bg, 5¢ Suite $13, 8th Fooe ‘Av. Big. Fria Lima, 1989 1st Foor, 441 St Kika Ra, 7.0. Box 58090, 10-8000 Fursteneldbruck 4-15 Nit Shin Chinachem Golden Paza, {80 Andor-Coni 62 Metoourne, 2004 Serta Gara, CA 950528090 West Germany Shinui, 77 Mody Road. Tsimshatsui East, 01451 Sao Pavio, SP, Gras Victory mesbaa ! Tet. 1800) 272-0059 Tet (0-81-41) 100-0 Tokye 160, Japan Kowloon, Hong Kong Tak (55/11) 212-5066 Tet (08) 267-5000 i TWX: (910) 339.9240 Tolox: 527-649 Tot 3.200.700" Tor 37231290 Fax (65/11) 211-1181 NSBR BR Fax: 61-9-2677498 Fax (08141) 103554 FAX: 3:286-7000 Telex. 52996 NSSEA Hx i Fax: 33112606, : "etre oscar ayer. ay ray seb, a crates We anda sae ey tie wha ete args uy are pecans