F100329D

F100329 NSC | Alldatasheet

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s —_ ZANational “orton | o Semiconductor @ o F100329 & Low Power Octal ECL/TTL Bidirectional = Translator with Register PY General Description 2 The F100329 is an octal registered bidirectional translator The F100329 is designed with FAST® TTL output buffers, designed to convert TTL logic levels to 100K ECL logic lev- featuring optimal DC drive and capable of quickly charging ° els and vice versa. The direction of the translation is deter- and discharging highly capacitive loads. All inputs have zy mined by the DIR input. A LOW on the output enable input 50 kf. pull-down resistors. » (OE) holds the ECL outputs in a cut-off state and the TTL = outputs at a high impedance level. The outputs change syn- Features m chronously with the rising edge of the clock input (CP) even Bidirectional translation ce) though only one output is enabled at the time. = ECL high impedance outputs c The cut-off state is designed to be more negative thana sg Registered outputs qj normal ECL LOW level. This allows the output emitter-fol- m= FAST TTL outputs lowers to turn off when the termination supply is —2.0V, 8 Te crates oarut r presenting a high impedance to the data bus. This high im- ‘ outputs . Pedance reduces the termination power and prevents loss ™ Voltage compensated operating range = -4.2V to Le] of low state noise margin when several loads share the bus. ~8.7V a oS Oo a Logic Symbol S [_PinNames |Description | = * a To Ty Th 13 Te 15 16 7 E9-E7 ECL Data 1/O x P| To-T7 TTL Data 1/0 8 ce ove OE Output Enable input i) cp Clock Pulse Input > fo EE Es & fs fe & (Active Rising Edge) -~ DIR Direction Control Input Q TUF /10563~1 All pins function at 100K ECL levels except for To-T7. <= Connection Diagrams > 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak P') ay, Tr Te Ts¥ees Ta Ts Ts Fo CP Voc Vee Ym. To & Ft B 24F-Es OOOO a 42 ake, (POO, 24 23 22 21 20 19 Q 1b oy a 18f—T, oO E43 22 E, vn 3 oa fe ison cd) i g ian i) 2 2 oan i 2 Eo ‘ew HD Veca E43 16 T. ors 20}—cP Vers © aa Vcc 5 3 Veed6 toey, Voc © M3 Voc Eas 15-1, ec cc corm | G2 OE E45 4b Ts Voca—47 18}=Ver f 13 f tes isk t, ORB ed ee \\GoCUCGUUT” 78 9 1011 12 ~ y-9 16-1) BonmaeaeE Lio ister & VersEs fs Fy £7 OF Vor VocqOR Ty 6 1 TWF r10583-3 TWF /10563-4 Isit 141, Yi 13-1; TLF/10509-2 FAST and TRISTATE® are registred radmarks of Natonal Semiconductor Corporation ©1990 National Semiconductor Corporation TL/F/10583 i} RRO-B20MBO/Printed in U.S.A

a TRANSLATOR "eGSre" OUTPUT BUFFER “a RO PE ye 1 1 [t=] ea <> om ecu ™1 | —| our oureut ecL2 rt m2 BUFFER | | aon > ECL3 [| ™3 HLA pimection L>—{ 0-1] 0 BD ecL4 | | I ma i D | oureur c tnasee [> tm TLF/10589-6 ECLS rc] || wu [e] |. | Truth Table ECL im ™Ss ECL TTL | a [ 2 | om | oe | Port Port | Cow [2 a] ecl7 m7 LOW |r ELF | | curoin 29 pe peter ee Petr | (cP) CLocK = poetry ow fu Ts | coin) ect pape pet x [nc | 1s | Note: DIR and OE use ECL logic levels TL/F/10583-5 [eT Pe] nw [x [as | H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High impedance ” = LOW-to-HIGH Clock Transition NC = No Change Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before CP.

Absolute Maximum Ratings (note 1) \\f Military/Aerospace specified devices are required, Voltage Applied to Output Please contact the National Semiconductor Sales in HIGH State Office/Distributors for availability and specifications. TRI-STATE Output -0.5V to +5.5V Storage Temperature (Tstq) ~65°C to + 150°C. Current Applied to TTL Maximum Junction Temperature (T)) Output in LOW State (Max) Twice the Rated Io, (mA) Ceramic +175°C ESD (Note 2) 2=2000V Plastic + 150°C Vee Pin Potential to Recommended Operating Ground Pin 7.0V to +0.5V Conditions Vr Pin Potential to C ‘ ase Temperature (Tc) Ground Pin +6.0V to -0.5V Commercial 0°C to +85°C ECL Input Voltage (DC) Vee to +0.5V Military —55°C to + 125°C ECL Output Current ECL Supply Voltage (Vee) (OC Output HIGH) —50 mA Commercial —5.7V to —4.2V TTL Input Voltage (Note 4) —0.5V to +7.0V Military —5.7V to —4.2V TTL Input Current (Note 4) ~30 mA to +5.0mA TTL Supply Voltage (Vir) Commercial +4.5V to +5.5V Military +4.5V to +5.5V Commercial Version TTL-to-ECL DC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND, Tc = 0°C to + 85°C, Vit, = +4.5V to +5.5V (Note 3) symbol | Parameter [min [typ | Max [Unite | Conditions Vou Outputs Voltage | —1025 | -955 | -e70 [mv | Vi = Vw (Man or Vi (Min Vor Output Low votage | —1ea0_ | —1705 Loading wih S00 fo ~2V Cutoff Voltage OE or DIR LOW, — 2000 -1950 mv Vin = Vin (Max) or Vit (Min), Loading with 502 to ~2V Vin = Vin (Min) or Vi, (Max) Voic Output LOW Voltage mv Loading with 502 to ~2V Corner Point LOW Vi InputticHvotage | 20 | [so |v | Over Vir. Ver, To Range Yi Inpurowvotage | 0 [| os |v | Overvin., Vee, To Range if tmputtiGHGurent [TT 0 Tp | v= 27v Breakdown Test | | Tt | ma | v= 488 in InputLowcurent | 700 | [Tn | Y= FOV Vecp Input Clamp _ __ Diode Voltage 12 v lin = —18 mA lee Vee Supply Current LE LOW, OE and DIR HIGH Inputs Open —189 —94 mA Vee = —4.2V to —4.8V 199 94 Vee = —4.2V to —5.7V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied, > Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. Note 4: Either voltage limit or current limit is sufficient to protect inputs.

Commercial Version (continued) ECL-to-TTL DC Electrical Characteristics Vee = ~—4.2V to —5.7V, Vec = Voca = GND, To = 0°C to + 85°C, CL = 50 pF, VTL = +4.5V to +5.5V (Note 3) Von Output High Voltage 27 34 v lon = —3mA, Vr = 4.75V 2.4 29 v lou = —3mA, VrtL = 4.50V Vin Input High Voltage 1165 _870 mv Guaranteed HIGH Signal for All Inputs Vit Input Low Voltage 1475 mv Guaranteed LOW Signal for All Inputs lozHt TRI-STATE Current _ Output High 70 BA Vout = +2.7V lozit TRI-STATE Current _ 7 Output Low 700 pA Vout = +0.5V los Output Short-Circuit = Current 150 mA Vout = 0.0V, VL = +5.5V hte Vrt_ Supply Current 74 mA TTL Outputs Low 49 mA TTL Outputs High 67 mA TTL Outputs in TRI-STATE Ceramic Dual-In-Line Package TTL-to-ECL AC Electrical Characteristics Vee = —4.2V to —5.7V, Vit = +4.5V to +5.5V, Voc = Voca = GND Puy CPIOEn 1736 Figures 1&2 tPHL tezH OE to Ep, . (Cutoff to HIGH) 1.3 4.2 15 44 1.7 48 Figures 1&2 tpHz OE to E, ; (HIGH to Cutoff 1.5 45 1.6 46 Figures 1&2 tpHz DIR to E, 4 4 (HIGH to Cutoff) 1.6 43 1.6 3 17 5 ‘igures 1&2 ttLH Transition Time . trot 20% to 80%, 80% to 20% 06 16 Figures 1&2

Commercial Version (continuea) Ceramic Dual-In-Line Package ECL-to-TTL AC Electrical Characteristics Vee = —4.2V to —5.7V, ViTL = +4.5V to +5.5V, Voc = Voca = GND, C = 50 pF syne ee eee ee cenavons tPLH CPtoTh 34 72 | 34 72 | 38 77 Figures 3 & 4 tPHL tezi (Enable Time) 38 9.2 40 9.2 43 9.95 Figures 3 & 5 tpiz (Disable Time) 3.0 77 3.4 87 41 9.95 Figures 3 & 5 tpuz DIR to Ty 27 8.2 28 8687 | 31 8.95 ; tpiz (Disable Time) 28 745 | 34 795 | 40 9.2 Figures 3 & 6 PCC and Cerpak TTL-to-ECL AC Electrical Characteristics Vee = ~4.2V to —5.7V, Viti = +4.5V to +5.5V tPLH CPIOEn 17 3.4 17 3.5 19 3.7 Figures 1&2 teHL tzu OE to En / (Cutoff to HIGH) 13 4.0 17 46 Figures 1&2 tpHz OE toE, . (HIGH to Cutoff) 1.5 43 1.6 43 16 44 Figures 1&2 tenz DIR to En (HIGH to Cutoff 1.6 41 1.6 41 17 43 Figures 1&2 tTLH Transition Time ' trHe 20% to 80%, 80% to 20% 06 16 Figures 1&2

Commercial Version (continued) PCC and Cerpak ECL-to-TTL AC Electrical Characteristics Vee = —4.2V to —5.7V, ViT_ = +4.5V to +5.5V, C, = 50 pF ‘ax MaxToggle Frequency | 125 | 125 | 125M tPHL tpZH OE toT, 3.4 8.25 37 8.75 4.0 95 ~ tz (Enable Time) 38 9.0 40 9.0 43. 9.75 Figures 3&5 teiz (Disable Time) 30 75 | 34 85 | 41 975 Figures 3 & 5 tpHz DIR to Tn 27 8.0 28 a5 | 31 675 tpiz (Disable Time) 28 725 | 31 775 | 40 90 Figures 3 & 6 Military Version-Preliminary TTL-to-ECL DC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND, Tc = —55°C to + 125°C, VTL = +4.5V to +5.5V symbol| Parameter [ Min | Max [Units| Tc [Conditions| Notes Von | Output HIGH Voltage _ OC to 870 mV + 125°C Vo. | Output LOW Voltage my | orcto | ONL Min) Loadingwith | , 54 + 125°C 502 to —2.0V “o [raeo | —r5s5 [av | se | Cutoff Voltage 1950] yy | O°Cto +125C | op or DIR LOW [a80 [av | ac | VoHc Output HIGH Voltage | _ OC to 1035 mv | iosec Voic Output LOW Voltage mv oCto | or Vii (Max) 502 to —2.0V + 125°C [ress | mv se | Vit Input LOW Voltage | fe |v | “see Yo Over Vit, Vee. Te Range 1.2.3.4 Vecp _ | Input Clamp _ —55°C to _ Diode Voltage 12 Vo} ¢tzsec | in = ~18mA 12:3 lee Vee Supply Current LE LOW, OE and DIR HIGH 55°C to | Inputs Open 123 220 | —70 Vee = —4.2V to —5.7V

Military Version-Preliminary (continued) ECL-to-TTL DC Electrical Characteristics Vee ~ —4.2V to —5.7V, Voc = Voca = GND, Tc = —55°C to +125°C, C, = 50 pF, Vit = +4.5V to +5.5V Vou Output HIGH Voltage | 2.5 mv | ~88°Ct0 | ton = —1 mA, Vr = 4.50V

24 H125°C | lon = —3mMA Vi = 450V | 4 59

Voi Output LOW Voltage —55°C to _ _ mv | Sec. | lou = 24mA, Vir, = 4.50V Vin InputHIGH Voltage | _ _ =86°C to | Guaranteed HIGH Signal 1165 870 mv +125°C | for All Inputs 1.2,3,4 Vit Input LOW Voltage _ =55°Cto | Guaranteed LOW Signal 1475 | mv +125°C | for All Inputs 12,34 I Input HIGH Current 350 BA OC to Vin = Vin (Max) es er eo Ne Input LOW Current a | ~58°Cto | Vee = —4.2v 123 uM +125°C | Vin = Vit (Min) es lozut | TRISTATE Current —55°C to _ Output High 70 BA +125°¢ | Your = +2.7V 1,2,3 lozit TRI-STATE Current —55°C to _ Output Low mA +125°¢ | Vout = +0.5V 1,2,3 los Output Short-Circuit _ —55°C to _ . Canont 150 mA | Sogo | Vout =0.0V, Vr = +55V | 1.2.3 hr Vr Supply Current 75 mA | seectg | TTL Outputs Low 50 mA | o5¢0. | TTL Outputs High 1,2,3 70 mA TTL Outputs in TRISTATE Note 1: F100K 300 Series cold temperature testing is performed by temperature ‘soaking (to guarantee junction temperature equals - 55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at — 55°C, + 25°C, and + 125°C, ‘Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table !) on each manutactured lot at — 55°C, +25°C, and + 125°C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing Vou/VoL.

Military Version-Preliminary (continued) Ceramic Dual-In-Line Package TTL-to-ECL AC Electrical Characteristics Vee = —4.2V to ~5.7V, VrT_ = +4.5V to +5.5V, Voc = Voca = GND tPLH CP IO En 13 38 16 37 19 43 Figures 1&2 tPHL tpzH OE to E, (Cutoff to HIGH) 1.0 43 15 44 17 5.1 Figures 1& 2 1,23 tpHz OE to En (HIGH to Cutoff) 1.6 45 1.6 5.0 Figures 1&2 tpuz DIR to E, . (HIGH to Cutoff 1.6 47 1.6 43 17 47 Figures 1&2 init [Puwowancr [as [ao | as | os | rawenraz| trun Transition Time . FE . F 4 7 trae 20% t0 80%, 80% to20% | 24 29 04 2 Figures 1&2 Ceramic Dual-In-Line Package ECL-to-TTL AC Electrical Characteristics Vee = —4.2V to —5.7V, VTL = +4.5V to +5.5V, Voc = Voca = GND, C, = 50 pF eLH CP tot a1 73 | 33 8.0 Figures 3 & 4 teHL tpzH OE toTh 3.4 941 37 9.0 4.0 10.1 tpzi (Enable Time) a7 95 | 40 93 | 43 10.4 Figures 3&5 123 tpuz OE toTn 3.2 100 | 33 90 | 35 9.3 i tez (Disable Time) 3.0 os | 34 a8 | 44 10.4 Figures 3&5 tpHz DIR toT, 26 9.5 28 8.8 3.0 9.0 7 teiz (Disable Time) 27 87 | 31 80 | 40 96 Figures 3&6

Military Verison-Preliminary (continued) Cerpak TTL-to-ECL AC Electrical Characteristics Vee = —4.2V to —5.7V, Vet, = +4.5V to +5.5V tPLH CPIOEn 13 38 |16 37] 19 43 Figures 1&2 tPHL tpzH OE toE, . (Cutoff to HIGH) 1.0 43 1.5 44 17 541 Figures 1&2 1,2,3 teuz | OE toE, (HIGH to Cutotfy 1.5 5.0 1.6 5.0 Figures 1&2 tpuz | DIRtoE, J . 1 . 4. (HIGH to Cutoff 1.6 47 6 43 1.7 7 Figures 1&2 trun | Transition Time i . 0.4 . trHe 20% to 80%, 80% to 20% | 4 28 24 Figures 1 & 2 Cerpak ECL-to-TTL AC Electrical Characteristics Veg = —4.2V to —5.7V, Vit, = +4.5V to 45.5V, CL = 50 pF 'PLH CP toTn 34 so | 31 73) 33 8.0 Figures 3 & 4 tPHL tpzH OE toT, 3.4 94 37 90 | 40 10.1 tezi (Enable Time) 37 9s | 40 93 | 43 10.4 Figures 3&5 123 tpuz OE to Tp 3.2 100 | 33 90] 35 93 ; i teiz (Disable Time) 3.0 98 | 34 ea | a4 10.4 Figures 3&5 tpnz DIR toTh 26 95 | 28 88 | 30 9.0 ; Fi tpiz (Disable Time) 27 a7 | 31 80] 40 96 ‘igures 3&6 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals - 55°C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures, Note 2: Screen tested 100% on each device at + 25°C temperature latched only, Subgroup AQ. Note 3: Sample tested (Method 5005, Table |) on each manufactured lot at + 25°C, Subgroup AQ, and at + 125°C and — 55°C. temperatures, Subgroups A10 and AN Note 4: Not tested at + 25°C, + 125°C, and — 55°C temperature (design characterization data).

FIGURE 1. TTL to ECL AC Test Circuit

1 I yo i

FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows:

100329 D C QR

Device Type (basic) re oe cL Special Variations QR = Commercial grade device Package Code with burn-in D = Ceramic DIP QB = Military grade device with F = Quad Cerpak environmental and burn-in Q = Plastic Leaded Chip Carrier (PCC) processing Temperature Range C = Commercial (0°C to + 85°C) M = Military (— 55°C to + 125°C)

Physical Dimensions inches (mitlimeters) Se (30.86) 0.025 MAX 0.030 — 0.055 fap | Ba _[23]_[22]_f2) feo] fis) fre) fi7]_ fe) iS) fra) fed ae a0 \\ D aso (9.906) — MAX (9.398) MAX GLASS !) OT Tz) ts) ey sy tel GT Te) Ge bo el 0.037 +0.005, | je SOS MIN (0.508 — 1.778) MAX —_“* 0.225 (5.715) - MAX _¥ 86° 94° me om tet TYP —? ip-203—0.305) 0.125 Te MAX Tye TYP BOTH ENDS JME (REV) 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)

Physical Dimensions inches (mitlimeters) (Continued)

6 SPACES AT

0.050 (1.270) ~ 0.130 ‘ae (3.302) i uA NOM | 1s PEDESTAL, Forlvivlelelelelant ; oe = a Ssmcesat = Ly Q | — 0.326 VIEW A-A 0.050 ry che (6280) 07) Ae a NOM SQUARE Be Om 4, Nig 0.045 218 0.045 16) he wr ssl a xa sas 0.410 ~0.430 (io.at— 10.92) l.. ‘SQUARE (CONTACT DIMENSION) 0.020 0.013-0.018 0.005 —0.015 f (0.127—0.381) PON. 1 oxs—ons—f o4-o8 went (060-0813) (2.6422 997) 0.450 we (1.43) AEF SO 0.485 — 0.495 (12.32 —12.57) ‘SQUARE V2GA (REY G) Note: Pedestal as shown on base is not available for F1000K ECL products 28-Lead Plastic Chip Carrier (Q)

3 Physical Dimensions inches (millimeters) (Continued) Lit. # 114910 bo osm 0.004—0,006_ a (6.350—9.144) MIN SQUARE 16:350—9.144) = H PIN NO. 1 - | Ss = | e fre gmnws £ | Ss | - 0.075 [s) | (7.905) o PLCS — 0.016—0.018 | MAX 0.035 ~ 0.050 0.400 TYP 2.159) -l (10.16) MAX = SQUARE MAX GLass ~ wa24B EC) Oo 24-Lead Quad Cerpak (F) Ww NS Package Number W24B s fs) [o] a a ao N o LIFE SUPPORT POLICY o (=) NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT r DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL uu SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury woe JS to the user. tee ee YF) National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semicondutores National Semiconductor Corporation ‘cmb Japan Ltd. Hong Kong Lia. Do Brasil Ltda. (Australia) PTY, Lic. 2900 Semeconductor Onve _indusiestrasse 10 Sansodo ig. SF Suto 513, 8th Foor Av. Big Fara Lina, 1389 1st Floor, 443 Si. Kida Ad P.O. Box 38000 0.8080 Furstenolgbruck 4-15 Nah Shinju Chnacher Golden Piaza, 80 Andor. Cony 62 Matboume, 2006 Santa Clara, CA 95052-8000 West Gormany Shinghu-ku, 77 Mody Road, Tamshatsu East, 01451 Sao Pauio, SP. Bras! Victory. Austahia Tet (408) 721-5000 Tet (084-44) 109.0 Tokyo 160, Japan Kowloon, Hong Kong Tok (55/11) 212.5066 Tet (03) 267-5000 TWX: (910) 399-6240 Telex: 527-649 Tot 3299-7001 Tor 3.7231200 Fax (65/11) 291-1181 NSBR BA Fax: 61-3-2677458 Fax (08141) 109564 FAX’ 3.290-7000 Telex. 52996 NSSEA HX Fae 3.311256 National doesnot assume any responstty for use of any crufty described, no crcut patent iconses are mph and National reserves the ight a any ime without notice to change sid crcusby and spactcations. ib