F100304

F100304 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 4

Technical content

i—J National 3 Semiconductor * Low Power Quint AND/NAND Gate General Description Features The F100304 is monolithic quint AND/NAND gate. The ™ Low Power Operation Function output is the wire-NOR of all five AND gate out- ™ 2000V ESD protection puts. All inputs have 50 kQ pull-down resistors. @ Pin/function compatible with F100104 ™ Voltage compensated operating range = —4.2V to -5.71V eS Ordering Code: see sections Logic Symbol Logic Equation e F = Dta* Daa) + (Dip * Day) + Dye Dac) + Dig ® Dag) + (Die * Dae). Dia Oe Die O Dna-Dne Data inputs Deo Op F Function Output Die Oc Qa~Oo Data Outputs Dae Oe 6,-5. Complementary Data Outputs Die Oa Dog os Die Oe Dee oO. TUF /10561~1 Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak Y Dag Dna Verse Op Oy Dag Dre Ore Yer D2 Dip oe 247-02 Hoan 3,42 2sbo,, 2423 22 21 20 19 2 | ous 22h O14 Oy Bo, a A ae oy PY ao Oop wo, Dez 17 Dig ‘eG Deca pds 160, rs 20D. Vers Dee 3 Veo“ 6 19 Dy. 0, Bec 4 157-0 You{7 18+ Vee 0, mr 45 4b, i Ogg % Os 130 0-48 17 Day 4 » 7.8 9 10 11 12 O79 16F=Dy, Batam OA 10 15}=Doq Mare DraVeEs% Oy Oy % F Yee Yoca 5¢ % Ott 4-01, THE/I0585-4 TL/F/10581-8 O,4t2 13-0, TUF 0581-2 2413

8] Absolute Maximum Ratings Recommended Operating J Apowe ion the useful life may te impaired (Note » wa Conditions ry/Aerospace specified devices are required, please contact the Natlonal Semiconductor Sales Case Temperature (Tc) Octo +85 Offie/Distrbutors for availability and specifications. Miltary gC to + 128°C Storage Temperature (Tgtg) —65°C to + 150°C Supply Voltage (Vee) Maximum Junction Temperature (Ty) Commercial -57V to -4.2V Ceramic +178C Military -5.7V to —4.2V Plastic +150°C Vee Pin Potential to Ground Pin -7.0V to +0.5V Input Voltage (DC) Veg to +0.5V Output Current (DC Output HIGH) —50 mA ESD (Note 2) 22000V Commercial Version Vee = —4.2V to -5.7V, Voc = Veca = GND, Tc = 0°C to +85°C (Note 3) symbol [Parameter [min | typ | Max | units | Conditions Vox OutputHIGH Voltage | —1025 | -955 | -870 | mv | Vin=Vinwwax | Loadingwith Vou OutputLOw Voltage | —1830 | —1705 | 1620 | mv | °rViLimin 500 to ~2.0V Vouc OutputHIGH Voltage | —1038 | | | mV. | Vin = Viewmiry | Loadingwith Vin Input HIGH Voltage 4168 870 my | Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage 1475 mv Guaranteed LOW Signal for All Inputs MW Inputow Curent [oso | [| wa | Vin = Vin hin Input High Current D2a-Dee BA Vin = Vin(Max) Dia-Dio Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the “worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Veca = GND teLy Propagation Delay tei Propagation Delay B . J x 14 i 1 tity Transition Time 244

Commercial Version (continue) 3 PCC and Cerpak AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = Voca = GND sym | ame ae aaa] ome | Sonn teLy Propagation Delay hivi Dra-Dro t0 0,0 040 145 | 040 1.55 tPLH Propagation Delay trLH Transition Time tron 20% to 80%, 80% to 20% 0.35 4.15 0.35 1.10 ts,a.¢ | Skew, Gate to Gate [reo [tap | rep | ps | POCOniy (Note 1) Note 1: Gate to gate skew is defined as the difference in propagation delays between each of the outputs. Military Version—Preliminary Vee = —4.2V to —5.7V, Voc = Voca = GND, Tc = —55°C to + 125°C symbol [Parameter [min [ Max [units [Te [Conditions _——|_—(Notes Vou Output HIGH Voltage _ 0°C to 870 | mV | asc [| ~1085 | -e70 [mv [7 —s50 | Viv= VuyiMax) | Loadingwith | 5 Vou Output LOW Voltage mv | oCto orViL (Min) | 500 to —2.0V +125°C | =ies0 | —v555 [mv [sero _| Vonc Output HIGH Voltage mv OC to + 125°C Voc | Output LOW Voltage my | Octo OF Vit. (Max) 500 to ~2.0V +125°C [| 1555 [mv [sec | Vin Input HIGH Voltage _ _ —55°C | Guaranteed HIGH Signal 1165 | —870 | mV | 4426 | for All inputs 1,2,3,4 Vit Input LOW Voltage _ _ —55°Cto | Guaranteed LOW Signal 1830 | —1475 | mV | toss | tor All Inputs 1.2.8.4 Ie Input LOW Current —55°Cto | Vee = —4.2V BA +125°C Vin = Vit (Min) 12,3 2 | Input High Current Dza-Dog BA oC to Dia-Die #1250 | Vee = -5.7V 1.23 i) Doa=Doe seq | NT Vivian 2 a | —55% Dia~D1o e Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals — 55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at —S5°C, + 25°C, and + 125°C, Subgroups, 1, 2 3, 7, and 8. Note 3: Sample tested (Method 5005, Table I} on each manufactured lot at — 55°C, +25°C, and + 125°C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing Vou/VoL- 2-15

Note 2: Screen tested 100% on each device at + 25°C temperature only, Subgroup Ag. Note 4: Not tested at +25°C, + 125°C, and — 55°C temperature (design characterization data). FIGURE 1. AC Test Circuit