F100183

F100183 NSC | Alldatasheet

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2 x 8-Bit Recode Multiplier General Description The F100183 is a 2 x 8-bit recode multiplier designed to F100183 performs parallel multiplication of two signed num- perform high-speed hardware multiplication. In conjunction _ bers in twos complement form to produce a signed twos with the F100182 Wallace Tree Adder, the F100179 Carry complement product. All inputs have 50 kf pull-down resis- Lookahead, and the F100180 High-speed Adder, the tors. Ordering Code: see sections Logic Symbol | PinNames | Description Bs Bg B83 Ba B; ant 7 Be Os Ds Ba Be Bs Bo Ag-Ag Multiplier (Recode) inputs At Bo-Bg Multiplicand Inputs Ag F Fo-F7 Partial Product Outputs Fe Fr Fe Fs Fa Fs Fo Fi Fo Fe Sign Extension Output TU 8675-3 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak a, Ay Ay Ar Ver By Bs Bo]! 24-8, Fo-q2 23-e, 24 23 22 21 20 19 ros z2be, es! 18} Bg Fomq4 21f—Ag bin Ue 17 By F545 20 A, a5 165 Bg Veo46 ha, Bom4 15 Fg Voca47 18} Vee Fo-5 14 Fy ys 7he, Fie 13 Fe F549 16}, 7.8 9 10 11 12 Feito 15}—B. Fy Fs VocVecaFy Fs Pie 14-8, TLIF/9875-2 Fiz 13}-8, TUF 9675-1 3-214

. . s Logic Diagram S$ Ar ———— pT i . ~ (SF a ° ae * tip a—Q Ly ; i. 2 eT =O Pip e—R i . =e . I] Tf 5 DED-n | or »—Q } ie . — eo ore | Th i ES ire } ED HOO HHO! | ite nt Ce re | HAs DED-* ot per (es Ah || Hest th U YOY Yo 0 OUQOU U U U in i. U U U Fe fr Fe TuF/9678-5 Truth Table Inputs Recode Outputs Ag Ay Ao Mode Fe Fy Fe Fs Fe Fy Fa Fy Fo L L L 0 H L L L L L L L L L L H +1 Be Bs B7 Be Bs By Bg Bo By L H L +1 Bg Bg B; Be Bs By Bg Ba By L H H +2 Bs By Be Bs Ba Bg Bo By Bo H L L -2 Bg By Be Bs By By By By Bo H L H -4 Bg Bs By Be Bs Ba Bs Bo By H H L -1 Bg Bs By Be Bs By B3 Bp By H H H cj H L L L L L L L L H = HIGH Voltage Level L = LOW Voltage Level 3-215

3 Absolute Maximum Ratings

S| Above which the useful life may be impaired. (Note 1) If Military/Aerospace specified devices are required, Case Temperature under Bias (To) O°C to +85°C please contact the National Semiconductor Sales Vee Pin Potential to Ground Pin -7.0V to +0.5V Sirice/Dietibutors for availability and specications. Input Voltage (DC) Vee to +0.5V torage Temperature ~65C to + 150°C Output Current (DC Output HIGH) —50 mA Maximum Junetion Temperature (T,) + 150°C Operating Range (Note 2) 5 7Vt0 -4.2V Vee = —4.5V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Vou OutputHIGH Voltage | -1025 [ -955 | -e80 | 4 | Vin=Vinimay | Loading with Vou Output LOW Voltage | —1810 | -1705 | —1620 | oF Vi (Min) 500 to ~2.0V Voxc OutputHiGH Voltage | -10395 | || agy | Yin = Vin awiny | Loadingwith Voc | Ouputtowvotage | | | 610 _| or Vit Men S00 to =20v Vin Input HIGH Voltage ~a165 880 my | Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage _ Guaranteed LOW Signal 1475 mv for All inputs in Inputvow current | 050] fT A Viv = Vic win Vee = —4.2V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) symbol [Parameter | min | Typ | Max | Units | Conditions (Note 4) Vou OutputHiGHVoltage | -1020 | | -870 | iy Vin = Vin (Max) | Loading with Vou Output LOW Voltage -1810 | ———[|_ —1605 | oF Vin (Min) 500 to ~2.0V Voxc Output HIGH Voltage | 1090 | || y Vin = Vin (miny | Loading with Vous | OutputLowvottage | || = 1505 _ | orMie (men) Sp to ~20N Vin Input HIGH Voltage 4150 870 mv Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage 4475 mv Guaranteed LOW Signal for All Inputs We inputtow Curent [oso TT Twa vv = Vin win Vee = —4.8V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Symbol | Parameter [min | typ | max | units | Conditions (Note 4) Vou OutputHiGH Voltage | -1035 | | 880 | iy Vin = Vin (Max) | Loading with You OutputLowVottage |" 1830 | | 1620 _| or Mi cin S00 to =20¥ Vouc OutputHiGH Voltage | -104 | || ay Vin = Vin (min) | Loading with Vouc. OutputLowVvoitage | || | 1610 or Vit (Max) 502 to —2.0V Vin Input HIGH Voltage 880 mv Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage — 1490 mv Guaranteed LOW Signal for All Inputs ‘Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Parametric values specified at —4.2V to —4.8V. Note 3: The specified limits represent the “worst case" value for the parameter. Since these “worst case” values normally occur at the temperature extremes, ‘additional noise immunity and guard banding can be achiaved by decreasing the allowable system operating ranges. Note 4: Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3-216

Vee = —4.2V to —4.8V unless otherwise specified, Voc = Voca = GND, Tc = 0°C to + 85°C g symbor [Parameter | __win [Typ | Max | Unte | Conditions im Input HIGH Current Bo-Be 215 Ag 215 _ Ay 285 pA Vin = Viz (Max) Ag 310 Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = —4.2V to —4.8V, Voc = Voca = GND Symbol [rama | ee = tan wax | = jm | Senamene PH - 2 von. = Figures 1 and 2 tPLH ropagation Delay er 0.90 3.20 | 100 310 | 1.00 3.60 PHL [ Rencstonooty | ome am | 100 a0 | 1a am | oe | tPHL Bo=Bg to Fo-F7 Figures 1 and 2 (Pun Propagation Delay 080 200 | 090 200 | 090 2.60 Jos | tPHL Bg toFe ‘LH Transition Time 045 250 | 045 240 | 045 260 Figures 1 and 2 trHt 20% to 80%, 80% to20% | : : ; : et Cerpak AC Electrical Characteristics Ver = —4.2V to -4.8V, Voc = Voca = GND 'PLH Propagation Delay 410 3.70 | 110 360 | 1.10 4.00 tert Ao~Aa to Fo-F7 Figures 1 and 2 tPLH Propagation Delay or 0.90 300 | 100 290 | 1.00 3.40 teHL Ag-A2 to Fa {Pu Propagation Delay 080 200 | 090 195 | 090 2.90 | | {PHL Bo-Bs to Fo-F7 Figures 1 and 2 teLH Propagation Delay 080 180 | 090 180 | 090 2.30 tPHL Bg toFs tTLH Transition Time , trHe 20% 10 80%, 80% to 20% | O45 240 Figures 1 and 2 3 3-217

FIGURE 1. AC Test Circuit

FIGURE 2. Propagation Delay and Transition Times: plying, the multiplier is partitioned into recode groups, then Tables | and Il. an additional 10.7 ns. Then the Carry Lookahead generator obtain a signed result.

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3 Application (continued)

r TABLE II. Package Count 100102 400117 100183 100182 100180 100179 Total 16x16 6 16 32 6 2 = 62 18x18 7 27 38 6 2 = 70 24x 24 9 36 60 8 2 = 115 32x32 11 64 96 1 4 = 186 36 x 36 13 80 116 12 4 = 225 64x64 24 256 328 22 6 = 634 For a quick review of the twos complement number format TABLE III. Twos Complement Format see Table III. Note that subtraction is accomplished by add- ing the negative number. An example of changing from a Sign Magnitude positive number to a negative number is shown. Bit 22 21 20 1011 negative number-5 0 1 1 1 +7 0100 bits inverted ° ' ‘ ° +e its inverte 0 1 +5 +0001 add one ' ° “OT0T Results 5 ° ' ° ° +4 0 0 1 1 +3 i) 0 1 O +2

9 O 0 1 +1

0 0 O ° +0 1 1 1 1 -1 1 1 1 ) -2 1 1 i} 1 -3 1 1 0 bY) —4 1 oO 1 1 -5 1 0 1 0 -6 1 oO oO 1 -7 1 oO 9 i -8 3-220

multiplicand. A forced zero is required to establish the least sults of four groups, 1228549, we have the correct answer.

1 LY) i) -2 ‘Subtract twice the

FIGURE 4. 16 x 16 Multiply

o S| Hardware Implementation S| For the nardware implementation of the F100183 recode Forces Zero multiplier the sign bit is connected to the Bg input, and B7 orr01001 f° = 105 through Bo are the magnitude bits. Two extend the word Orto1Ig” = 17 length greater than eight bits, the Bo and Bg inputs of adja- = cent devices are connected together (see Figure 7). The 4241 device outputs Fo through F7 are used as the partial prod- —_ ucts; these correspond to Ag through Az, or Ag through Ajs5, fiG1101001) or Bo through B7, etc. To reduce the hardware, the Fg bit ° (Aig in Figure 7) is used as the sign bit of the partial prod- Forr0100y uct. The sign bits are extended by using hardware wired Hardware- 2 logic “1s”. The ones are located in front of each partial Wied cor0119 product with an extra “'1” at the sign bit of the first partial Logic 19) Rounding Bits product as in Figure 4. The logic ‘‘1s” are wired as inputs ones “ {external gates! into the Wallace Tree Adders as shown in Figure 6. If the 771010010) recode group requires the multiplicand to be added, then ———1__ the F100183 outputs the correct partial products to be add- O010199191111101 = 12285 ed. But when the recode group requires that the multipli- TL/F/9875-10 cand be subtracted, then the F100183 outputs the ones FIGURE 5. Example of Multiplication complement. External gates are required to generate a “1” Using Rounding Bits to be added to the ones complement to complete the twos complement for the partial product (Figure 7). These exter- nal gates generate the rounding bits, Kg ... Kn, which are input to the Wallace Tree Adder. Figures 4, 6 and 7 show the location. An example of multiplication which has the rounding bits and the hardware wired logic “1s” is shown in Figure 5. The weighted partial products are added together using F 100182, 9-bit Wallace Tree Adders as shown in Figure 6. The output is a partial sum and partial carry which can be reduced to the final product using Carry Lookahead and 6- bit adders. See Figure 8. 3-222

FIGURE 6. F100182 Hook-up for 16 x 16 Multiplier

3 Hardware Implementation (continued)

FIGURE 7. F100183 Hook-Up for 16 x 16 Multiplier

FIGURE 8. Final Summation for 16 x 16 Multiplier