F100151 NSC | Alldatasheet

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Semiconductor ~ Hex D Flip-Flop General Description The F100151 contains six D-type edge-triggered, master/ and makes the Q outputs LOW. All inputs have 50 k. pull- slave flip-flops with true and complement outputs, a pair of down resistors. common Clock inputs (CP, and CP,) and common Master —_ Refer to the F100351 datasheet for: Reset (MR) input. Data enters a master when both CPa and PCC packaging Pp are LOW and transfers to the slave when CPa and CPh Lower power (or both) go HIGH. The MA input overrides all other inputs Military versions Extended voltage specs (—4.2V to —5.7V) Ordering Code: see sections Logic Symbol crs| |cre [_PinNames | Description ) Do-Ds, Data Inputs CP, CPp Common Clock Inputs CP Do Dy Dz D3 Oy Ds MR Asynchronous Master Reset Input Qo-Qs5, Data Outputs MR QQ; = Q@2— 3, as Qo-Os, Complementary Data Outputs TLIF/9059-3 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak ay, CPy, CP, MR Ver Dy Dp a) eo yz 23d, 24 23 22 21 20 19 es Fd 22D, os 185-0, a4 21h cr, O52 1750p as 20,-cP, he 18 Q% Voo—46 19, =MR a4 15} Q Veca-47 18 Ver Qs 14a, a-48 17/-D; i be ee of 160, 78 9 1012 Q-qi0 155, Os 3 Vor Veca 2 Oy Qa" 14-0p TUF 9859-2 O12 13} Q Top View TUF /9859-1 3-119

3 Logic Diagram

r Do Dy O2 Os De MR CPACPy Ds YU ee ee ee ee ee ee ee eee ee G a a @ a @ a& a Gs Os ‘TL/F/9859-5 Truth Table (Each Fiip-tiop) Synchronous Operation | On | ces | ce | ma | antsy L zs L L L H a L L H L L a L L H L Ma L 4 x H a L Qalt) x a H L On(t) x L L L Qn(t) Asynchronous Operation Lx] « | x fu To | H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care t = Time before CP positive transition t+1 = Time after CP positive transition 7 = LOW-40-HIGH transition 3-120

Absolute Maximum Ratings 8 Above which the useful life may be impaired. (Note 1) a If Military/Aerospace specified devices are required, Case Temperature under Bias (Tc) O°C to + 85°C please contact the National Semiconductor Sales Vee Pin Potential to Ground Pin -7.0V to +0.5V orre/Dietrbutors for availability and specitications. Input Voltage (DC) Veg to +0.5V Storage Temperature BEC to + 150°C Output Current (DC Output HIGH) 50 mA Maximum Junction Temperature (Ty) +150°C Operating Range (Note 2) ~5.7V to -4.2V Vee = —4.5V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Symbol [Parameter [Min | Typ | Max | unite | Conditions (Note 4) Vox OutputHIGH Voltage | —1025 | -955 | -e80 | (4 | Vin=Vinimax | Loading with VoL Output LOW Voltage ~isio | -1705 | —1620 or Vit (Min) 502 to —2.0V Vouc OutputHiGHVottage | 10395 [|| ay | Yin = Vinny | Loading with Vor | Outputrowvotage | | | — 1610 _| or Vi. (en) 500 to =2.0N Vin Input HIGH Voltage _ _ Guaranteed HIGH Signal 1165 880 mV | for All inputs Vit Input LOW Voltage 1475 | mv _ | Guaranteed LOW Signal for All Inputs in Inputtow Curent | oso [fw | Vv = View Vee = —4.2V, Voc = Voca = GND, Tc = 0°C to + 85°C (Note 3) symbol [Parameter | Min | Typ [| Max | Units | Conditions (Note 4) Vou Output LOW Voltage | -1810 | | —1605 | or Vit (min) 10-2 Vous | OutputtigHvotage [ -roo [| ay | Min= Viktny | Loading with Voc | OutputLowvoitage | | | 1595 | oN ones) one Vin Input HIGH Voltage Guaranteed HIGH Signal 870 mv for All Inputs Viv Input LOW Voltage _ _ Guaranteed LOW Signal 1810 1475 mV for All Inputs Vee = ~4.8V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) symbol | Parameter [win | typ | Max | Units | Conditions (Note 4) Vou OutputHIGH Voltage | 1095 | | 880 | Vin = Vin (max | Loading with Vou OutputLowvortage | -1e30 | | -1620_| or Ni (iy S00 to 7 20V Vou OutputHiGHVottage | -1045 [| | my Vin = Vin (min) | Loading with Vin Input HIGH Voltage —e80 mv Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage ~1830 ~1490 mv Guarantoed LOW Signal for All Inputs Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Parametric values specified at —4.2V to —4.8V. Note 3: The specified limits represent the “worst case” value for the parameter. Since these “worst case" values normally occur at the temperature extremes, additional noise immunity and quard banding can be achieved by decreasing the allowable system operating ranges. Note 4: Conditions for testing shown in the tables are chosen to guarantee operation under “worst case" conditions. 3-121

wo . . . 5 | DC Electrical Characteristics s Vee = —4.2V to ~4.8V unless otherwise specified, Voc = Voca = GND, Tc = 0°C to +85°C mm Input HIGH Current MR Do-Ds BA Vin = VIH (Max) CPa, CPh lee Powersupply Curent | -2t0 | -155_ | 98 | ma | inputs Open Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = —4.2V to —4.8V, Voc = Veca = GND tel Propagation Delay ; tPLH Propagation Delay . tea MR to Output 1.20 2.90 1.30 3.00 Figures 1 and 4 tTLH Transition Time . ts Setup Time ‘ Do-Ds 0.70 0.70 0.70 Figure 5 MR (Release Time) 2.30 2.30 2.60 Figure 4 th Hold Time - femme [ow fom [om | | Pawo? Pulse Width HIGH - ‘raft CPa, CPb, MR feo jem fem | Figures Gand 4 Cerpak AC Electrical Characteristics Vee = —4.2V to —4.8V, Voc = Veca = GND fpex___|_ Toggle Frequency [sms | ars as [ie | Figures 2ana 9 tPLH Propagation Delay 5 tPLH Propagation Delay tPHL MR to Output 1.20 2.70 1.30 2.80 Figures t and 4 tTLH Transition Time ts Setup Time 5 Do-Ds 0.60 0.60 0.60 Figure & MR (Release Time) 2.20 2.20 2.50 Figure 4 th Hold Time Figure 5 Pulse Width HIGH . ‘endl CPay CP, MR fem [20 fam | | Figures Sand 4 3-122