F100141 NSC | Alldatasheet
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8 A National
The F100141 contains eight edge-triggered, D-type flip- “parallel entry”, “hold”, “shift left” or “‘shift right” as de- flops with individual inputs (Pp) and outputs (Q,) for parallel __scribed in the Truth Table. All inputs have 50 kQ. pull-down operation, and with serial inputs (D,) and steering logic for _ resistors. bidirectional shifting. The flip-flops accept input dataa setup —_ Refer to the F100341 datasheet for: time before the positive-going transition of the clock pulse PCC packaging and their outputs respond a propagation delay after this ris- Lower power ing clock edge. Military versions The circuit operating mode is determined by the Select in- Extended voltage specs (—4.2V to —5.7V) puts Sg and S;, which are internally decoded to select either Ordering Code: see sections Logic Symbol cp cP Clock Input ° So, $1 Select inputs St Gy 1 Qe Q Oe Os Os QF Do, D7 Serial Inputs Po-Pz Parallel Inputs TUF /9856-1 Qo-@7 Data Outputs Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak ay, Ps Sy So Ver cp Py Do! 24b=Po 42 2b, 24 23 22 21 20 19 ads ne, Pot 18 Ps aa 21 Py Pymq2 17 Pg as-45 noes, Pos 16 =P, Yoo 19S D4 155 Dy Youu 47 18-Vep M45 4a, ae 17 cP ays 137-05 7 8 9 10 11 12 ®49 16 P, Q-410 15-5 O 3 Vor Vora Oy 25 Qait 14 =P TL/F/9856-3 Diz 13,;-P, TUF/9856-2 3-100
. Po PARALLEL Poe 8 0 6 we Py ~ pepe HDS tS tb o— it “D7 |en -—Da;} -Dal Dp =e. ROT FE FO] | Ol oil Ta ttéSeat ltseat titseat [llseat Soe Sea Hon cP. Q Qe eee 6 6 Oe ra Truth Table ee Shift Left H L Zs | % 4 Q | H Shift Right H H L ~~ H Q; Qs Qy Hold x H H x 00a Hold x x x L H = HIGH Voltage Levet L = LOW Voltage Level X = Don't Care _/ = LOW-to-HIGH transition 3-101
S| Absolute Maximum Ratings Ss Above which the useful life may be impaired. (Note 1) If Military/Aerospace specified devices are required, Case Temperature under Bias (To) O°C to +85°C please contact the National Semiconductor Sales Vee Pin Potential to Ground Pin ~7.0V to +0.5V Office/Distributors for availability and specifications. Input Voltage (DC) Vee to +0.5V Storage Tempera + ~85'C to + 160°C Output Current (DC Output HIGH) —50mA Maximum Junction Temperature (Ty) +150°C Operating Range (Note 2) -57Vt0 —4.2V Vee = —4.5V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) symbol | Parameter | Min | typ | Max | units | Conditions (Note 4) Vox OutputHIGH Voltage | -1025 | —955 | -se0 | | Vin=Vinimag | Loading with Voxc OuputHiGHVottage | -1035 | | || YiIn= Minin) | Loading with Via Input HIGH Voltage _ _ Guaranteed HIGH Signal 1165 880 ™V | for All inputs Viv Input LOW Voltage ~4810 1475 | my | Guaranteed LOW Signal for All Inputs Vee = —4.2V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) symbol | Parameter | min | typ | Max | Unite | Conditions (Note 4) Vou OuiputHiGH Voltage | -1020 | | -e70 | Vin = Vin (Max) ] Loading with Vou Output LOW Voltage -is10 | | -1605 | OF ViL (Min) 509 to —2.0V Vouc Output HiGHVoitage | -1090 | || Vin = Vid (Min) | Loading with Vin Input HIGH Voltage 1150 —e70 mv Guaranteed HIGH Signal for All Inputs Vie Input LOW Voltage 4810 4475 mv Guaranteed LOW Signal for All Inputs Vee = —4.8V, Voc ~ Voca = GND, To = 0°C to +85°C (Note 3) symbol | Parameter | Min | Typ | Max | Units _| Conditions (Note 4) Vou OutputHIGH Voltage | -1095 [| 880 | oy Vin = Vin(Max | Loading with Vou Output LOW Voltage | -1890 | | —1620 oF Vit (Min) 500 to —2.0V Vouc Output HIGH Voltage -0 [| oy Vin = Vit (Min) Loading with Vorc | OutputLowvottage | || 610 _| oN en S00 to 20N Vie Input HIGH Voltage aa165 p80 mv Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage Guaranteed LOW Signal mv for All Inputs in Inputtow current | 050 | [Te Vin = Vii Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Parametric values specified at —4.2V to — 4.BV. Note 3: The specified limits represent the “worst case" value for the parameter. Since these “worst case” values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Note 4: Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3-102
Vee = —4.2V to —4.8V unless otherwise specified, Voc = Voca = GND, To = 0°C to +85°C = tin Input HIGH Current Dn. Pr: Sn BA Vin = Vix (Max) cP Ceramic Dual-In-Line Package AC Electrical Characteristics Veg = —4.2V to —4.8V, Voc = Voca = GND sim [Parente a [ [ae Um | conto teHL CP to Output : 7 7 ° Figures 1 and 3 tTLH Transition Time ts Setup Time Dn. Pr 0.85 0.85 0.85 Sp 2.20 2.20 2.20 Figure 4 tH Hold Dn Pr 0.60 0.60 0.60 Sh 0.10 0.10 0.10 tow(H) Pulse Width HIGH 7 Cerpak AC Electrical Characteristics Veg = —4.2V to —4.8V, Voc = Voca = GND srmet [ramet | isa Ute | conto fgnit___| Shift Frequency [soo | a00 | aso Me | Figures 2and 9 ‘PLH Propagation Delay 090 220 | 110 210 | 110 230 Le | tPHL CP to Output : : . : . : Figures 1 and 3 tTLH Transition Time ts Setup Time Da Pr 0.75 0.75 0.75 Sa 2.10 2.10 2.10 Figure 4 tH Hold Dp. Pr 0.50 0.50 Sn i) 0 cp | s 3-103
FIGURE 1. AC Test Circuit
500 Qp Qs Gz Qs Q4 Os Qs Q7
Pulse generator connected to Sy has a LOW frequency 99% duty cycle, which allows occasional parallel load. ‘The feedback path from output to input should be as short as possible. FIGURE 2. Shift Frequency Test Circuit (Shift Left)