F100131

F100131 NSC | Alldatasheet

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8 GA National

7 Semiconductor

The F100131 contains three D-type, edge-triggered master/ Master Reset and individual CD, and SD, inputs override slave flip-flops with true and complement outputs, a Com- _ the Ciock inputs. All inputs have 50 kM pull-down resistors. mon Clock (CP), and Master Set (MS) and Master Reset Refer to the F100331 datasheet for: (MR) inputs. Each flip-flop has individual Clock (CP,), Direct PCC packaging Set (SD,) and Direct Clear (CD,) inputs. Data enters a mas- Lower power ter when both CP, and CPc are LOW and transfers to a Military versions slave when CP, or CPc (or both) go HIGH. The Master Set, Extended voltage specs (—4.2V to —5.7V) Ordering Code: see sections Logic Symbol TT TF [PinNames [Description CPo-CP2 Individual Clock Inputs JOY oP Common Clock rp . DD Do-Do Data Inputs Ste CPr GPa Da 01 Oe CDp-CDz Individual Direct Clear Inputs cD, SDp Individual Direct Set Inputs De MR Master Reset Input SDo Ms Master Set Input sp Qo-Q2 Data Outputs so, Go-Fe2 Complementary Data Outputs AMS Qo QQ TLF/98s3-9 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak a, Dy SD MR Veg CPe MS ct 240, P22 23--cd, 24 23 22 21 20 19 ods r2bcr, crt 18} $09 as 2ifo, 0,42 17} cq as 20s, $0243 16 cPy Ves tole co, 44 15F-0, Voca—47 18F-Veg CPS 4 % 0-46 3G 8 17 cr, 2 ‘0 a c 78 9 101112 as 16;-ws G-F10 15F-SD Qp Oy Vee Voc, 2} fit 14F-Cdp TLF/9853-2 Dp] 12 13, CPy TLF/98s3—1 3-76

o SDp Do = CPo Dp SD; Dy CP, CD; SD2 Dz CP2CPe = CDz - LJ cP | I [J cP | ' Oo cP r so co " r So © i So Cp wa — DD a es Q Qo Qa, a Q2 Q TUF/9959-5 Truth Tables (ach Fiip-Fiop) Synchronous Operation Asynchronous Operation [pute tte] te Yt L a L L L L x x H L H H ~ L L L H x x L H L L cl} 7 L L L x x H H u H L sy L L H x L L L L nity x H x L L Qnit) x x H L L Qnit) H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care ‘U = Undefined 1 = Time before CP Positive Transition t+1 = Time after CP Positive Transition — = LOW to HIGH Transition 3-77

&| Absolute Maximum Ratings Ss Above which the useful life may be impaired. (Note 1) If Military/Aerospace specified devices are required, Case Temperature under Bias (Tc) OC to +85°C Please contact the National Semiconductor Sales Vee Pin Potential to Ground Pin —7.0V to +0.5V Office/Distributors for availabilty and specifications. Input Voltage (DC) Vezto +0.5V Storage Temperature 65°C to + 180°C Output Curent (0G Output HIGH) 50 mA Maximum Junction Temperature (T,) +150°C Operating Range (Note 2) -57Vto -4.2V Vee = —4.5V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) symbol | Parameter [min | typ [Max | Units | Conditions (Note 4) Vox OutputHIGH Voltage | -1026 | -955 | -ee0 | 4, | Vin=Vinqmax | Loading with Vou Output LOW Voltage | -1810 | -1705 | —1620 | OF Vit. (Min) 509 to ~2.0V Vouc OutputHIGH Voltage | -1035 | | si mv My, = Vintwin) Loading with Voc | Ouputvowvorage | | | ~t610_| oN an) on? Via Input HIGH Voltage —e80 my | Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage —4810 447s | mv__| Guaranteed LOW Signal for All Inputs in Inputtow Curent | oso [TT wa [Vv = Vin in Vee = —4.2V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Symbol | Parameter [Min | typ | Max | Units | Conditions (Note 4) Vou Output HIGH Voltage | -1020 | | -870 | 1 | Vin=Vincway | Loading with Vou Ouiputrowvotage | -te10 | | -1605_| or Mie imi S00 to =2.0V Vouc Output HIGH Voltage [ 1090 | || Vin = Vin (Min) Loading with Vor | OutputLowvottage | || 15095 | or Vit Ma S00 to = 20V Vin Input HIGH Voltage 1180 870 mv Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage ~t810 a 147s my | Guaranteed LOW Signal for All inputs in InputLow Current [oso |] Twa Vv = Vici Vee = —4.8V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Symbol | Parameter | min | typ | Mex | unite | Conditions (Note 4) Vou OutputHIGH Voltage | -1035 | | -800 | 7. | Vin=Vinqway | Loadingwith Vou OutputLOw Voltage | -1830 | (| —1620 or Vib (min) 500 to —2.0¥ Vouc OutputHiGH Voltage | -1045 | || ay Vin = Vin (in) | Loading with Vouc OutputLow Voltage | |_| — 10610 or Vit (Max) 500 to —2.0V Vin Input HIGH Voltage 4165 980 mv Guaranteed HIGH Signal for Al Inputs Vit Input LOW Voltage 1830 1490 mv Guaranteed LOW Signal for All Inputs in InputtowCurent | oso | [TA | Vin = Vin Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Parametic values specitied at ~4.2V to ~4.8V. Note 3: The specified limits represent the “worst case" value for the parameter. Since these “worst case” values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Note 4: Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3-78

Vee = —4.2V to —4.8V unless otherwise specified, Voc = Voca = GND, To = 0°C to +85°C a Symbol [Parameter [Min [Typ | Max | Units’ | Conditions im Input HIGH Current CPp, Dn 240 MS, MR, CP 450 pA Vin = Vin (Max) CDp. SDp 530 tee Power SupplyGurent [-149 | -106 | -74_ | ma inputs Open Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = —4.2V to —4.8V, Voc = Voca = GND {max | Toggle Frequency a ee ee ‘ety | Propagation Delay 0.75 240 | 0.75 248 | 0.70 230 | os | teHL CP to Output Figures 1 and 3 tpy _ | Propagation Delay tere | cP, to Output 0.70 220 | 070 200 | 070 2.20 tPLH Propagation Delay = tor | Con $Dq to Output 070 190 | 070 1.70 | 0.70 1.80 Pp, GPg = L PH 0.70 210] 070 200 | 070 220 CPy, CPg = H PHL Figures tPLH Propagation Delay = tand4 ee | Ms. MR to Output 1.10 270 | 1.10 260 | 110 270 Pp, CPo = L tPLH 105 2.95 CP, CPo = H tru | Transition Time ; tan | 20% to 80%, 80% 10 20% 045 1.80 | 0.45 1.90 Figures 1,3 and 4 ts Setup Time ; Dn 0.90 0.70 0.90 Figure & CDn, SDp (Release Time) | 1.50 1.30 1.50 MS, MR (Release Time) | 2.50 2.30 2.50 Figure 4 ty__| Hold Time Dn [oso | oso | oo ns | Figures tow) | Pulse Width HIGH CP,, CP¢, CDp, Figures 3 and 4 SD, MR, MS 3-79

a S| Cerpak AC Electrical Characteristics vec = —4.2v to —4.8V, Voc = Voca = GND S Syme | ranma rc cs ex i ti co ° tmax | Toggle Frequency [a0 | aso | 50 ite | Figures 2 ana s teHL ¢ to Output Figures 1 and 3 ten _ | Propagation Delay tore | CPx to Output 0.70 200 | 0.70 1.80 | 070 2.00 tpLy _ | Propagation Delay m1 CP. CPe = L tH 0.70 190] 070 1.80 | 070 200 CPp, CPo = H tPHL Figures teLy | Propagation Delay 1 ao | 110 250 CP, Co =L tand4 teu, _| MS, MR to Output 1410-240 | 1. im CP PLH 105 285 | 1.05 275 | 105 285 CP, CPo = H {PHL trun | Transition Time 1 4 tre | 20% to 80%. 80% to 20% | 045 200 | 046 1.60 | 045 1.70 Figures 1, 3 and ts Setup Time j Dn 0.80 0.60 0.80 Figure 5 CDn, SDp (Release Time) | 1.40 1.20 1.40 MS, MR (Release Time) 2.40 2.20 2.40 Figure 4 ty___| Hola Time Dn [oso [oso foro | ns Figures tow(H) | Pulse Width HIGH OPp, CP, CDp, Figure 3 and 4 SDp, MR, MS 3-80

FIGURE 5. Data Setup and Hold Time ty ia the minimum time betore the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input.