F100130

F100130 NSC | Alldatasheet

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o s National i? Semiconductor Triple D Latch General Description The F100130 contains three D-type latches with true and (or both) are HIGH, a latch stores the last valid data present complement outputs and with Common Enable (Ec), Master__on its Dp, input before E, or Ec goes HIGH. Set (MS) and Master Reset (MR) inputs. Each latch has its Both Master Reset (MR) and Master Set (MS) inputs over- own Enable (E,), Direct Set (SD,) and Direct Clear (CDp) ride the Enable inputs. The individual CD, and SD, also inputs. The Q output follows its Data (D) input when both En —_gverride the Enable inputs. All inputs have 50 kO. pull-down and Ec are LOW (transparent mode). When either E, orEc resistors, Ordering Code: see sections Logic Symbo!t vlels CDo-CDz2 Individual Direct Clear Inputs SDp-SD2 Individual Direct Set Inputs FoF Ezy Os Dz Ey-E, Individual Enable Inputs (Active LOW) Eo Common Enable Input (Active LOW) baad Do-Do Data Inputs cor MR Master Reset Input Ca Ms Master Set Input SDo Qo-Qz Data Outputs 801 -O2 Complementary Data Outputs SD2 MR MS Qo Q; a2 TL/F/9052-3 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak

7 Dy SD, MR Veg Eg MS

CD) 24 sD. &42 23}-co, - 24 23 22 21 20 19 d-43 22--é, sie 18 $0 as 21-0, COy—72 17 Cg as 20F-s0, S02 “13 165 Ey Yoo 6 19}-wR Cop —14 sd a) Veca47 18 Vee Bas of ied aa whe, 0.46 ; 13 a 9 16eus 8 9 10 11 12 Ato 15FSDp QQ VeocVeca Qs 4 it t4Fcdy TLIF/9852-2 Dg-4i2 13 Ey TUF /@852—1 3-70

r=] i BI Logic Diagram 3 SDo Dp E Dp SD; Dy & CD; SD. D2 E,Ec Cz U || [oO |] ie [J E 8p co wpt Lt Por Ty | un —S a | Q Ge a a Q, & Turrees2-5 Truth Tables (ach Latch) Latch Operation Asynchronous Operation L L L L L L x x x H L H H L L L L H x x x L H L x H x L L Latched* x x x H H U x x H L L Latched* “Retains data presented before E positive transition H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care U = Undetined 3-71

i=] oO S| Absolute Maximum Ratings Ss Above which the useful life may be impaired. (Note 1) If Military/Aerospace specified devices are required, Case Temperature under Bias (Tc) OC to +85°C please contact the National Semiconductor Sales Vee Pin Potential to Ground Pin -7.0V to +0.5V once! Distributors for availability and specifications. Input Voltage (DC) Veg to +0.5V torage Temperature ~ 650 to + 150°C Output Current (DC Output HIGH) 50 mA Maximum Junction Temperature (Tj) +150°C Operating Range (Note 2) -5.7Vto —4.2V Vee = —4.5V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) symbol | Parameter | min | tye | max | unite | Conditions (Note 4) Vou Oupunichvorage | —r025 | 955 | —e80 | ay | Vin =Vinawan) | Loading wit Vou Output LOW Voltage | —1810 | -1705 | —1620 | HL ein) : You | Oupurnistvotage [ross [TT ay | Yin= Viniany ] Loading with Vorc | Outputtowvortage | | | 1610 | or Ni en) a Via Input HIGH Voltage _ Guaranteed HIGH Signal 880 mV | tor All Inputs Viv Input LOW Voltage 4810 1475 mV Guaranteed LOW Signal for All Inputs in InputLoweurrent | oso [| Twa | Vv = Vici Vee = —4.2V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) symbol [Parameter | min | typ | Max | Unite | Conditions (Note 4) Vou OutputHIGH Voltage | -1020 | | -e70 | iy Vin = Vin (Max) | Loading with Vou OuiputLow voltage | -se10 | | -1605_ | or Va. ome) S00 to ~20V Vouc OutputHiGHVoltage | -1090 | || ny Vin = Vin min) | Loading with Voc | OutpurLowvotage | [| — 1595 | Or Vit (Man S00 to = 20V Vie Input HIGH Voltage 870 mv Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage “4475 mv Guaranteed LOW Signal for All nputs. in Inputrow Curent | oso [| Twa | Viv = Yn in Vee = —4.8V, Voo = Voca = GND, To = 0°C to +85°C (Note 3) symbol | Parameter | min | typ | Max [Unite | Conditions (Note 4) Vox Output HIGH Voltage | -1095 | | -880 | iy Vin = Vin (Max) | Loading with Vou OuiputLow voltage | -1ea0 | | -1620 | ori cy S00 to =2.0V Vouc Output HIGH Voltage | -1045 | || my Viy= Vain) ] Loading wth Vous | OutputLowvvotage | [|| 1610 | ort (a a Vie Input HIGH Voltage _ Guaranteed HIGH Signal 880 mv for All Inputs Vit Input LOW Voltage Guaranteed LOW Signal mv for All Inputs In InputLow Curent | oso [| Tek | Vi = Vin in Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Parametric valves specified at ~4.2V to ~ 48V. Note 3: The specified limits represent the “worst case” value for the parameter. Since these “worst case" values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Note 4: Conditions for testing shown in the tables are chosen to guarantee operation under “worst case" conditions. 372

Vee = —4.2V to —4.8V unless otherwise specified, Vcc = Voca = GND, To = 0°C to +85°C gs symbol_| Parameter | win | Typ | Max__| Unts | Conditions NH Input HIGH Current Da 350 CDp, SDp 530 pA Vin = Vin (Max) En 240 Ec, MR, MS 450 Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = —4.2V to —4.8V, Voc = Voca = GND ton Cuba (raneparnt Mo [oso a0 | oso 170 | oso 190 | me | tpHL Output (Transparent Mode) Figures 1 and 2 teLH Propagation Delay trHL Ec to Output 0.75 2.00 0.75 2.10 ns tPLH Propagation Delay 5 tPLH Propagation Delay troy Transition Time ts Setup Time Do-Dz 0.90 0.70 0.90 CDp, SDp (Release Time) | 1.20 4.10 1.40 Figures 3 and 4 MR, MS (Release Time) 1.90 1.90 2.00 tow(L) Pulse Width LOW tow Pulse Figure 2 En Ec ou tow(H) Pulse Width HIGH J CDp, SD, MR, MS Figure 3 3-73