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Gain at 3500MHz 34.5dB typical in High Gain Mode 28.5dB typical in Low Gain Mode 1.35dB NF at 3500MHz +23dBm OIP3 at 3500MHz OP1dB at 3500MHz +15dBm in High Gain Mode +14dBm in Low Gain Mode 50Ω single-ended input / output amplifier impedances IDD = 130mA Independent Standby Mode for power savings Supply voltage: +3.15V to +3.45V 5 5 mm, 32-LGA package -40°C to +105°C exposed pad operating temperature range Block Diagram SW1_CTRL ATT1_CTRL STBY1 STBY2 SW2_CTRL ATT2_CTRL RX2_OUT VDD VDD SW1_IN SW2_IN RX1_OUT VDD VDD SW1_OUTSW2_OUT
Figure 1. Pin Assignments for 5 5 0.8 mm 32-LGA – Top View
Table 1. Pin Descriptions resistor is connected between this input and GND.
3 SW1_CTRL
6 SW2_CTRL
resistor connects between this input and GND. 10 RX2_OUT RF output path 2 matched to 50Ω. Use external DC block as close to the pin as possible. 18 SW2_IN RF2 switch input matched to 50Ω. Use external DC block as close to the pin as possible. 23 SW1_IN RF1 switch input matched to 50Ω. Use external DC block as close to the pin as possible. 31 RX1_OUT RF output path 1 matched to 50Ω. Use external DC block as close to the pin as possible. required to achieve the noted RF performance.
for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings [a] TEPAD = Temperature of the exposed paddle. maximum recommended input junction temperature is exceeded.
Table 3. Recommended Operating Conditions maximum junction temperature of 125°C. levels beyond what is specified in this table. Figure 2. Typical TX Input Power and Reduced Exposed Pad Temperature Profile[c] [c] Profile represents estimates to maintain maximum junction temperature ≤ 125°C using IDT specific evaluation board and test environment.
Table 4. Electrical Characteristics: General STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
© 2019 Integrated Device Technology, Inc. 10 December 9, 2019 Parameter Symbol Condition Minimum Typical Maximum Units Power ON from Standby Mode [b] SWON_STANDBY To Rx Mode from Standby Mode 50% STBY to RF output settled within ±0.1dB of final value 1 µs Power OFF to Standby Mode [b] SWOFF_STANDBY To Standby Mode from Rx Mode 50% STBY to gain below -25dB from max gain 1 µs [a] Items in the Minimum/Maximum columns in bold italics are guaranteed by test. Items in the Minimum/Maximum columns NOT in bold italics are guaranteed by design characterization. [b] fRF = 3500MHz. Assumes the control signal is clean and no external RC circuitry is required on the pin. Adding RC circuitry incre ases switching time.
Table 5. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance [a] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with an RL > 22dB. [b] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
Table 6. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance guaranteed by design characterization. [b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
Table 7. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance guaranteed by design characterization. [b] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with a RL > 22dB. [c] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
Table 8. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance guaranteed by design characterization. [b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
Table 9. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance guaranteed by design characterization. [b] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with a RL > 22dB. [c] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
Table 10. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance guaranteed by design characterization. [b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
Table 11. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance guaranteed by design characterization. [b] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with a RL > 22dB. [c] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
Table 12. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance guaranteed by design characterization. [b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
Table 13. Thermal Characteristics
Table 14. Gain Step Truth Table Table 15. Standby and RF Switch Truth Table In TX Mode, the amplifiers are OFF, but the bias will remain ON for fast turn-on recovery time.
Figure 29. Electrical Schematic
Table 16. Bill of Material (BOM)
and 3 of header J1 for CH1_VDD, and wiring to Pin 1 and 3 of header J8 for CH2_VDD, as displayed in Figure 30. Figure 30. Connections of Evaluation Board CH1_VDD of header J1 or CH2_VDD of header J8. Apply a logic LOW signal to STBY1 by making a connection between pin 1 and pin 2 of J5.
Apply a logic LOW signal to STBY2 by making a connection between pin 7 and pin 8 of J5. also Error! Reference source not found.). In contrast, if J4 is open or logic LOW the minimum attenuation is obtained for channel 1. To get 6dB gain attenuation for channel 2, make a connection of SMA Connector J6, marked as “CH2_att_ctr” in Figure 30, to logic HIGH. In contrast, if J6 is open or logic LOW the minimum attenuation is obtained for channel 2. source not found.). In contrast, if pin 4 of J5 is open or logic LOW the result is to switch channel 1 into RX throw. is open or logic LOW the result is to switch channel 2 into RX throw. Standby (STBY) Pin and in Switch Control Pin. The standby and switch control logic are displayed in the following figure. Figure 31. Standby and Switch Control Logics then enable the power supply.
© 2019 Integrated Device Technology, Inc. 30 December 9, 2019
Application Information
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at 0V (±0.3V) while the supply voltage ramps up or while it returns to zero. Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to control pins 1, 2, 3, 6, 7, and 8 displayed in Figure 32. Figure 32. Control Pin Interface Schematic
© 2019 Integrated Device Technology, Inc. 31 December 9, 2019 Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package inf ormation is the most current data available. www.idt.com/document/psc/leg32-package-outline-50-x-50-mm-body-08-mm-thick-05mm-pitch-lga
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F0453BLEGK 5.0 5.0 0.8 mm 32-LGA MSL3 Tray -40° to +105°C F0453BLEGK8 5.0 5.0 0.8 mm 32-LGA MSL3 Reel -40° to +105°C F0453BEVBK Evaluation Board Marking Diagram IDTF04 53BLEGK #YYWW$ LOT Lines 1 and 2 indicate the part number Line 3 indicates the following: “#” denotes stepping “YY” is the last two digits of the year; “WW” is the work week number when the part was assembled. “$” denotes the mark code.
© 2019 Integrated Device Technology, Inc. 32 December 9, 2019
Revision History
Revision Date Description of Change December 9, 2019 Updated to reflect 3.3GHz specifications. August 29, 2019 Updated to reflect 4GHz specifications Completed other minor improvements March 20, 2019 Initial release.
© 2019 Integrated Device Technology, Inc. 33 December 9, 2019 Corporate Headquarters
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