F0448_V01 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 43
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 Recommended Operating Conditions
- 2.5 Thermal Characteristics
- 4.1 Serial Control – DSA1
- 7.1 Evaluation Board Schematic
- 7.4 Evaluation Board Operation
- 8.1 Power Supplies
- 8.2 RSET and RDSET
- 8.3 Control Pin Interface
Features
■ RF Frequency Range: 3.3GHz to 4.2GHz ■ Dual Channel RF amp and DSAs for Diversity / MIMO Receivers ■ < 2dB overshoot between DSA transitions ■ 13dB typical maximum gain at 3.6GHz ■ DSA0: Single 6dB coarse step ■ DSA1: 23dB total gain range in 1dB steps ■ DSA2: 18dB gain range in 6dB steps ■ +37dBm OIP3 at 3.6GHz ■ 6dB Noise figure at 3.6GHz ■ +5V Supply voltage ■ ICC = 220mA ■ Independent standby: 7mA standby current ■ SPI interface for DSA1 ■ 1-bit control for DSA0 ■ 2-bit control for DSA2 ■ 50Ω input and output impedance ■ Internally matched ■ Temperature range: -40°C to +105°C ■ 6 × 6 × 0.75 mm, 36-QFN package
Applications
■ Multi-mode, Multi-carrier Receivers ■ PHS/PAS Base Stations ■ Distributed Antenna Systems ■ Digital Radio DATA CLK CSb RFIN_A RFIN_B RFOUT_A RFOUT_B DSA0A DSA2A F0448 STBY RF AMP A Gl itch - Free TM Gl itch - Free TM Zero - Distortion TM Zero - Distortion TM VCTRL0 DSA1A 6dB 23dB 18dB VCTRL1 VCTRL2 RF AMP B 6dB 23dB 18dB DSA0B DSA2BDSA1B Decode Logic / Bias
1.1 Pin Assignments
Figure 2. Pin Assignments – Top View
1.2 Pin Descriptions
1 RFIN_A Input RF port for channel A which is internally matched to 50Ω. Must use external DC block. 17, 29, 30, 31 GND Internally grounded. This pin must be grounded with a via as close to the pin as possible.
X0008129 Rev.1.4 Feb 17, 2021 Page 7 Number Name Description 3 VCTRL0_A 1-bit DSA0 6dB attenuator control for channel A. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated. 4 DATA Data input: 3.3V or 1.8V CMOS compatible. 5 CLK Clock input: 3.3V or 1.8V CMOS compatible. 6, 21, 23, 25 VCC Power Supply. Use bypass capacitors as close to pin as possible. 7 VCTRL0_B 1-bit DSA0 6dB attenuator control for channel B. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated. 9 RFIN_B Input RF port for channel B that is internally matched to 50Ω. Must use external DC block. 10, 18, 20, 26, 28, 36 NC No internal connection. These pins can be left unconnected or be connected to ground (recommended). Use a via as close to the pin as possible if grounded. 11 CSb_B Chip Select bar input for channel B: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in.
12 STBY_B Standby pin for channel B (LOW/Open = device power ON, HIGH = device power OFF with SPI
still powered ON). An internal pull-down resistor of 57kΩ connects between this pin and GND. 13 VCTRL1_B Bit 0 for DSA2 channel B attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated. 14 VCTRL2_B Bit 1 for DSA2 channel B attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated. 19 RFOUT_B Output RF port for channel B. Use external DC block as close to the pin as possible. 22 RDSET Connect external resistor to GND to optimize amplifier bias. Used with pin 24. 24 RSET Connect external resistor to GND to optimize amplifier bias. Used with pin 22. 27 RFOUT_A Output RF port for channel A. Use external DC block as close to the pin as possible. 32 VCTRL2_A Bit 1 for DSA2 channel A attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated. 33 VCTRL1_A Bit 0 for DSA2 channel A attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated.
34 STBY_A Standby pin for channel A (LOW/Open = device power ON, HIGH = device power OFF with SPI
still powered ON). An internal pull-down resistor of 57kΩ connects between this pin and GND. 35 CSb_A Chip Select bar input for channel A: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in. — EPAD Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance.
2.1 Absolute Maximum Ratings
permanent damage to the device. Functional operation of the F0448 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 1. Absolute Maximum Ratings
- Exposure to these maximum RF levels can result in significant VCC current draw due to overdriving the amplifier stage.
2.2 Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Table 3. Electrical Characteristics (3.4GHz to 3.8GHz)
X0008129 Rev.1.4 Feb 17, 2021 Page 10 Parameter Symbol Condition Min. Typ. Max. Unit DSA0 Phase Settling Time tDSA0_1_PH 50% CTRL to within 1 degree of final value, 0dB state to 6dB state 24 35 ns tDSA0_2_PH 50% CTRL to within 1 degree of final value, 6dB state to 0dB state 18 35 DSA2 Phase Settling Time tDSA2_1_PH 50% CTRL to within 1 degree of final value, 0dB state to 18dB state 16 35 ns tDSA0_1_PH 50% CTRL to within 1 degree of final value, 18dB state to 0dB state 15 35 Stability K factor KFACT Over entire temperature range 1.4 unit Serial Clock Speed SPICLK 10 MHz CSb_A, CSb_B to first serial clock rising edge t LS SPI 3 wire bus. 50% of CSb falling edge to 50% of CLK rising edge. 10 ns Serial Data Hold Time tH SPI 3 wire bus. 50% of CLK rising edge to 50% of Data falling edge. 10 ns Final serial clock rising edge to CSb tLC SPI 3 wire bus. 50% of CLK rising edge to 50% of CSb rising edge. 10 ns RF Input Return Loss RLIN 15 dB RF Output Return Loss RLOUT 20 dB Gain GMAX 12 13 13.5 dB GMIN Maximum attenuation -38.1 -32 -26.4 GTEMP Variation over temperature ±0.15 GVAR Variation over frequency [3] ±0.2 DSA1 Step Error DNLDSA1 0.16 dB DSA2 Step Error DNLDSA2 0.32 dB Relative Phase DSA0 ΦPH_DSA0 6.6 deg Phase Deviation DSA1 ΦPH_DSA1 Between adjacent states 3 deg
X0008129 Rev.1.4 Feb 17, 2021 Page 11 Parameter Symbol Condition Min. Typ. Max. Unit Relative Phase DSA2 ΦPH_ DSA2 Any State 6.6 deg Noise Figure NF 5.9 dB NFHOT TEPAD = +105°C 6.6 NF22 DSA1 22dB attenuation 27.7 Output Third Order Intercept Point OIP31 1MHz tone separation 34 37 dBm OIP32 1MHz tone separation POUT = -10dBm/tone 33 35 OIP36dB 1MHz tone separation DSA0 full attenuation 37 OIP33 1MHz tone separation Worst case over temp range 33 36 OIP318dB POUT = -18dBm/tone 1MHz tone separation DSA2 full 18dB attenuation Input 1dB Compression [4] IP1dB Full attenuation 24 dBm Output 1dB Compression OP1dB 18 dBm Reverse Isolation REVISO 19 22 dB Channel Isolation [5] CHISO 35 39 dB Over voltage and temperature 39 1. Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are not shown in bold italics are guaranteed by design characterization. 2. During standby mode, SPI is to be left ON and previous state is maintained when device is powered up. 3. Including frequency and ripple variations valid within each individual 3GPP band. 4. Input 1dB compression point is a linearity figure of merit. For maximum RF input power, see Absolute Maximum Ratings . 5. Signal applied to RFIN_A (RFIN_B), measure desired signal at RFOUT_A (RFOUT_B) and compare to signal level at RFOUT_B (RFOUT_A). Maximum gain setting.
2.4 Electrical Characteristics – For Wideband Performance
embedded, unless otherwise stated. For BOM details of this specific band, see Table 12. Table 4. Electrical Characteristics (3.3GHz to 4.2GHz)
- Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
- During standby mode, SPI is to be left ON and previous state is maintained when device is powered up.
- Including frequency and ripple variations valid within each individual 3GPP band.
- Input 1dB compression point is a linearity figure of merit. For maximum RF input power, see Absolute Maximum Ratings .
- Signal applied to RFIN_A (RFIN_B), measure desired signal at RFOUT_A (RFOUT_B) and compare to signal level at
RFOUT_B (RFOUT_A). Maximum gain setting.
2.5 Thermal Characteristics
Table 5. Package Thermal Characteristics Junction to Case Thermal Resistance.
X0008129 Rev.1.4 Feb 17, 2021 Page 14 3. Typical Performance Graphs Unless otherwise noted, for the typical performance graphs on the following pages, the following conditions apply: ■ Vcc = 5.0V ■ ZL = ZS = 50Ω Single ended ■ fRF = 3.6GHz ■ TEPAD = +25°C ■ Gain setting = Maximum gain ■ STBY = LOW ■ POUT = 0dBm/tone ■ 1MHz Tone Spacing ■ ATTN setting = 0dB (Maximum gain; DSA0 = DSA1 = DSA2 = 0dB) ■ All temperatures are referenced to the exposed paddle ■ Evaluation Kit traces and connector losses are de-embedded
Figure 67. NF vs. Frequency as a Function of Temperature three-wire serial control line. You choose which channel is programmed by using either or both CSb lines.
4.1 Serial Control – DSA1
The serial interface uses an 8-bit word with only 5 bits used. The serial word is shifted in LSB (D0) first. Figure 68. Serial Register Data Flow Diagram (LSB Clock in First) When the device is first powered up, DSA1 will default to the Maximum Attenuation setting as shown.
Figure 69. DSA1 Default Condition Table 6. DSA1 Attenuation Word Truth Table (LSB = First In)
Figure 70. Serial Timing Diagram Table 7. SPI Timing Diagram Values for Figure 70 [b] Once all desired DATA is clocked in, tLC represents the time a CSb high needs to occur before any subsequent CLK signals.
- Parallel Control Mode – DSA0, DSA2, STBY
Externally set the parallel control pins either logic LOW or HIGH. Table 8. DSA0 Truth Table Table 9. DSA2 Truth Table Table 10. STANDBY Truth Table
7.1 Evaluation Board Schematic
Figure 74 is the evaluation board schematic. Figure 74. Evaluation Board Schematic
Table 11. Bill of Materials (3.4GHz to 3.8GHz)
1 Printed Circuit Board F0440 EVKIT REV 01 Renesas
Table 12. Bill of Materials – For Wideband Performance (3.3GHz to 4.2GHz)
7.4 Evaluation Board Operation
is applied via the SMA connector, J1, show in Figure 75 and Figure 76. Figure 75. Power Supply Connections – Top View Figure 76. Power Supply Connections – Bottom View Figure 77. Two Ground Jumper Connections
Figure 78. Two Standby Pin Connections ■ Make no connections on J4. ■ Apply a logic LOW signal to STBY (pin 2 of J4 or the middle pin). ■ Make a connection between pin 1 (GND) and pin 2 (STBY, the middle pin) of J4. ■ Apply a logic HIGH signal to the STBY (pin 2 of J4 or the middle pin). ■ Make a connection between pin 3 (VCC) and pin 2 (STBY, the middle pin) of J4. ■ Make no connections on J11. ■ Apply a logic LOW signal to STBY (pin 2 of J11 or the middle pin). ■ Make a connection between pin 1 (GND) and pin 2 (STBY, the middle pin) of J11. ■ Apply a logic HIGH signal to the STBY (pin 2 of J11 or the middle pin). ■ Make a connection between pin 3 (VCC) and pin 2 (STBY, the middle pin) of J11.
Both channels have a digital controlled attenuator, DSA1_A and DSA1_B, which share the serial control word. Figure 79. Two Jumpers for Serial Programming Connections Table 13. J13 Header Pins
1 GND 2 GND
3 DATA 4 GND
5 CLK 6 GND
7 CSb_A 8 GND
9 CSb_B 10 GND
11 VCTRL0_A 12 GND
13 VCTRL0_B 14 GND
15 VCTRL1_A 16 GND
17 VCTRL1_B 18 GND
19 VCTRL2_A 20 GND
21 VCTRL2_B 22 GND
attenuator achieved using headers J12 and J15. The latch signal must be applied to CSb_A (pin 7 of J13). Table 14 lists the operation for the connections on these headers. Figure 54 shows the J12 and J15 headers.
The F0448 is optimized for use in high-performance RF applications from 3.3GHz to 4.2GHz.
8.1 Power Supplies
while the supply voltage ramps or while it returns to zero.
8.2 RSET and RDSET
The F0448 is optimized for gain and intermodulation products by adjusting the bias resistors RSET and RDSET. For the optimized setting, RSET (R26) and RDSET (R25) are 4.42kΩ.
8.3 Control Pin Interface
match the EVKit BOM for the case of poor control signal integrity. Figure 82. Control Pin Interface
X0008129 Rev.1.4 Feb 17, 2021 Page 40 9. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 10. Marking Diagram IDTF0448 NBGK ZW1707L Q86A034MY ■ Line 1 and 2 are the part number. ■ Line 3 “ZW” is for die version. ■ Line 3 “yyww = 1707 has two digits for the year and week that the part was assembled. ■ Line 3 “L” denotes Assembly Site. ■ Line 4 “Q86A034MY” is the Assembly Lot number. 11. Ordering Information Orderable Part Number Package Description MSL Rating Carrier Type Temperature F0448NBGK 6 × 6 × 0.75 mm, 36-QFN 1 Tray -40°C to +105°C F0448NBGK8 6 × 6 × 0.75 mm, 36-QFN 1 Tape and Reel -40°C to +105°C F0448EVB Evaluation Board F0448EVS Evaluation Solution
X0008129 Rev.1.4 Feb 17, 2021 Page 41 12. Revision History Revision Date Description
1.4 Feb 17, 2021 Updated spec table, plots, and BOM for wideband frequency tune
Added Plots and a BOM for wide band operation of the device from 3.3GHz to 4.2GHz. The Operating Range has also been appropriately adjusted. Updated the document to the latest template
1.3 Oct 24, 2018 Removed “or pin open” from Pin Descriptions
Removed “or open” from Table 8 and Table 9 Updated Figure 79
1.2 Oct 18, 2018 Updated various logic levels
Update Typical Performance Characteristics Completed other minor improvements
1.1 Aug 29, 2018 Added θJA and θJC-BOT values to Table 5
1.0 Aug 8, 2018 Initial release.
(PCB Top View, NSMD Design) 0.35 Seating Plane 6.00 ±0.15 6.00 ±0.15 Pin 1 ID TOP VIEWBOTTOM VIEW (0.40) 0.25 0.55 4.10 ±0.10 4.10 ±0.10 0.50 SIDE VIEW0.08C RECOMMENDED LAND PATTERN 0.75 ±0.05 C(0.20)0.05 Max 4.10 6.304.90 6.30 4.100.35 Package Outline0.250.50 © Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit www.renesas.com /contact-us/ . Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers who are designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only to develop an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third-party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising from your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Disclaimer Rev.1.01) © 2025 Renesas Electronics Corporation. All rights reserved.