DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 29
Technical content
Features
Dual Path RF amp and DSAs for Diversity / MIMO Receivers RF: 400MHz to 2700MHz < 2dB overshoot between DSA transitions 11.6dB typical max gain at 900MHz DSA0 is a single 6dB coarse step DSA1 has 23dB total gain range in 1dB steps DSA2 has 18dB gain range in 6dB steps +41dBm OIP3 at 2000MHz 4.7dB Noise Figure at 900MHz +5V Supply Voltage ICC = 245mA Independent standby: 7mA standby current SPI interface for DSA1 1-bit control for DSA0 2-bit control for DSA2 50Ω input and output impedance Broadband, Internally Matched 6 x 6 mm, 36-TQFN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 6 x 6 mm 36-TQFN Package – Top View
Table 2. Pin Descriptions 1 RFin_A RF Path A input internally matched to 50Ω. Must use external DC block.
3 VCTRL0_A 1bit DSA0 6dB attenuator control for path A
4 SPI Data[a] Data input: 3.3V or 1.8V CMOS compatible. 5 SPI Clk[a] Clock input: 3.3V or 1.8V CMOS compatible. 6, 21, 23, 25 VCC +5V Power Supply. Use bypass capacitors as close to pin as possible.
7 VCTRL0_B 1bit DSA0 6dB attenuator control for path B
9 RFin_B RF Path B input internally matched to 50Ω. Must use external DC block. 11 SPI CSb_B[a] Chip Select bar input path B: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data. down resistor connects between input and GND. 13 VCTRL1_B See separate attenuation logic table for Path B DSA2. 14 VCTRL2_B See separate attenuation logic table for Path B DSA2. 19 RFout_B RF output Path B. Use external DC block as close to the pin as possible. 22 RDset Connect external resistor to GND to optimize amplifier bias. Used with pin 24. 24 Rset Connect external resistor to GND to optimize amplifier bias. Used with pin 22. 27 RFout_A RF output Path A. Use external DC block as close to the pin as possible. 32 VCTRL2_A See separate attenuation logic table for Path A DSA2. 33 VCTRL1_A See separate attenuation logic table for Path A DSA2. down resistor connects between input and GND. 35 SPI CSb_A[a] Chip Select bar input path A: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data. vias are also required to achieve the noted RF performance. a. See Serial Control Mode section for description.
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Table 3. Absolute Maximum Ratings overdriving the amplifier stages. Table 4. Recommended Operating Conditions
© 2021 Renesas Electronics Corporation 5 November 4, 2021
Electrical Characteristics
Table 5. Electrical Characteristics noted, Max gain setting, output power = 0dBm, ZRFI = ZRFO = 50Ω, unless otherwise noted.
a. Items in min/max columns in bold italics are confirmed by Test. b. Items in min/max columns that are not bold/italics are confirmed by Design Characterization. c. During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up. d. Time for the gain to settle within ±0.1dB and relative to SPI command latch. Table 6. Electrical Characteristics – 450MHz Performance de-embedded, unless otherwise noted.
a. Items in min/max columns in bold italics are confirmed by Test. b. Items in min/max columns that are not bold/italics are confirmed by Design Characterization. c. Including frequency and ripple variations valid within each individual 3GPP band. d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power. Table 7. Electrical Characteristics – Lowband Performance de-embedded, unless otherwise noted.
© 2021 Renesas Electronics Corporation 8 November 4, 2021 Parameter Symbol Condition Minimum Typical Maximum Units DSA2 Step Error GDSA2SE_LB Between adjacent states ± 0.03 dB Relative Phase DSA0 GPH_DSA0_LB 0.7 Deg Phase Deviation DSA1 GPH_DSA1_LB Between adjacent states 0.26 Deg Relative Phase DSA2 GPH_ DSA2_LB Between any two states 2.5 Deg Noise Figure NFLB 4.7 dB NFLB_HOT Tcase = +105°C 5.4 NFLB_RG DSA1 22dB attenuation 27 Output Third Order Intercept Point OIP3_LB-1 1MHz tone separation 38.5 40 dBm OIP3_LB-2 1MHz tone separation Pout = -10dBm/tone 39 OIP3_LB-6dB 1MHz tone separation DSA0 full attenuation 40 OIP3_LB-3 1MHz tone separation Worst case over temp range 38 39 OIP3_LB_18dB Pout = -18dBm / tone 1MHz tone separation DSA2 full 18dB attenuation Input 1dB Compression d IP1dB_LB Full attenuation 27 dBm Output 1dB Compression OP1dB_LB 18.4 20.2 dBm Output 1dB Compression Degradation OP1_DEG_LB OP1dB_DEGLB= OP1dBLB (DSA2 =0dB atten) - ATTNLB_DSA2_MAX - OP1dBLB (DSA2=max atten) 0.05 0.5 dB Output 0.2dB Compression OP0.2dB_LB 18.7 dBm Output Saturated Power PSAT_LB 3 dB compression 20.9 dBm Reverse Isolation REVISO_LB 20 20.5 dB Path Isolation PATHISO_LB RFOUT_B vs. RFOUT_A w/ signal applied to RFIN_A 43 45 dB Same gain settings over PVT 45 a. Items in min/max columns in bold italics are confirmed by Test. b. Items in min/max columns that are not bold/italics are confirmed by Design Characterization. c. Including frequency and ripple variations valid within each individual 3GPP band. d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power.
Table 8. Electrical Characteristics – Midband Performance de-embedded, unless otherwise noted.
1 MHz tone separation
a. Items in min/max columns in bold italics are confirmed by Test. b. Items in min/max columns that are not bold/italics are confirmed by Design Characterization. c. Including frequency and ripple variations valid within each individual 3GPP band. d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power. Table 9. Electrical Characteristics – Highband Performance de-embedded, unless otherwise noted.
a. Items in min/max columns in bold italics are confirmed by Test. b. Items in min/max columns that are not bold/italics are confirmed by Design Characterization. c. Including frequency and ripple variations valid within each individual 3GPP band. d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power. Table 10. Package Thermal Characteristics
Figure 47. Serial Register Timing Diagram (LSB-FIRST) Table 13. DSA1 Serial Mode Default Condition When the device is first powered up, DS1 will default to the Maximum Attenuation setting as shown. is recommended that CSb be pulled high (>VIH) when the device is not being programmed.
Table 14. DSA1 Attenuation Word Truth Table (LSB = first in) Table 15. DSA0 Attenuator Truth Table Table 16. DSA2 Truth Table Table 17. Standby Truth Table
Figure 48. Top View
Figure 49. Schematic
Table 18. Bill of Material (BOM) Part Reference QTY Description Mfr. Part # Mfr.
1 Printed Circuit Board F0440 EVKIT REV 01 IDT
1 PCB Schematic (Rev 01) IDT
F0440 has been optimized for use in high performance RF applications from 400MHz to 2700MHz. minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. while the supply voltage ramps or while it returns to zero. Jumpers J6 and J10 must be grounded (header in place) for optimum RF performance.
Figure 50. Control Pin Interface capacitor values do not necessarily match the EV kit BOM for the case of poor control signal integrity.
© 2021 Renesas Electronics Corporation 26 November 4, 2021 Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revision of this document.
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F0440NBGI 6 × 6 × 0.75 mm 36-TQFN 1 Tray -40° to +105°C F0440NBGI8 6 × 6 × 0.75 mm 36-TQFN 1 Tape and Reel -40° to +105°C F0440EVBI Evaluation Board - - - Marking Diagram IDTF0440 NBGI ZW1607L Q86A034MY Part Number ASM Test Step Lot Number Date Code (Week 7 of 2016) Assembler Code
Revision History
Revision Date Description of Change November 4, 2021 Updated Package Outline Drawings section and added POD links in the Ordering Information table. Added Low Band Plots; updated operating range down to 400MHz. August 13, 2020 Added Spec Table at 450MHz. May 13, 2020 Rebranded datasheet. July 27, 2016 First release (Rev O) of the F0440 datasheet.
© Renesas Electronics Corporation
© Renesas Electronics Corporation 01Apr 6, 2016 00Initial Release Package Revision HistoryRev No.Date CreatedDescriptionNov 8, 2021Update IDT format to Renesas format
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2020 Renesas Electronics Corporation. All rights reserved.