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Dual Path RF amp & DSAs for Diversity / MIMO Receivers RF: 450MHz to 2700MHz < 2dB overshoot between DSA transitions 11.6dB typical max gain @ 900MHz DSA0 is a single 6dB coarse step DSA1 has 23dB total gain range in 1dB steps DSA2 has 18dB gain range in 6dB steps +41dBm OIP3 @ 2000MHz 4.7dB Noise Figure @ 900MHz +5V Supply Voltage ICC = 245mA Independent standby: 7mA standby current SPI interface for DSA1 1-bit control for DSA0 2-bit control for DSA2 50 Ω input and output impedance Broadband, Internally Matched 6mm x 6mm, 36-pin TQFN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 6 x 6 mm 36-TQFN Package – Top View
Table 2. Pin Descriptions 1 RFin_A RF Path A input internally matched to 50 Ω. Must use external DC block.
3 VCTRL0_A 1bit DSA0 6dB attenuator control for path A
4 SPI Data[a] Data input: 3.3V or 1.8V CMOS compatible. 5 SPI Clk[a] Clock input: 3.3V or 1.8V CMOS compatible. 6, 21, 23, 25 VCC +5V Power Supply. Use bypass capacitors as close to pin as possible.
7 VCTRL0_B 1bit DSA0 6dB attenuator control for path B
9 RFin_B RF Path B input internally matched to 50 Ω. Must use external DC block. 11 SPI CSb_B[a] Chip Select bar input path B: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data. down resistor connects between input and GND. 13 VCTRL1_B See separate attenuation logic table for Path B DSA2. 14 VCTRL2_B See separate attenuation logic table for Path B DSA2. 19 RFout_B RF output Path B. Use external DC block as close to the pin as possible. 22 RDset Connect external resistor to GND to optimize amplifier bias. Used with pin 24. 24 Rset Connect external resistor to GND to optimize amplifier bias. Used with pin 22. 27 RFout_A RF output Path A. Use external DC block as close to the pin as possible. 32 VCTRL2_A See separate attenuation logic table for Path A DSA2. 33 VCTRL1_A See separate attenuation logic table for Path A DSA2. down resistor connects between input and GND. 35 SPI CSb_A[a] Chip Select bar input path A: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data. vias are also required to achieve the noted RF performance. a. See Serial Control Word section for description.
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Table 3. Absolute Maximum Ratings overdriving the amplifier stages. Table 4. Recommended Operating Conditions
© 2020 Renesas Electronics Corporation 5 August 13, 2020
Electrical Characteristics
Table 5. Electrical Characteristics noted, Max gain setting, output power = 0dBm, ZRFI = ZRFO = 50 Ω, unless otherwise noted.
© 2020 Renesas Electronics Corporation 6 August 13, 2020 Parameter Symbol Condition Minimum Typical Maximum Units Serial Clock Speed SPICLK 10 MHz CSb_A, CSb_B to first serial clock rising edge A SPI 3 wire Bus. 50% of CSb falling edge to 50% of CLK rising edge. 10 ns Serial Data Hold Time B SPI 3 wire Bus. 50% of CLK rising edge to 50% of Data falling edge. 10 ns Final serial clock rising edge to CSb C SPI 3 wire Bus. 50% of CLK rising edge to 50% of CSb rising edge. 10 ns DSA0 Phase Settling Time ATT0_PH_0to6 50% CTL to within 1 degree of final value, 0 dB state to 6 dB state 24 35 ns ATT0_PH_6to0 50% CTL to within 1 degree of final value, 6 dB state to 0 dB state 18 35 ns a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. c. During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up. d. Time for the gain to settle within ± 0.1 dB and relative to SPI command latch.
Table 6. Electrical Characteristics – 450MHz Performance are de-embedded, unless otherwise noted.
1 MHz tone separation
© 2020 Renesas Electronics Corporation 8 August 13, 2020 Parameter Symbol Condition Minimum Typical Maximum Units Reverse Isolation REVISO_450 21 dB Path Isolation PATHISO_450 RFOUT_B vs. RFOUT_A w/ signal applied to RFIN_A 39 dB Same gain settings over PVT 39 a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. c. Including frequency and ripple variations valid within each individual 3GPP band d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power
Table 7. Electrical Characteristics – Lowband Performance are de-embedded, unless otherwise noted.
© 2020 Renesas Electronics Corporation 10 August 13, 2020 Parameter Symbol Condition Minimum Typical Maximum Units Output 0.2dB Compression OP0.2dB_LB 18.7 dBm Output Saturated Power PSAT_LB 3 dB compression 20.9 dBm Reverse Isolation REVISO_LB 20 20.5 dB Path Isolation PATHISO_LB RFOUT_B vs. RFOUT_A w/ signal applied to RFIN_A 43 45 dB Same gain settings over PVT 45 a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. c. Including frequency and ripple variations valid within each individual 3GPP band d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power
Table 8. Electrical Characteristics – Midband Performance de-embedded, unless otherwise noted.
© 2020 Renesas Electronics Corporation 12 August 13, 2020 Parameter Symbol Condition Minimum Typical Maximum Units Output 0.2dB Compression OP0.2dB_MB 18.8 dBm Output Saturated Power PSAT_MB 3 dB compression 20.5 dBm Reverse Isolation REVISO_MB 20 20.5 dB Path Isolation PATHISO_MB RFOUT_B vs. RFOUT_A w/ signal applied to RFIN_A 44 45 dB Same gain settings over PVT 45 a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. c. Including frequency and ripple variations valid within each individual 3GPP band d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power
Table 9. Electrical Characteristics – Highband Performance de-embedded, unless otherwise noted.
a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Table 10. Package Thermal Characteristics Junction to Case Thermal Resistance.
Figure 41. Serial Register Timing Diagram (LSB-FIRST) Table 13. DSA1 Serial Mode Default Condition When the device is first powered up, DS1 will default to the Maximum Attenuation setting as shown. is recommended that CSb be pulled high (>VIH) when the device is not being programmed.
Table 14. DSA1 Attenuation Word Truth Table (LSB = first in) Table 15. DSA0 ATTENUATOR TRUTH TABLE Table 16. DSA2 TRUTH TABLE
Table 17. STANDBY TRUTH TABLE Figure 42. Top View
Figure 43. Schematic
Table 18. Bill of Material (BOM) Part Reference QTY DESCRIPTION Mfr. Part # Mfr.
1 Printed Circuit Board F0440 EVKIT REV 01 IDT
1 PCB Schematic (Rev 01) IDT
F0440 has been optimized for use in high performance RF applications from 450MHz to 2700MHz. minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. while the supply voltage ramps or while it returns to zero. Jumpers J6 and J10 must be grounded (header in place) for optimum RF performance.
Figure 44. Control Pin Interface and capacitor values do not necessarily match the EV kit BOM for the case of poor control signal integrity.
© 2020 Renesas Electronics Corporation 28 August 13, 2020 Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/us/en/document/psc/nbnbg36-package-outline-60-x-60-mm-body-epad-410-mm-sq-050-mm-pitch-qfn
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Temperature F0440NBGI 6 x 6 x 0.75 mm 36-TQFN 1 Tray -40° to +105°C F0440NBGI8 6 x 6 x 0.75 mm 36-TQFN 1 Tape and Reel -40° to +105°C F0440EVBI Evaluation Board Marking Diagram IDTF0440 NBGI ZW1607L Q86A034MY Part Number ASM Test Step Lot Number Date Code (Week 7 of 2016) Assembler Code
Revision History
Revision Date Description of Change August 13, 2020 Added Spec Table at 450MHz May 13, 2020 Rebranded datasheet. July 27, 2016 First release (Rev O) of the F0440 datasheet
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