EVM629AXF

EDGE629 SEMTECH | Alldatasheet

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Technical content

TEST AND MEASUREMENT PRODUCTS 1 www .semtech.com Edge629

1 GHz Timing Deskew and Quad

Applications

Revision 3 / August 1, 2005

• Fmax ≥ 1 GHz
• Independent Falling Edge Adjust
• Small Footprint (10 mm x 10 mm)
• Excellent Timing Accuracy
• Very Stable Timing Delays
• 5 ps Resolution
• ECL, CMOS Compatible Inputs
• Memory Test Equipment – Data Fanout – Channel Deskew
• Logic Testers – Per Pin Deskew
• Clock / Signal Fanout ∆T∆T– ∆T Coarse Fine OUT0 / OUT0* IN0 / IN0* IN / IN* Coarse Fine OUT1 / OUT1* IN1/ IN1* Coarse Fine OUT2 / OUT2* IN2 / IN2* Coarse Fine OUT3 / OUT3* IN3 / IN3* SEL / SEL* ∆T ∆T ∆T ∆T ∆T ∆T ∆T– ∆T– ∆T– The Edge629 is a monolithic timing delay and signal fanout solution manufactured in a high-performance bipolar pro- cess. In Automatic Test Equipment (ATE) applications, the Edge629 buffers, distributes, and aligns timing signals across multiple channels (typically found inside Memory Test Systems). It is also suitable for per pin deskew in Logic Testers. The Edge629 supports:
• Minimum pulse width = 330 ps with Falling Edge Adjust disabled, 500 ps with Falling Edge Adjust enabled
• Net usable delay span ≥ 4.0 ns
• Falling Edge Adjust ± 250 ps
• On Board DACs to generate 5 ps resolution With a maximum operating frequency of 1 GHz, the Edge629 is optimized for extremely high speed, high ac- curacy testers, particularly those aimed to test memory devices. The Edge629 solves several difficult problems associated with aligning multiple timing signals because it can:
• delay very narrow pulses over a long timing span
• adjust the falling edge independently from the overall propagation delay
• maintain extreme timing accuracy for very narrow (sub-ns) pulses
• maintain tight timing accuracy over changes in frequency, duty cycle, and pattern.

TEST AND MEASUREMENT PRODUCTS Edge629  2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com PIN Description emaNniP# niPn oitpircseD *NI/NI8 ,9. tuonaflangis4:1rofdesulangistupnilaitnereffiD *0NI,0NI *1NI/1NI *2NI/2NI *3NI/3NI 61,51 21,11 5,6 1,2 .tuonaflangis1:1rofdesuslangistupnilaitnereffiD *0TUO/0TUO *1TUO/1TUO *2TUO/2TUO *3TUO/3TUO 43,33 83,73 34,44 74,84 .slangistuptuolaitnereffiD *LES/LES3 2,22 .ecruoslangistupniehttcelesotdesuslangistupnilaitnereffiD IDS8 5. tupniatadlaireS KC6 5. IDSnihctalotdesukcolC SC9 5. tcelespihC ETADPU7 5. sretsigeryaledehtsdaolhcihwtupnilatigiD EDONA,EDOHTAC5 2,42. gnirtsedoidlamrehtpihc-nonafoslanimreT 3-0PMOC1 6,26,91,02. snipnoitasnepmocpmapolanretxE )3-0(_LLAF_CAD4 5,25,92,72 ebdluohsgnihton;ylnosesopruptsetroF.stuptuoCADtsujdaegdegnillaF .snipesehtotdetcennoc )3-0(_ENIF_CAD3 5,15,03,82 detcennocebdluohsgnihton;ylnosesopruptsetroF.stuptuoCADyaledeniF .snipesehtot CCV, 62,41,31,4,3 ,54,04,63,53,13 55,05,64 .ylppusrewopevitisoP EEV, 12,81,71,01,7 ,94,24,14,93,23 46,36,06 .ylppusrewopevitageN

3 2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com TEST AND MEASUREMENT PRODUCTS Edge629 PIN Description (continued) OUT3 OUT3* VCC3 VCC2 OUT2 OUT2* VEE2 VEE4 VCC4 VEE1 OUT1* OUT1 VCC1 VCC0 OUT0* OUT0 IN3* IN3 VCC3 VCC2 IN2* IN2 VEE2 IN* IN VEE1 IN1 IN1* VCC1 VCC0 IN0 IN0* VEE3 VEE5 COMP2 COMP3 VEE5 CS SDI UPDATE CK VCC5 DAC_FALL_3 DAC_FINE_3 DAC_FALL_2 DAC_FINE_2 VCC5 VEE3 VEE0 VEE6 COMP1 COMP0 VEE6 SEL SEL* CATHODE ANODE VCC6 DAC_FALL_0 DAC_FINE_0 DAC_FALL_1 DAC_FINE_1 VCC6 VEE0 64 49 Top View E629AXF

64 Pin

independent for each channel.

1 Coarse LSB = 90 ps

2 Coarse LSB = 180 ps

4 Coarse LSB = 360 ps

8 Coarse LSB = 720 ps

will track each other over the entire coarse delay span.

16 Bit Serial Register

Figure 1. Coarse Delay Architecture

should be connected to these pins. is designed to be ~2X the coarse delay resolution.

2 Fine LSB = 5 ps

4 Fine LSB = 10 ps

8 Fine LSB = 20 ps

16 Fine LSB = 40 ps

0 ns ≤ Fine Delay Range ≤ 157.5 ps. LSB steps could be as large as 5 ps. be programmed independently from all other channels. Figure 2. Fine Delay Architecture

6 Bit DAC

analog delay cell and an on-chip 7 bit DAC (see Figure 3). FEA affects only the propagation delay of the falling edge. It has no effect on the propagation delay of a rising edge. There is a limitation on FEA range vs. pulse width. should be connected to these pins. accurate die temperature measurements. Figure 4. Thermal Diode String junction temperature (see Figure 5).

7 Bit DAC

Figure 3. Falling Edge Adjust Architecture

7 2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com TEST AND MEASUREMENT PRODUCTS Edge629 Circuit Description (continued) Programming The Edge629 is programmed serially with 3 control lines: SDI – serial data input CS – chip select UPDATE – register update which are all synchronous with CK. With CS valid (high), rising edge of CK will load SDI into the 16 bit shift register. With CS valid and UPDATE valid (high), CK high will make the selected latch go transparent. The falling edge of CK will then latch the data (see Figures 6 and 7). Data and address information are combined in the 16 bit word. Bits 0–6 are used for data, bits 11–15 for address. Bits 11–14 select 1 of 16 destinations, bit 15, if high, selects all 16 locations to be loaded simultaneously (use- ful for preloading all registers to a default state).Figure 5. Voltage vs. Temperature for Thermal Diode String 4.20 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 0.00 50.0 100 150 Temp (˚C) V = Vanode – Vcathode [V] : IFORCE = 100µ/Anode : IFORCE = 10µ/Anode : IFORCE = 1µ/Anode V = Vanode – Vcathode; Vcathode = VEE tiB5 14 13 12 11 10 1 -dA rd AL3 A2 A1 A0 An oitcnuFyaleD 0 00000X y aleDesraoC,0lennahC 1 000011 y aleDeniF,0lennahC 2 000101 t sujdAegdEgnillaF,0lennahC 3 00011X d esUtoN 4 00100X y aleDesraoC,1lennahC 5 001011 y aleDeniF,1lennahC 6 001101 t sujdAegdEgnillaF,1lennahC 7 00111X d esUtoN 8 01000X y aleDesraoC,2lennahC 9 010011 y aleDeniF,2lennahC A 010101 t sujdAegdEgnillaF,2lennahC B 01011X d esUtoN C 01100X y aleDesraoC,3lennahC D 011011 y aleDeniF,3lennahC E 011101 t sujdAegdEgnillaF,3lennahC F 01111X d esUtoN X 1XXXX0 y aleDesraoC,slennahCllA X 1XXXX1 s noitcnuFllA,slennahCllA

Figure 6. Synchronous Loading

629 Digital Interface Timing

16 Bit Loads

Figure 7. Data Interface

TEST AND MEASUREMENT PRODUCTS Edge629  2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com Circuit Description (continued) Timing Inputs IN/IN* and IN0/IN0* – IN3/IN3* are high speed differen- tial inputs which require >300 mV of differential input voltage for reliable switching. These inputs may receive differential input signals with amplitudes up to 3.3V. This wide range input voltage com- pliance allows CMOS signals to drive the Edge629 directly. The inputs may go all the way up to VCC and still not cause any saturation. The Edge629 will operate at full performance under these input conditions. Do not leave any differential inputs floating as they will be in an indeterminate state. All unused inputs must be tied to either a high or low level. Connecting unused timing inputs to VCC is an acceptable method to make an input high. However, to make an input low, it must be con- nected to VEE +2.0V or higher. Input Mux Select Each delay channel can select its input from one of two sources. If Mux Select is high (SEL > SEL*), IN/IN* will be selected for all four channels. If Mux Select is low (SEL < SEL*), IN0/IN0* – IN3/IN3* will be selected for each channel. SEL/SEL* have internal pull-up/pull-down resistors which, when left floating, place the chip in fanout mode. Data Interface Digital Inputs All data digital inputs are standard, single ended ECL in- puts with V bb = –1.3V relative to VCC. However, all digital inputs may receive input signals anywhere between VCC and VEE. This wide input voltage compliance allows CMOS signals to program the Edge629 without causing satura- tion problems. All digital interface inputs are "3.3V rail to rail" CMOS compatible provided VCC = +3.3V and VEE = –2V. CK, SDI, and UPDATE all have an internal pull-down resis- tor network to establish a default condition of a logical 0 when left floating. CS has a large (~50 KΩ ) internal pull- up resistor to VCC to establish a default condition of a logical 1 when left floating. For optimal performance, all data interface digital inputs should be static when the Edge 629 is actively delaying signals. (However, it is acceptable if CK continues to run.) Timing Outputs OUT0/OUT0* – OUT3/OUT3* are standard differential ECL open emitter outputs. Compensation Pins COMP0, COMP1, COMP2, and COMP3 are op amp compensation pins requiring external 100 pF capacitors to VEE. SEL* VCC SEL 50KΩ 50KΩ VEE VCC CK, SDI, UPDATE VCC CS VEE VCC 50KΩ 50KΩ 50KΩ *LES/LESe cruoStupnIe doM 0* 3NI/3NI–*0NI/0NIh guorhTssaP 1* NI/NIt uonaF

11 2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com TEST AND MEASUREMENT PRODUCTS Edge629

Package Information

10 mm x 10 mm x 1.4 mm D E E1–A– –B– –D– N 1EXPOSED HEATSINK 3.56 ± .50 DIA. 12 TYP .˚ 12 TYP .˚ AA2 A L θ b.17 MAX .25 –C– LEAD COMPLANARITY SEATING PLANE STANDOFF ddd M C A–B S D S ccc C .20 RAD. TYP . 20 RAD. TYP . 6˚±4˚ Notes: 1. All dimensions in millimeters. 2. Dimensions shown are nominal with tolerances as indicated. 3. L/F: EFTEC 64T copper or equivalent, 4. Foot length “L” is measured at gage plane, at 0.25 above the seating plane. .smiDe cnareloTe ulaV A. XAM0 6.1 1Ax am51./.nim50. 2A5 0.±0 4.1 D0 2.±0 0.21 1D0 1.±0 0.01 E0 2.±0 0.21 1E0 1.±0 0.01 L0 1.–/51.+0 6. eC ISAB0 5. b5 0.±2 2. θ ˚7-˚0 ddd. XAM8 0. ccc. XAM8 0. ssenkcihTegakcaP0 4.1 tnirptooFm m2+ydoB Top View

TEST AND MEASUREMENT PRODUCTS Edge629  2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com Recommended Operating Conditions Absolute Maximum Ratings Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. retemaraPl obmySn iMp yTx aMs tinU ylppuSrewoPlatoTE EV–CCV2 .42 .55 .5+V erutarepmeTnoitcnuJJ T0 0 01+C ˚ retemaraPl obmySn iMp yTx aMs tinU ylppuSrewoPE EV–CCV0 0 .7V niPtupnIlatigiDynanoegatloV 5.0–EEV5 .0+CCVV niPtupnIgolanAynanoegatloV 5.0–EEV5 .0+CCVV tnerruCtuptuO0 5– Am erutarepmeTegarotSS T5 6– 051+C ˚ erutarepmeTnoitcnuJJ T0 51+C ˚ erutarepmeTgniredloS )nipehtmorf"52.,sdnoces5( LOST0 62+C ˚ θ CJ )esacfopotot( θ CJ 5.1C ˚ θ AJ )riallits@( θ AJ 82C ˚ θ AJ )MPFL004@( θ AJ 12C ˚

13 2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com TEST AND MEASUREMENT PRODUCTS Edge629 DC Characteristics retemaraPl obmySn iMp yTx aMs tinU stupnIgnimiT )*3NI/3NI–*0NI/0NI,*NI/NI( egatloVtupnIlaitnereffiD| *NI–NI|3 .E EV–CCVV egnaRegatloVhgiHtupnIH IV0 .2+EEVC CVV egnaRegatloVwoLtupnIL IV0 .2+EEV3 .–HIVV tnerruChgiHtupnIH II0 01– 001+A µ tnerruCwoLtupnIL II0 01– 001+A µ )*LES/LES(tupnItceleS egatloVhgiHtupnI* LES–LES3 .E EV–CCVV egatloVwoLtupnIL ES–*LES3 .E EV–CCVV egnaRedoMnommoChgiHtupnIH IV0 .2+EEVC CVV egnaRedoMnommoCwoLtupnIL IV0 .2+EEV3 .–HIVV tnerruChgiHtupnIH II0 52A µ tnerruCwoLtupnIL II0 52A µ )IDS,SC,ETADPU,KC(stupnIgnimmargorP egatloVhgiHtupnIH IV1 .1–CCVC CVV egatloVwoLtupnIL IV0 .2+EEV5 .1–CCVV tnerruChgiHtupnIH II0 52A µ tnerruCwoLtupnIL II0 52A µ stuptuOlatigiD egatloVhgiHtuptuOlatigiD* TUO–TUO0 060 96V m egatloVwoLtuptuOlatigiDT UO–*TUO0 060 96V m egnaRedoMnommoCtuptuO* TUO+TUO 5.1–CCV3 .1–CCV1 .1–CCVV tnerruCtuptuOt uoI0 3A m tnerruCylppuSrewoP V2.4=EEV–CCVE EI1 650 09A m V2.5=EEV–CCVE EI4 060 09A m V5.5=EEV–CCVE EI3 160 09A m

TEST AND MEASUREMENT PRODUCTS Edge629  2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com AC Characteristics Test Conditions (unless otherwise specified): "Recommended Operating Conditions." retemaraPl obmySn iMp yTx aMs tinU stuptuO/stupnIgnimiT )2etoN(yaleDnoitagaporPmuminiM )3,0(TUOotNI )3,0(TUOot3,0NI ∆ 0=DFotdelbasiDDF,dpT ∆ 0=AEFotdelbasiDAEF,dpT niMdpT niMdpT ∆ dpT ∆ dpT 282.1 604.1 753.1 184.1 023 059 234.1 655.1 sn sn sp sp noitagaporPegdEgnillaF/egdEgnisiR )delbasidAEF(ecnereffiDyaleD |–dpT–+dpT| 30 1s p )2etoN(wekSlennahC-ot-lennahC )edoMtuonaF()3,0(TUOotNI )3,0(TUOot)3,0(NI 1weksT 2weksT sp sp )2etoN(yaleDelbammargorP yaleDesraoC yaleDeniF esraoC_napsT eniF_napsT 5.5 011 0.6 051 5.6 081 sn sp )1etoN()1=EFS(tsujdAegdEgnillaFA EF0 02±0 52±0 03±s p )3etoN(eziSpetSyaleDelbammargorP yaleDesraoC yaleDeniF tsujdAegdEgnillaF esraoC_petsT eniF_petsT AEF_petsT 0.1 0.1 0.1 011 sp sp sp )delbanEAEF(ycneuqerFgnitarepOmumixaMx amF0 .1z HG )delbasiDAEF(ycneuqerFgnitarepOmumixaMx amF3 .1z HG )stuptuota(htdiWesluPmuminiMn imWP0 53s p )%08-%02(semiTllaFdnaesiRtuptuOf T/rT0 110 51s p )pmeTeiD.sv(tneiciffeoCerutarepmeT delbasiDAEF&DF,niM=DC delbasiDAEF&DF,xaM=DC delbasiDAEF,niM=DF&DC delbasiDAEF,xaM=DF&DC niM=AEF&,DF,DC xaM=AEF&,DF,DC ∆ /dpT ∆T 4.2 3.31 3.3 1.51 2.5 8.81 C˚/sp C˚/sp C˚/sp C˚/sp C˚/sp C˚/sp rorrEgnimiTlatoT ∆ ycneuqerF.svdpT klatssorClennahC-ot-lennahC ∆ elcyCytuD.svdpT yaleDmuminiM@rettiJ yaleDmumixaM@rettiJ sp sp sp sp

15 2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com TEST AND MEASUREMENT PRODUCTS Edge629 AC Characteristics (continued) Test Conditions (unless otherwise specified): "Recommended Operating Conditions." AC Characteristics are guaranteed by design and characterization. Not production tested. retemaraP lobmySn iMp yTx aMs tinU ecafretnIataD emiTpUteS KCotIDS ↑ KCotSC ↑ KCotETADPU ↓ usT usT usT sn sn sn emiTdloH KC ↑ IDSot KC ↑ SCot KC ↓ ETADPUot hT hT hT sn sn sn shtdiWesluPmuminiM hgiHKC woLKC doirePKCT sn sn sn emiTgniltteSCAD 1s µ Test Conditions (unless otherwise specified): "Recommended Operating Conditions." Note 1: Tested with an input pulse = 50 ns. This parameter is guaranteed by characterization for input pulse widths ≥ 700 ps. Note 2: Coarse Delay = 0, Fine Delay and Falling Edge Adjust disabled. Case Temperature = 50˚C. Note 3: Coarse Delay is monotonic. Fine Delay is Monotonic. Since the fine delay spans close to 2 LSBs of coarse delay, the summation of digital codes for coarse and fine delays is not monotonic. Proper binary searching using both the coarse and fine delays is achieved first with the coarse (with SFD=1), and then with the fine delays as separate searches.

TEST AND MEASUREMENT PRODUCTS Edge629  2005 Semtech Corp. Rev. 3, 8/1/05 www.semtech.com Ordering Infor mation Contact Infor mation Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633 rebmuNledoMe gakcaP FXA926E PFQTmm4.1x01x01 poTnoknistaeHdesopxE/w FXA926MVEd raoBnoitaulavE926egdE