EVKT-USBI2C-02

MP5424 MPS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 44

Technical content

5V PMIC with Four 4.5A/2.5A/4.5A/2A Buck Converters, 3 LDOs, 1 Load Switch, and Flexible System Settings via I2C and MTP MP5424 Rev. 1.0 MonolithicPower.com 1 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

DESCRIPTION

The MP5424 is a com plete power management solution that integrates four high-efficiency step- down DC/DC converters, three low-dropout (LDO) regulators, one load switch, and a flexible logic interface. Constant-on-time (COT) control in the DC/DC converter provides fast transient response. The 1.1MHz default switching frequency (fSW) during continuous conduction mode ( CCM) greatly reduces the external inductance and capacitance. Full protection features include under-voltage lockout ( UVLO) protection, over- current protection (OCP), over-voltage protection (OVP), and thermal shutdown. The output voltage (VOUT) can be adjusted via the I2C bus or preset by the multiple-time programmable (MTP) interface. The start- up/shutdown sequence can also be con figured via the MTP and controlled via the I2C bus. The MP5424 requires a minimal number of external components, and is available in a small QFN-26 (3.5mmx4.5mm) package.

FEATURES

• High-Efficiency Step-Down Converters: o Buck 1: 4.5A DC/DC Converter o Buck 2: 2.5A DC/DC Converter o Buck 3: 4.5A DC/DC Converter o Buck 4: 2A DC/DC Converter o Buck 1 and Buck 3 Can Work in Parallel o Buck 2 and Buck 4 Can Work in Parallel o 2.7V to 5.5V Operating VIN Range o Buck 1, Buck 2, and Buck 3 Selectable VOUT Range: 0.4V to 2.2V/7.4mV Step or 0.4V to 3.58V VOUT/12.5mV Step o Buck 4 VOUT Range: 0.4V to 3.58V VOUT/12.5mV Step o Adjustable Switching Frequency (fSW) o Adjustable Soft-Start Time (tSS) o Adjustable Phase Delay o Configurable Forced PWM (FPWM) Mode or Auto-PFM/PWM Mode o Output OCP and OVP
• Low-Dropout (LDO) Regulators: o Three 300mA, Low-Noise LDOs o Two Separate Input Power Supplies o 50mV Dropout at 300mA Load
• Load Switch: o 2.7V to 5.5V/3A Load Switch o 50mΩ On Resistance at VIN = 5V o On/Off Control via the I2C and Programmable Sequence o Configurable Output Discharge Function via the I2C (Default: On)
• System: o I2C Bus and User-Programmable MTP o Two-Time Programmable MTP (1) o Start-Up/Shutdown Control o Enable Pin (EN1) for Sleep Mode Entry and Recovery Control o Start-Up Reset Output o Flexible Start-Up/Shutdown Sequence via MTP (0.5ms, 2ms, 8ms, or 16ms Selectable Time Slot) o Available in a QFN-26 (3.5mmx4.5mm) Package Optimized Performance with MPS Inductor MPL-AL6050 Series Note: 1) The two -time programmable MTP is only for the standard version of the MP5424GRM-0000.

APPLICATIONS

• General Consumer
• Camera Modules
• 3.3V/5V Powered Systems
• Space-Limited Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are registered trademarks of Monolithic Power Systems, Inc. or its subsidiaries.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 2 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION MP5424 VIN1 GND1 PWRON SCL SW1 FB1 LSWI LSWO /EN1 OUT2 VIN1 = 2.7V to 5.5V VOUT1 = 1.05V 22µF 22µF x 2 1µH SW2 FB2 22µF x 2 1.5µH SW3 FB3 22µF x 2 SW4 FB4 22µF x 2 VIN2 GND2 22µF VIN3 22µF VIN4 22µF VOUT3.3V/ 10µF C10 10µF C15 VIN5 2.2µF C14 OUT5 3.3V 2.2µF C13 OUT4 3.3V RSTO AVIN 0.1µF AGND SDA VOUT2 = 1.0375V VOUT3 = 1.05V VOUT4 = 1.35V 1µH 1.5µH 100k 3.3V VIN5 = 5V 10µF C11 2.2µF C12 1.8V MTP-EFUSE SELECTED TABLE BY DEFAULT (MP5424GRM-0000) MTP Items Buck 1 Buck 2 Buck 3 Buck 4 LSWO (2) LDO 2 LDO 4 LDO 5 Initial on/off On On On On On On On On Mode FPWM FPWM FPWM FPWM N/A Start-up delay 1.5ms 1ms 1.5ms 0.5ms 2ms 0ms 5ms 5.5ms Soft-start time (tSS) 300μs 300μs 300μs 300μs N/A Switching frequency (fSW) 1.1MHz PWRON MODE 0 (level trigger) RSTODELAY 50ms Buck 1 peak current limit 7.6A Buck 2 peak current limit 3.9A Buck 3 peak current limit 7.6A Buck 4 peak current limit 3.9A I2C slave address 0x69 MTP configuration code 0000 Note: 2) The load switch supply is on the LSWI pin. The supply voltage range is between 2.7V and 5.5V.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 3 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL MP5424GRM-xxxx** QFN-26 (3.5mmx4.5mm) See Below 1 MP5424GRM-0000 QFN-26 (3.5mmx4.5mm) See Below 1 * For Tape & Reel, add suffix -Z (e.g. MP5424GRM-0000-Z, MP5424GRM-xxxx-Z). ** “xxxx” is the configuration code identifier for the register setting stored in the MTP. The default number is “0000”. Each “x” can be a hexadecimal value between 0 and F. Contact an MPS FAE to create this unique number. TOP MARKING MPS: MPS prefix Y: Year code W: Week code M5424: Part number LLLLL: Lot number EVALUATION KIT EVKT-MP5424 EVKT-MP5424 kit contents (items below can be ordered separately): # Part Number Item Quantity

1 EV5424-R-00A MP5424GRM evaluation board 1

2 EVKT-USBI2C-02 Includes one USB to I 2C communication interface device, one USB

cable, and one ribbon cable 1

3 MP5424-0000 MP5424 IC which can be used for MTP programming 2

Order direct from MonolithicPower.com or our distributors. Evaluation Board Load Ribbon Cable GUI Output Input USB to I2C Communication Interface Input Power Supply USB Cable Load Figure 1: EVKT-MP5424 Evaluation Kit Set-Up

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 4 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW 3VIN1 4SW1 5GND1 6SW3 VIN3 VIN2 SW2 GND2 SW4 VIN4 26 25 AVIN AGND LSWO/ EN1 LSWI SCL SDA OUT4 VIN5 2PWRON 2324

21 FB2

15 FB4FB3

QFN-26 (3.5mmx4.5mm)

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 5 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 FB1 Buck 1 feedback. Connect buck 1’s output directly to the FB1 pin. 2 PWRON Start-up/shutdown input. The PWRON pin is a logic input pin that can start up or shut down the device. PWRON has a weak internal pull-up current.

3 VIN1

Buck 1 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN1 path. VIN1, VIN2, VIN3, VIN4, and AVIN should be connected to the same bus voltage (VBUS). 4 SW1 Buck 1 switch output. Use a wide PCB trace for SW1 path. 5 GND1 Buck 1 and buck 3 power ground. The GND1 pin requires special consideration during PCB layout. Connect GND1 to ground using copper traces and vias. 6 SW3 Buck 3 switch output. Use a wide PCB trace for SW3 path.

7 VIN3

Buck 3 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN3 path. VIN1, VIN2, VIN3, VIN4, and AVIN should be connected to the same VBUS. 8 FB3 Feedback of buck3. Connect buck 3’s output directly to the FB3 pin. 9 RSTO Reset output from the PMIC to CPU. The RSTO pin is an open-drain output. RSTO requires an external pull-up resistor. 10 SCL I2C clock signal input. 11 SDA I2C data pin. 12 OUT4 LDO4 output. The LDO4 pin is powered by VIN5. 13 VIN5 LDO4 and LDO5 power input pin. This VIN5 pin operates from a 2.7V to 5.5V input voltage (VIN). Connect the VIN5 and VIN1 pins if LDO4 and LDO5 are not used. 15 FB4 Buck 4 feedback. Connect buck ’s output directly to the FB4 pin.

16 VIN4

Buck 4 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN4 path. VIN1, VIN2, VIN3, VIN4, and AVIN should be connected to the same VBUS. 17 SW4 Buck 4 switch output. Use a wide PCB trace for SW4 path 18 GND2 Buck 2 and buck 4 power ground. The GND2 pin requires special consideration during PCB layout. Connect GND2 to ground using copper traces and vias. 19 SW2 Buck 2 switch output. Use a wide PCB trace for SW2 path

20 VIN2

Buck 2 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN2 path. VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage. 21 FB2 Buck 2 feedback. Connect buck 2’s output directly to the FB2 pin. 22 OUT2 LDO 2 output. LDO 2 is powered by VIN2. If the OUT2 pin is configured as EN1, then OUT2 acts as an input pin. Pull EN1 high to turn on the PMIC; pull EN1 low to turn it off. 23 LSWI Load switch input.

24 LSWO/

Load switch output or EN1. If the LSWO/EN1 pin is configured as EN1, then LSWO/EN1 acts as an input pin. 25 AGND Analog ground. Connect the AGND pin to the GND1 and GND2 pins.

26 AVIN

Power supply input for logic circuitry. Use a 0.1µF ceramic capacitor to bypass the AVIN pin to AGND. Connect AVIN to the system input via a . Ω resistor. VIN1, VIN2, VIN3, VIN4, and AVIN should be connected to the same VBUS.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 6 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (3) ………………….-0.3V to +6.5V (6.8V for 300ms) -0.6V (-5V for <10ns) to VINx + 0.3V (7V for <10ns) Continuous power dissipation (TA = 25°C) (4) (8) ESD Ratings (5) (6) Recommended Operating Conditions (7) Operating junction temp (TJ) .... -40°C to +125°C Thermal Resistance θJA θJC QFN-26 (3.5mmx4.5mm) Notes: 3) Exceeding these ratings may damage the device. 4) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable contin uous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can cause excessive die temperature, and the device may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 5) HBM is measured in accordance with JEDEC specification JESD22-A114. JEDEC document JEP155 states that a 500V HBM allows for safe manufacturing with a standard ES D control process. 6) CDM is measured in accordance with JEDEC specification JESD22-C101. JEDEC document JEP157 states that a 250V CDM allows for safe manufacturing with a standard ESD control process. 7) The device is not guaranteed to function outside of its operating conditions. 8) Measured on EV5424-R-00A, 4-layer PCB. 9) Measured on JESD51-7, 4-layer PCB. The values given in this table are only valid for comparison with other package s and cannot be used for design purposes. 10) These values were calculated in accordance with JESD51 -7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 7 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = VAVIN = 5V, TJ = -40°C to +125 °C (11), typical values are tested at TJ = 25°C, unless otherwise noted. (12) Parameter Symbol Condition Min Typ Max Units Shutdown current ISD RSTO_MODE = 01/11, PWRON = 0, TJ = 25°C 25 60 μA Supply current IIN FBx is high, no switching, TJ = 25°C 220 450 μA Default switching frequency fSW 0.8 1.1 1.4 MHz Thermal shutdown entry threshold (13) TSD_ENTRY 153 °C Thermal shutdown recovery threshold (13) TSD_RECOVERY 130 °C Step-Down Regulator VAVIN under-voltage lockout (UVLO) rising threshold VAVIN_UVLO_ RISING 2.4 2.55 2.7 V VAVIN UVLO hysteresis VAVIN_UVLO_ HYS 300 mV VIN1 UVLO rising threshold VIN1_UVLO_ RISING 2.3 2.45 2.6 V VIN1 UVLO hysteresis VIN1_UVLO _HYS 300 mV VIN2 UVLO rising threshold VIN2_UVLO_ RISING 2.3 2.45 2.6 V VIN2 UVLO hysteresis VIN2_UVLO _HYS 300 mV VIN3 UVLO rising threshold VIN3_UVLO_ RISING 2.3 2.45 2.6 V VIN3 UVLO hysteresis VIN3_UVLO _HYS 300 mV VIN4 UVLO rising threshold VIN4_UVLO_ RISING 2.3 2.45 2.6 V VIN4 UVLO hysteresis VIN4_UVLO _HYS 300 mV VIN5 UVLO rising threshold VIN5_UVLO_ RISING 2.3 2.45 2.6 V VIN5 UVLO hysteresis VIN5_UVLO _HYS 300 mV Feedback voltage VFB1 Buck 1 default output 1.029 1.05 1.071 V VFB2 Buck 2 default output 1.01675 1.0375 1.0583 V VFB3 Buck 3 default output 1.029 1.05 1.071 V VFB4 Buck 4 default output 1.323 1.35 1.377 V Maximum duty cycle (13) DMAX Buck 1 to Buck 4 100 % Buck 1 and Buck 3 (4.5A/4.5A) High-side MOSFET (HS- FET) on resistance RDS(ON)_HS1 500mA, TJ = 25°C 25 35 mΩ RDS(ON)_HS3 RDS(ON)_HS1 500mA, TJ = -40°C to +125°C 25 45 mΩ RDS(ON)_HS3 Low-side MOSFET (LS- FET) on resistance RDS(ON)_LS1 500mA, TJ = 25°C 12 16 mΩ RDS(ON)_LS3 RDS(ON)_LS1 500mA, TJ = -40°C to +125°C 12 20 mΩ RDS(ON)_LS3 HS-FET switch leakage ISWLK_HS1 Shutdown, VINx = 5.5V, VSWx = 0V or 5.5V, TJ = 25°C 0 1 μA ISWLK_HS3

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 8 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = VAVIN = 5V, TJ = -40°C to +125 °C (11), typical values are tested at TJ = 25°C, unless otherwise noted. (12) Parameter Symbol Condition Min Typ Max Units LS-FET switch leakage ISWLK_LS1 Shutdown, VINx = 5.5V, VSWx = 0V or 5.5V, TJ = 25°C 0 1 μA ISWLK_LS3 HS-FET current limit ILIMIT1 20% duty cycle, TJ = 25°C 5.7 7.6 9.3 A ILIMIT3 Minimum on time (13) tON_MIN1 50 ns tON_MIN3 50 ns Minimum off time (13) tOFF_MIN1 120 ns tOFF_MIN3 120 ns Output discharge resistance ROUT_DIS1 3 7 20 Ω Soft-start time tSS_B1 VOUTx = 10% to 90% 140 300 430 μs tSS_B3 VOUTx = 10% to 90% 140 300 430 μs Output over-voltage protection (OVP) rising threshold VOVP1_RISING Buck 1 115 120 125 % of VREF Buck 3 115 120 125 % of VREF Output OVP falling threshold VOVP1_FALLING Buck 1 105 110 115 % of VREF Buck 3 105 110 115 % of VREF Buck 2 and Buck 4 (2.5A/2A) HS-FET on resistance RDS(ON)_HS2 500mA, TJ = 25°C 40 55 mΩ RDS(ON)_HS4 RDS(ON)_HS2 500mA, TJ = -40°C to +125°C 40 70 mΩ RDS(ON)_HS4 LS-FET on resistance RDS(ON)_LS2 500mA, TJ = 25°C 40 55 mΩ RDS(ON)_LS4 RDS(ON)_LS2 500mA, TJ = -40°C to +125°C 40 85 mΩ RDS(ON)_LS4 HS-FET switch leakage ISWLK_HS2 Shutdown, VINx = 5.5V, VSWx = 0V or 5.5V, TJ = 25°C 0 1 μA ISWLK_HS4 LS-FET switch leakage ISWLK_LS2 Shutdown, VINx = 5.5V, VSWx = 0V or 5.5V, TJ = 25°C 0 1 μA ISWLK_LS4 HS-FET current limit ILIMIT2 20% duty cycle, TJ = 25°C 2.8 3.9 5 A ILIMIT4 Minimum on time (13) tON_MIN2 50 ns tON_MIN4 50 ns Minimum off time (13) tOFF_MIN2 100 ns tOFF_MIN4 100 ns Output discharge resistance ROUT_DIS2 3 8 20 Ω Soft-start time tSS_B2 VOUT = 10% to 90% 140 300 430 μs tSS_B4 VOUT = 10% to 90% 140 300 430 ms Output OVP rising threshold VOVP2_RISING Buck 2 115 120 125 % of VREF Buck 4 115 120 125 % of VREF

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 9 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = VAVIN = 5V, TJ = -40°C to +125 °C (11), typical values are tested at TJ = 25°C, unless otherwise noted. (12) Parameter Symbol Condition Min Typ Max Units Output OVP falling threshold VOVP2_FALLING Buck 2 105 110 115 % of VREF Buck 4 105 110 115 % of VREF Load Switch Operating input voltage range VIN_LSW 2.7 5.5 V Load switch on resistance RDS(ON)_LSW VLSWI = 5V, 1A load 50 mΩ Output discharge resistance ROUT_DIS3 3 7 20 Ω Soft-start slew rate tSS_LSW COUT = 10µF 1.5 mV/μs Low Dropout (LDO) Regulators (LDO 2, LDO 4, and LDO 5) Output voltage VLDO2 IOUT = 10mA 1.764 1.8 1.836 V VLDO4 IOUT = 10mA 3.234 3.3 3.366 V VLDO5 IOUT = 10mA 3.234 3.3 3.366 V PSRR (13) PSRR1k LDO4 and LDO5, VOUTx = 1.8V 52 dB Dropout voltage VDROP1 VOUTx = 3V, IOUT = 300mA 50 mV Current limit ILIMIT_LDO2 VINx = 3.3V, VOUTx drops 33% 300 430 600 mA ILIMIT_LDO_LS LDO4 and LDO5 set ILIM bit to 0, VINx = 3.3V, VOUTx drops 33% 380 520 660 mA ILIMIT_LDO_HS LDO4 and LDO5 set ILIM bit to 1, VINx = 3.3V, VOUTx drops 33% 580 790 1000 mA Output discharge resistance ROUT_DIS4 3 7 20 Ω Soft-start time tSS_B2 VOUTx = 10% to 90%, COUT = 2.2µF 50 μs Line regulation VIN2 = VIN5 = 2.8V to 5.5V 0.3 %/V Load regulation VIN2 = VIN5 = 3.3V, IOUT = 10mA to 100mA 0.5 % Logic Pins PWRON pull-up current IPWRON AVIN is pulled up internally 5 9 13 μA PWRON rising threshold VPWR_RISING 0.8 1 1.2 V PWRON voltage hysteresis VPWR_HYS 100 mV EN1 rising threshold VPWR_ RISING 0.8 1 1.2 V EN1 voltage hysteresis VPWR_HYS 100 mV PG rising threshold VPG_ RISING RSTO_MODE = 01 86 90 94 % of VFB PG falling threshold VPG_FALLING RSTO_MODE = 01 76 80 84 % of VFB PFI rising threshold VPFI_ RISING RSTO_MODE = 10 3.8 4 4.2 V PFI hysteresis VPFI_HYS 7 % of VPFI_ RISING RSTO rising delay tDELAY_RSTO Adjustable via the I2C/MTP 30 50 70 ms

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 10 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = VAVIN = 5V, TJ = -40°C to +125 °C (11), typical values are tested at TJ = 25°C, unless otherwise noted. (12) Parameter Symbol Condition Min Typ Max Units I2C Interface Specifications (14) Input logic high VIN_HIGH 1.4 V Input logic low VIN_LOW 0.4 V Output voltage logic low VOUT_LOW RSTO pin, 4mA sink 0.4 V SCL clock frequency fSCL 3.4 MHz SCL high time tHIGH_SCL 60 ns SCL low time tLOW_SCL 160 ns Data setup time tSU_DATA 10 ns Data hold time tHD_DATA 70 ns Set-up time for repeated start tSU.START 160 ns Hold time for repeated start tHOLD.START 160 ns Bus free time between a start and a stop condition tBUS_FREE 160 ns Set-up time for stop condition tSU_STOP 160 ns Rise time of SCL and SDA tRISE 10 300 ns Fall time of SCL and SDA tFALL 10 300 ns Suppressed spike pulse width tSPIKE 0 50 ns Capacitance for each bus line CBUS 400 pF Notes: 11) Guaranteed by over-temperature correlation. Not tested in production. 12) Tested with default version (MP5424GRM-0000), unless otherwise noted. 13) Guaranteed by engineering sample characterization. 14) It is recommended to use I2C function after the start-up sequence is complete (e.g. all enabled power rails have completed start up). Figure 2 shows the I2C timing diagram for reading the I2C interface specifications. I2C TIMING DIAGRAM Figure 2: I2C Timing Diagram

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 11 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS Performance waveforms are tested on the evaluation board , VIN = 5V, T A = 25°C, test ed using default spec parts, unless otherwise noted. 100 0.01 0.1 1 10 EFFICIENCY (%) LOAD CURRENT (A) Efficiency vs. Load Current VIN = 5V, fSW = 1.1MHz, all bucks operate in FPWM mode buck1=1.05V buck2=1.0375V buck3=1.05V buck4=1.35V 100 0.01 0.1 1 10 EFFICIENCY (%) LOAD CURRENT (A) Efficiency vs. Load Current VIN = 5V, fSW = 1.1MHz, all bucks operate in FPWM mode buck1=0.8V buck2=1.2V buck3=1.5V buck4=1.8V -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0 2 4 6 LOAD REGULATION (%) INPUT VOLTAGE (V) Load Regulation buck1=1.05V buck2=1.0375V buck3=1.05V buck4=1.35V 100 120 0 2 4 6 CASE TEMPERATURE RISE ( C) IC POWER DISSIPATION (W) Case Temperature Rise vs. IC Power Dissipation Tested on 4-layer PCB (9.3cmx8.5cm) 100 150 200 250 300 2 3 4 5 6 QUIESCENT CURRENT (mA) INPUT VOLTAGE (V) Quiescent Current vs. Input Voltage 2.2 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 -40 10 60 110 VIN RISING THRESHOLD (V) TEMPERATURE ( C) VIN Rising Threshold vs. Temperature AVIN VIN1 VIN2 VIN3 VIN4 VIN5

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 12 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board, V IN = 5V, T A = 25°C, tested using default spec parts, unless otherwise noted. 0.9 0.95 1.05 1.1 1.15 1.2 -50 0 50 100 150 SWITCHING FREQEUNCY (MHz) TEMPERATURE ( C) Switching Freqeuncy vs. Temperature

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 13 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS Performance waveforms are tested on the evaluation board, V IN = 5V, T A = 25°C, tested using default spec parts, unless otherwise noted. Steady State All buck rails, no load Steady State All buck rails, full load CH1: VSW1 5V/div. CH2: VSW2 5V/div. CH3: VSW3 5V/div. CH4: VSW4 5V/div. CH1: VSW1 5V/div. CH2: VSW2 5V/div. CH3: VSW3 5V/div. CH4: VSW4 5V/div. 1μs/div. 1μs/div. Start-Up through PWRON All buck rails, no load Start-Up through PWRON All LDO rails, no load, VLSWI = 3.3V Ref: VPWRON 5V/div. CH1: Buck 1 1V/div. CH2: Buck 2 1V/div. CH3: Buck 3 1V/div. CH4: Buck 4 2V/div. Ref: VPWRON 5V/div. CH1: VLSWO 5V/div. CH2: LDO 2 2V/div. CH3: LDO 4 5V/div. CH4: LDO 5 5V/div. 1ms/div. 2ms/div. Shutdown through PWRON All buck rails without load Shutdown through PWRON All LDO rails, no load, VLSWI = 3.3V, all buck rails disabled Ref: VPWRON 5V/div. CH1: Buck 1 1V/div. CH2: Buck 2 1V/div. CH3: Buck 3 1V/div. CH4: Buck 4 2V/div. Ref: VPWRON 5V/div. CH1: VLSWO 5V/div. CH2: LDO 2 2V/div. CH3: LDO 4 5V/div. CH4: LDO 5 5V/div. 1ms/div. 2ms/div.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 14 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board, V IN = 5V, T A = 25°C, tested using default spec parts, unless otherwise noted. Start-Up through VIN All buck rails, no load Shutdown through VIN All buck rails, no load Ref: VIN 5V/div. CH1: Buck 1 1V/div. CH2: Buck 2 1V/div. CH3: Buck 3 1V/div. CH4: Buck 4 2V/div. Ref: VIN 5V/div. CH1: Buck 1 1V/div. CH2: Buck 2 1V/div. CH3: Buck 3 1V/div. CH4: Buck 4 2V/div. 2ms/div. 10ms/div. SCP Entry Buck 4 output = 1.35V, RSTO_MODE = 01 SCP Steady State Buck 4 output = 1.35V, RSTO_MODE = 01 CH1: Buck 4 1V/div. CH2: VRSTO 5V/div. CH3: VSW4 5V/div. CH4: IL4 5A/div. CH1: Buck 4 1V/div. CH2: VRSTO 5V/div. CH3: VSW4 5V/div. CH4: IL4 5A/div. 10ms/div. 10ms/div. SCP Recovery Buck 4 output = 1.35V, RSTO_MODE = 01 Load Transient Response IOUT transient from 2.25A to 4.5A, 2.5A/µs slew rate CH1: Buck 4 1V/div. CH2: VRSTO 5V/div. CH3: VSW4 5V/div. CH4: IL4 5A/div. CH1: Buck 1/AC 50mV/div. CH4: IOUT1 2A/div. 20ms/div. 100μs/div.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 15 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board, V IN = 5V, T A = 25°C, tested using default spec parts, unless otherwise noted. Load Transient Response IOUT transient from 1.25A to 2.5A, 2.5A/µs slew rate Load Transient Response IOUT transient from 2.25A to 4.5A, 2.5A/µs slew rate CH1: Buck 2/AC 50mV/div. CH4: IOUT2 1A/div. CH1: Buck 3/AC 50mV/div. CH4: IOUT3 2A/div. 100μs/div. 100μs/div. Load Transient Response IOUT transient from 1A to 2A, 2.5A/µs slew rate CH1: Buck 4/AC 50mV/div. CH4: IOUT4 1A/div. 100μs/div.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 16 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM 3A Load Switch 300mA/550mA LDO4 DCDC1 5.5V/4.5A I2C VID, 0.4V to 3.5875V with 12.5mV/Step or 0.4V to 2.2V with 7.4mV/Step UVLO 1.1MHz OSC Phase shift GND1 SW1 FB1 Driver and Control I2C Register and MTP Power Logic Control SW2 FB2 SW3 FB3 SW4 FB4 OUT4 300mA/550mA LDO5 Driver and Control OUT5 Control Logic VIN1 VIN3 AGND Driver and Control 300mA LDO 2 Driver and Control LSWI LSWO/EN1OUT2 VIN2 AVIN VIN5 GND2 VIN2 VIN4 SCL SDA PWRON RSTO Configurable EN1 Logic DCDC2 5.5V/2.5A I2C VID, 0.4V to 3.5875V with 12.5mV/Step or 0.4V to 2.2V with 7.4mV/Step DCDC3 5.5V/4.5A I2C VID, 0.4V to 3.5875V with 12.5mV/Step or 0.4V to 2.2V with 7.4mV/Step DCDC4 5.5V/2A I2C VID, 0.4V to 3.5875V with 12.5mV/Step Figure 3: Functional Block Diagram

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 17 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. OPERATION The MP5424 provides a complete power management solution for 5 V systems, such as televisions. It integrates four high-frequency, synchronous rectification, step -down switch- mode converters, as well as three low-dropout (LDO) regulators and one load switch . The compact QFN-26 (3.5mmx4.5mm) package reduces component count and PCB space. The d efault output voltage (VOUT), start-up sequence, and dynamic voltage scaling can be adjusted via the I 2C and multiple -time programmable (MTP ) interfaces. The I2C also provides powerful logic functions . See the I2C Register Map section on page 35 for more details. Any State No Supply Shutdown Thermal Shutdown (Following Shutdown Sequence) Start Up Start-Up Sequence Shutdown Sequence Detect the Power-On Factor The DC/DC converters and LDOs turn on sequentially, depending on the MTP and register settings. RSTO switches high Detect Power-Off Factor RSTO is Pulled Low VAVIN > VAVIN UVLO Rising Threshold VAVIN < VAVIN UVLO Falling Threshold Configure MTP Detect MTP Entry Factor MTP done, re-load MTP to I2C registers Figure 4: Power Control State Machine Diagram

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 18 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Power Control State Machine Description The state machine has a number of status options, including no supply, shutdown, start-up sequence, start-up, shutdown sequence, configure MTP, and shutdown event (see Figure 4 on page 17 ). These statuses are described below. No Supply The PMIC’s input pin (AVIN) has a UVLO detection circuit. If the input voltage (VAVIN) drops below the under-voltage lockout ( UVLO) rising threshold, then all of the PMIC’s functions are disabled. Shutdown All of the power rails turn off, and the PMIC enters the shutdown state once VAVIN drops below its UVLO falling threshold. In the shutdown state, the PMIC monitors the power- on factors. Once a power-on factor is detected, the device begins the start-up sequence. Start-Up Sequence The DC/DC converters, LDOs , and load switch turn on sequentially according to the order configured via the MTP e-fuse. Start-Up The DC/DC converters, LDOs and load switch turn on, and the RSTO pin’s output goes high. In the start-up state, the PMIC monitors the power- off factors and configure MTP factors. Shutdown Sequence If the PMIC detects the shutdown factors during a start-up state, then the PMIC enters the shutdown sequence. RSTO is pulled low. Then the DC/DC converters, LDOs , and load switch turn off sequentially according to the order configured via the MTP e-fuse. MTP Configure The buck converters, LDOs, and load switch turn off in the shutdown sequence when entering MTP mode. After MTP configuration is complete, the PMIC reloads the MTP to the I 2C registers and monitors the power-on factors. Shutdown Event If the PMIC detects any of the following conditions, then it enters a no supply or shutdown state, regardless of the current state.

• If the input voltage (VIN) drops below the UVLO falling threshold, then the device enters a no supply state.
• If thermal shutdown is triggered, then the device enters a shutdown state. Power-On Factor The PMIC has several power -on factors, including PWR_ON, thermal recovery, and EN1. These factors are described below. PWRON_ON If the PWRON pin is pulled to logic high (PWRON_MODE = 0) or there is a falling edge on the PWRON pin (PWRON_MODE = 1), then the PMIC enters the start-up sequence. See the PWRON Functions section on page 21 for more details. Thermal Recovery If the die temperature exceeds the thermal shutdown threshold, then the PMIC enters the shutdown state. Once the die temperature drops below the threshold, the PMIC enters the start- up sequence. EN1 If the EN1 function is enabled, and EN1 is pulled high (EN1_INV defines EN1’s active high) or EN1 is pulled low (EN1_INV defines EN1’s active low), then the power rails controlled by EN1 enter the start-up sequence. See the EN1 Functions section on page 22 for more details. Start-Up Sequence There are 16 selectable time slots for the start- up sequence. All of the DC/DC converters, LDOs, and load switch can be configured between 0 and 15 time slots by the MTP e -fuse. The delay time between each time slot can be adjusted via the MTP TIME_SLOT bits. The time does not change with the switching frequency (fSW). RSTO goes high with the RSTO_DELAY time once the start-up sequence is complete. The DC/DC converter, LDOs, and load switch start- up sequences are set by POWER_ON_SLOT_ NO and PWR_ON_TIME_SLOT_MODE . See the MTP E -Fuse Description on page 28 for more details.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 20 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Configurable MTP Follow the steps below to configure the MTP e- fuse via the I2C interface: 1. Before configuring the e-fuse, ensure that all of the buck converters and LDOs have no load. 2. Write the correct MTP program password to register 0x26. 3. Set ENTER_MTP_MODE to 1 to enter MTP configure mode. All buck s and LDOs are turned off in this mode. 4. Write the desired content to the I2C registers. 5. Set VIN1 and VAVIN between 6.4V and 6.5V , with a minimum 150mA current capability. 6. Set PROGRAM_MTP to 1 to start the MTP e-fuse program. 7. The PMIC calculates the sum of all the related I2C registers to be burned to the MTP register. The checksum result is also written to the MTP register. 8. After the MTP write operation is complete (typically 100ms), the PMIC sets the PROGRAM_MTP bit to 0, and the I 2C register write protection is unlocked. ENTER_MTP_MODE is also set to 0. 9. After MTP configuration, the PMIC reloads the MTP to the related I 2C registers and the PWRON pin function is re-enabled. Then the bucks, LDOs, and load switch then start -up based on their power -on factors. I 2C communication is enabled after the start -up sequence is complete. 10. Decrease V IN1 and V AVIN below 5.5V, then restart the power supply to resume normal operation. Before loading the MTP data into the I2C register during a start-up through VIN, the PMIC does a checksum calculation for all of the related MTP registers, and compares the checksum calculation to the checksum byte. If they match, then the MTP data is loaded into the I2C register. If they do not match, then the I 2C register uses the hard -coded default value. There is an I 2C register flag bit to indicate a checksum error. Shutdown Sequence If the VINx drops below its UVLO falling threshold or if thermal shutdown is triggered, then the PMIC enters the shutdown sequence. All of the DC/DC converters, LDO regulators, and load switch turn off at the same time. RSTO DC/DC1 DC/DCx LDOx LSWO ... Shutdown Event Detected Figure 7: Shutdown Sequence High-Efficiency Buck Converter Buck 1, buck 2, buck 3, and buck 4 are synchronous, step-down DC/DC converters that have built -in UVLO protection, soft start (SS) , compensation, and over -current protection (OCP) with hiccup mode. Constant-on-time (COT) control with fixed frequency provides fast transient response. The switching clock is phase-shifted from buck 1 to buck 4 during continuous conduction mode (CCM). All of the buck converters can support a 100% duty cycle. Power Supply and Under-Voltage Lockout (UVLO) Protection VIN1 is the power supply for buck 1. VIN2 is the power supply for buck 2 , LDO2 . VIN3 is the power supply for buck 3. VIN4 is the power supply for buck 4. VIN5 is the power supply for LDO 4 and LDO 5. LSWI is the power supply for load switch. AVIN is the power input to bias the internal logic blocks. VIN1, VIN2, VIN3, VIN4, VIN5, and AVIN have their own UVLO thresholds with hysteresis. Once VAVIN exceeds its UVLO rising threshold, the PWRON logic is enabled and ready to accept start-up and shutdown commands. Internal Soft Start (SS) SS is implemented to prevent the PMIC V OUT from overshooting during start -up. As the PMIC starts up, the internal circuitry of each power rail generates a soft -start voltage (V SS) that ramps up from 0V. The soft-start time (tSS) lasts until VSS

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 21 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. exceeds the reference voltage (VREF). Once VSS exceeds VREF, then V REF takes over as the reference. The four buck outputs’ t SS are adjustable via the MTP. For the LDO2 through LDO5 outputs, tSS is fixed internally at 50µs. For the load switch, the soft -start slew rate is consistent at 1.5mV/µs. Output Discharge In order to discharge the output capacitor (COUT) during the shutdown sequence, there is a passive discharge path from the DC/DC converter outputs, LDO outputs, and load switch output to ground. The discharge path turns on once the corresponding channel is disabled. The typical discharge resistance is Ω. The discharge function can be enabled or disabled through the I2C interface. Over-Voltage Protection (OVP) The MP5424 monitors the feedback voltage (VFB) to detect possible over-voltage (OV) conditions. If VFB exceeds 120% of the target voltage, then both the high-side MOSFET (HS-FET) and low- side MOSFET (LS -FET) turn off, and the discharge path is turned on. The part exits this regulation period once VFB drops below 110% of VREF. Over-Current Protection (OCP) If the peak induc tor current (IL_PEAK) reaches its set limit and the HS -FET is on, then OCP is triggered. The LS-FET turns on until the inductor current (IL) drops to the valley current limit (ILIMIT_VALLEY). Once I L reaches I LIMIT_VALLEY, then the HS-FET turns on. The part does not exit OCP unless IL_PEAK drops below its set limit. If the OCP lasts longer than 150µs , then the buck enters hiccup mode. System Control Signals PWRON Functions PWRON is an input pin to that generates a start- up or shutdown event. This pin ca n be configured to detect a level or a falling edge via the MTP. If the PWRON_MODE bit is set to 1, then the PWRON_DEBOUNCE_TIMER bit can set the PWRON pin’s debounce timer to filter mechanical switch short-press noise. If the PWRON_MODE bit is set to 0, then PWRON operates as an enable (EN) pin. Pull PWRON high to turn the PMIC on; pull PWRON low to turn it off. PWRON_MODE = 1 (Edge Trigger) Start-Up The start-up sequence begins once V AVIN exceeds its UVLO threshold and PWRON is pulled low for longer than PWRON_DEBOUNCE_TIMER while the PMIC is off. Once the start-up sequence is complete, then the PWRON detection function can be enabled. OUT2 OUT4 RSTO PWRON Debounce timer Stay in power on state when PWRON keeps low Figure 8: PWRON_MODE = 1 (Press PWRON to Start Up)

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 25 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. S Slave Address Wr A Register Address K Read Data KA A P Master to Slave Slave to Master A = Acknowledge (SDA = Low) S = Start Condition P = Stop ConditionNA = NOT Acknowledge (SDA = High) 8 bits 8 bits 8 bits Sr Slave Address RD NA 8 bits Wr (Write) = 0 Rd (Read) = 1 Register address to read specified Read register data from current register location Sr = Repeat Start Condition Figure 16: Read Single Register

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 26 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REGISTER DESCRIPTION MTP E-Fuse Configuration Table Offset Name D7 D6 D5 D4 D3 D2 D1 D0

00 CTL0 DVS SLEW RATE FREQUENCY N/A PWRON_DEBOUNCE_TIMER N/A

01 CTL1 RSTO_MODE RSTO_DELAY RSTO_PFI_THLD N/A

02 CTL2 N/A TIME_SLOT

PWR_ON_ TIME_SLOT_ MODE PWR_OFF_ TIME_SLOT_ MODE Buck 1

04 N/A OVPEN1 DISCHGEN1 MODE

05 ILIM1 PHASE_DELAY1 SOFTSTART1 N/A

06 POWER_OFF_SLOT_NO_B1 POWER_ON_SLOT_NO_B1

08 N/A OVPEN2 DISCHGEN2 MODE

09 ILIM2 PHASE_DELAY2 SOFTSTART2 N/A

0A POWER_OFF_SLOT_NO_B2 POWER_ON_SLOT_NO_B2 Buck 3 0C N/A OVPEN3 DISCHGEN3 MODE BUCK3 N/A 0D ILIM3 PHASE_DELAY3 SOFTSTART3 N/A 0E POWER_OFF_SLOT_NO_B3 POWER_ON_SLOT_NO_B3 Buck 4 BUCK4_VREF: 0.4V to 3.5875V/12.5mV step

10 N/A OVPEN4 DISCHGEN4 MODE

11 ILIM4 PHASE_DELAY4 SOFTSTART4 N/A

12 POWER_OFF_SLOT_NO_B4 POWER_ON_SLOT_NO_B4

13 CTL3 N/A EN1_

EN_OFF_ DELAY EN_OFF_ MODE BUCK3_VID BUCK2_VID BUCK1_VID LDO 2 LDO2_VREF: 0.65V to 3.5875V/12.5mV step

15 N/A N/A DISCHGEN_

LDO2 I2C_SLAVE_ADDRESS

16 POWER_OFF_SLOT_NO_LDO2 POWER_ON_SLOT_NO_LDO2

LOAD_ SW N/A

18 N/A N/A DISCHGEN_

19 POWER_OFF_SLOT_NO_LDSW POWER_ON_SLOT_NO_LDSW

LDO4_VREF: 0.65V to 3.5875V/12.5mV step 1B N/A ILIM_ LDO4 DISCHGEN_ LDO4 N/A N/A 1C POWER_OFF_SLOT_NO_LDO4 POWER_ON_SLOT_NO_LDO4 LDO 5 LDO5_VREF: 0.65V to 3.5875V/12.5mV step 1E N/A ILIM_ LDO5 DISCHGEN_ LDO5 N/A N/A 1F POWER_OFF_SLOT_NO_LDO5 POWER_ON_SLOT_NO_LDO5

20 Mode PARALL

EL_1 PARALL EL_2 PWRON _MODE EN_EN1_ PIN N/A N/A

21 EN1 EN1_INV EN1_POWER_RAILS_CONTROL

22 EN EN_

EN_ BUCK2 EN_BUCK3 EN_BUCK4 EN_LDO2 EN_LDSW EN_LDO4 EN_LDO5

23 ID1 MTP configure code ("0x00" for standard MP5424-0000, "0x01" for MP5424-0001)

24 ID2 MTP revision number (MTP revision number is stored here in case the user has to update the MTP)

25 CRC

Checksum of MTP registers 0x00 to 0x24. While writing the I2C register data to the MTP, the PMIC initiates a checksum of all the related I2C registers and writes the result in this byte. During start-up, the PMIC calculates and compares the MTP data with the 0x25 register’s content. If they match, the MTP data is loaded to the I2C register; otherwise, the I2C register ignores the MTP data and uses the default setting.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 27 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. MTP E-Fuse Description Name Bits Default Description DVS SLEW RATE D[7:6] 10 Voltage scaling slew rate for the buck 1, buck 2, buck 3, and buck 4 converters. The soft-start slew rate is set by the SOFTSTART bits. 00: Reserved 01: Reserved 10: 8mV/µs 11: 4mV/µs FREQUENCY D[5:4] 00 Switching frequency (fSW) setting bit. 00: 1.1MHz 01: 1.65MHz 10: 2.2MHz 11: 2.75MHz PWRON_DEBO UNCE_TIMER D[2:1] 01 Sets the PWRON pin’s debounce timer. It is valid only if PWRON_MODE is set to 1. See the PWRON_MODE = 1 (Edge Trigger) section on page 21 for more information. The debounce time is not related to default fSW. 00: 0.5ms 01: 10ms 10: 40ms 11: 160ms RSTO_MODE D[7:6] 00 Sets the RSTO behavior. 00: Does not monitor any power rails. If the PMIC enters the shutdown sequence or VIN1 drops below its under-voltage lockout (UVLO) threshold , then RSTO goes low . RSTO goes high once the RSTO delay (tRSTO) is complete 01: Monitors buck ’s power good ( PG). If buck ’s PG (PG4) is good after tRSTO, RSTO goes high . If buck 4 is turned off by the I2C, then PG4 is high. If PG4 goes low, then there is no tRSTO 10: Monitors VIN1 (see the RSTO_PFI_THLD register). RSTO goes high if VIN1 > VIN1 UVLO threshold. RSTO goes low if VIN1 < VIN1 UVLO threshold. RSTO goes high after tRSTO. RSTO goes low with no delay. If VIN1 > VIN1 UVLO threshold and PWRON is active, then RSTO monitors VIN1 while the PMIC is on 11: Monitors all enabled buck and LDO power rails . If the enabled bucks’ PG and LDOs’ PG are good, then RSTO goes high after tRSTO. If any PG goes low, RSTO goes low without a delay. RSTO_DELAY D[5:4] 01 Sets tRSTO before RSTO goes high. tRSTO is not related to the default fSW. 00: 100ms 01: 50ms 10: 10ms 11: 1ms RSTO_PFI_ THLD D[3:2] 10 Sets the VIN1 UVLO rising threshold when RSTO_MODE is set to 10. 00: 2.7V 01: 2.9V 10: 4V 11: 4.4V TIME_SLOT D[3:2] 00 Sets the start-up/shutdown sequence time slot interval s. The start -up/shutdown sequences share the same time slot value. The time slot value is not related to the default fSW. 00: 0.5ms 01: 2ms 10: 8ms 11: 16ms

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 28 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Name Bits Default Description PWR_ON_ TIME_SLOT_ MODE D[1] 0 Selects the start-up sequence time slot mode. 0: The time slot is a fixed number set by TIME_SLOT 1: The time slot increases linearly, as shown below:

• Time slot 0 to slot 3 has a TIME_SLOT x 1 interval
• Time slot 3 to slot 7 has a TIME_SLOT x 2 interval
• Time slot 7 to slot 11 has a TIME_SLOT x 4 interval
• Time slot 11 to slot 15 has a TIME_SLOT x 8 interval Time Slot Number 0.5ms 0.5ms 0.5ms 3 4 1ms 1ms 6 7 1ms1ms 2ms 2ms 2ms 2ms 4ms 4ms 4ms 2 11 12 13 14 15 VOUT TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 Example: 4ms In a standard application, the start-up sequence ends at the maximum time slot of enabled channels. For example, if time slot 7 is the maximum slot number of the enabled channels ( i.e. slot number s above 7 are not used) during the start -up sequence, then the counter only works until time slot 7. The start-up sequence is complete, and the higher time slots are not executed. PWR_OFF_ TIME_SLOT_ MODE D[0] 0 Selects the shutdown sequence time slot mode. 0: The time slot is a fixed number set by TIME_SLOT 1: The time slot increases linearly, as shown below:
• Time slot 0 to slot 3 has a TIME_SLOT x 1 interval
• Time slot 3 to slot 7 has a TIME_SLOT x 2 interval
• Time slot 7 to slot 11 has a TIME_SLOT x 4 interval
• Time slot 11 to slot 15 has a TIME_SLOT x 8 interval Time Slot Number 0.5ms0.5ms0.5ms1ms1ms1ms 1ms2ms 2ms 2ms 2ms4ms4ms4ms 21112131415 VOUT TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 Example: 1 034567 4ms If the EN_OFF_DELAY is disabled, then the shutdown sequence begins at the maximum time slot of the enabled channels. For example, if time slot 7 is the maximum slot number of the enabled channels (i.e. slot numbers above 7 are not used) during the shutdown sequence, then the counter only works from time slot 7 to time slot 0. The shutdown sequence is complete, and the higher time slots are not executed. If the EN_OFF_DELAY is enabled, then the shutdown sequence starts from the 60th time interval, and the power rail turns off once the time interval decreases to the power rail’s time slot. The shutdown delay of each power rail is determined by the TIME_SLOT, PWR_OFF_TIME_SLOT_MODE and the time slot number.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 29 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Name Bits Default Description BUCK1_VREF, BUCK2_VREF, BUCK3_VREF, BUCK4_VREF, LDO2_VREF, LDO4_VREF, LDO5_VREF D[7:0] 00110100, 00110011, 00110100, 01001100, 01110000, 11101000, 11101000 Sets the internal reference voltage (VREF). Buck outputs are between 400mV and 3587.5mV with 12.5mV per step. LDO outputs are from 650mV to 3587.5mV with 12.5mV per step. See Table 1 on page 32 for more details. 0000 0000: 400mV 0000 0001: 412.5mV ... 1111 1111: 3587.5mV If the Buck1_VID, Buck2_VID, and Buck3_VID bits are set to 1, then the buck 1, buck 2, and buck 3 VOUT range is between 400mV and 2.2V with a 7.4mV per step. OVPEN1, OVPEN2, OVPEN3, OVPEN4 D[6] 1 Enable bit for buck 1 , buck 2, buck 3, and buck 4 output over -voltage protection (OVP). 0: OVP disabled 1: OVP enabled DISCHGEN1, DISCHGEN2, DISCHGEN3, DISCHGEN4 D[5] 1 Enable bit for buck 1, buck 2, buck 3, and buck 4 output discharge function. 0: Discharge function disabled 1: Discharge function enabled MODEBUCK1, MODEBUCK2, MODEBUCK3, MODEBUCK4 D[4] 1 Selects auto-PFM/PWM mode or forced pulse-width modulation (FPWM) mode. 0: Auto-PFM/PWM mode 1: Forced PWM mode (FPWM) ILIM1, ILIM3 D[7:6] 10 Configures the high-side MOSFET (HS -FET) peak current limit (ILIMIT_PEAK) for buck 1 and buck 3. 00: 4.6A typical HS-FET ILIMIT_PEAK 01: 6.6A typical HS-FET ILIMIT_PEAK 10: 7.6A typical HS-FET ILIMIT_PEAK 11: 9.3A typical HS-FET ILIMIT_PEAK ILIM2, ILIM4 D[7:6] 01 Configures the HS-FET ILIMIT_PEAK for buck 2 and buck 4. 00: 2.7A typical HS-FET ILIMIT_PEAK 01: 3.9A typical HS-FET ILIMIT_PEAK 10: 5.1A typical HS-FET ILIMIT_PEAK 11: 6.1A typical HS-FET ILIMIT_PEAK PHASE_ DELAY1, PHASE_ DELAY2, PHASE_ DELAY3, PHASE_ DELAY4 D[5:4] 00, 01, 01, Sets the phase delay for buck 1, buck 2, buck 3, and buck 4. 00: 0° delay 01: 90° delay 10: 180° delay 11: 270° delay SOFTSTART1, SOFTSTART2, SOFTSTART3, SOFTSTART4 D[3:2] 01 Soft-start time (tSS) setting bit for buck 1, buck 2, buck 3, and buck 4. tSS is between 10% and 90% of the target VOUT. 00 :150μs 01: 300μs 10: 610μs 11: 920μs

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 30 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Name Bits Default Description POWER_OFF_ SLOT_NO_B1, POWER_OFF_ SLOT_NO_B2, POWER_OFF_ SLOT_NO_B3, POWER_OFF_ SLOT_NO_B4, POWER_OFF_ SLOT_NO_ LDO2, POWER_OFF_ SLOT_NO_ LDSW, POWER_OFF_ SLOT_NO_ LDO4, POWER_OFF_ SLOT_NO_ LDO5 D[7:4] 0011, 0010, 0011, 0001, 0000, 0100 1010 1011 This bit sets each power rail’s time slot number during the shutdown sequence. See the TIME_SLOT register on page 2 8 and the PWR_OFF_TIME_SLOT_MODE register on page 29 for more details. The delay times between neighboring slots a re not related to default fSW. 0000: Time slot 0 0001: Time slot 1 0010: Time slot 2 0011: Time slot 3 0100: Time slot 4 0101: Time slot 5 0110: Time slot 6 0111: Time slot 7 1000: Time slot 8 1001: Time slot 9 1010: Time slot 10 1011: Time slot 11 1100: Time slot 12 1101: Time slot 13 1110: Time slot 14 1111: Time slot 15 POWER_ON_ SLOT_NO_B1, POWER_ON_ SLOT_NO_B2, POWER_ON_ SLOT_NO_B3, POWER_ON_ SLOT_NO_B4, POWER_ON_ SLOT_NO_ LDO2, POWER_ON_ SLOT_NO_ LDSW, POWER_ON_ SLOT_NO_ LDO4, POWER_ON_ SLOT_NO_ LDO5 D[3:0] 0011, 0010, 0011, 0001, 0000, 0100101 1011 This bit sets each power rail’s time slot number during the start-up sequence (see the TIME_SLOT register on page 28 and the PWR_ON_TIME_SLOT_MODE register on page 29 for more details). The delay times between neighboring slots are not related to the default fSW. 0000: Time slot 0 0001: Time slot 1 0010: Time slot 2 0011: Time slot 3 0100: Time slot 4 0101: Time slot 5 0110: Time slot 6 0111: Time slot 7 1000: Time slot 8 1001: Time slot 9 1010: Time slot 10 1011: Time slot 11 1100: Time slot 12 1101: Time slot 13 1110: Time slot 14 1111: Time slot 15 DISCHGEN_ LDO2, DISCHGEN_ LDO4, DISCHGEN_ LDO5 D[5] 1 Enable bit for the LDO2, LDO4 and LDO5 output discharge function. 0: Discharge function disabled 1: Discharge function enabled BUCK1_VID, BUCK2_VID, BUCK3_VID D[2:0] 000 Sets the buck 1, buck 2, and buck 3 VOUT range and resolution. 0: VOUT is 400mV to 3.5875V with 12.5mV per step 1: VOUT range is 400mV to 2.2V with 7.4mV per step EN1_SELECT D[5] 0 Selects LSWO or LDO 2 as the EN1 pin. If the EN1 function is enabled, then the corresponding load switch or LDO 2 channel and its discharge function should be turned off. 0: Selects LSWO as EN1 pin 1: Selects LDO2 as EN1 pin

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 31 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Name Bits Default Description EN_OFF_ DELAY D[4] 0 Enables the shutdown delay. This bit is only active if EN_OFF_MODE = 0. 0: Shutdown delay disabled. The shutdown sequence begins at the largest time slot of the enabled channel 1: Enable shutdown delay. The shutdown sequence begins at the 60th time interval, the power rail turns off once the time interval decreases to the power rail’s time interval. The time interval of each power rail is determined by TIME_SLOT, PWR_OFF_TIME_SLOT_MODE, and the time slot number EN_OFF_ MODE D[3] 0 Sets the shutdown sequence behavior controlled by the PWRON pin. There is always a shutdown sequence while controlled by EN1. 0: Shutdown sequence 1: No shutdown sequence. All power rails turn off at the same time DISCHGEN_ LDSW D[5] 1 Enable bit for the load switch output discharge function. 0: Discharge function disabled 1: Discharge function enabled I2C_SLAVE_ ADDRESS D[4:0] 01001 Sets the A5 to A1 bit of the slave I2C address. See the I2C Bus Slave Address section on page 34 for more details. ILIM_LDO4, ILIM_LDO5 D[6] 0 Selects the LDO 4 and LDO 5 current limit (ILIMIT). 0: Lower ILIMIT supports 300mA IOUT 1: Higher ILIMIT supports 550mA IOUT PARALLEL_1 D[7] 0 Sets whether buck 1 and buck 3 operate in parallel. Use FB1 as the feedback pin. After the buck converters enter parallel mode, buck 3’s I 2C/MTP register is invalid. Parallel mode takes effect during a start-up through VIN. After start-up, the PMIC does not respond to changes on this bit. ILIMIT is doubled based on buck 1’s register setting. 0: Buck 1 and buck 3 do not operate in parallel 1: Buck 1 and buck 3 operate in parallel PARALLEL_2 D[6] 0 Sets whether buck 2 and buck 4 operate in parallel mode. Use FB2 as the feedback pin. After the buck converters enter parallel mode , buck ’s I 2C/MTP register is invalid. Parallel mode takes effect during a start-up through VIN. After start-up, the PMIC does not respond to changes on this bit. ILIMIT is doubled based on buck 2’s register setting. 0: Buck 2 and buck 4 do not operate in parallel 1: Buck 2 and buck 4 operate in parallel PWRON_ MODE D[5] 0 This bit defines the PWRON pin’s behavior (level trigger or falling-edge trigger). 0: Level trigger. This functions as an EN pin. If the PWRON pin’s VIN exceeds the rising threshold, then the PMIC begins the start-up sequence 1: Falling-edge trigger. If the PWRON pin detects a high to low transition and the PMIC is off, then the PMIC begins the start-up sequence after a delay. If the PMIC is on, then the PMIC begins the shutdown sequence after a delay. The delay time is set by PWRON_DEBOUNCE_TIMER EN_EN1_PIN D[4] 0 Enable bit of EN1 function. EN1_POWER_RAILS_CONTROL defines which power rails are controlled by the EN1 pin. EN1_INV defines EN1 active low or active high. EN_SELECT defines LSWO or LDO 2 as EN1. 0: EN1 function disabled 1: EN1 function enabled EN1_INV D[7] 1 Sets EN1 to active low or active high. 0: A low-level input to EN1 turns on the corresponding power rails 1: A high-level input to EN1 turns on the corresponding power rails

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 32 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Table 1: Output Reference Voltage Chart (BUCK1_VID = 0, Buck2_VID = 0, Buck3_VID = 0) D[7:0] VREF (mV) D[7:0] VREF (mV) D[7:0] VREF (mV) 00000000 400 01010110 1475 10101100 2550 00000001 412.5 01010111 1487.5 10101101 2562.5 00000010 425 01011000 1500 10101110 2575 00000011 437.5 01011001 1512.5 10101111 2587.5 00000100 450 01011010 1525 10110000 2600 00000101 462.5 01011011 1537.5 10110001 2612.5 00000110 475 01011100 1550 10110010 2625 00000111 487.5 01011101 1562.5 10110011 2637.5 00001000 500 01011110 1575 10110100 2650 00001001 512.5 01011111 1587.5 10110101 2662.5 00001010 525 01100000 1600 10110110 2675 00001011 537.5 01100001 1612.5 10110111 2687.5 00001100 550 01100010 1625 10111000 2700 00001101 562.5 01100011 1637.5 10111001 2712.5 00001110 575 01100100 1650 10111010 2725 00001111 587.5 01100101 1662.5 10111011 2737.5 00010000 600 01100110 1675 10111100 2750 00010001 612.5 01100111 1687.5 10111101 2762.5 00010010 625 01101000 1700 10111110 2775 00010011 637.5 01101001 1712.5 10111111 2787.5 00010100 650 01101010 1725 11000000 2800 00010101 662.5 01101011 1737.5 11000001 2812.5 00010110 675 01101100 1750 11000010 2825 00010111 687.5 01101101 1762.5 11000011 2837.5 Name Bits Default Description EN1_POWER_ RAILS_ CONTROL D[6:0] 0000111 This bit sets which power rails are controlled by EN1. Each bit controls 1 power rail from D[6] to D[0]. Buck 1 Buck 2 Buck 3 Buck 4 LDSW LDO 4 LDO 5 0: EN1 does not control the power rail’s start-up/shutdown sequence 1: EN1 controls this power rail’s start-up/shutdown sequence If the EN1 function is enabled, the corresponding load switch or LDO 2 channel and its discharge function should be turned off. Note that EN1 cannot control LDO 2. LDO 2 can only be controlled by PWRON EN_BUCK1, EN_BUCK2, EN_BUCK3, EN_BUCK4, EN_LDO2, EN_LDSW, EN_LDO4, EN_LDO5 D[7:0] 0xFF Enable control bit for each power rail. 0: Disabled 1: Enabled

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 33 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. D[7:0] VREF (mV) D[7:0] VREF (mV) D[7:0] VREF (mV) 00011000 700 01101110 1775 11000100 2850 00011001 712.5 01101111 1787.5 11000101 2862.5 00011010 725 01110000 1800 11000110 2875 00011011 737.5 01110001 1812.5 11000111 2887.5 00011100 750 01110010 1825 11001000 2900 00011101 762.5 01110011 1837.5 11001001 2912.5 00011110 775 01110100 1850 11001010 2925 00011111 787.5 01110101 1862.5 11001011 2937.5 00100000 800 01110110 1875 11001100 2950 00100001 812.5 01110111 1887.5 11001101 2962.5 00100010 825 01111000 1900 11001110 2975 00100011 837.5 01111001 1912.5 11001111 2987.5 00100100 850 01111010 1925 11010000 3000 00100101 862.5 01111011 1937.5 11010001 3012.5 00100110 875 01111100 1950 11010010 3025 00100111 887.5 01111101 1962.5 11010011 3037.5 00101000 900 01111110 1975 11010100 3050 00101001 912.5 01111111 1987.5 11010101 3062.5 00101010 925 10000000 2000 11010110 3075 00101011 937.5 10000001 2012.5 11010111 3087.5 00101100 950 10000010 2025 11011000 3100 00101101 962.5 10000011 2037.5 11011001 3112.5 00101110 975 10000100 2050 11011010 3125 00101111 987.5 10000101 2062.5 11011011 3137.5 00110000 1000 10000110 2075 11011100 3150 00110001 1012.5 10000111 2087.5 11011101 3162.5 00110010 1025 10001000 2100 11011110 3175 00110011 1037.5 10001001 2112.5 11011111 3187.5 00110100 1050 10001010 2125 11100000 3200 00110101 1062.5 10001011 2137.5 11100001 3212.5 00110110 1075 10001100 2150 11100010 3225 00110111 1087.5 10001101 2162.5 11100011 3237.5 00111000 1100 10001110 2175 11100100 3250 00111001 1112.5 10001111 2187.5 11100101 3262.5 00111010 1125 10010000 2200 11100110 3275 00111011 1137.5 10010001 2212.5 11100111 3287.5 00111100 1150 10010010 2225 11101000 3300 00111101 1162.5 10010011 2237.5 11101001 3312.5 00111110 1175 10010100 2250 11101010 3325

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 34 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. D[7:0] VREF (mV) D[7:0] VREF (mV) D[7:0] VREF (mV) 00111111 1187.5 10010101 2262.5 11101011 3337.5 01000000 1200 10010110 2275 11101100 3350 01000001 1212.5 10010111 2287.5 11101101 3362.5 01000010 1225 10011000 2300 11101110 3375 01000011 1237.5 10011001 2312.5 11101111 3387.5 01000100 1250 10011010 2325 11110000 3400 01000101 1262.5 10011011 2337.5 11110001 3412.5 01000110 1275 10011100 2350 11110010 3425 01000111 1287.5 10011101 2362.5 11110011 3437.5 01001000 1300 10011110 2375 11110100 3450 01001001 1312.5 10011111 2387.5 11110101 3462.5 01001010 1325 10100000 2400 11110110 3475 01001011 1337.5 10100001 2412.5 11110111 3487.5 01001100 1350 10100010 2425 11111000 3500 01001101 1362.5 10100011 2437.5 11111001 3512.5 01001110 1375 10100100 2450 11111010 3525 01001111 1387.5 10100101 2462.5 11111011 3537.5 01010000 1400 10100110 2475 11111100 3550 01010001 1412.5 10100111 2487.5 11111101 3562.5 01010010 1425 10101000 2500 11111110 3575 01010011 1437.5 10101001 2512.5 11111111 3587.5 01010100 1450 10101010 2525 01010101 1462.5 10101011 2537.5 I2C Bus Slave Address The slave address is a 7 -bit address followed by an 8th read or write (R/W) data direction bit. The A5 , A4, A3, A2, and A1 bits can be configured via the MTP e-fuse. A7 A6 A5 A4 A3 A2 A1 Setting Value 1 1 0 (15) 1 (15) 0 (15) 0 (15) 1 (15) Notes: 15) This bit is configurable via the MTP e-fuse. 16) The slave address is 0x69 (A[7:1] = 1101 001) by default.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 35 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. I2C REGISTER MAP Add (hex) NAME R/W D7 D6 D5 D4 D3 D2 D1 D0

00 CTL0 R/W DVS SLEW RATE FREQUENCY Reserved

(18) PWRON_DEBOUNCE_ TIMER Reserved

01 CTL1 R/W RSTO_MODE RSTO_DELAY RSTO_PFI_THLD Reserved

02 CTL2 R/W Reserved Reserved TIME_SLOT

PWR_ON_ TIME_SLOT _MODE PWR_OFF_ TIME_SLOT _MODE Buck 1

04 R/W Reserved OVPEN1 DISCHGEN1 MODEBUCK1 Reserved

05 R/W ILIM1 PHASE_DELAY1 SOFTSTART1 Reserved

06 R/W POWER_OFF_SLOT_NO_B1 POWER_ON_SLOT_NO_B1

08 R/W Reserved OVPEN2 DISCHGEN2 MODEBUCK2 RESERVED

09 R/W ILIM2 PHASE_DELAY2 SOFTSTART2 Reserved

0A R/W POWER_OFF_SLOT_NO_B2 POWER_ON_SLOT_NO_B2 Buck 3 0C R/W Reserved OVPEN3 DISCHGEN3 MODEBUCK3 Reserved 0D R/W ILIM3 PHASE_DELAY3 SOFTSTART3 Reserved 0E R/W POWER_OFF_SLOT_NO_B3 POWER_ON_SLOT_NO_B3 Buck 4 R/W BUCK4_VREF: 0.4V to 3.5875V/12.5mV step

10 R/W RESERVED OVPEN4 DISCHGEN4 MODEBUCK4 Reserved

11 R/W ILIM4 PHASE_DELAY4 SOFTSTART4 RESERVED

12 R/W POWER_OFF_SLOT_NO_B4 POWER_ON_SLOT_NO_B4

13 CTL3 R/W RESERVED EN1_SELECT EN_OFF_

EN_OFF_ MODE BUCK3_ VID BUCK2_ VID BUCK1_VID LDO 2 R/W LDO2_VREF: 0.65V to 3.5875V/12.5mV step

15 R/W Reserved Reserved DISCHGEN_

LDO2 I2C_SLAVE_ADDRESS

16 R/W POWER_OFF_SLOT_NO_LDO2 POWER_ON_SLOT_NO_LDO2

LOAD_ SW R/W Reserved

18 R/W Reserved Reserved DISCHGEN_

19 R/W POWER_OFF_SLOT_NO_LDSW POWER_ON_SLOT_NO_LDSW

R/W LDO4_VREF: 0.65V to 3.5875V/12.5mV step 1B R/W Reserved ILIM_LDO4 DISCHGEN_ LDO4 Reserved Reserved 1C R/W POWER_OFF_SLOT_NO_LDO4 POWER_ON_SLOT_NO_LDO4 LDO 5 R/W LDO5_VREF: 0.65V to 3.5875V/12.5mV step 1E R/W Reserved ILIM_LDO5 DISCHGEN_ LDO5 Reserved RESERVED 1F R/W POWER_OFF_SLOT_NO_LDO5 POWER_ON_SLOT_NO_LDO5

20 Parallel

Mode R/W PARALLEL_1 (17) PARALLEL_2 (17) PWRON_ MODE (17) EN_EN1_ PIN (17) RESERVED

21 Standby 1 R/W EN1_INV (17) EN1_POWER_RAILS_CONTROL(17)

22 EN R/W EN_BUCK1 EN_BUCK2 EN_BUCK3 EN_BUCK4 EN_LDO2 EN_

LDSW EN_LDO4 EN_LDO5 MTP_CTL R/W MTP configure code ("0x00" for standard MP5424-0000, "0x01" for MP5424-0001)

24 R/W MTP revision number (MTP revision number is stored here, in case the user must update the MTP)

25 R/W ENTER_MTP_

PROGRAM_ MTP (18) Reserved Reserved Reserved Reserved Reserved Reserved

26 W MTP Program Password

27 Status 1 R PGLDO4 Reserved "1" PGLDO2 Reserved "1" PGBUCK4 PG

28 Status 2 R OTWARNING OTEMPP Reserved CHECKSUM

FLAG Reserved Reserved Reserved Reserved

29 ID2 R VENDOR ID Reserved PGLDO5 CURRENT MTP PAGE

Notes: 17) The I2C bits do not control the real circuitry. Only the MTP bits control those functions. The MTP value only reloads the circuitry when the PWRON pin turns off, the MTP is configured, or AVIN > UVLO threshold. 18) Reserved bits must be written to 0. Register Description

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE MP5424 Rev. 0.81 MonolithicPower.com 36 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. Preliminary Specifications Subject to Change © 2021 MPS. All Rights Reserved. Most of the register bits share the same description as the MTP e-fuse configuration table on page 26. Table 2 shows the descriptions of the I2C register bits that are different from the MTP register bits. The I2C register's default values are determined by the MTP table. The I2C register can be reset to the hard -coded default values under two conditions: 1. There is a CRC error while loading the MTP. 2. The MTP page is set to 0. Thermal shutdown does not reset the I2C register. Table 2: I2C Register Descriptions Name Bits Default Description ENTER_MTP_ MODE D[7] 0 Set ENTER_MTP_MODE to 1 to enter pre -MTP configure mode. After MTP configuration is complete, ENTER_MTP_MODE resets automatically to 0. PROGRAM_ MTP D[6] 0 If PROGRAM_MTP is set 1, then the PMIC executes an MTP configure action . After MTP configuration is complete, PROGRAM_MTP resets automatically to 0. PGx D[X] 0 PG indicator for the buck converters and LDOs. If VOUT exceeds 90% of the VREF, then PGx = 1. If VOUT drops below 80% of VREF, then PGx = 0. During I 2C-controlled dynamic voltage scaling, the PG deglitch timer blanks the possible PG glitch. These PG bits change dynamically to indicate the power good of each buck’s and each LDO’s status. OTWARNING D[7] 0 Die temperature early warning bit. If OTWARNING is high, this indicates that the die temperature has exceeded 120°C. OTWARNING latches once it is triggered. Write 1 to OTWARNING to clear it. OTEMPP D[6] 0 Over-temperature (OT) indicator. If OTEMPP is high, this indicates that thermal shutdown has been triggered. OTEMPP latches once it is triggered. Write 1 to OTEMPP to clear it. VENDOR ID D[7:4] 1000 Vendor identification. CHECKSUM FLAG D[4] 0 1: The current MTP page has a CRC or checksum error 0: The current MTP data passes the CRC test CURRENT MTP PAGE INDEX D[1:0] 00 CURRENT MTP PAGE INDEX stores the current MTP page index information. The IC cannot access the MTP while D[1:0] = 10b. The MP54 24 MTP can only be configured two times. 00: Default page; two other pages can be used 01: First page 10: Second page 11: Reserved

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 37 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

APPLICATION INFORMATION

Optimized Performance with MPS Inductor MPL-AL6050 Series For most applications, use a 0.47µH to 2.2µH inductor with a DC current rating at least 25% greater than the maximum load current (ILOAD_MAX). For improved efficiency, use an inductor with a DC resistance below 15mΩ. For most designs, the inductance (L1) can be calculated with Equation (1): OUT IN OUT IN L OSC V (V V )L V I f Where ∆IL is the inductor ripple current. Choose the inductor ripple current to be approximately 30% of ILOAD_MAX. The maximum inductor peak current (IL(MAX)) can be estimated with Equation (2): III L LOAD)MAX(L += (2) Choose an inductor with a higher inductance to improve efficiency under light -load conditions (<100mA). MPS inductors are optimized and tested for use with our complete line of integrated circuits. Table 3 lists MPS’s power inductor recommendations for use with the MP5424. Select a part number based on your design requirements. Table 3: Power Inductor Selection Part Number Inductance Manufacturer Select family series (MPL-AL) 1µH to 1.5µH MPS MPL-AL6050-1R0 1μH MPS MPL-AL6050-1R5 1.5μH MPS Visit MonolithicPower.com under Products > Inductors for more information. Selecting the Step-Down Converter Input Capacitor (C1) The step -down converter has a discontinuous input current (IIN), and requires a capacitor to supply the AC current to the converter while maintaining the DC VIN. Use low-ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are recommended due to their low ESR and small temperature coefficients. For most applications, a 22µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in C1 (IC1) can be estimated with Equation (3):  −= IN OUT IN OUTLOAD1C V V1V VII (3) The worst-case condition occurs at VIN = 2 x VOUT, which can be estimated with Equation (4): II LOAD 1C = (4) For simplification, choose C1 to have an RMS current rating greater than half of ILOAD_MAX. C1 can be electrolytic, tantalum, or ceramic. If using electrolytic or tantalum capacitors, add a small, high -quality ceramic capacitor ( 0.1μF) placed as close to the IC as possible. If using ceramic capacitors, ensure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at the input. The input voltage ripple (∆VIN) caused by the capacitance can be calculated with Equation (5): LOAD OUT OUT IN INSW IN I V VV1 f C1 V V Selecting the Step-Down Converter Output Capacitor (C2) The output capacitor (C2) for the step -down converter maintains the DC VOUT. C2 can be ceramic, tantalum, or electrolytic. For the best results, use low -ESR capacitors to keep the output voltage ripple (∆VOUT) low. For most applications, two 22µF ceramic capacitors are sufficient . ∆VOUT can be estimated with Equation (6): OUT OUT OUT ESR SW 1 IN SW VV 1V 1 R f L V 8 f C2 Where RESR is the equivalent series resistance (ESR) value of C2.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 38 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. For ceramic capacitors, the capacitance dominates the impedance at fSW, and causes the majority of ∆VOUT. For simplification, ∆VOUT can be calculated with Equation (7): OUT OUT OUT 2 SW 1 IN VVΔV1 8 f L C2 V For tantalum or electrolytic capacitors, the ESR dominates the impedance at fSW. For simplification, ∆VOUT be estimated with Equation (8): OUT OUT OUT ESR INSW 1 VVΔV 1 R f L V The characteristics of C2 also affect the system stability. Table 4 lists the recommended components for MP5424. Table 4: Recommended External Components for DC/DC Converters and LDOs Component Value Notes VIN1 input capacitor (CIN) 22μF 0805 size/10V ceramic capacitor VIN2 CIN 22μF 0805 size/10V ceramic capacitor VIN3 CIN 22μF 0805 size/10V ceramic capacitor VIN4 CIN 22μF 0805 size/10V ceramic capacitor VIN5 CIN 10μF 0805 size/10V ceramic capacitor AVIN CIN 0.1μF 0603 size/10V ceramic capacitor Buck 1 output capacitor (COUT) 22μF x 2 0805 size/10V ceramic capacitor Buck 1 inductor 1μH ISAT > current limit Buck 2 COUT 22μF x 2 0805 size/10V ceramic capacitor Buck 2 inductor 1.5μH ISAT > current limit Buck 3 COUT 22μF x 2 0805 size/10V ceramic capacitor Buck 3 inductor 1μH ISAT > current limit Buck 4 COUT 22μF x 2 0805 size/10V ceramic capacitor Buck 4 inductor 1.5μH ISAT > current limit LSWI CIN 10μF 0603 size/6.3V ceramic capacitor LDO 2 COUT 2.2μF 0603 size/6.3V ceramic capacitor LSWO COUT 10μF 0603 size/6.3V ceramic capacitor LDO 4 COUT 2.2μF 0603 size/6.3V ceramic capacitor LDO 5 COUT 2.2μF 0603 size/6.3V ceramic capacitor RSTO pull-up resistor 100kΩ 0603 or 0402 size film resistor AVIN series resistor to VIN1 RSTO pull- up resistor 4.7Ω 0603 or 0402 size film resistor

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 39 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PCB Layout Guidelines (19) Efficient PCB layout is critical for stable operation. It is recommended to use a 4 -layer board for improved performance. For the best results, refer to Figure 17 and follow the guidelines below: 1. Connect the input ground to the GND x pin using short and wide traces. 2. Connect the input capacitor to the VIN x pin using short and wide traces. 3. Ensure FB1, FB2, FB3, and FB4 are Kelvin- connected to the buck 1, buck 2, buck 3, and buck 4 output capacitors. Do not connect FB directly to the inductor’s output node. 4. Route SW away from sensitive analog areas, such as FB1, FB2, FB3, and FB4. C14R1 Buck 1 Buck 3 Buck 2 Buck 4 VIN1 VIN2 VIN3 VIN4 VIN5 SW3 SW1 SW2 SW4 PGND PGND PGND PGND AGND 3VIN1 4SW1 5GND1 6SW3 VIN2 SW2 GND2 SW4 VIN4 26 25 AVIN AGND LSWO/ EN1 LSW1 SCL SDA OUT4 VIN5 2PWRON 2324 FB2 7 16 10 11 1312 Figure 17: Recommended PCB Layout (20) Notes: 19) The recommended PCB layout is based on Figure 18 on page 40. 20) It is recommended to separate buck 1’s PGND and buck 3’s PGND from buck 2’s PGND and buck ’s PGND on the top layer.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 40 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUITS MP5424 VIN1 GND1 PWRON SCL SW1 FB1 LSWI LSWO /EN1 OUT2 VIN1 = 2.7V to 5.5V VOUT1 = 1.05V 22µF 22µF x 2 1µH SW2 FB2 22µF x 2 1.5µH SW3 FB3 22µF x 2 SW4 FB4 22µF x 2 VIN2 GND2 22µF VIN3 22µF VIN4 22µF VOUT3.3V/ 10µF C10 VIN5OUT5 3.3V OUT4 3.3V RSTO AVIN 0.1µF AGND SDA VOUT2 = 1.0375V VOUT3 = 1.05V VOUT4 = 1.35V 1µH 1.5µH 100k 3.3V VIN5 = 5V . Ω 10µF C11 2.2µF C12 1.8V 25 2423 22 29 12 14 13 10µF C15 2.2µF C14 2.2µF C13 Figure 18: Typical Application Circuit (21) (22)

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 41 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUITS (continued) MP5424 VIN1 GND1 PWRON SCL SW1 FB1 LSWI LSWO /EN1 OUT2 VIN1 = 2.7V to 5.5V VOUT1 = 1.05V 22µF 22µF x 4 1µH SW2 FB2 22µF x 2 1.5µH SW3 SW4 FB4 22µF x 2 VIN2 GND2 22µF VIN3 22µF VIN4 22µF VOUT3.3V/ 10µF C10 10µF C15 VIN5 2.2µF C14 OUT5 3.3V 2.2µF C13 OUT4 3.3V RSTO AVIN 0.1µF AGND SDA VOUT2 = 1.0375V VOUT4 = 1.35V1.5µH 100k 3.3V VIN5: 5V . Ω 10µF C11 2.2µF C12 1.8V 25 2423 22 29 12 14 13 FB3 8 Figure 19: Typical Application Circuit (with Buck 1 and Buck 3 in Parallel) (21) (22) Notes: 21) VIN5’s minimum VIN is equal to the maximum nominal VOUT of LDO 4 and LDO 5. Connect the VIN5 and VIN1 pins if LDO 4 and LDO 5 are not used. 22) If operating at a 2.2MHz fSW and with a small duty cycle, ensure that the buck’s on time is >100ns for increased system stability.

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 42 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-26 (3.5mmx4.5mm) PACKAGE OUTLINE DRAWING FOR 26L FCQFN (3.5X4.5MM)-2 MF-PO-D-0426 revision 0.0 SIDE VIEW BOTTOM VIEW NOTE: 1) LAND PATTERNS OF PIN1,9,14,22 HAVE THE SAME LENGTH AND WIDTH. 2)ALL DIMENSIONS ARE IN MILLIMETERS. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID 0.15X45º TYP 0.15X45º

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 43 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package (3.5mmx4.5mm) 5000 N/A N/A 13in 12mm 8mm Pin1 1 1 1 1 ABCD ABCD ABCD ABCD Feed Direction

MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP5424 Rev. 1.0 MonolithicPower.com 44 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 12/06/2021 Initial Release -