EVKT-USBI2C-02-BAG

MP2696B MPSIND | Alldatasheet

Document overview

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Technical content

I2C-Controlled, Single-Cell Switching Charger with Power-Path Management, Boost Output, and 3.5A Input Current Limit MP2696B Rev. 1.0 MonolithicPower.com 1 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

DESCRIPTION

The MP 2696B is a highly integrated, flexible , switch-mode, battery-charging, power -path management device designed for a single-cell Li-ion and Li -polymer battery. This device can be used in a wide range of portable applications. The MP2696B integrates three battery-charging phases: pre -charge, constant current charge, and constant voltage charge . This device also manages the input power source through input current limit regulation and minimum input voltage regulation. The MP2696B can swi tch to boost mode to generate the system power output from the battery. The MP2696B has an integrated IN to SYS pass-through path to pass the input voltage to the system. Using an I2C interface, the host can flexibly configure the charg e and boost parameters. The device operating status can also be read in the registers. Safety features include SYS short-circuit protection (SCP), input over -voltage protection (OVP), battery under -voltage protection (UVP), thermal shutdown, and JEITA battery temperature monitoring. The MP2696B is available in a QFN-21 (3mmx3mm) package.

FEATURES

 4.0V to 11V Operating Voltage Range  Up to 16V Sustainable Input Voltage  500mA to 3.6A Configurable Charge Current  3.6V to 4.45V Configurable Charge Regulation Voltage with ±0.5% Accuracy  500mA to 3.5A Configurable Input Current Limit with ±10% Accuracy  Minimum Input Voltage Loop for Maximum Adapter Power Tracking  Ultra-Low 25μA Battery Discharge Current in Idle Mode  Boost Converter with Up to 4.0A of Output Current: o Configurable Output Current Limit Loop o Configurable Boost Output Voltage o USB Output Cable Compensation o Configurable Inductor Peak Current Limiting  Comprehensive Safety Features: o Fully Customizable JEITA Profile with Configurable Temperature Threshold o Charge Safety Timer o Input Over-Voltage Protection (OVP) o Thermal Shutdown o SYS Over-Current (OC) and Short- Circuit Protection (SCP)  Analog Voltage Output IB Pin for Battery Current Monitoring  SYS Plug-In Detection  SYS No Load Detection  SYS DP/DM Interface for BC1.2 and Non- Standard Adapters  Status and Fault Monitoring  Available in a QFN-21 (3mmx3mm) Package

APPLICATIONS

 Sub-Battery Applications  Power Bank Applications for Smartphones, Tablets, and Other Portable Devices All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are registered trademarks of Monolithic Power Systems, Inc. or its subsidiaries.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 2 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION IN SW BATT INT SYS CIN CVCC NTC PGND MP2696B SCL AGND CSYS CMID BST SDA PMID VCC DP DM USB1 USB2 VRNTC IB CBATT RS1 CSP SMID CBST RT1 RT2 HOST

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 3 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL Rating MP2696BGQ-0000** QFN-21 (3mmx3mm) See Below 1 EVKT-MP2696B Evaluation kit - * For Tape & Reel, add suffix -Z (e.g. MP2696BGQ-xxxx-Z). **“xxxx” is the register setting option. The factory default is “0000.” This content can be viewed in the I2C register map. Contact an MPS FAE to obtain an “xxxx” value. TOP MARKING BPF: Product code of MP2696BGQ Y: Year code LLLL: Lot number EVALUATION KIT EVKT-MP2696B EVKT-MP2696B kit contents (items below can be ordered separately): # Part Number Item Quantity

1 EV2696B-Q-00A MP2696B evaluation board 1

2 EVKT-USBI2C-02-BAG Includes one USB to I 2C communication interface , one USB

cable, and one ribbon cable 1

3 Online resources Include datasheet, user guide, product brief, and GUI 1

Order directly from MonolithicPower.com or our distributors. USB to I2C Communication Interface USB Cable Ribbon Cable Input Power Supply EV2696B-Q-00A Load Input Output GUI Figure 1: EVKT-MP2696B Evaluation Kit Set-Up

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 4 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW QFN-21 (3mmx3mm)

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 5 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name I/O Description 1 PGND Power Power ground. 2 SW Power Switching output node. Connect SW to the inductor. 3 PMID Power Drain of the high -side switching MOSFET. Bypass PMID with ceramic capacitors from PMID to PGND, placed as close to the IC as possible. 4 SMID Power Connected to the drain of Q1 and Q2. Short SMID to PMID on the PCB. 5, 6 SYS Power System power output. Place ceramic capacitors from SYS to PGND. 7, 8 IN Power Power input of the IC. Place ceramic capacitors from IN to PGND. 9 CSP I Battery current-sense positive input. 10 BATT I Battery positive terminal. 11 AGND Power Analog ground. Short to PGND on the PCB. 12 DP I/O Positive port of the USB data for the output. High ESD rating. 13 DM I/O Negative port of the USB data for the output. High ESD rating. 14 INT O Open-drain interrupt output. Connect INT to the logic rail through a 10kΩ resistor. 15 SCL I I2C interface clock. Connect SCL to the logic rail through a 10k Ω resistor. 16 SDA I/O I2C interface data. Connect SDA to the logic rail through a 10kΩ resistor.

17 IB O

Battery current indicator. The voltage at IB indicates the battery’s charge current in charge mode , and the battery’s discharge current in boost mode.

18 NTC I

Temperature-sense input . Connect NTC to a negative temperature coefficient thermistor. Configure the temperature window with a resistor divider from VRNTC to NTC to GND. Configurable JEITA thresholds are supported.

19 VCC Power

Internal circuit and switch driver power supply. Bypass VCC to AGND with a ceramic capacitor, placed as close to the IC as possible. For the external load capacity, see the VCC Power Supply section on page 15. 20 VRNTC Power Reference voltage output for powering up NTC. 21 BST Power Bootstrap. Connect a 470nF bootstrap capacitor between BST and SW to form a floating supply across the high-side power switch driver.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 6 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) +14V (16V for 20ns) ESD Ratings DP, DM pins: All other pins: Recommended Operating Conditions (3) Operating junction temp (TJ) .... -40°C to +125°C Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junct ion temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can cause excessive die temperature, and the regulator may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The devi ce is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 7 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 5.0V, VBATT = 3.5V, RS1 = 10mΩ, TA = 25°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Quiescent Current Battery discharge current in idle mode IBATT_IDLE Idle mode 25 36 μA Input quiescent current without switching IIN_Q VIN > VIN_UVLO, VIN > VBATT + VHDRM, charge disabled, float SYS 0.6 1 mA Input quiescent current when switching IIN_QSW VIN > VIN_UVLO, VIN > VBATT + VHDRM, charge enabled, float BATT and SYS 1 mA Battery discharge current in boost mode IBOOST_Q ISYS = 0, VBOOST, bits[2:0] = 5.15V, boost enabled, VBATT = 4.2V 2 mA Power On/Off IN operating range VIN_OP Converter switching 4 11 V Input under-voltage lockout VIN_UV VIN falling 2.95 3.10 3.25 V Input under-voltage lockout hysteresis VIN rising 305 mV Input vs. battery headroom VHDRM VIN rising 200 310 mV VIN falling 10 80 mV Battery under-voltage lockout VBATT_UV During boost 2.4 2.5 2.6 V Before boost starts 2.8 2.9 3.0 V VCC LDO output voltage VVCC VIN = 5V, IVCC = 30mA 3.3 3.55 3.8 V VCC under-voltage lockout VCC_UV VCC rising 1.9 2.1 2.3 V VCC under-voltage lockout hysteresis 80 mV Power Path IN to PMID MOSFET (Q1) on resistance RON_Q1 25 mΩ PMID to SYS MOSFET (Q2) on resistance RON_Q2 15 mΩ High-side MOSFET (Q3) on resistance RON_HS 15 mΩ Low-side MOSFET (Q4) on resistance RON_LS 14 mΩ Peak current limit for high- side MOSFET in buck mode IHS_PK Constant current charge mode 6.5 A Pre-charge mode 1.3 A Peak current limit for low- side MOSFET in boost mode ILS_PK BST_IPK, bits[1:0] = 6.5A 5.9 6.6 7.3 A BST_IPK, bits[1:0] = 5A 4.2 4.9 5.6 A Switching frequency fSW SW_FREQ = 700kHz 720 kHz SW_FREQ = 1200kHz 1200 kHz

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 8 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 5.0V, VBATT = 3.5V, RS1 = 10mΩ, TA = 25°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Charge Mode Charge voltage regulation VBATT_REG BATT_REG range (5) 3.6 4.45 V BATT_REG, bits[2:0] = 3.6V 3.582 3.6 3.618 V BATT_REG, bits[2:0] = 4.1V 4.080 4.1 4.120 V BATT_REG, bits[2:0] = 4.2V 4.179 4.2 4.221 V BATT_REG, bits[2:0] = 4.3V 4.279 4.3 4.321 V BATT_REG, bits[2:0] = 4.35V 4.328 4.35 4.372 V BATT_REG, bits[2:0] = 4.4V 4.378 4.40 4.422 V BATT_REG, bits[2:0] = 4.45V 4.428 4.45 4.472 V Fast charge current ICC ICC, bits[4:0] = 3A 2.7 3 3.4 A ICC, bits[4:0] = 1.5A 1.35 1.5 1.7 A ICC, bits[4:0] = 0.5A 0.41 0.5 0.62 A Charge termination current ITERM ITERM, bits[1:0] = 100mA 40 100 160 mA ITERM, bits[1:0] = 200mA 100 200 300 mA Recharge threshold below VBATT_REG VRECH VBATT falling 100 200 320 mV Pre-charge to fast charge threshold VBATT_PRE VBATT rising 2.9 3.0 3.1 V Pre-charge to fast charge hysteresis VBATT falling 290 mV Pre-charge current IPRE IPRE, bits[1:0] = 150mA, VBATT = 1.8V 150 mA IPRE, bits[1:0] = 350mA, VBATT = 1.8V 350 mA Safety timer for charging cycle 20 hours Input Regulation Input minimum voltage regulation VIN_MIN VINMIN, bits[2:0] = 4.5V 4.41 4.51 4.61 V VINMIN, bits[2:0] = 4.65V 4.56 4.66 4.76 V Input current limit IIN_LIM IINLIM, bits[2:0] = 3A 2.62 2.75 2.9 A IINLIM, bits[2:0] = 1.5A 1.3 1.38 1.5 A IINLIM, bits[2:0] = 0.5A 0.4 0.45 0.5 A Boost Mode Boost output voltage at PMID VPMID_BST VBOOST, bits[2:0] = 5.15V, ISYS = 10mA 5.05 5.13 5.21 V VBOOST, bits[2:0] = 5.225V, ISYS = 10mA 5.13 5.21 5.29 V Boost output current limit IBST_LMT IOLIM, bits[3:0] = 3A 3.0 3.16 3.37 A IOLIM, bits[3:0] = 2A 2 2.25 2.5 A IOLIM, bits[3:0] = 1A 1.05 1.25 1.45 A

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 9 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 5.0V, VBATT = 3.5V, RS1 = 10mΩ, TA = 25°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Analog Control SYS no load current threshold IBST_OFF NOLOAD_THR, bits[1:0] = 30mA 30 mA NOLOAD_THR, bits[1:0] = 50mA 50 mA NOLOAD_THR, bits[1:0] = 75mA 75 mA NOLOAD_THR, bits[1:0] = 100mA 100 mA SYS plug-in detection threshold VPLUG_IN SYS falling, percentage of VBATT 70 75 80 % Discharge dummy load at IN RIN_DUM 250 Ω Discharge dummy load at SYS RSYS_DUM 30 Ω Protection Battery over-voltage threshold VBATT_OVP 102 104 106 % BATT over-voltage hysteresis 1.5 % IN over-voltage protection VIN_OV VIN rising, VIN_OVP = 6V 5.8 6 6.2 V VIN rising, VIN_OVP = 11V 10.6 11 11.4 V IN over-voltage protection hysteresis VIN falling 300 mV Thermal Shutdown and Temperature Control Thermal shutdown rising threshold (5) TJ_SHDN TJ rising 150 °C Thermal shutdown hysteresis (5) 20 °C

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 10 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 5.0V, VBATT = 3.5V, RS1 = 10mΩ, TA = 25°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units VRNTC voltage VVRNTC VIN = 5V, IVRNTC = 100μA 3.5 V NTC low temp rising threshold VCOLD As a percentage of VVRNTC, VCOLD, bits[1:0] = 72% 72 73.1 74.3 % NTC low temp rising threshold hysteresis As a percentage of VVRNTC 1.6 % NTC cool temp rising threshold VCOOL As a percentage of VVRNTC, VCOOL, bits[1:0] = 60% 59.7 61 62.2 % NTC cool temp rising threshold hysteresis As a percentage of VVRNTC 1.6 % NTC warm temp falling threshold VWARM As a percentage of VVRNTC, VWARM, bits[1:0] = 40% 39.4 40.6 42 % NTC warm temp falling threshold hysteresis As a percentage of VVRNTC 1.6 % NTC hot temp falling threshold VHOT As a percentage of VVRNTC, NTC hot temp falling threshold hysteresis As percentage of VVRNTC 1.6 % SYS DP/DM Signaling DP/DM source voltage 2V7 VSRC_2V7 2.6 2.7 2.8 V DP/DM source resistance RSRC 23 30 37 kΩ DP/DM comparator threshold 2.9V VTH_2V9 2.75 2.9 3.1 V DP/DM comparator threshold 2.1V VTH_2V1 1.95 2.1 2.25 V Deglitch time for exiting non- standard adapter 8 10 12 ms DP/DM short resistance RSHORT 150 Ω Pull-down resistor on DP pin RPULL_DWN 300 kΩ Timer for DCP to enter non- standard adapter 2 s I2C Interface Input high threshold level SDA and SCL 1.3 V Input low threshold level SDA and SCL 0.4 V Output low threshold level ISINK = 5mA 0.3 V I2C clock frequency fSCL 400 kHz Battery Current Indicator IB voltage output ICC = 1A in charge mode 0.28 0.34 0.4 V IDSCHG = 1A in boost mode 0.135 0.155 0.175 V Note: 5) Guaranteed by design.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 11 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS IBATT_IDLE vs. Temperature VBATT = 5V VBATT_REG vs. Temperature VBATT_REG = 4.2V 100 -50 0 50 100 IBATT_IDLE (μA) TEMPERATURE (°C) 4.1 4.15 4.2 4.25 4.3 -50 0 50 100 VBATT_REG (V) TEMPERATURE (°C) ICC vs. Temperature ICC = 3A ITERM vs. Temperature ITERM = 100mA 2700 2850 3000 3150 3300 -50 0 50 100 ICC (mA) TEMPERATURE (°C) 100 120 140 160 -50 0 50 100 ITERM (mA) TEMPERATURE (°C) VBATT_UV vs. Temperature During boost VIN_MIN vs. Temperature VIN_MIN = 4.65V 2.4 2.43 2.46 2.49 2.52 2.55 2.58 -50 0 50 100 VBATT_UV (V) TEMPERATURE (°C) 4.5 4.55 4.6 4.65 4.7 4.75 -50 0 50 100 VIN_MIN (V) TEMPERATURE (°C)

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 12 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS L1 = 1μH/10mΩ, CBATT = 22µF, RS1 = 10mΩ, TA = 25°C, battery simulator load, unless otherwise noted. Constant Current Charge Mode Efficiency VIN = 5V, ICC = 2.5A Constant Voltage Charge Mode Efficiency VIN = 5V, VBATT = 4.2V 80% 84% 88% 92% 96% 100% 2.9 3.3 3.7 4.1 EFFICIENCY VBATT(V) 80% 84% 88% 92% 96% 100% 0 0.5 1 1.5 2 2.5 EFFICIENCY IBATT(A) Boost Mode Efficiency VBATT = 3.5V, VSYS = 5.15V Battery Charge Curve VIN = 5V 80% 84% 88% 92% 96% 100% 0 1 2 3 4 EFFICIENCY ILOAD (A) CH2: VIN 2V/div. CH1: VBATT 1V/div. CH4: IBATT 1A/div. CH3: VSW 5V/div. 4s/div. Pre-Charge Steady State VIN = 5V, VBATT = 1.5V, IPRE = 150mA Constant Current Charge Steady State VIN = 5V, VBATT = 3.5V, ICC = 2A CH1: VIN 2V/div. CH2: VBATT 2V/div. CH4: IL 1A/div. CH3: VSW 5V/div. 1μs/div. CH1: VIN 2V/div. CH2: VBATT 2V/div. CH4: IL 1A/div. CH3: VSW 5V/div. 1μs/div.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 13 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) L1 = 1μH/10mΩ, CBATT = 22µF, RS1 = 10mΩ, TA = 25°C, battery simulator load, unless otherwise noted. Constant Voltage Charge Steady State VIN = 5V, VBATT = 4.2V Start-Up in Constant Current Charge Mode VIN = 5V, VBATT = 3.5V, ICC = 3A CH1: VIN 2V/div. CH2: VBATT 2V/div. CH4: IL 1A/div. CH3: VSW 5V/div. CH2: VBATT 2V/div. CH1: VIN 2V/div. CH4: ICHG 2A/div. CH3: VSW 5V/div. 1μs/div. 2ms/div. Shutdown in Constant Current Charge Mode VIN = 5V, VBATT = 3.5V, ICC = 3A Boost Steady State VBATT = 4V, ISYS = 3.5A CH2: VBATT 2V/div. CH1: VIN 2V/div. CH4: ICHG 2A/div. CH3: VSW 5V/div. CH2: VSYS 2V/div. CH1: VBATT 1V/div. CH4: IL 2A/div. CH3: VSW 2V/div. 2ms/div. 1μs/div.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 14 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM SYS Control Logic and Mode Selection SW VCC Driver PWM Controller Mode Control NTC VRNTC PWM Signal QL BATT CSP Current Sense K1 x ICHG VBATT PGNDLDO PMID Charge Pump QH JEITA I2C Setting K3 x ISYS VIN_MIN K3 x VIN SDA SCL VIN Detect. DMDP BST Output Signaling IN IB GMI GMV GMINI IIN_LIM Thermal Protection VBATT_REG K1 x ICHG VBATT K2 x IIN GMINV IPRE / ICC Charge Pump K2 x IIN A3USB1 USB2 AGND INT SMID LDO Figure 2: Functional Block Diagram

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 15 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. OPERATION Introduction The MP 2696B is a n I2C-controlled switching charger with bidirectional operation that can step up the battery voltage to power the system. Depending on the input and output status , the device operates in one of three modes: charge mode, boost mode , or idle mode. In charge mode, the IC supports a precision Li -ion or Li - polymer charging system for single -cell applications. In boost mode, the IC boosts the battery voltage to a regulated voltage at SYS to power the load . In idle mode, the IC stops charging or boosting , and opera tes at a low current from the input or the battery . This reduces power consumption when the IC is not operating. VCC Power Supply VCC provides power for the internal bias circuit, as well as the low -side switch driver. VCC is powered from the higher voltage between the PMID and BATT pins. When the VCC voltage rises above the under-voltage lockout threshold (VVCC_UV), the I2C interface is ready for communication, and all the registers are reset to the ir default valu es. When the device is switching, VCC can provide up to 30mA for the external load. CHARGER MODE OPERATION Battery Charging Profile The IC can run a charging cycle autonomously without host involvement. The host can also control the charge operati ons and parameters via the registers. A new charge cycle can start w hen the following conditions are valid:  VIN is above VIN_UV  VIN is below VIN_OV  VIN is above VBATT + VHDRM  The NTC voltage is in the proper range (if the NTC_STOP bit is set to 1)  There is no charge timer fault  Charging is enabled (CHG_EN = 1)  There is no battery over-voltage condition After charging is done, unplug and re-insert VIN or toggle the CHG_EN bit to start a new charge cycle. Charge Cycle The IC checks the bat tery voltage to provide three main charging phases: pre -charge, constant current (CC) charge, and constant voltage (CV) charge. The IC regulates the voltage drop on the current-sense resistor (RS1) for the battery pre- charge and constant current charge current. Table 1 shows the default value f or a 10m Ω resistor. Table 1: Charge Current vs. Battery Voltage (RS1 = 10mΩ) Battery Voltage Charge Current Default Value CHG_STAT BATT < 3V IPRE, bits[1:0] 150mA 01 BATT > 3V ICC, bits[4:0] 1A 10 The charge current can be scaled by implementing different current-sense resistor values. The charge current for constant current charge and pre -charge can be calculated with Equation (1) and Equation (2), respectively: CC ICC[4 : 0]x10mI RS1 (1) PRE IPRE[1: 0]x10mI RS1 (2) Note that the soldering tin for the current -sense resistor has resistance, which must be compensated. During the entire charging process, the actual charge current may be less than the register setting due to other loop regulations , such as the input current limit or the input voltage limit. Charge Termination Charging terminate s if all of the following conditions are met:  The charge current is below the termination threshold for 20ms.  The IC works in a constant voltage charge loop.  The IC is not in the input current loop or input voltage loop.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 17 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Cold Cool Charge Voltage JEITA_VSET = 0 Warm Hot VBATT VBATT - 100mV VBATT - 200mV JEITA_VSET = 1 Figure 5: JEITA Profile (Charge Voltage) The hot and cold thresholds have two options in the register. The warm and cool thresholds have four options in the register, which offers accurate and flexible JEITA control. Interrupt to Host (INT) A 50μs interrupt pulse is generated on the open-drain INT pin w hen any of the events below occur:  A good input source is detected  A USB2 plug-in is detected  Status register 05h changes  Fault register 06h changes Battery Over-Voltage Protection (OVP) When the battery voltage exceeds 104% of VBATT_REG, the IC suspends charging immediately, and the BATT_OVP bit is set to 1. An 800μA current source discharges the battery until the battery voltage returns to the normal range. Battery o ver-voltage protection (OVP) can b e disabled by setting the BATT_OVP_DIS bit to 1. Input Over-Voltage Protection (OVP) Once IN senses a voltage greater than the VIN over-voltage protection ( OVP) threshold, the DC/DC converter stops immediately. The input OVP threshold can be set to 6V or 11V by the VIN_OVP bit. BOOST MODE OPERATION The IC can supply a regulated 5V output at SYS to power the system. To ensure that the battery is not drained, b oost mode does not start if BATT is below 2.9V. To enable boost mode, the IN voltage must be below 2.0V. The boost output current limit can be configured to be between 1.0A and 4.0A. Boost mode has an output current limit loop when VSYS > VBATT. Once boost mode is enabled, the IC boosts PMID to the preset voltage first, and then the block MOSFET (Q2) turns on linearly. When VSYS is charged above 4.2V within 3ms, Q2 turns on fully. Otherwise, Q2 turns off and tr ies to turn on again after 300ms. Boost Power Limitation During boost operation, the inductor peak current in each switching cycle is limited by the peak current limit of the low-side switch (QL), set b y BST_IPK, bits [1:0]. This helps limit the maximum battery discharge current. Battery Under-Voltage Lockout ( UVLO) Protection If the battery voltage drops below 2.5V in boost mode, boost mode stops, and the BATT_UVLO bit is set to 1 . Boost mode recovers when the battery voltage rises above 2.9V, but the BATT_UVLO bit is not reset until the input source plug-in and battery is charged again. SYS Over-Current (OC) and Short-Circuit Protection (SCP) In boost mode, t he MP 2696B always monitors the current flowing through Q2. When the SYS output current exceeds the preset boost output current limit , the output current loop take s control, and both the PMID and SYS voltages decrease. When VSYS drops to VBATT + 200mV, Q2 turns off. After 300ms, Q2 tries to restart. The IC also features fast SYS over-current protection (OCP) in both boost mode and pass- through mode. If the Q2 current exceeds 8A, Q2 turns off immediately. After 300ms, Q2 tries to restart. Impedance Compensation for Boost Output The IC allows the user to compensate the intrinsic resistance of Q2 and the USB2 output wire voltage drop by adjusting the boost output voltage according to the system load current , calculated with Equation (3): VPMID = VBOOST + (ISYS x RSYS_CMP) (3) Where VPMID is the voltage at PMID, and VBOOST is the boost regulation voltage set by VBOOST, bits[2:0]. I SYS is the real -time SYS load current during normal operation, and RSYS_CMP is the cable resistance compensation set by RSYS_CMP, bits[2:0]

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 18 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. USB2 Plug-In Detection If the USB2_EN_PLUG bit is enabled in standby mode, the SYS voltage (VSYS) is pulled up to the BATT voltage (V BATT). After VSYS reaches 90% of VBATT, detection starts. Once VSYS drops to 75% of VBATT, the USB2 plug-in is detected, the USB2_PLUG _IN bit is set to 1 , and an INT pulse is generated. The host can respond to the interrupt signal and enable boost mode Q2. The host must clear the USB2_PLUG_IN bit , and toggle the USB2_EN_PLUG bit for the next detection. Note that writing 1 to the USB2_PLUG_IN bit clears it to 0. No-Load Detection During boost or pass-through operation, the Q2 current is monitored. If the Q2 current is below the value set by NOLOAD_THR, bits [1:0], the NO_LOAD bit is set to 1 , and an INT pulse is generated. The host can monitor the NO_LOAD bit to decide whether boost mode or Q2 must be turned off. Thermal Shutdown The IC continuously monitors the internal junction temperature to maximize power delivery and avoid overheating the chip. If the junction temperature reaches 1 50°C, the converter shuts down. If the junction temperature drops to 120°C, normal operation resumes. Battery Current Analog Output The device has an IB pin to obtain the real-time battery current value in both charge and boost mode. The voltage at IB is a fraction of the battery current. The IB pin indicates the current flowing in and out of the battery during charge and boost mode. With a 10mΩ current-sense resistor. calculate the voltage at IB for charge mode and boost mode with Equation (4) and Equation (5), respectively: VIB = ICHG x 0.35(V) (4) VIB = IDSCHG x 0.16(V) (5) Note that scaling the current-sense resistor also scales the gain of IB. Idle Mode When the input power source is not present and boost mode is disabled, the IC goes into idle mode. In idle mode, all the MOSFETs and most of the internal circuits are turned off to minimize leakage and extend the battery run time. SYS DP/DM Signaling Initially, the DP and DM pins are biased at 2.7V with an internal resistance of 30kΩ for non - standard adapter imitation. If the DP or DM pin is out of the 2.1V to 2.9V range for 10ms in DCP mode , the 2.7V reference is disconnected , and DP and DM are tied together with a 100Ω resistor. If DP stays below 0.35V for 2 seconds in DCP mode, the IC returns to non -standard adapt er mode with DP/DM biased at 2.7V. Series Interface The IC use s an I2C-compatible in terface for flexible charging paramet er setting and instantaneous device status reporting. I 2C is a 2-wire serial interface with two bus lines required: a serial data line (SDA) and a serial clock line (SCL). Both SDA and SCL lines are open drain and must be connected to the positive supply voltage via a pull-up resistor. The IC operates as a slave device, receiving control inputs from the master device such as a microcontroller. The SCL line is always driven by the master device. The I2C interface supports both standard mode (up to 100 kb/s), and fast mode (up to 400kb/s). All transactions begin with a start (S) condition and are terminated by a stop (P) condition. The start and stop conditions are always generated by the master. A high to low transition on the SDA lin e while SC L is high defines a start condition. A low to high transition on the SDA line when the SCL is high defines a stop condition (see Figure 6). SDA SCL Start (S) Stop (P) Figure 6: Start and Stop Conditions

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 21 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. I2C REGISTER MAP IC Address: 6Bh Register Name Address R/W Description REG00h 0x00 R/W Input voltage regulation setting and input current limit setting. REG01h 0x01 R/W Charge current setting and pre-charge current setting. REG02h 0x02 R/W Battery regulation voltage and termination current setting. REG03h 0x03 R/W Boost output current limit setting and cable impedance compensation. REG04h 0x04 R/W Boost output voltage setting and boost control. REG05h 0x05 R Status register. REG06h 0x06 R Fault register. REG07h 0x07 R/W Boost no-load setting and miscellaneous control. REG08h 0x08 R/W JEITA control.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 22 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REG00h Bit Name POR Reset by REG_RST R/W Description Comment

7 REG_RST 0 Y R/W 0: Keep current settings

1: Reset This bit resets all registers to their default values. After a reset, this bit returns to 0 automatically.

6 EN_TIMER 1 Y R/W 0: Disabled

1: Enabled This bit enables the c harge safety timer control . This bit is set to 1 by default.

5 VINMIN[2] 1 Y R/W 200mV These bits regulate the

dynamic i nput voltage. They have a 4.45V offset, range between 4.45V and 4.8V, and are set to 200mV (4.65V) by default.

4 VINMIN[1] 0 Y R/W 100mV

3 VINMIN[0] 0 Y R/W 50mV

2 IINLIM[2] 0 Y R/W 000: 500mA

001: 1000mA 010: 1500mA 011: 1800mA 100: 2100mA 101: 2400mA 110: 3000mA 111: 3500mA These bits set the i nput current limit. They are set to 500mA by default.

1 IINLIM[1] 0 Y R/W

0 IINLIM[0] 0 Y R/W

REG_RST R/W Description Comment

7 ICC[4] 0 Y R/W 1600mA

These bits set the c harge current for a 10mΩ sensing resistor. They have a 500mA offset, ra nge between 500mA and 3.6A, and are set to 1A by default. A s caling sense resistor scales the sett value at the same ratio.

6 ICC[3] 0 Y R/W 800mA

5 ICC[2] 1 Y R/W 400mA

4 ICC[1] 0 Y R/W 200mA

3 ICC[0] 1 Y R/W 100mA

2 EN_NTC 1 Y R/W 0: Disabled

1: Enabled This bit is set to 1 by default.

1 IPRE[1] 0 Y R/W 01: 150mA

10: 250mA 11: 350mA These bits set the pre-charge current with a 10mΩ sensing resistor. These bits range between 150mA and 350mA, with a 150mA default. 0 IPRE[0] 1 Y R/W

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 23 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REG02h Bit Name POR Reset by REG_RST R/W Description Comment

7 BATT_OVP_

0: Enable battery over-voltage protection (OVP) 1: Disable battery OVP This bit is set to 0 by default. 6 BATT_REG[2] 0 Y R/W 000: 3.6V 001: 4.1V 010: 4.2V 011: 4.3V 100: 4.35V 101: 4.4V 110: 4.45V These bits set the regulated charge voltage. They are set to 010 by default.

5 BATT_REG[1] 1 Y R/W

4 BATT_REG[0] 0 Y R/W

3 JEITA_DIS 1 Y R/W

0: JEITA enabled, NTC warm / cool decrease ICC or VBATT_REG 1: JEITA disabled, NTC warm / cool only reports status and INT This bit is set to 1 by default.

2 ITERM[1] 0 Y R/W 200mA Charge termination current

for a 10mΩ sensing resistor. These bits have a 100mA offset, range between 100mA and 400mA, and are set to 100mA by default.

1 ITERM[0] 0 Y R/W 100mA

0 CHG_EN 1 Y R/W 0: Disable charge

1: Enable charge This bit is set to 1 by default. REG03h Bit Name POR Reset by REG_RST R/W Description Comment

7 IOLIM[3] 1 Y R/W 1600mA

output current limit . They have a 1A offset, range betwen 1A and 4A, an d are set to 3A by default.

6 IOLIM[2] 0 Y R/W 800mA

5 IOLIM[1] 1 Y R/W 400mA

4 IOLIM[0] 0 Y R/W 200mA

3 RSYS_CMP[2] 0 Y R/W 80mΩ These bits set the SYS

compensation threshold. They are set to 60mΩ by default.

2 RSYS_CMP[1] 1 Y R/W 40mΩ

1 RSYS_CMP[0] 1 Y R/W 20mΩ

0 NO_LOAD 0 Y R 0: Q2 load normal

1: Q2 no load

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 24 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REG04h Bit Name POR Reset by REG_RST R/W Description Comment

7 VBOOST[2] 0 Y R/W -100mV These bits set the b oost

regulation voltage at the PMID pin. They have a 5.2V offset, range between 5.05V and 5.225V, and are set to 5.15V by default.

6 VBOOST[1] 1 Y R/W -50mV

5 VBOOST[0] 0 Y R/W 25mV

4 BST_EN 0 Y R/W 0: Disable boost mode

1: Enable boost mode This bit is set to 0 by default. Boost mode can be enabled only when VIN < 2V.

3 Q2_EN 0 Y R/W 0: Q2 is off

1: Q2 is on This bit is set to 0 by default.

2 SYS_DSC 0 Y R/W 0: Disable SYS discharge

1: Enable SYS discharge This bit enables the SYS to GND discharge resistance (25Ω).

1 USB2_EN_

0: Disable USB2 plug-in detection 1: Enable USB2 plug-in detection Enables the USB2 plug-in detection circuit. Toggle this bit for new detection.

0 USB2_

PLUG_IN 0 Y R/W 0: USB2 is not plugged in 1: USB2 plug-in has been detected After VSYS is pulled up to 90% of VBATT, detection starts. Once VSYS drops to 75% VBATT, the USB2 plug-in signal is asserted. Write 1 to this bit to reset it to 0. This bit should be cleared manually after a read to enable the next detection. REG05h An interrupt is asserted if any bit in REG 05h changes. Bit Name POR Reset by REG_RST R/W Description Comment

7 CHIP_STAT[1] 0 Y R 00: Idle mode

01: Charge mode 10: Boost mode 11: Power path and charge

6 CHIP_STAT[0] 0 Y R

5 CHG_STAT[1] 0 Y R 00: Not charging

01: Pre-charge 10: Constant current or constant voltage charge 11: Charge done

4 CHG_STAT[0] 0 Y R

3 VPPM_STAT 0 Y R 0: No VINPPM

1: VINPPM

2 IPPM_STAT 0 Y R 0: No IINPPM

1: INPPM

1 USB1_PLUG_

IN 0 Y R 0: USB1 is not plugged in 1: USB1 is plugged in This bit is set to 1 when max (VIN_UV, VBATT+VHDRM ) < VIN < VIN_OV

0 RESERVED 0 Y R

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 25 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REG06h An interrupt is asserted if any bit in REG 06h changes. Bit Name POR Reset by REG_RST R/W Description Comment

7 BATT_UVLO 0 Y R

0: No battery under-voltage lockout (UVLO) has occurred 1: Battery UVLO has occurred If the battery reaches the under-voltage lockout (UVLO) threshold, this bit is set to 1. This bit is reset to 0 once the battery is charged again.

6 SYS_SHORT 0 Y R

0: Normal 1: A SYS short circuit has occurred

5 BST_LMT 0 Y R

0: Normal 1: Boost mode works in the Q2 current limit

4 CHG_FAULT[1] 0 Y R 00: Normal operation

01: A USB1 under-voltage (UV) condition has occurred 10: A USB1 over-voltage (OV) condition has occurred 11: The safety timer has expired

3 CHG_FAULT[0] 0 Y R

2 NTC_FAULT[2] 0 Y R 000: Normal

001: Warm 010: Cool 011: Cold 100: Hot

1 NTC_FAULT[1] 0 Y R

0 NTC_FAULT[0] 0 Y R

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 26 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REG07h Bit Name POR Reset by REG_RST R/W Description Comment

7 NOLOAD_

THR[1] 0 Y R/W 00: 30mA 01: 50mA 10: 75mA 11: 100mA These bits set the SYS no load current threshold. This bit is set to 00 by default. 6 NOLOAD_ THR[0] 0 Y R/W

5 BATT_OVP 0 Y R

0: The battery is operating normally 1: Battery over-voltage protection (OVP) has occurred

4 NTC_STOP 1 Y R/W

0: Only report in the register if NTC is outside its threshold 1: Suspend the charge and boost operation if NTC is outside its threshold

3 VIN_OVP 0 Y R/W 0: 6V

1: 11V This bit sets the VIN over- voltage protection (OVP) threshold.

2 SW_FREQ 0 Y R/W 0: 700kHz

1: 1200kHz This bit is set to 0 by default.

1 BST_IPK[1] 1 Y R/W 00: 5A

01: 5.5A 10: 6A 11: 6.5A These bits set the l ow-side switch peak current limit in boost mode . These bits are set to 11 by default. 0 BST_IPK[0] 1 Y R/W REG08h Bit Name POR Reset by REG_RST R/W Description Comment

7 JEITA_VSET 1 Y R/W 0: VBATT_REG - 100mV

1: VBATT_REG - 200mV This bit is set to 1 by default. 6 JEITA_ISET 1 Y R/W 0: 14.3% of ICC 1: 50% of ICC This bit is set to 1 by default.

5 VHOT 1 Y R/W 0: 34%

1: 36% This bit sets the hot threshold. This bit is set to 1 by default.

4 VWARM[1] 0 Y R/W 00: 44%

01: 40% 10: 38% 11: 36% These bits sets the warm threshold. These bits are set to 01 by default. 3 VWARM[0] 1 Y R/W

2 VCOOL[1] 1 Y R/W 00: 72%

01: 68% 10: 64% 11: 60% These bit sets the c ool threshold. These bit are set to 11 by default. 1 VCOOL[0] 1 Y R/W

0 VCOLD 0 Y R/W 0: 72%

1: 68% This bit sets the cold threshold. This bit is set to 0 by default.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 27 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REG0Ah (6) Bit Name POR Reset by REG_RST R/W Description Comment

7 TMR 0 N/A N/A 0: The charge timer is 20hrs

1: The charge timer is 10hrs This bit is set to 0 by default. 6 RESERVED N/A N/A N/A Reserved. 5 RESERVED N/A N/A N/A Reserved. 4 RESERVED N/A N/A N/A Reserved.

3 VPRE 0 N/A N/A

0: The pre-charge threshold is 1: The pre-charge threshold is 2.5V This bit is set to 0 by default. 2 RESERVED N/A N/A N/A Reserved. 1 RESERVED N/A N/A N/A Reserved. 0 RESERVED N/A N/A N/A Reserved. Note: 6) Register 0Ah is for the one-time programmable (OTP) only. It is not accessible to users.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 28 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. OTP MAP # Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] 0x02 N/A BATT_REG: 3.6V to 4.45V N/A N/A N/A N/A 0x07 NOLOAD_THR N/A NTC_STOP VIN_OVP N/A N/A N/A 0x0A TMR N/A N/A N/A VPRE N/A N/A N/A OTP DEFAULT OTP Items Default BATT_REG, bits[2:0] 4.2V NOLOAD_THR, bits[1:0] 30mA NTC_STOP 1: Suspend the charge and boost operation if NTC is outside its threshold VIN_OVP 0: VIN_OVP = 6V TMR 0: The charge timer is 20hrs VPRE 0: The pre-charge threshold is 3V

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 30 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Compensate the Current-Sense Resistor The soldering tin has resistance. For a 10m Ω resistor soldered on the PCB, t he total resistance between the resistor pads is between 11mΩ and 12mΩ. One method to compensate for this resistance consists of applying a resistor divider to the CSP/BATT pins (see Figure 15). SW BATT MP2696B CBATT RS1 CSP 10Ω Figure 15: Current-Sense Compensation After the PCB is assembled, apply a 2A DC current source between SW and BATT . Measure the voltage drop across the current- sense resistor on its PCB pad s (VCS). Calculate R1 with Equation (12): CSV 2 RS1R1 10 2 RS1 (12) PCB Layout Guidelines Efficient PCB layout is critical to meet specified noise, efficiency, and stability requirements. For the best results, follow the guidelines below: 1. Place the PMID capacitor as close as possible to the PMID and PGND pins using a short copper plane connection . Place the PMID capacitor on the same layer as the IC. 2. Minimize the high -frequency current path loop between the PMID capacitor and the switching pow er MOSFETs (PMID pin to capacitor, capacitor to PGND pin). 3. Connect the IC’s power pin to as many copper planes as possible to conduct heat away from the IC. 4. Place decoupling capacitors (e.g. the VCC pin capacitor) as close as possible to the IC pins, and make the connection as short as possible. 5. Ensure the number and physical size of the vias is sufficient for a current path.

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 31 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUIT IN SW BATT INT SYS CIN CVCC NTC PGND MP2696B SCL AGND CSYS CMID BST SDA PMID VCC DP DM USB1 USB2 VRNTC IB CBATT RS1 CSP SMID CBST RT1 RT2 HOST Figure 16: Typical Application Circuit for Power Bank Table 3: Key BOM from Figure 16 Qty Ref Value Description Package Manufacturer

1 CIN 1μF Ceramic capacitor, 16V, X5R or X7R 0603 Any

1 CMID 10μF Ceramic capacitor, 16V, X5R or X7R 0805 Any

2 CSYS 10μF Ceramic capacitor, 16V, X5R or X7R 0805 Any

1 CBATT 22μF Ceramic capacitor, 10V, X5R or X7R 0805 Any

1 CVCC 2.2μF Ceramic capacitor, 6.3V, X5R or X7R 0603 Any

1 CBST 470nF Ceramic capacitor, 16V, X5R or X7R 0603 Any

1 L1 1μH Inductor, 1μH, low DCR SMD Any

1 RS1 10mΩ Film resistor, 1% 1206 Any

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 www.MonolithicPower.com 32 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-21 (3mmx3mm)

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT MP2696B Rev. 1.0 MonolithicPower.com 33 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CARRIER INFORMATION Pin1 1 1 1 1 ABCD ABCD ABCD ABCD Feed Direction Part Number Package Description Quantity/Reel Quantity/ Tray Quantity/ Tube Reel Diameter Carrier Tape Width Carrier Tape Pitch MP2696BGQ- 0000** QFN-21 (3mmx3mm) 5000 N/A N/A 13in 12mm 8mm

MP2696B – SW CHARGER WITH I2C CONTROL, BOOST OUTPUT Notice: The information in this document is subject to change wi thout notice. Please contact MPS for current specifications. Users should warrant and guarantee that third -party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2696B Rev. 1.0 MonolithicPower.com 34 4/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 4/16/2021 Initial Release -