EVKT-USBI2C-02-BAG

MPQ4210_V01 MPS | Alldatasheet

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Technical content

MPQ4210 40V, 100W Synchronous Buck-Boost Controller with I2C and Current Monitor, AEC-Q100 Qualified MPQ4210 Rev. 1.1 www.MonolithicPower.com 1 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

DESCRIPTION

The MPQ4210 is a synchronous, four-switch, buck-boost controller capable of regulating different output voltages with a wide input voltage range and high efficiency. It provides an I2C interface, which supports V OUT voltage programmability, V OUT slew-rate control, and output constant current limit programmability, making the MPQ4210 suitable for USB power delivery (PD) design in USB Type-C power supplies. The MPQ4210 uses valley current control in buck mode and peak current control in boost mode, providing fast load transient response and smooth buck-boost mode transient. The MPQ4210 provides forced continuous conduction mode (FCCM) and a programmable average current limit, which supports flexible designs for different applications. It also features progr ammable over-current protection (OCP) mode, programmable over- voltage protection (OVP) mode, and programmable V IN UVLO hysteresis. The MPQ4210 is available in a QFN-27 (5mmx5mm) package.

FEATURES

 6V to 40V Start-Up Input Voltage Range  5V to 40V Operation Input Voltage Range  Flexible I 2C Interface Control for: o 0.5V to 28V Output Voltage Range o 0.3V to 2.047V Reference Voltage Range with 1mV Step o Selectable V OUT Slew Rate o Programmable Constant Current Limit  Output Current Monitor Function (IMON)  Programmable Soft-Start Time  Switching Frequency Spread Spectrum for EMI Optimization  Integrated V OUT Discharge Function  Selectable 200kHz, 300kHz, 400kHz, and 600kHz Switching Frequency  Forced CCM Operation Mode  Programmable V IN UVLO Hysteresis  OCP, SCP, and OVP  Interrupt Indicator for OCP, OVP, and PNG  Available in a QFN-27 (5mmx5mm) Package with Wettable Flank  AEC-Q100 Qualified

APPLICATIONS

 USB Power Delivery  Industrial PC Power Supplies  Super-Capacitor Charging All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are registered trademarks o f Monolithic Power Systems, Inc. or its subsidiaries.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 2 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL APPLICATION HG1 LG1 SW1 BST1 CSP CSN LG2 HG2 SW2 BST2 VIN VOUT IAVGP IAVGN VOUT 5V/9V/ 15V/20V VIN AVDD VCC AGND PGND COMP FB VOUT SWA SWB SWD SWC INT EN IMON SCL SDA ADDR SS C2A C2B C10 C3C12 R16 MPQ4210

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 3 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number Package Top Marking MPQ4210GU-AEC1* QFN-27 (5mmx5mm) See Below * For Tape & Reel, add suffix –Z (e.g. MPQ4210GU–AEC1-Z). TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP4210: Part number LLLLLLL: Lot number EVALUATION KIT EVKT-MPQ4210 EVKT-MPQ4210 Kit contents: (Items below can be ordered separately). # Part Number Item Quantity

1 EVQ4210-U-00B MPQ4210GU Evaluation Board 1

2 EVKT-USBI2C-02-

Includes USB to I2C Communication interface device, USB Cable, and Ribbon Cable 1 Order direct from MonolithicPower.com or our distributors. Figure A-1: EVKT-MPQ4210 Evaluation Kit Set-Up

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 4 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW QFN-27 (5mmx5mm) PIN FUNCTIONS Pin # Name Description 1 ADDR I2C slave address set pin. 2 SDA I2C data signal. 3 SCL I2C clock signal.

4 INT

Interrupt for PNG, OCP, OTP and OVP events. In default set-up, INT is masked off for response to a PNG event. It is an open-drain output, and is pulled low when an interrupt event occurs, recovering to open drain when the fault is cleared. INT is an open drain when the IC is not enabled. 5 IMON Current monitor output. Represents the signal between IAVGP and IAVGN. 6 CSP Positive input of the switching current-sense signal. Connect to the high side of the current-sense resistor. 7 CSN Negative input of the switching current-sense signal. Connect to the low side of the current-sense resistor. 8 AVDD 5V internal control circuit bias supply. Decouple with a ≥2.2μF capacitor. 9 AGND Analog ground. 10 COMP Internal error amplifier output pin. Connect a capacitor and resistor in series to AGND for loop compensation. 11 FB VOUT voltage feedback pin. Connect a resistor divider from VOUT to FB. 12 SS Soft-start set pin. Sets the hiccup off-time period. Connect an external capacitor to SS.

13 IAVGN

Negative terminal of average current limit sense input. The IAVGN and IAVGP pins can only be used for the output current limit setting by connecting to the positive terminal of the output rail.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 5 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PIN FUNCTIONS (continued) Pin # Name Description

14 IAVGP

Positive terminal of average current limit sense input. The IAVGN and IAVGP pins can only be used for the output current limit setting by connecting to the positive terminal of the output rail. 15 VOUT Voltage sense input. Supplies power to VCC based on VCC power logic. Connect to the output capacitor. 16 SW2 Boost switch node of the converter. Connect to the source of SWD and the drain of SWC. 17 HG2 Boost high-side MOSFET gate driver pin. Connect directly to the gate of SWD. 18 BST2 Bootstrap power pin for boost high-side MOSFET gate driver. Connect one capacitor between BST2 and SW2. BST2 is supplied by VCC or BST1. 19 LG2 Boost high-side MOSFET gate driver pin. Connect directly to the gate of SWC. 20 PGND Power ground. Gate-driving current return pin. 21 VCC Driver circuit and internal bias suppl y. Powered by VIN or VOUT. Decouple with a ≥2.2μF ceramic capacitor as close to this pin as possible. 22 LG1 Buck low-side MOSFET gate driver pin. Connect directly to the gate of the SWB. 23 BST1 Bootstrap power pin for buck high-side MOSFET gate driver. Supplied by VCC or BST2. Connect one capacitor between BST1 and SW1. 24 HG1 Buck high-side MOSFET gate driver pin. Connect directly to the gate of SWA. 25 SW1 Buck switch node of the converter. Connect to the source of SWA and the drain of SWB. 26 VIN VIN power supply and voltage sense input. 27 EN Chip enable control pin. If not used, connect EN to the input source for automatic start- up. EN can also program VIN UVLO. Do not float this pin. Exposed Pad Connect to ground.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 6 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) SW1 + 8.5V Recommended Operating Conditions (3) Thermal Resistance θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - T A) / θJA. Exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Operation voltage after V OUT is regulated to 5V or highe r voltage, and the VCC load is smaller than 10mA. 5) Measured on EVQ4210-U-00B, 6-layer PCB, 2oz-1oz-1oz- 1oz-1oz-2oz. 6) The value of θJA given in this table is only valid for comparison with other packages, and cannot be used for design purposes. These values were calculated in accordance with JESD51-7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 7 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 12V, VOUT = 12V, VEN = 2V, TJ = -40°C to 125°C, typical values are tested at T J = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Power Supply Operating VCC voltage VCC VIN = 6V or VOUT = 6V, 0mA to 20mA on VCC 5.1 5.95 6 V VIN = 12V or VOUT = 12V, 0mA to 60mA on VCC 6.7 7.2 7.7 V VIN UVLO (7) VIN UVLO-R VIN rising 5 5.5 5.9 V VCC UVLO (7) VCC UVLO-R VCC falling 3.8 4.3 4.8 V VCC power source change threshold VINTH_VCC VOUT = 12V, ramp VIN from 5V to 10V 8.1 8.8 9.5 V VOUTTH_VC C VIN = 12V, ramp VOUT from 5V to 10V 8.1 8.8 9.5 V AVDD voltage V AVDD V IN = 12V, 0mA to 5mA 4.7 5.2 5.6 V Shutdown current I SD VEN = 0V, measured on VIN and VOUT pins 2 μA ENPWR bit = 0, VIN = 12V, VO = 0V, measured on VIN pin, V EN = 2V 300 450 600 μA Enable Control (EN Pin) EN turn-on threshold voltage V EN-ON V EN rising (switching) 1.25 1.35 1.45 V EN high threshold voltage V EN-H V EN rising (micro-power) 1.1 V EN low threshold voltage V EN-L V EN falling (micro-power) 0.4 V EN turn-on hysteresis current I EN-HYS EN > VEN-ON, EN source current 3.2 4.7 6.2 μA EN input current I EN V EN = 0V, 3.3V 0.01 μA ENPWR turn-on delay (8) T ENPWR_Delay From ENPWR = 1 to switching, CSS = 47nF 1 ms Feedback Control Reference voltage V REF VREF bits = 7FFH, TJ = 25°C -1% 2.047 1% V VREF bits = 7FFH, TJ = -40°C to 125°C -2% 2.047 2% V VREF bits = 1F4H, VREF bits = 1F4H, TJ = -40°C to 125°C -3% 0.5 3% V FB input current I FB V FB = 0.52V 200 nA Error amp transconductance G EA VFB = VREF + 10mV, VCOMP = 2.5V 1220 μA/V Comp to current sense gain (8) Gcs ∆VCS / ∆VCOMP 200 mV/V SS charge current I CHG_SS During soft start and overload recovery 2 6 10 μA SS discharge current I DSG_SS After hiccup protection is triggered 1 μA

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 8 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VOUT = 12V, VEN = 2V, TJ = -40°C to 125°C, typical values are tested at T J = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units VREF change slew-rate T REF SR = 00 25 38 51 mV/ms SR = 11 130 150 170 mV/ms Current Limit Buck valley current limit I LIMIT_BUCK 113 133 153 mV Boost peak current limit I LIMIT_BOOST 130 150 170 mV OCP hiccup threshold (8) V TH_OCP 60% V REF Average constant current limit I AV_LIMIT ILIM bits = 011, IAVGN = 12V, ramp IAVGP voltage up 39 45 51 mV ILIM bits = 111, IAVGN = 12V, ramp IAVGP voltage up 60 68 76 mV CSP and CSN bias current I CS_BIAS V CSP = VCSN = 0V 70 μA IAVGP and IAVGN bias current I AV_BIAS IAVGN = 5V IAVGN = 20V IAVGP - IAVGN = 40mV 55 μA Switching Frequency Switching frequency f SW fSW bits = 10, VOUT = 5V 300 400 500 kHz fSW bits = 00 VOUT = 5V 140 200 260 kHz Frequency spread span (8) f SS Dither bit = 1 ±6% f SW Frequency spread spectrum modulation frequency (8) fMODULATION Dither bit = 1 2 kHz Gate Driver Gate source current capability (8) IHG_SO VCC = 7.2V, 4.7nF load 0.7 A ILG_SO 0.85 A Gate sink current capability (8) IHG_SI VCC = 7.2V, 4.7nF load 1.6 A ILG_SI 2 A Low-side gate output high voltage VLS_HIGH VCC- 0.05 V Low-side gate output low voltage VLS_LOW 0.05 V High-side gate output high voltage VHS_HIGH VBST-SW- 0.05 V High-side gate output low voltage VHS_LOW 0.05 V Dead-time between high-side gate and low-side gate (8) TDEAD 30 ns OVP Protection FB feedback OVP trigger threshold VOVP_RISING 119% 127% 135% V REF FB feedback OVP recover threshold VOVP_FALLING 104% 111% 118% V REF Thermal Protection Thermal shutdown (8) T SD 150 C Thermal shutdown hysteresis (8) T SD-HYS 25 C

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 9 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VOUT = 12V, VEN = 2V, TJ = -40°C to 125°C, typical values are tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Power Good (INT Pin) Power good upper trip threshold PGH_FALLIN G PNG bit sets to 1, and INT pin pulls low 110% 117% 124% V REF PGH_RISING PNG bit resets to 0, and INT pin rises to high 101% 106.5% 112% V REF Power good lower trip threshold PGL_FALLIN G PNG bit sets to 1, and INT pin pulls low 80% 85.5% 91% V REF PGL_RISING PNG bit resets to 0, and INT pin rises to high 85% 91% 97% V REF Power good delay (INT response to PNG event) PGDELAY Low to high 10 μs VOUT UV, high to low 2 μs VOUT OV, high to low 6.5 μs INT sink current capability I SINK_INT Sink 4mA 0.1 0.4 V INT leakage current I LKG_INT V INT = 5V 1 μA I2C Interface (400kHz) Input logic low voltage V LI SCL, SDA 0.8 V Input logic high voltage V HI SCL, SDA 2 V Logic input current ISCL_SDA_LK G SCL/SDA = 5V -1 1 μA Output logic low voltage V LO SDA, sink 4mA 0.4 V ADDR Pin Setting Threshold Voltage threshold 1 ADDR1 Set I 2C address 64H 0.51 0.68 AVDD Voltage threshold 2 ADDR2 Set I 2C address 66H 0.74 AVDD Pin to GND pull-down resistor R ADDR ADDR pin 2 M Ω Current Monitor Function IMON output voltage gain GAINIMON +5mV IAVG sense voltage 18.8 V/V IMON output voltage gain +55mV IAVG sense voltage 16.92 18.8 20.68 V/V Notes: 7) The MPQ4210 has a minimum start-up voltage of 6V, and VIN UVLO falling is lower than VCC UVLO falling. 8) Guaranteed by characterization.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 10 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. VIN UVLO Rising vs. Temperature VCC UVLO Falling vs. Temperature EN UVLO Rising vs. Temperature EN UVLO Falling vs. Temperature EN Source Current vs. Temperature Frequency vs. Temperature 4.5 5.5 6.5 -45 -20 5 30 55 80 105 130 VIN UVLO RISING (V) TEMPERATURE (ºC) 3.5 4.5 5.5 -45 -20 5 30 55 80 105 130 VCC UVLO FALLING (V) TEMPERATURE (ºC) 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 - 4 5 - 2 05 3 05 58 0 1 0 5 1 3 0 EN UVLO RISING (V) TEMPERATURE (ºC) 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -45 -20 5 30 55 80 105 130 EN UVLO FALLING (V) TEMPERATURE (ºC) 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 - 4 5 - 2 05 3 05 58 0 1 0 5 1 3 0 EN SOURCE CURRENT (µA) TEMPERATURE (ºC) 100 200 300 400 500 600 -45 -20 5 30 55 80 105 130 FREQEU NC Y (k Hz) TEMPERATURE (ºC)

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 11 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. FB Reference Voltage vs. Temperature IMON Voltage vs. Temperature Boost Peak Current Limit vs. Temperature, ILIM = 111b Buck Valley Current Limit vs. Temperature, I LIM = 111b Output Current Limit vs. Temperature, ILIM = 111b 450 460 470 480 490 500 510 520 530 540 550 -45 -20 5 30 55 80 105 130 FB REFERENCE VOLTAGE (mV) TEMPERATURE (ºC) 900 920 940 960 980 1000 1020 1040 1060 1080 1100 - 4 5 - 2 05 3 05 58 0 1 0 5 1 3 0 IMON VOLTAGE (mV) TEMPERATURE (ºC) 140 142 144 146 148 150 152 154 156 158 160 - 4 5 - 2 05 3 05 58 0 1 0 5 1 3 0 BOOST PEAK CURRENT LIMIT (mV) TEMPERATURE (ºC) 110 115 120 125 130 135 140 145 150 155 160 -45 -20 5 30 55 80 105 130 BUCK VALLEY CURRENT LIMIT (mV) TEMPERATURE (ºC) - 4 5 - 2 05 3 05 58 0 1 0 5 1 3 0 OUTPUT CURRENT LIMIT (mV) TEMPERATURE (ºC)

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 12 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. Efficiency vs. Load VIN = 12V Load Regulation VIN = 12V Line Regulation VOUT = 5V Line Regulation VOUT = 9V Line Regulation VOUT = 15V Line Regulation VOUT = 20V 82.5 87.5 92.5 97.5 100 EFFICIENCY (%) IOUT (A) Vo=5V Vo=15V Vo=20V Vo=9V -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 LOAD REGULATION (%) IOUT (A) Vo=5V Vo=15V Vo=20V Vo=9V -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 8 1 01 21 41 61 82 02 2 LINE REGULATION (%) VIN (V) Io=10mA Io=4A -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 8 1 01 21 41 61 82 02 2 LINE REGULATION (%) VIN (V) Io=10mA Io=4A -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 8 1 01 21 41 61 82 02 2 LINE REGULATION (%) VIN (V) Io=10mA Io=4A -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 8 1 01 21 41 61 82 02 2 LINE REGULATION (%) VIN (V) Io=10mA Io=4A

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 13 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. Bode Plot VOUT = 5V, IOUT = 3A, BW = 3.06kHz, PM = 73.73deg Bode Plot VOUT = 12V, IOUT = 3A, BW = 2.64kHz, PM = 75deg Bode Plot VOUT = 20V, IOUT = 3A, BW = 2.3kHz, PM = 64.48deg Thermal Rise VIN = 12V, VOUT = 5V, fSW = 400kHz, based on EVQ4210-U-00B Thermal Rise VIN = 12V, VOUT = 9V, fSW = 400kHz, based on EVQ4210-U-00B Thermal Rise VIN = 12V, VOUT = 15V, fSW = 400kHz, based on EVQ4210-U-00B -200 -150 -100 -50 100 150 200 -60 -40 -20 1000 10000 100000 1000000 PHASE (deg) GAIN (dB) FREQUENCY (Hz) Gain Phase -200 -150 -100 -50 100 150 200 -60 -40 -20 1000 10000 100000 1000000 PHASE (deg) GAIN (dB) FREQUENC Y (Hz) Gain Phase -200 -150 -100 -50 100 150 200 -60 -40 -20 1000 10000 100000 1000000 PHASe (deg) GAIN (dB) FREQUENCY (Hz) Gain Phase 2.5 7.5 12.5 11 . 522 . 533 . 544 . 55 CASE TEMPERATURE RISE (℃) LOAD CURRENT (A) Inductor SWA SWB SWC SWD MPQ4210 2.5 7.5 12.5 11 . 522 . 533 . 544 . 55 CASE TEMPERATURE RISE (℃) LOAD CURRENT (A) Inductor SWA SWB SWC SWD MPQ4210 12345 CASE TEMPERATURE RISE (℃) LOAD CURRENT (A) Inductor SWA SWB SWC SWD MPQ4210

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 14 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. Thermal Rise VIN = 12V, VOUT = 20V, fSW = 400kHz, based on EVQ4210-U-00B 12345 CASE TEMPERATURE RISE (℃) LOAD CURRENT (A) Inductor SWA SWB SWC SWD MPQ4210

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 15 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. ENPWR Bit Enable through I2C Command, Load = 0A ENPWR Bit Enable through I2C Command, Load = 5A CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 2A/div. CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. 4ms/div. 4ms/div. ENPWR Bit Disable through I 2C Command, Load = 0A ENPWR Bit Disable through I2C Command, Load = 5A CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 2A/div. CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div 10ms/div. 200μs/div. EN Pin Disable, Load = 10mA EN Pin Disable, Load = 5A CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 2A/div. CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. 10ms/div. 200μs/div.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 16 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. Steady State VOUT = 5V, load = 0A Steady State VOUT = 5V, load = 5A CH1: VOUT/AC 20mV/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 2A/div. CH1: VOUT/AC 20mV/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. 2μs/div. 2μs/div. Steady State VOUT = 12V, BB_FSW = 1, load = 0A Steady State VOUT = 12V, BB_FSW = 1, load = 5A CH1: VOUT/AC 50mV/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 2A/div. CH1: VOUT/AC 200mV/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div. 2μs/div. 2μs/div. Steady State VOUT = 20V, load = 0A Steady State VOUT = 20V, load = 5A CH1: VOUT/AC 50mV/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div CH1: VOUT/AC 200mV/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 10A/div 2µs/div. 2µs/div.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 17 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. Load Transient VIN = 12V, VOUT = 5V, load = 0A to 2.5A, 150mA/μs Load Transient VIN = 12V, VOUT = 5V, load = 2.5A to 5A, 150mA/μs CH1: VOUT/AC 200mV/div. CH4: IOUT 2A/div. CH1: VOUT/AC 200mV/div. CH4: IOUT 2A/div. 1ms/div. 1ms/div. Load Transient VIN = 12V, VOUT = 20V, load = 0A to 2.5A, 150mA/μs Load Transient VIN = 12V, VOUT = 20V, load = 2.5A to 5A, 150mA/μs CH1: VOUT/AC 500mV/div. CH4: IOUT 2A/div. CH1: VOUT/AC 500mV/div. CH4: IOUT 2A/div. 1ms/div. 1ms/div. Input Voltage Transient VIN = 9V to 20V, VOUT = 15V, load = 0A Input Voltage Transient VIN = 9V to 20V, VOUT = 15V, load = 5A CH1: VOUT 5V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div. CH1: VOUT 5V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 10A/div. 100ms/div. 100ms/div.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 18 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. Input Voltage Transient VIN = 20V to 9V, VOUT = 15V, load = 0A Input Voltage Transient VIN = 20V to 9V, VOUT = 15V, load = 5A CH1: V OUT 5V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div. CH1: VOUT 5V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 10A/div 100ms/div. 100ms/div. Output Voltage Transient VOUT = 5V to 12V, IOUT = 5A Output Voltage Transient VOUT = 12V to 5V, load = 5A CH1: VOUT 5V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div. CH1: VOUT 5V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div. 4ms/div. 4ms/div. Output Voltage Transient VOUT = 5V to 20V, load = 5A Output Voltage Transient VOUT = 20V to 5V, load = 5A CH1: V OUT 10V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div. CH1: VOUT 10V/div. CH2: VSW1 10V/div. CH3: VSW2 10V/div. CH4: IL 5A/div. 10ms/div. 10ms/div.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 19 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, TA = 25°C, unless otherwise noted. OCP Entry Ramp up load current slowly OCP Recovery Remove load current CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. 40ms/div. 40ms/div. SCP Entry Short output to ground, RCC = 10mΩ SCP Recovery Remove short circuit, RCC = 10mΩ CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. 20ms/div. 4ms/div. SCP Steady State Short output to ground, RCC = 10mΩ CH1: VOUT 2V/div. CH2: VSW1 10V/div. CH3: VSW2 5V/div. CH4: IL 5A/div. 40µs/div.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 20 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM SDA ADDR VIN EN VOUT SCL VCC LG2 Regulator and UVLOEnable Circuit BST Charge BST2BST1 Buck Boost Control VCC HG2 SW2 BST2 LG1 VCC HG1 SW1 BST1 CSN CSP Peak / Valley Current Limit IAVGN IAVGP IREF FB AGND GMVREF SR Comparator I2C INT VREF & SR IREF tON/tOFF & DitherPG & OVP OVP PGND COMP IMON SS SS AVDDRegulator and UVLO Register Control Discharge Figure 1: Functional Block Diagram

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 22 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. Power Supply The MPQ4210’s internal circuit is powered by 5.2V AVDD, while the gate drivers are powered by 7.2V VCC. VCC is regulated from V IN and VOUT, while AVDD is powered by VCC. When VIN power is supplied and EN is high, the MPQ4210 tries to regulate VCC at 7.2V, and at the same time AVDD is regulated to 5.2V. When AVDD rises above the UVLO voltage, the part starts switching if ENPWR is high, and regulates V OUT by soft-start control. If VIN and VOUT are both above 8.8V, the MPQ4210 powers VCC from whichever is the lower voltage source to reduce power-loss. Otherwise, it powers VCC from the higher voltage power source of V IN and V OUT to get enough VCC voltage. VCC and BST have separate UVLO, which keeps the gate signal off. VCC and BST should have enough voltage to enable MPQ4210 switching, except for AVDD UVLO. The MPQ4210 operates within a 6V to 40V input voltage range. When VCC is powered from VOUT after start-up, the part works until V IN drops below 5V. When the MPQ4210 is powered off by AVDD_UVLO or the EN signal, the I 2C interface cannot respond to the host, and COMP is immediately pulled low. The VCC, AVDD, and BST voltages drop slowly with leakage, but all logic is off. Start-Up When the MPQ4210 is enabled, it starts switching with soft-start (SS) control. The SS circuit charges current to the SS pin and ramps the SS voltage up from 0V. It then feeds to the error amplifier to control output voltage. After the SS signal rises to the programmed reference voltage (set by VREF bits), soft start completes and closed-loop regulation starts. The SS voltage rises and clamps at 0.6V higher than V REF in steady state, unless a protection is triggered. Normally the MPQ4210 starts with buck switching after start-up because V OUT is much lower than V IN. If there is some bias voltage on VOUT, the part will not switch until the SS signal rises above VFB, which is proportional to the VOUT bias voltage. During SS, the IC works in auto PFM mode. OVP and hiccup-OCP do not work during the SS period. Enable (EN) and Programmable UVLO The EN pin enables and disables the MPQ4210. When applying a voltage higher than the EN high threshold (>1.1V), the part starts up some of the internal circuits (micro-power mode). If the EN voltage exceeds the turn-on threshold (1.35V), the MPQ4210 enables all functions and starts switching operation. Switching operation is disabled when the EN voltage falls below its lower threshold (<1.28V). If V EN < 0.4V, the MPQ4210 completely shuts down. After shutdown, the part sinks a small amount of current from the input power (typically <1µA). EN is compatible with voltage up to 40V. For automatic start-up, connect EN directly to VIN. During EN shutdown, the I 2C resets to its default value after a 200ms discharge time. The MPQ4210 features a programmable UVLO hysteresis. When powering up, EN sources a 4.7μA current out of the EN pin (see Figure 5) once the EN voltage is higher than 1.35V. V IN must decrease to overcome the current source and stop switching after the IC starts. The VIN start-and-stop switching threshold is determined with Equation (1) and Equation (2): TOP IN_ON EN_ON BOT TOP IN_OFF EN_OFF TOP BOT Where VEN_ON is about 1.35V (typical), V EN_OFF is about 1.28V. Figure 5: VIN UVLO Program

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 23 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. Forced CCM Mode The MPQ4210 works in forced continuous conduction mode (FCCM). Buck on time and boost off time are determined by an internal circuit to get fixed frequency, based on the V IN/VOUT ratio. When the load decreases, the average input current drops and the inductor current may go to negative from V OUT to V IN during the SWD on-period. This forces the inductor current to work in continuous mode with fixed frequency, producing a low V OUT ripple. Switching Current Limit The MPQ4210 senses the low-side MOSFET current with the CSP and CSN pins. It provides the valley current limit in buck mode and peak current limit in boost mode for each cycle-by- cycle switch. In buck mode, the next period will not start before I L drops to the valley current limit, so it may foldback the frequency when the valley current limit is triggered. The switching current limit can be programmed with an external sense resistor. The SWB and SWC current signal is blanked internally for about 180ns to enhance noise rejection. When the cycle-by-cycle current limit is triggered, the interrupt OCP bit is set to 1; and if the OCP bit is not masked off, the INT is pulled low. During over-current condition, the MPQ4210 runs in cycle-by-cycle current limit. It may also trigger hiccup protection or latch-off protection, depending on the OCP_MODE bit’s setting. In hiccup mode, the IC turns off once FB drops below 60% of V REF and triggers the switching current limit after SS period. It will attempt recovery after a fixed off time, programmed by SS capacitor discharge period. In latch-off mode, the IC turns off if FB falls below 60% of V REF. Once the latch off protect is triggered, the chip doesn't recover until a new Vin power cycle, EN toggle or ENPWR bit toggle. If the hiccup and latch-off protections are disabled, the IC continues switching with a cycle-by-cycle current limit. The hiccup and latch-off protections are masked during the SS period. Based on the cycle-by-cycle switching current limit, the MPQ4210 maximum input current can be calculated with Equation (3) in buck mode and Equation (4) in boost mode: INmax sense VoI( A ) VIN Buckvalleycurrentlimit(mV) VIN Vo( R( m ) 2 L ( H ) f ( k H z ) Vo 10 )VIN    (3) INmax sense Boostpeakcurrentlimit(mV) VINI( A ) R( m ) 2 L ( H ) f ( k H z ) Vo VIN 10 )Vo   (4) Where η is the efficiency, the buck valley current limit typical value is 133mV, the boost peak current limit typical value is 150mV, and R SENSE is the cycle-by-cycle switching current limit sense resistor. Average Current Limit The IAVGP and IAVGN pins sense the output current in the MPQ4210. A sense resistor can be connected to the VOUT line for average output current limit control. Once the sensed signal is higher than the current limit reference voltage, one internal EA pulls down V SS. Eventually, VSS replaces VREF to control COMP, and the inductor current is limited by COMP to transfer less energy to output. SS regulates output low until the average load current drops. If the switching current is regulated by the average current limit, and it does not trigger cycle-by-cycle current limit, the MPQ4210 will not trigger hiccup or latch-off protection even if the average current limit is reached. This feature makes constant current charge possible in the MPQ4210. If only the average current limit is triggered, the interrupt OCP bit does not set to 1, and INT will not pull low. It is recommended to add a 100Ω/220nF current sense filter (see Figure 13). Overload and Short-Circuit Protection When overload occurs, the MPQ4210 limits the output current by average current limit loop regulation. If average current limit loop is disabled, the cycle-by-cycle switching current limit works. In cycle-by-cycle current limit condition, if the IC works in boost mode and the SWC peak current is limited. If the IC works in buck mode, SWB remains on until I L drops to the buck valley current limit level, and then the next

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 24 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. cycle can kick in. Therefore, the inductor current can be controlled in all work modes. Output Voltage Regulation The MPQ4210 regulates V OUT through FB pin feedback. V FB is compared to the internal reference, which is between 300mV and 2.047V depending on the VREF register bit’s setting. The EA output on COMP controls the inductor current to supply output voltage. Switching Frequency and Frequency Spread Spectrum Function The MPQ4210 programs switching frequency with a 2-bit FSW register. The frequency is selectable at 200kHz, 300kHz, 400kHz, and 600kHz. Typically, a 400kHz switching frequency is recommended. The MPQ4210 has a frequency spread spectrum function. Set the Dither bit = 1 (0x02, D[4]) to enable this function. Set the Dither bit = 0 to disable the function. The purpose of the spread spectrum is to minimize the peak emissions at certain frequencies. The MPQ4210 uses a 2kHz triangle wave to modulate the internal oscillator. The frequency span of the spread spectrum operation is ±6%. t500μs fS = 400KHz fS = 424KHz fS = 376KHz Fundemantal Frequency Figure 6: Frequency Spread Spectrum The MPQ4210 frequency spread frequency can be enabled for a 200kHz, 300kHz, 400kHz, or 600kHz switching frequency. Gate Driver and BST Power The MPQ4210 provides four N-channel MOSFET gate drivers for the H-bridge MOSFETs (see Figure 2). Each driver is capable of sourcing and sinking current. In buck operation, LG1 and HG1 switch while HG2 remains on. In boost operation, LG2 and HG2 switch while HG1 remains on. LG1 and LG2 are powered by VCC power, while HG1 and HG2 are powered by BST1 and BST2 power. Capacitors between BST1 to SW1 and BST2 to SW2 are necessary to supply the power, which can be from an internal diode from VCC or from charging each other. Over-Voltage Protection The MPQ4210 monitors FB. If V FB exceeds 127% of VREF and the OVP_MODE bits are 01, the IC discharges the V OUT capacitor through one internal discharge resistor . It stops discharging when VFB drops to 111% of the regulation voltage. If the OVP_MODE bits are 00, there is no logic to stop switching even if V FB is higher than the OVP threshold. If the OVP_MODE bits are 10, the IC latches off when V OUT rises to 127% of VREF. Interrupt (INT Pin) The MPQ4210 has one interrupt pin for the following fault events: OCP, OVP, OTP, and PNG (VOUT power not good) reporting. When the switching peak cycle-by-cycle current limit (OCP), output over -voltage (FB OVP), or over-temperature protection (OTP) is triggered, the corresponding register bit sets to 1. At the same time, INT pulls low to indicate an interrupt signal, depending on the related Mask register setting. INT is an open-drain output. When the MPQ4210 is disabled, INT is an open drain. Slew-Rate Control and Output Discharge The MPQ4210 sets the output voltage change slew-rate through internal SR bits. Four kinds of V REF change (rising and falling) slew rate can be selected in different application requirement: 38mV/ms, 50mV/ms, 75mV/ms and 150mV/ms. During voltage transient, the discharge function works when GO-BIT sets to 1. The discharge function is disabled automatically after GO_BIT resets to 0 (which means V REF change completes). If V OUT has not been discharged to the goal voltage when V REF change completes due to too large of an output capacitor, the OVP discharge function or DISCHG bit can be used to continue discharging C OUT. The output discharge function is enabled in the following conditions:

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 27 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

APPLICATION INFORMATION

The default output voltage is set using a resistor divider to FB. The default reference voltage (VREF) is 0.5V. The bottom resistor in the resistor divider is typically in the 1kΩ to 50kΩ range. The top resistor in the feedback resistor divider is selected using Equation (7): OUT REF REF VVR1 R2 V  (7) It is possible to use the I2C interface to select the FB VREF and get another output voltage. Inductor Selection The inductor selection is based on the work mode. The inductance for the buck mode is calculated with Equation (8): OUT OUT Buck SW L IN (8) Where ∆IL is the peak-to-peak inductor ripple current, and it is about 30% to 50% of the maximum load current. In boost mode, the inductor selection is based on limiting ∆I L to about 30% to 50% of the maximum input current. The target inductance for boost mode is calculated with Equation (9) and Equation (10): IN OUT IN Boost OUT SW L V( V V )L VF I (9) OUT LOAD(max) IN(max) IN VI )I V   (10) Where ILOAD(max) is the maximum load current, ∆IL is the peak-to-peak ripple current (about 30% to 50% of the maximum input current), and ƞ is the efficiency. Choosing a larger inductance reduces the ripple current but also increases the size of the inductor and reduces the achievable bandwidth of the converter by moving the right half-plane zero to lower frequencies. The appropriate balance should be chosen based on the application requirements. Input Capacitor Selection In buck mode, the MPQ4210 has a discontinuous input current (boost mode is continuous), and requires a capacitor to supply the AC current during buck mode while maintaining the DC input voltage. Ceramic capacitors are recommended for best performance, and should be placed as close to VIN as possible. Capacitors with X5R or X7R ceramic dielectrics are recommended because of their stable temperature characteristics. The capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. The buck mode input ripple current can be estimated with Equation (11): OUT OUT CIN_ RMS OUT IN IN VVII ( 1 ) VV   (11) The worst-case condition in buck mode occurs at VIN = 2VOUT, calculated with Equation (12): OUT CIN _ RMS II 2 (12) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitance value determines the input voltage ripple of the converter. If there is an input voltage ripple requirement in the system, choose an input capacitor that meets the specification. In buck mode, the input voltage ripple can be estimated with Equation (13): OUT OUT OUT IN SW IN IN IN (13) The worst-case condition occurs at VIN = 2VOUT, calculated with Equation (14): OUT IN SW IN I1V 4F C  (14)

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 28 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. Output Capacitor Selection In boost mode, the output current is discontinuous, so C OUT must be capable of reducing the output voltage ripple. A higher capacitance value may be required to lower the output ripple and the transient response. Low-ESR capacitors, such as X5R or X7R ceramic capacitors, are recommended. If using ceramic capacitors, the capacitance dominates the impedance at the switching frequency, so the output voltage ripple is independent of the ESR. The output voltage ripple is estimated with Equation (15): IN LOAD OUT OUT OUT SW V(1 ) IVV CF   (15) Where VRIPPLE is the output ripple voltage, and COUT is the capacitance of the output capacitor. If using hybrid, polymer, or low-ESR electrolytic capacitors, the ESR dominates the impedance at the switching frequency, so the output ripple is estimated using Equation (16): IN LOAD OUT LOAD ESR OUT OUT OUT SW IN V(1 ) IVI R VV CF V (16) Where RESR is the equivalent series resistance of the output capacitors. For a 100W USB PD application, one 330µF electrolytic capacitor and four 10µF ceramic capacitors are recommended. Choose output capacitors to satisfy the output ripple and load transient requirements of the design. Capacitance derating should be taken into consideration when designing high output voltage applications. External MOSFET Selection The MPQ4210 requires four external N-channel power MOSFETs. Figure 10 shows two for the top switches (switches A and D) and two for the bottom switches (switches B and C). In buck mode, SWA and SWB switch while SWD remains on. In boost mode, SWC and SWD switch while SWA remains on. VIN VOUT SWA RSENSE SWC SW1 SW2 SWD SWB Figure 10: Buck-Boost Topology The critical parameters of selecting a MOSFET are: 1. Maximum drain-to-source voltage, V DS(MAX) The SWA and SWB need to withstand the maximum input voltage and the transient spikes at SW1 during switching. Therefore, it is recommended to select V DS(MAX) for SWA and SWB at 1.5 times the input voltage. The SWC and SWD see output voltage and transient spikes at SW2 during switching. Therefore, it is recommended to select SWC and SWD at ≥1.5 times the output voltage. 2. Maximum current, I D(MAX) 3. V TH: The driver voltages of the MPQ4210 are supplied by VCC. The gate plateau voltages of the MOSFETs should be smaller than the minimum VCC voltage of the converter, otherwise the MOSFETs may not fully enhance during start-up or overload conditions. 4. On resistance, R DS(ON) 5. Total gate charge, Q G For the MPQ4210, all switches QG should be smaller than 50nC (at 7.2V GATE condition). If there are two MOSFETs in parallel, each MOSFET QG need be smaller than 25nC. MOSFET SWA When the MPQ4210 works in boost mode, SWA is on consistently. Its conduction power loss can be calculated with Equation (17): 2OUT C _ Loss(SWA) o DSON(SWA) IN VP( I ) R V  (17)

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 30 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. When the MPQ4210 works in buck mode, the DC gain of the voltage feedback loop is calculated with Equation (28): CS FB VDC LOAD V EA SENSE OUT G VAR A RV Where A V-EA is the error-amplifier voltage gain (300V/V), GCS is the COMP to current sense gain, RSENSE is the current sense resistor, and RLOAD is the load resistor value. The system has two important poles: one is from the compensation capacitor (C10) and the output resistor of the error amplifier, and the other one is from the output capacitor and the load resistor. These poles can be calculated with Equation (29) and Equation (30), respectively: EA VE A GF 2C 1 0 A     (29) OUT LOAD 1F 2C R   (30) Where G EA is the error-amplifier transconductance (1220 μA/V), and C OUT is the output capacitor. The system may have another significant zero if the output capacitor has a large capacitance or a high ESR value. This zero can be located with Equation (31): ESR OUT ESR 1F 2C R   (31) When the MPQ4210 works in boost mode, the DC gain of the voltage feedback loop is calculated with Equation (32): IN V EA LOAD FB CS VDC 2 OUT SENSE VA R V G R 1 3A 2V R (32) There is also a right-half-plane zero (F RHPZ) that exists in boost mode. The frequency of the right half-plane zero is determined with Equation (33): 2LOAD IN RHPZ OUT (33) The right half-plane zero increases the gain and reduces the phase simultaneously, which results in a smaller phase and gain margin. The worst- case condition occurs when the input voltage is at its minimum and the output power is at its maximum.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 31 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PCB Layout Guidelines Efficient layout is a critical step in designing a buck-boost controller. Improper layout may result in reduced perform ance, EMI problems, resistive loss, and even system instability. For best results, refer to Figure 13 and follow the steps below: 1. In buck mode, place the input power loop — including the input filter capacitor (C IN), the power MOSFETs (SWA and SWB), and the cycle-by-cycle current sense resistor (R4) — as close as possible. 2. In boost mode, place the output power loop — including the output filter capacitor (C OUT), the power MOSFETs (SWC and SWD), and the cycle-by-cycle current sense resistor (R4) — as close as possible. 3. Use wide copper traces and power loop vias to help thermal dissipation. 4. Connect the exposed pad to GND, and place vias on the exposed pad for IC thermal dissipation. 5. Place small decoupling capacitors close to VIN, VOUT, and AGND. 6. Lay out the gate drive traces and return paths as directly as possible. Lay out the forward and return traces close together, either running side by side or on top of each other on adjacent layers, to minimize the inductance of the gate drive path. 7. Use Kelvin connections to R3 (for the average current sense) and R4 (for the cycle- by-cycle current), and run lines in parallel from the R3/R4 terminals to the IC pins. Avoid crossing noisy areas such as SW1 and SW2 or gate drive traces. 8. Place the filter capacitor for the current sense signal as close to the IC pins as possible. 9. Place the VCC and AVDD capacitors as close as possible to the VCC and AVDD pins. 10. Place the BST1 bootstrap capacitor close to the IC, and connect directly to the BST1 and SW1 pins. 11. Place the BST2 bootstrap capacitor close to the IC, and connect directly to the BST2 and SW2 pins. 12. The feedback loop should be far away from any noise source. Place the FB dividers (R1 and R2) as close as possible to the FB and AGND pins. 13. Separate the power and signal paths so that no power or switching current flows through the AGND connections. Connect the PGND and AGND traces near the PGND pin, near the VCC capacitor PGND connection, or near the PGND connection of the cycle by cycle current sense resistor (R4). Top Layer Via Bottom Layer SWA SWB SWC SWD C2H C2I C2J C2A C2B C2C C2D C2E C2F C1G C1A C1B C1C C1D C1E C1F Top Layer Bottom Layer Figure 13: Recommended PCB Layout

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 32 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUITS HG1 LG1 SW1 BST1 CSP CSN LG2 HG2 SW2 BST2 VIN VOUT IAVGP IAVGN VOUT VIN AVDD VCC AGND PGNDCOMP FB VOUT SWA SWB SWD SWC INT EN SCL SDA ADDR SS C1A 0.1µF C1C 10µF 2.2µF C8 2.2µFR9 100kΩ 82kΩ 9.1kΩ C10 68nF R13 1.2kΩ 47nF 220nF R5 100Ω R6 100Ω 0.22µF 5mΩ 47pF R7 100Ω R8 100Ω L1 4.7µH 0.22µF C2C 22µF C2G 330µF C2I 22µF 10mΩ C2B 0.1µF C2A 0.1µF 5V/9V/15V/20V R10 29.4kΩ C2D 22µF C2E 22µF C2H 22µF C1B 0.1µF C1D 10µF C1E 10µF C1G 100µF C1F 10µF C2F 22µF IMONC12 100pF C11 NS MPQ4210 AVDD AVDD R14 2.2kΩ R15 2.2kΩ R16 10kΩ 92 0 1526 ESR = 80mΩ Aluminum Electrolytic Capacitor ESR = 160mΩ Aluminum Electrolytic Capacitor Figure 14: VIN = 12V, VOUT = 5V/9V/15V/20V for 100W USB PD

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 33 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. REGISER DESCRIPTION Register Map Address Register Type D7 D6 D5 D4 D3 D2 D1 D0 Reset State 0x00 REF_LS B R/W - - - - - VREF_L 0000 0100 0x01 REF_MS B R/W VREF_H 0011 1110 0x02 Control 1 R/W SR DISCHG Dither PNG_Latch Reserved (9) GO_BIT ENPWR 0100 0000 0x03 Control 2 R/W FSW - BB_FSW OCP_MODE OVP_MODE 1000 0101 0x04 ILIM R/W - - - - Reserved ILIM 0000 1001 0x05 Interrupt status R/W - - - OTP - OVP OCP PNG 0000 0000 0x06 Interrupt mask R/W - - - M_OTP - M_OVP M_OCP M_PNG 0000 0001 Note: 9) This bit must be written to 1 before start-up. Register Name: REF_LSB, 0x00, Read/Write Name Bits Default Value Description VREF_L D[2:0] 100 Feedback VREF low 3 bits. LSB = 1mV. Register Name: REF_MSB, 0x01, Read/Write Name Bits Default Value Description VREF_H D[7:0] 0011 1110 Feedback VREF high 8 bits. LSB = 8mV. See below for FB reference data format. Name VREF Format Direct, unsigned binary integer Register Name N/A VREF_H D[7:0] VREF_L D[2:0] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access N/A r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w Function N/A Data bit high Data bit low Default Value (0.5V) N/A 500 integer Total 11 bits to set reference voltage. If V is an 11-bit, unsigned binary integer of VREF [10:0], then: VFB (V) = V/1000.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 34 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. Register Name: Control 1, 0x02, Read/Write Name Bits Default Value Description SR D[7:6] 01 Program the VREF changing slew rate. This SR control only works after SS finishes. During the SS period, the V OUT slew rate is controlled by SS. VOUT slew rate = VREF slew rate × feedback ratio of (R1 + R2) / R2. SR Bits Value V REF Slew Rate 00 38mV/ms 01 50mV/ms 10 75mV/ms 11 150mV/ms DISCHG D[5] 0 Turn on or turn off the output-to-ground discharge path. Write DISCHG bit 1 to always turn on the internal discharge resistor. Write DISCHG bit 0 to turn off output discharge resistor. DISCHG bit function works even ENPWR bit is low. This bit does not affect the output discharge behavior in the following cases: 1) V OUT voltage changed by I2C 2) ENPWR power off 3) EN pin power off 4) Output OVP (When OVP_MODE enables discharge) 5) VIN UVLO When GO_BIT is set to 1, V OUT discharges will automatically turn on. After GO_BIT resets to 0 with 20ms extra delay, the VOUT discharge path turns off. Normally, it is suggested to set the slew rate low so VOUT can follow the VREF change with this internal discharge current. If V OUT cannot follow the VREF change even with the discharge due to a large COUT capacitor, there is an additional 20ms discharge. Dither D[4] 0 Frequency spread sprectrum enable bit. Dither is enabled when this bit is 1, and disabled when this bit is 0. PNG_Latch D[3] 0 PNG status bit reset control bit. Refer to PNG bit description on page 36. 0 = PNG bit status recovers to 0 once VOUT returns to its normal voltage range 1 = PNG bit status latches to 1 once V OUT exceeds the power good voltage range Reserved D[2] 0 This bit must be set to 1 before the IC starts up.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 35 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. GO_BIT D[1] 0 VREF change function enable bit. Set GO_BIT to 1 to enable the output change based on the VREF register. When the command completes (internal reference voltage steps to the goal of VREF), GO_BIT auto-resets to 0. This prevents false operation of the VOUT scaling. Write the VREF registers (00h and 01h register) first, then write GO_BIT = 1. The reference and output voltage will change based on the new V REF. GO_BIT resets to 0 when V REF reaches a new level. The host reads GO_BIT to determine whether the VREF scaling is finished or not. The VOUT discharge path enables when GO_BIT is 1, no matter what the DISCHG bit is. This can help pull V OUT from high to low in light-load condition. After GO_BIT resets to 0, the discharge continues and turn off after a 20ms delay. 0 = VOUT cannot be changed 1 = V OUT changes based on VREF registers. After V REF reaches the new level set by the VREF bits, GO_BIT resets to 0 automatically ENPWR D[0] 0 The MPQ4210 power switching enable bit. 1 = Enables power switching 0 = Disables power switching, but other internal control circuits work ENPWR start-up sequence: Step 1: Set V REF first, ENPWR = 0 Step 2: Set GO_BIT = 1 Step 3: Wait 200ms, then set ENPWR = 1 to start After ENPWER is set to 0 and a 200ms delay, the discharge function works. Register Name: Control 2, 0x03, Read/Write Name Bits Default Value Description FSW D[7:6] 10 Switching frequency setting bit. Writable during both ENPWR = 0 and ENPWR = 1 conditions. The switching frequency changes smoothly after I2C writes these bits. FSW bits 00 01 10 11 Frequency 200kHz 300kHz 400kHz 600kHz BB_FSW D[4] 0 Buck-boost region switching frequency set bit. See Figure 4. 1 = higher switching frequency in buck-boost region. The higher Buck- Boost switching frequency is 62.5% of the base switching frequency. 0 = lower switching frequency in buck-boost region. The lowers Buck-Boost switching frequency is 37.5% of the base switching frequency.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 36 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. OCP_MODE D[3:2] 01 Set OCP protection mode after triggering the cycle-by-cycle switching current limit (valley current limit in buck, or peak current limit in boost). 00 = No hiccup or latch-off protection. Inductor current is limited by cycle- by-cycle current limit 01 = Hiccup protection after triggering the switching current limit and FB < 60% of VREF. Off-period is controlled by SS discharge 10 = Latch-off protection. Must re-power or re-enable for the IC to restart 11 = Reserved OVP_MODE D[1:0] 01 Set OVP protection mode after triggering the threshold at 127% of VREF. 00 = No protection after OVP, V OUT is regulated by COMP. No discharge after OVP 01 = Discharge VOUT through an internal resistor and stop switching when VFB exceeds 127% of VREF. Recover when VFB drops to 111% of VREF 10 = Latch-off protection. No discharge after OVP 11 = Reserved Register Name: ILIM, 0x04, Read/Write Name Bits Default Value Description ILIM D[2:0] 001 Average current limit. Can be used to program output current limit. ILIM Bits Current Limit Threshold Current Limit with 10mΩ RSENSE 000 27.9mV 2.79A 001 33.3mV 3.33A 010 39.3mV 3.93A 011 45.1mV 4.51A 100 51.2mV 5.12A 101 56.8mV 5.68A 110 62.8mV 6.28A 111 68.7mV 6.87A

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C MPQ4210 Rev. 1.1 www.MonolithicPower.com 37 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. Register Name: Interrupt Status, 0x05, Read/Write Name Bits Default Value Description Reset Condition OTP D[4] 0 Over-temperature protection indication. 0: Normal state 1: Chip is in over-temperature protection state This bit is latched once triggered. Write 0xFF to this register to reset the interrupt status and INT’s state. OVP D[2] 0 VOUT OVP indicator. 0: Normal state 1: Chip is in over-temperature protection state OCP D[1] 0 Cycle-by-cycle switching current limit indication. 0: Normal state 1: Cycle-by-cycle current limit is triggered, V FB < 60% of VREF, and soft-start is finished PNG D[0] 0 VOUT power not good indicator. 0: Normal state 1: Output power is not good. It indicates when VOUT is out of both its upper and lower thresholds The PNG_Latch bit controls the PNG reset behavior. Related to PNG_Latch setting: PNG_Latch = 0: This bit indicates instantaneous value. INT indicates instantaneous state PNG_Latch = 1: This bit is latched once triggered. Write 0xFF to reset the interrupt status and INT’s state Register Name: Interrupt Mask, 0x06, Read/Write Name Bits Default Value Description M_OTP D[4] 0 Set M_OTP = 1 to mask off the OTP alert. M_OTP = 1 only masks INT’s output. It is similar for other mask bits. M_OVP D[2] 0 OVP mask bit. Set 1 to mask off the OVP alert. M_OVP = 1 only masks INT’s output. M_OCP D[1] 0 OCP mask bit. Set 1 to mask off the OCP alert. M_OCP = 1 only masks INT’s output. M_PNG D[0] 1 PNG mask bit. Set 1 to mask off the PNG alert. M_PNG = 1 only masks INT’s output.

MPQ4210 – 40V, SYNCHRONOUS BUCK-BOOST CONTROLLER WITH I2C NOTICE: The information in this document is subject to change wi thout notice. Please contact MP S for current specifications. Users should warrant and guarantee that third- party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4210 Rev. 1.1 MonolithicPower.com 38 7/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-27 (5mmx5mm) 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) DRAWING REFERENCE TO JEDEC MO-220. 5) DRAWING IS NOT TO SCALE.

Summary

40V, 100W Synchronous 40V, 100W Synchronous Current Monitor, AEC-Q100 Qualified 7/12/2019 Rev. 1.1

Description