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MP2624 I2C Controlled 4.5A Single Cell USB / Adaptor Charger with Narrow VDC Power Path Management USB OTG and Shipping Mode MP2624 Rev.1.05 www.MonolithicPower.com 1 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. The Future of Analog IC Technology
DESCRIPTION
The MP2624 is a 4.5A, highly integrated, switching-mode battery charger IC for single- cell Li-ion or Li-polymer batteries. This device supports NVDC architecture with power path management suitable for different portable applications, such as tablets, MID, and smart phones. Its low impedance power path optimizes efficiency, reduces battery charging time, and extends battery life. The I 2C serial interface with charging and system settings allows the device to be controlled flexibly. The MP2624 supports a wide range of input sources, including standard USB host ports and wall adapters. The MP2624 detects the input source type according to the USB Battery Charging Spec 1.2 ( BC1.2) and then informs the host to set the proper input current limit. Also, this device is compliant with USB2.0 and USB3.0 power specifications by adopting a proper input current and voltage regulation scheme. In addition, the MP2624 supports USB On-The-Go operation by supplying 5V with current up to 1.3A The power path management regulates the system voltage slightly above the set maximum voltage between the battery voltage and the I 2C programmable lowest voltage level (e.g. 3.6V). With this feature, the system is able to operate even when the battery is depleted completely or removed. When the input source current or voltage limit is reached, the power path management reduces automatically the charge current to meet the priority of the system power requirement. If the system current continues increasing, even when the charge current is reduced to zero, the supplement mode allows the battery to power both the system and the input power supply at the same time. The MP2624 is available in a QFN-22 3mm x 4mm package.
FEATURES
High Efficiency 4.5A 1.5MHz Buck Charger and 1.5MHz 1.3A Boost Mode to Support OTG o 94% Efficiency @ 2A o Fast Charge Time by Battery Path Impedance Compensation o USB OTG o 94% Efficiency @ 5V, 1.2A OTG o Selectable OTG Current Outputs 3.9V to 7.0V Operating Input Voltage Range Highest Battery Discharge Efficiency with 10mΩ Battery Discharge MOSFET up to 9A Single Input USB Compliant Charge Narrow System Bus Voltage Power Path Management o Instant On Works with No Battery or Deeply Discharged Battery o Ideal Diode Operation in Battery Supplemental Mode Constant-Off-Time Control to Reduce Charging Time under Lower Input Voltages High Accuracy of Charging Parameter I 2C Port for Flexible System Parameter Setting and Status Reporting Full DISC Control to Support Shipping Mode High Integration o Fully Integrated Power Switches and No External Blocking Diode and Sense Resistor Required o Built-In Robust Charging Protection including Battery Temperature Monitor and Programmable Timer o Built-In Battery Disconnection Function High Accuracy o ±0.5% Charge Voltage Regulation o ±5% Charge Current Regulation o ±5% Input Current Regulation o ±2% Output Regulation in Boost Mode Safety o Battery Temperature Sensing for Charge Mode o Battery Charging Safety Timer
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 2 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. o Thermal Regulation and Thermal Shutdown o Battery/System Over-Voltage Protection o MOSFET Over-Current Protection Charging Operation Indicator Thermal Limiting Regulation on Chip Tiny QFN-22 3mm x 4mm Package
APPLICATIONS
Tablet PCs Smart Phones Mobile Internet Devices All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website unde r Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 3 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking MP2624GL QFN-22 (3mm x 4mm) See Below EVKT-2624 Evaluation Kit * For Tape & Reel, add suffix –Z (e.g. MP2624GL–Z) TOP MARKING MP: MPS prefix Y: Year code W: Week code 2624: First four digits of the part number LLL: Lot number EVALUATION KIT EVKT-2624 EVKT-2624 Kit contents: (Items can be ordered separately). # Part Number Item Quantity
1 EV2624-L-00A MP2624 Evaluation Board 1
2 EVKT-USBI2C-02-
Includes one USB to I2C Dongle, one USB Cable, and one Ribbon Cable 1
3 Tdrive-2624 USB Flash drive that stores the GUI installation file and
Order direct from MonolithicPower.com or our distributors EVKT-2624 Evaluation Kit Set-Up
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 4 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW 1DP IN PMID SW PGND VNTC SCL SDA VREF ILIM AGND BST SW SYS BATT DISC OTG CE NTC STAT INT DM QFN-22 (3mm x 4mm)
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 5 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PIN FUNCTIONS Package Pin # Name Type Description 1 DP I Positive pin of the USB data line pair. DP and DM achieve USB host/charging port detection automatically. 2 IN Power Power input of the IC from the adapter or USB. Place a 1 μF ceramic capacitor from IN to PGND as close as possible to the IC.
3 PMID Power
Internal Power Pin . Connect to the drain of the reverse-blocking MOSFET and the drain of the high-side MOSFET. Bypass with a 4.7 μF capacitor from PMID to PGND as close as possible to the IC. 4, 14 SW Power Switching node. 5 PGND Power Power ground.
6 VNTC O Pull-up voltage bias of the NTC comparator resistive divider for both the
feedback and the reference. 7 SCL I/O I2C interface clock. Connect SCL to the logic rail through a 10kΩ resistor. 8 SDA I/O I2C interface data. Connect SDA to the logic rail through a 10kΩ resistor. 9 VREF P PWM low-side driver output. Connect a 10 μF ceramic capacitor from VREF to AGND as close as possible to the IC.
10 ILIM I
Programmable input current limit. A resistor is connected from ILIM to ground to set the minimum input current limit. The actual input current limit is the lowest setting by ILIM and I2C. 11 AGND I/O Analog ground.
12 OTG I
Boost mode enable control or input current limiting selection pin. The On-The- Go is enabled through I 2C. During boost operation, OTG low suspends boost operation. If the input is detected as the U SB host, OTG is used as the input current limiting selection pin. When OTG = high, IIN_LMT = 500mA. When OTG = low, IIN_LMT = 100mA.
13 BST P
Bootstrap. Connect a 470nF bootstrap capacitor between BST and SW to form a floating supply across the power switch driver to drive the power switch’s gate above the supply voltage. 15 SYS P System output. Connect a 2x22 μF ceramic capacitor from SYS to PGND as close as possible to the IC. 16 BATT P Battery positive terminal. Connect a 2x22 μF ceramic capacitor from BATT to PGND as close as possible to the IC. 17 DISC I Battery disconnection control. 18 CE I Active low charge enable. Battery charging is enabled when the corresponding register is set to active, and CE is low.
19 NTC I
Temperature sense input. Connect a negative temperatur e coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VNTC to NTC to AGND. The charge is suspended when NTC is out of range.
20 STAT
O Indicator for charging operation. 21 INT O Open-drain interrupt output. INT sends the charging status, and the fault interrupts the host. 22 DM I Negative pin of the USB date line pair. DM and DP achieve USB host/charging port detection automatically.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 6 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) BATT, SYS to GND………………. .. -0.3V to +6V Continuous power dissipation (TA = +25C)(2) Recommended Operating Conditions (3) Operating junction temp. (TJ) ... -40C to +125C Thermal Resistance (5) θJA θJC NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable powe r dissipation will produce an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) The inherent switching noise voltage should not exceed the absolute maximum rating on either BST or SW. A tight layout minimizes switching loss. 5) Measured on JESD51-7, 4-layer PCB.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 7 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Step-Down Converter Input voltage range V IN 3.9 7.0 V Input shutdown current VIN = 5V, both DC/DC and battery FET are disabled 65 μA Input quiescent current VIN > VIN_UVLO, VIN > VBATT, charge disabled, switching, SYS float 3 5 mA VIN > VIN_UVLO, VIN > VBATT, charge enabled, switching BATT and SYS float 3 5 Input under-voltage lockout V IN UVLO V IN rising 3.45 3.6 V VIN_UVLO hysteresis V IN falling 200 mV VIN vs. VBATT headroom VIN rising 200 250 300 mV VIN falling 65 90 115 mV Internal reverse-blocking MOSFET on resistance RIN to PMID Measure from IN to PMID 25 35 m Ω High-side NMOS on resistance RH_DS Measure from PMID to SW 25 35 m Ω Low-side NMOS on resistance R LD S Measure from SW to PGND 28 35 m Ω High-side NMOS peak current limit 7.5 A Low-side NMOS peak current limit 7 A Switching frequency V BATT = 4.2V, ICHG = 2A 1.4 1.7 2.0 MHz SYS Output Minimum system regulation voltage [I2C] VSYS_MIN ISYS = 0, VBATT = 3.4V, POR default, REG01[2:0] = 110 3.6 V System regulation voltage V SYS_MAX 50mV or 100mV (REG01[0]) higher than VBATT_FULL depends on the I2C setting 3.53 4.525 V Ideal diode forward voltage in supplement mode VF_IDD 50mA discharge current 24 mV
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 8 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units SYS/BAT comparator V SYS falling 40 mV Battery good comparator (Threshold compared with V SYS_MIN) VBATT rising to the battery FET being turned on fully 60 mV V BATT falling -40 mV Battery Charger Battery charge full voltage [I2C] VBATT_FULL Depends on the I2C setting default 3.48 4.425 V Charge voltage regulation accuracy V BATT_FULL = 4.2V -0.5 0.5 % Constant current charge current [I2C] Depends on the I 2C setting 0.512 4.544 A Charge current regulation accuracy I CHG = 2A -5 5 % Battery pre-charge threshold [I2C] VBATT_PRE REG04[4]=1, V BATT rising 2.8 3.0 3.1 V Battery pre-charge hysteresis V BATT falling 220 mV Battery short threshold V BATT SHORT V BATT rising 2.0 2.1 2.2 V Battery short threshold hysteresis V BATT falling 130 mV Trickle-charge current I TC V BATT = 1.8V 128 mA Pre-charge current [I2C] I PRE Depends on the I 2C setting 64 1024 mA Pre-charge current accuracy V BATT = 2.6V, IPRE = 256mA -25 25 % Termination current [I2C] I BF Depends on the l 2C setting 128 1024 mA Termination current accuracy VBATT_FULL = 4.2V, IBF = 512mA -30 30 % VBATT_FULL = 4.2V, IBF = 128mA 15 98 250 mA Recharge threshold below VBATT FULL VRECH REG04[0] = 1 180 mV Recharge threshold delay 20 ms BATT to SYS FET on resistance RBATFET V BATT = 3.8V 10 15 m Ω Battery discharge peak current limit IDSG_LMT VIN = 0V, VBATT = 3.8V, OTG disabled, ISYS rising 11 A Battery discharge function controlled by DISC tDISC DISC pulled low time period to turn off the battery discharge function 6.6 s DISC pulled high and low time period to turn on the battery discharge function 0.5
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 9 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Input Voltage and Input Current Based Power Path Input voltage regulation threshold [I2C] VIN_REG 3.9 5.1 V Input voltage regulation accuracy REG00[6:3] = 1011, VIN REG = 4.76V -4 4 % Input current limit I IN_LMT USB100 70 100 mA USB150 120 150 USB500 400 500 USB900 750 900 Input current limit accuracy IIN_LMT = 1.8A, REG00[2:0] = 101 1450 1800 mA Protection Battery over-voltage protection V BATT_OVP Rising. Compared to VBATT FULL 200 mV Battery over-voltage protection hysteresis Compared to V BATT_FULL 68 mV Thermal shutdown rising threshold(6) TJ_SHDN TJ rising 184 ºC Thermal shutdown hysteresis (6) 20 ºC NTC low temp rising threshold V COLD As percentage of V VNTC 70.9 71.5 72.1 % NTC low temp rising threshold hysteresis As percentage of V VNTC 1.4 % NTC cool temp rising threshold VCOOL As percentage of V VNTC 68.6 69.2 69.8 % NTC cool temp rising threshold hysteresis As percentage of V VNTC 1.3 % NTC warm temp falling threshold VWARM As percentage of V VNTC 55.9 56.5 57.1 % NTC warm temp falling threshold hysteresis As percentage of V VNTC 1.4 % NTC hot temp falling threshold V HOT As percentage of V VNTC 47.9 48.5 49.1 % NTC hot temp falling threshold hysteresis As percentage of V VNTC 1.3 % NOTE: 6) Guaranteed by design.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 10 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units VREF LDO VREF LDO output voltage V IN = 10V, IVREF = 40mA 4.82 5 V V IN = 5V, IVREF = 20mA 4.8 VREF LDO current limit V VREF = 4V 50 mA OTG Boost Mode Battery operating range V BATT OTG 2.5 4.5 V Battery discharge current I BATT_OTG VIN < VIN_UVLO, VBATT_OTG = 4.2V, battery FET is off 20 μA VIN < VIN_UVLO, VBATT_OTG = 4.2V, battery FET is on 35 μA OTG output voltage V IN OTG I OTG = 0A 5.15 V OTG output voltage accuracy As percentage of VIN_OTG, IOTG = 0A. -2 2 % Battery operation UVLO V BATT UVLO V BATT falling 2.5 V Battery operation UVLO hysteresis 200 mV OTG output voltage protection threshold VOTG_OVP VBATT = 3.7V, OTG is enabled, force a voltage at IN until switching is off 5.75 V OTG output voltage protection threshold hysteresis 175 mV OTG output current limit [I2C] I OLIM REG02[1:0] = 00, VBATT = 3.7V 0.5 0.6 0.7 A REG02[1:0] = 01, VBATT = 3.7V 1.3 1.5 1.7 DP/DM USB Detection DP voltage source V DP SRC 0.5 0.6 0.7 V Data connect detect current source IDP_SRC 7 13 μA DM sink current I DM SINK 50 100 150 μA Leakage current input DP/DM IDP LKG -1 1 μA IDM LKG -1 1 μA Data detect voltage V DAT REF 0.25 0.4 V Logic low V LGC LOW 0.8 V Session valid to connect time for powered up peripheral 45 mins
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 11 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Logic I/O Characteristics Low logic voltage threshold V L 0.4 V High logic voltage threshold V H 1.3 V I2C Interface (SDA, SCL) Input high threshold level VPULL UP = 1.8V, SDA and SCL 1.3 V Input low threshold level VPULL_UP = 1.8V, SDA and SCL 0.4 V Output low threshold level I SINK = 5mA 0.4 V I2C clock frequency F SCL 400 kHz Digital Clock and Watchdog Timer Digital clock 1 F DIG1 VREF LDO enabled 1400 1700 2000 kHz Digital clock 2 F DIG2 39 kHz Watchdog timer t WDT REG05 [5:4] = 11 160 s
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 12 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. VBATT 1V/div. VSYS 1V/div. CHGOK 2V/div. IBATT 2A/div. VBATT 1V/div. VSYS 1V/div. CHGOK 2V/div. IBATT 2A/div. VSW 1V/div. VSYS 1V/div. IL 1A/div. IBATT 200mA /div. VSW 2V/div. VSYS 1V/div. IL 2A/div. IBATT 2A/div. VSW 2V/div.VSYS 1V/div. IL 1A/div.IBATT 1A/div. Battery Charge Curve VIN=5V, ISYS=0A Auto Recharge VIN=5V, ISYS=0A Trickle Charge Steady State VIN=5V, VBATT=2.8V Constant Current Charge Steady State VIN=5V, VBATT=3.6V Constant Voltage Charge Steady State VIN=5V, VBATT=4.2V VSYS 1V/div. IBATT 2A/div. VIN 2V/div. VSW 2V/div. VBATT 1V/div. IL 1A/div. ISYS 2A/div. IIN 2A/div. COT Operation VIN=4.5V Input Current Limit VIN=5V, VBATT=4.2V, ICHG=3.5A IIN 1A/div. ISYS 2A/div. IBATT 500mA/div. VIN 1V/div. Input Voltage Limit VIN=5V/1.0A, VBATT=2.8V, ICHG=2A VSYS 1V/div. IBATT 200mA/div. VIN 2V/div. IL 1A/div. Power On VIN=5V, VBATT=3.7V
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 13 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, unless otherwise noted. IBATT 2A/div. IL 2A/div. VSYS 1V/div. VSYS 1V/div. IBATT 200mA/div. VIN 2V/div. IL 1A/div. VSW 5V/div. EN On VIN=5V, VBATT=3.7V Power Off VIN=5V, VBATT=3.7V VIN 1V/div. VSW 2V/div. VPMID 1V/div. IL 1A/div. VIN 1V/div. VSW 2V/div. VPMID 1V/div. IOTG 1A/div. VIN 1V/div. VSYS 1V/div. VBATT 1V/div. ISYS 2A/div. OTG Mode Start-Up VIN_OTG=5V,VBATT_OTG=3.6V, IOTG=1.3A OTG Output CC Mode VIN_OTG=5V,VBATT_OTG=3.6V, IOTG=1.3A Battery Discharge Current VIN=Float, ISYS=9A,VBATT=4.0V VDISC 2V/div. VBATT 1V/div. VSYS 1V/div. IBATT 1A/div. DISC Function VIN=Float, ISYS=1A,VBATT=4.2V VNTC 1V/div. VSYS 1V/div. IL 1A/div. IBATT 1A/div. VNTC 1V/div. VSYS 1V/div. IL 1A/div. IBATT 1A/div. NTC Function VIN=5V,VBATT=3.8V, ICHG=2A NTC Function VIN=5V,VBATT=3.8V, ICHG=2A VBATT 1V/div. VSYS 1V/div. CHGOK 2V/div. IBATT 2A/div. Battery Charge Curve VIN=9V, ISYS=0A
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 14 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM USB Port IN DP DM PMID SW BST SYS ILIM SDA CE OTG PGND AGNG STAT VSYS PWM Driver Linear Charge& Ideal Diode Control LD O VREF BATT Li-ion Battery Pack VNTC I2C + Logic Control + Non- Volatile Memory Power Control SCL NTC INT Syste m Output DISC NTC Protectio n 25mΩ 25mΩ 28mΩ 10mΩ Figure 1: Functional Block Diagram
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 15 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. OPERATION Introduction The MP2624 is a highly integrated I 2C controlled switching-mode battery charger IC with NVDC power path management for single-cell lithium- ion or lithium-polymer battery applications. The MP2624 integrates a reverse blocking FET, a high-side switching FET, a low-side switching FET, and a battery FET between SYS and BATT. Its low impedance and high efficiency allows higher current (4.5A) capacity for a given package size. Power Supply The internal bias circuit of the MP2624 is powered from the higher voltage of V IN and VBATT. When V IN or V BATT rises above the respective UVLO threshold, the sleep comparator, battery depletion comparator, and the battery FET driver are active; the I 2C interface is ready for communication and all the registers are reset to the default value. The host can access all the registers. Input Power Status Indication The MP2624 qualifies the voltage and current of the input source before start-up. The input source has to meet the following requirements: 1. V IN > VBATT + 250mV 2. V IN_UVLO < VIN 3. OTG is not enabled by host Once the input power source meets the conditions above, the syst em status register REG08 Bit [2] asserts that the input power is good, and the DP/DM detection starts (if enabled). Then the step-down converter is ready to operate. The conditions above are monitored continuously, and the charge cycle is suspended if a condition is outside one of the limits (see Figure 2). or DC/DC Battery FET DC/DC Rails Backlighting 3G Module Charger IC or or DC/DC Battery FET DC/DC Rails Backlighting 3G Module Charger IC Figure 2: NVDC Power Path Management Structure Narrow VDC Power Structure The MP2624 employs a narrow VDC (NVDC) power structure with the battery FET decoupling the system from the battery, thus allowing separate control between the system and the battery. The system is always given priority to start-up even with a deeply-discharged or missing battery. When the input power is available (even with a depleted battery), the system voltage is always above the preset minimum system voltage (V SYS_MIN) set by the I 2C register REG01 Bit [3:1]. As depicted in Figure 2, the NVDC power structure is composed of a front-end, step-down DC/DC converter and a battery FET between SYS and BATT. The DC/DC converter is a 1.5MHz step-down switching regulator adopting constant-off-time (COT) control to provide power to the system, which drives the system load directly and charges the battery through the battery FET. For system voltage control: (1) A minimum system voltage (V SYS_MIN) can be set via the register REG01 Bit [3:1]. When the battery voltage is lower than V SYS_MIN + 60mV, the system voltage is regulated at Max (V SYS_MIN, V BATT) + ∆V, and the battery FET works linearly to charge the battery with trickle-charge, pre-charge, or fast-charge current through the battery FET, depending on the battery voltage. ∆V can be set to 50mV or 100mV via the I 2C register REG01 Bit [0]. (2) When the battery voltage exceeds V SYS_MIN + 60mV, the system voltage tracks the battery voltage with a voltage differential of ICHGRBATFET, where the R BATFET is the on resistance of the battery FET. (3) When the charging is suspended or completed, the system voltage is regulated at ∆V higher than Max (V SYS_MIN, VBATT). ∆V can be set to 50mV or 100mV via the I 2C register REG01 Bit [0].
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 17 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Trickle charge Charge Current Pre-charge Constant Voltage ChargeCC Fast Charge Charge Full VBATT_FULL VBATT_PRE VBATT_SHORT ITC IBF IPRE ICHG VSYS_MIN System Voltage Figure 4: Battery Charge Profile During the entire charging process, the actual charge current may be less than the register setting due to other loop regulations like dynamic power management (DPM) regulation (input current limit or input voltage regulation loop), or thermal regulation. Thermal regulation reduces the charge current, so the IC junction temperature does not exceed the pre-set limit. The multiple thermal regulation thresholds (from 60ºC to 120ºC) help system design meet thermal requirements for different applications. The junction temperature regulation threshold can be set via the REG06 Bit [1:0]. A new charge cycle starts when the following conditions are valid: The input power is re-plugged. Battery charging is enabled by I 2C, and CE is forced to a low logic. No thermistor fault. No safety timer fault. No battery over voltage. The BATT FET is not forced to turn off. Automatic Recharge When the battery is charged full or the charging is terminated, the battery may be discharged because of the system consumption or self- discharge. When the battery voltage is discharged below the recharge threshold, automatically the MP2624 starts a new charging cycle. CE Control CE is a logic input pin for enabling or disabling battery charging by turning on/off the DC/DC or restarting a new charging cycle. The battery charging is enabled when the REG01 Bit [5:4] is set to 01, and CE is pulled to low logic. Indication Apart from multiple status bits designed in the I2C registers, the MP2624 also has a hardware status output pin (STAT ). The status STAT in different states is shown in Table 1. Table 1: Operation Indications Charging State STAT Charging Low Charging complete, sleep mode, charge disable High Charging suspended Blinking at 1Hz Battery Over-Voltage Protection The MP2624 is designed with built-in battery over-voltage protection. When the battery voltage exceeds V BATT_FULL + 160mV, the MP2624 suspends immediately the charging and asserts a fault. When battery over-voltage protection occurs, only the charging is disabled, and the DC/DC will keep operating.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 19 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Battery Dectection Sink 3mA for 1.5s VBATT < 2.1V? Source 3mA, Start 1s Timer VBATT > 3.6V? Battery Absent Yes Yes Source 3mA for 1s Set the V SYS to Max (VSYS_MIN, VBATT) + 50mV or 100mV Charge Start Battery PresentNo Battery Present No Disable 3mA Source Current 1s Timer Expired? Yes No 1s Timer Expired? Yes No Set the VSYS to VBATT _FULL+ 50mV or 100mV Disable Charge Battery Present As Default 1. EnChg 2. Auto-recharge 3. Battery OVP Recover Figure 6: Battery Float Detection Flow
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 20 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Input Voltage Based and Input Current Based Power Management To meet the maximum current limit for the USB specification and avoid overloading the adapter, the MP2624 features both input current and input voltage power management by continuously monitoring the input current and input voltage. The total input current limit is programmable to prevent the input source from being overloaded. When the input current hits the limit, the charge current tapers off to keep the input current from increasing further. If the pre-set input current limit is higher than the rating of the adapter, the back-up input voltage based power management works to prevent the input source from being overloaded. When the input voltage falls below the input voltage regulation threshold, due to the heavy load, the charge current is reduced to keep the input voltage from dropping further. During CV mode, while battery voltage has been charged to the value only 100mV lower than the battery full threshold, if the power path management happens and charge current drops be lower than I BF, the charge full will be fault detected. The operation of the power path management is applied in the following two cases: As mentioned in the “NVDC Power Structure” section, a) When V BATT < V SYS_MIN + 60mV, the system voltage is regulated at Max (V SYS_MIN, VBATT) + ∆V. If the input current or voltage regulation threshold is reached, the system voltage loop will lose the control of the DC/DC converter, which will cause system voltage drops. Once the system voltage drops by 2% V SYS_MIN, the charge current will be decreased to keep the system voltage from dropping further. b) When V BATT > V SYS_MIN + 60mV (since the battery is connected to the system directly due to the free transition between each control loop), the charge current will decrease automatically when the input current limit or the voltage regulation threshold is reached. Battery Supplement Mode During battery supplement mode, the charge current is reduced to keep the input current or input voltage from dropping when DPM occurs. If the input source is still overloaded, even when the charge current has decreased to zero, the system voltage starts to fall off. Once the system voltage falls below the battery voltage, the MP2624 enters battery supplement mode. The battery will power both the system and the DC/DC converter simultaneously. An ideal diode mode is designed in the MP2624 to optimize the control transition between the battery FET and DC/DC converter. The battery FET will enter ideal diode mode under the following conditions: a) Charging start-up when V BATT > VSYS_MIN + ∆V. b) When V BATT < V SYS_MIN + ∆V, if the system voltage drops below the battery voltage, the battery FET will enter ideal diode mode. During ideal diode mode, the battery FET operates as an ideal diode. When the system voltage is 40mV below the battery voltage, the battery FET turns on and regulates the gate drive of the battery FET; the V DS of the battery FET remains around 20mV. As the discharge current increases, the battery FET obtains a stronger gate drive and a smaller RDS until the battery FET is fully on. NTC (Negative Temperature Coefficient) Thermistor “Thermistor” is the generic name given to a thermally sensitive resistor. Generally, a negative temperature coefficient thermistor is called a thermistor. Depending on the manufacturing method and the structure, there are many thermistor shapes and characteristics for various applications. The thermistor resistance values, unless otherwise specified, are classified at a standard temperature of 25ºC. The resistance of a temperature is solely a function of its absolute temperature. Refer to the thermistor datasheet. The mathematical expression, which relates to the resistance and the absolute temperature of a thermistor, is shown in Equation (1): T1 T2 12RR e Where R1 is the resistance at the absolute temperature T1, R2 is the resistance at the
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 22 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Check VBUS VBUS>3.8V? No Start 500ms Timer Enable IDP_SRC (10µA) Connect RDM_PULL_DOWN (20kΩ) DP< VDAT_REF(0.325V) for 40ms? 500ms Timer Expires? No Yes No Primary Detection Enable VDP_SRC (0.6V) Enable IDM_SINK (50µA) DM< VDAT_REF(0.325V) after 56ms? Yes Release DP/DM, set IIN_LMT at 100mA (OTG=Low) 500mA(OTG=High) DCD Yes Release DP, DM Yes DM/DP Floating Release DP/DM, set IIN_LMT at 100mA No Release DP/DM, set IIN_LMT at 1800mA Figure 9: USB Detection Flow Chart
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 24 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. When the detection algorithm is complete, the DP and DM signal lines enter a high-Z (HZ) state with an approximate 4pF capacitive load. Input Current Limit Setting via ILIM For safe operation, the MP2624 has an additional hardware pin (ILIM) to adjust the maximum input current limit. It can be set by a resistor connected from ILIM to GND. The actual input current limit is the lower value between the ILIM setting and the register setting value via I 2C. Interrupt to Host (INT) The MP2624 has an alert mechanism, which can output an interrupt signal via INT to notify the system of the operation by outputting a 256 μs low state INT pulse. All of the events below trigger the INT output: Good input source detected USB detection completed UVLO Charge completed Any fault in REG09 (Watchdog timer fault, OTG fault, thermal fault, safety timer fault, battery OVP fault, and NTC fault) When a fault occurs, the charger device sends out an INT signal and latches the fault state in REG09 until the host reads the fault register. Before the host reads REG09, the charger device will not send a new INT signal upon new faults except for NTC faults. The NTC fault is not latched and always reports the current thermistor conditions. In order to read the current fault status, the host has to read REG09 two times consecutively. The st reads the fault register status from the last INT, and the 2nd reads the current fault register status. Safety Timer The MP2624 provides both a pre-charge and complete charge safety timer to prevent an extended charging cycle due to abnormal battery conditions. The total safety timer for both trickle charge and pre-charge is 1 hour when the battery voltage is lower than V BATT_PRE. The complete charge safety timer starts when the battery enters constant-current charge. The constant- current charge safety timer can be programmed by I 2C. The safety timer feature can be disabled via I2C. The safety timer does not operate in USB OTG mode. The safety timer is reset at the beginning of a new charging cycle. Also, it can be reset by toggling CE or write 00 and 01 sequentially to the REG01 Bit [5:4]. The following actions restart the safety timer: A new charge cycle has begun. Toggling CE from low to high to low (charge enable) Write REG01 Bit [5:4] from 00 to 01 (charge enable) Write REG05 Bit [3] from 0 to 1 (safety timer enable) Write REG01 Bit [7] from 0 to 1 (software reset) The timer can be refreshed after timer out when one of the following thing happens: The input power reset. Toggling CE from low to high to low (charge enable). Writing REG01 Bit[5:4] from 00 to 01 (charge enable). MP2624 adjusts automatically or suspends the timer when a fault occurs. The timer is suspended during the conditions below: The battery is discharging System OVP occurs NTC hot or cold fault If the input current limit, input voltage regulation, or thermal regulation threshold is reached, the rest of the timer is doubled by enable the 2X timer in PPM function (REG07H Bit[6]=1). Once the PPM operation is removed, the rest of the timer returns to the original setting. This setting may cause an application issue, if the IC operates in and out of PPM frequently, the single timer period will be divided, which causes false timer out termination. The solution is to disable the 2X timer function by set REG07H Bit[6] to 0.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 31 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Figure 23: Multi Read If the register address is not defined, the charger IC sends back NACK and returns to an idle state. The charger device supports multi-read and multi-write on REG00 through REG08. The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if the charge safety timer expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time; it returns to normal when it is read the second time. To verify a real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write. REG09 is a fault register. It keeps all the fault information from the last read until the host issues a new read. For example, if there is a TS fault but it is recovered immediately, the host still sees the TS fault during the first read. In order to get the present fault information, the host has to read REG09 for the second time. REG09 does not support multi-read and multi-write.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 32 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. I2C REGISTER MAP IC Address: 4BH Input Source Control Register/ Address: 00H (Default: 0011 0000) Bit Symbol Description Read/ Write Default Bit 7 EN _HIZ(7) 0 – Disable, 1 – Enable Read/ Write Default: Disable (0) Input Voltage Regulation Bit 6 V IN_REG [3] 640mV Read/ Write Offset: 3.88V Range:3.88V – 5.08V Default: 4.36V (0110) Bit 5 V IN_REG [2] 320mV Bit 4 V IN_REG [1] 160mV Bit 3 V IN_REG [0] 80mV Input Current Limit Bit 2 I IN_LMT [2] 000 – 100mA 001 – 150mA 010 – 500mA 011 – 900mA 100 – 1200mA 101 – 1800mA 110 – 2000mA 111 – 3000mA Read/ Write Default: SDP: 100mA (000) or 500mA (010) Default: DCP/CDP: 1.8A (101) Bit 1 I IN_LMT [1] Bit 0 I IN_LMT [0] Power-On Configuration Register / Address: 01H (Default: 0001 1011) Bit Symbol Description Read/ Write Default Bit 7 Register reset 0 – Keep current setting 1 - Reset Read/ Write Keep current register setting (0) Bit 6 I 2C watchdog timer reset 0 – Normal 1 – Reset Read/ Write Normal (0) Charger Configuration Bit 5 Mode [1] 00 – Charge disable 01 – Charge battery 10/11 – OTG, Read/ Write Charge battery (01) Bit 4 Mode [0] Minimum System Voltage Bit 3 V SYS_MIN [2] 0.4V Read/ Write Offset: 3V Range: 3V – 3.7V Default: 3.6V (110) Bit 2 V SYS_MIN [1] 0.2V Bit 1 V SYS MIN [0] 0.1V System Regulation Voltage Higher than Full Battery Voltage Bit 0 V SYS_MAX [0] 0 – 50mV 1 – 100mV Read/ Write Default: 100mV (1) NOTE: 7) This is used to turn off the DC/DC only. At this time, the system is powered by the battery.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 33 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Charge Current Control Register/ Address: 02H (Default: 0010 0001) Bit Symbol Description Read/ Write Default Bit 7 I CHG [5] 2048mA Read/ Write Offset: 512mA Range: 512mA – 4544mA Default: 1024mA (001000) Bit 6 I CHG [4] 1024mA Bit 5 I CHG [3] 512mA Bit 4 I CHG [2] 256mA Bit 3 I CHG [1] 128mA Bit 2 I CHG [0] 64mA USB OTG Current Limit Bit 1 I OLIM[1] 00 – 500mA 01 – 1.3A Read/ Write 1.3A (01) Bit 0 I OLIM[0] Pre-Charge/ Termination Current/ Address: 03H (Default: 0011 0011) Bit Symbol Description Read/ Write Default Pre-Charge Current Bit 7 I PRE [3] 512mA Read/ Write Offset: 64mA Range: 64mA – 1024mA Default: 256mA (0011) Bit 6 I PRE [2] 256mA Bit 5 I PRE [1] 128mA Bit 4 I PRE [0] 64mA Termination Current Bit 3 I BF [3] 512mA Read/ Write Offset: 64mA Range: 64mA – 1024mA Default: 256mA (0011) Bit 2 I BF [2] 256mA Bit 1 I BF [1] 128mA Bit 0 I BF [0] 64mA
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 34 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Charge Voltage Control Register/ Address: 04H (Default 1100 0011) Bit Symbol Description Read/ Write Default Charge Full Voltage Bit 7 V BATT_FULL [5] 480mV Read/ Write Offset: 3.48V Range: 3.48V – 4.425V Default: 4.2V (110000) Bit 6 V BATT FULL [4] 240mV Bit 5 V BATT_FULL [3] 120mV Bit 4 V BATT_FULL [2] 60mV Bit 3 V BATT_FULL [1] 30mV Bit 2 V BATT_FULL [0] 15mV Pre-Charge Threshold Bit 1 V BATT_PRE 0 – 2.8V 1 – 3.0V Read/ Write 3.0V (1) Battery Recharge Threshold (below VBATT_FULL) Bit 0 V RECH 0 – 200mV 1 – 100mV Read/ Write 100mV (1) Charge Termination/Timer Control Register / Address: 05H (default: 1001 1000) Bit Symbol Description Read/ Write Default Termination Setting Bit 7 EN_BF 0 – Disable 1 – Enable Read/ Write Enable (1) Termination Indicator Threshold Bit 6 BF_STAT 0 – Match IBF 1 – Indicate before the actual termination on START Read/ Write Match I BF (0) I2C Watchdog Timer Limit Bit 5 WATCHDOG [1] 00 – Disable timer 01 – 40s 10 – 80s 11 – 160s Read/ Write 40s (01) Bit 4 WATCHDOG [0] Safety Timer Setting Bit 3 EN_TIMER 0 – Disable 1 – Enable Read/ Write Enable timer (1) Constant-Current Charge Timer (2x during PPM) Bit 2 CHG _TMR [1] 00 – 5hrs 01 – 8hrs 10 – 12hrs 11 – 20hrs Read/ Write 5hrs (00) Bit 1 CHG _TMR [2] Bit 0 Reserved Read/ Write (0)
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 35 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Compensation/ Thermal Regulation Control Register / Address: 06H (Default: 0000 0011) Bit Symbol Description Read/ Write Default Bit 7 R BAT_CMP [2] 40m Ω Read/ Write Range: 0 – 70mΩ Default: 0mΩ (000) Bit 6 R BAT_CMP [1] 20m Ω Bit 5 R BAT CMP [0] 10m Ω Battery Compensation Voltage Clamp (above VBATT_FULL) Bit 4 V CLAMP [2] 64mV Read/ Write Range: 0 – 112mV Default: 0mV (000) Bit 3 V CLAMP [1] 32mV Bit 2 V CLAMP [0] 16mV Thermal Regulation Threshold Bit 1 T REG [1] 00 – 60ºC 01 – 80 ºC 10 – 100 ºC 11 – 120ºC Read/ Write Default: 120ºC (11) Bit 0 T REG [0] Miscellaneous Operation Control Register/ Address: 07H (Default: 0101 1011) Bit Symbol Description Read/ Write Default Bit 7 USB_DET_EN 0 – Not in DP/DM detection 1 – Force DP/DM detection Read/ Write Not in DP/DM detection (0) Bit 6 TMR2X_EN 0 – Disable 2x extended safety timer 1 – Enable 2x extended safety timer Read/ Write Enable (1) Bit 5 BATFET_DIS 0 – Enable 1 – Turn off Read/ Write Enable (0) Bit 4 Reserved Read/ Write (0) Bit 3 EN_NTC 0 – Disable 1 – Enable Read/ Write Enable (1) Bit 2 BATUVLO_DIS 0 – Enable 1 – Disable Read/ Write (0) Bit 1 INT_MASK [1] 0 – No INT during CHG_FAULT 1 – INT in CHG_FAULT Read/ Write INT in CHG_FAULT (1) Bit 0 INT_MAST [0] 0 – No INT during BAT_FAULT 1 – INT in BAT_FAULT Read/ Write INT in BAT_FAULT (1)
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 36 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. System Status Register/ Address: 08H (Default: 0000 0001) Bit Symbol Description Read/ Write Default Bit 7 V BUS_STAT [1] 00 – Unknown 01 – Adaptor port 10 – USB host 11 – OTG Read only Unknown (00) (Including no input or DPDM detection incomplete) Bit 6 V BUS_STAT [0] Bit 5 CHG_STAT [1] 00 – Not charging 01 – Trickle charge 10 – Constant-current charge 11 – Charge done Read only Not charging (00) Bit 4 CHG_STAT [0] Bit 3 PPM_STAT 0 – No PPM 1 – VINPPM or IINPPM Read only No PPM (0) (No power path management occurs) Bit 2 PG_STAT 0 – No power good 1 – Power good Read only No power good (0) Bit 1 THERM_STAT 0 – Normal 1 – Thermal regulation Read only Normal (0) Bit 0 VSYS_STAT 0 – In VSYSMIN regulation 1 – Not in VSYSMIN regulation Read only Not in VSYSMIN regulation (1) Fault Register/ Address: 09H (Default: 0000 0000) Bit Symbol Description Read/ Write Default Bit 7 WATCHDOG_F AULT 0 – Normal 1 – Watchdog timer expiration Read only Normal (0) Bit 6 OTG_FAULT 0 – Normal 1 – VBUS overloaded, VBUS OVP, or battery under voltage Read only Normal (0) Bit 5 CHG_FAULT [1] 00 – Normal 01 – Input fault (bad source) 00 – Thermal shutdown 11 – Safety timer expiration Read only Normal (00) Bit 4 CHG_FAULT [0] Bit 3 BAT_FAULT 0 – Normal 1 – Battery OVP Read only Normal (0) Bit 2 NTC_FAULT [2] 000 – Normal 001 – NTC cold 010 – NTC cool 011 – NTC warm 100 – NTC hot Read only Normal (000) Bit 1 NTC_FAULT [1] Bit 0 NTC_FAULT [0]
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 37 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Vender/ Part/ Reversion Status Register/ Address: 0AH (Default: 0000 0100) Bit Symbol Description Read/ Write Default Bit 7 Reserved Read only (0) Bit 6 Reserved Read only (0) Part Number Bit 5 PN [2] MP2624 (000) Read only (000) Bit 4 PN [1] Bit 3 PN [0] Bit 2 NTC_TYPE 0 – Standard 1 – JEITA Read only (1) Revision Bit 1 Rev [1] Read only (00) Bit 0 Rev [0]
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 38 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. CONTROL FLOW CHART Different Operations in Host Mode
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 39 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. CONTROL FLOW CHART (continued) Charging Process vSYS= Max (VSYS_MIN, vBATT) + ∆V Done? No Charger Enabled by /CE? Charger Enabled by Host? No No Yes Yes Yes vSYS= Max (VSYS_MIN, vBATT) + ∆V ∆V=50mV or 100mV depending on I2C Setting Battery Present or Not?vSYS= VBATT_FULL + ∆V Yes No
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 40 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. CONTROL FLOW CHART (continued) Charging Process Charging Start Charge Mode? VBATT>VBATT_GDICHG<IBF ? Charger “Off”, Indicate battery full vSYS = vBATT + ∆V CV Charge Battery FET On vSYS=VBATT_FULL+ ICHG*RBATFET CC Charge vSYS=VSYS_MIN + ∆V TC Charge vSYS=VSYS_MIN + ∆V vBATT< VRECH ? VBATT_TC < VBATT < VBATT_GDVBATT = VBATT_FULL Yes No Yes Yes Wake Up vSYS=VSYS_MIN + ∆V VBATT>VBATT_SC ? VBATT <VBATT_SCVBATT < VBATT_TC NoNo Yes VBATT=VBATT_FULL? CC Charge Battery FET On vSYS=vBATT + ICHG*RBATFET No VBATT_GD < VBATT < VBATT_FULL Yes ∆V=50mV or 100mV depending on I2C Setting VBATT>VBATT_TC ? NoNo Yes
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 41 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Input Current Limit The input current limit setting is set according to the input power source. For an adapter input, the input current limit can be set through I 2C by the GUI. To set a value that is not provided by the I 2C, the input current limit can be set through ILIM. Connect a resistor from ILIM to AGND to program the input current limit. The relationship is calculated using Equation (3): ）（）（ AkRI ILIM IN_LMT 48.48 (3) The MP2624 selects the lower one of the I 2C and resistor setting for its input current limit setting. For resistor setting, use 1% accuracy resistor. For a USB input, the input current limit is set according to Table 2. Selecting the Inductor Inductor selection is a trade off between cost, size, and efficiency. A lower inductance value corresponds to a smaller size, but it results in a higher ripple current, a higher magnetic hysteretic loss, and a higher output capacitance. Choosing a higher inductance value gives the benefit of a lower ripple current and smaller output filter capacitors, but it may result in higher inductor DC resistance (DCR) loss and larger size. From a practical standpoint, the inductor ripple current should not exceed 30% of the maximum load current under worst-case conditions. When operating with a typical 5V input voltage, the maximum inductor current ripple occurs at the corner point between the trickle charge and the CC charge (V BATT = 3V). Estimate the required inductance with Equation (4) and Equation (5): )(_ MHzfV V I VVL SIN BATT MAXL BATTIN (H) (4) ripple%1(II )MAX(LOADPEAK (A) (5) Where, V IN, V BATT, and f S are the typical input voltage, battery voltage, and switching frequency, respectively. ∆IL_MAX is the maximum inductor ripple current, which is usually 30% of the CC charge current. Although the maximum charge current can be set to a high 4.5A, the real charge current cannot reach this value as the input current limit. For most applications, allow a large enough margin to avoid hitting the peak current limit of the high- side switch (7A, typically). The maximum inductor current ripple is set to 1.0A with 5Vin (30% of the max load- about 3.5A considering the input current limit); the inductor is 0.75µH. Select 1.0µH in the application with the saturation current over 4.5A Select 1.0µH in the application with the saturation current over 4.5A Choose a larger inductance such as 2.2uH is good for the EMI consideration with smaller current ripple, while the size may be larger. Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low ESR electrolytic capacitors will suffice. Choose X5R or X7R dielectrics when using ceramic capacitors. Since the input capacitor (C IN) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (6): IN OUT OUT CL O A D IN IN VVII 1 VV (6) Where, VOUT is VSYS. The worst-case condition occurs at V IN = 2V OUT, where ICIN = ILOAD/2. For simplification, choose the input capacitor with a RMS current rating greater than half of the maximum load current. For the MP2624, the RMS current in the input capacitor comes from PMID to GND, so a small, high-quality ceramic capacitor (e.g., 4.7 μF), should be placed as close to the IC as possible from VPMID to PGND. The remaining capacitor should be placed from VIN to GND.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 42 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. When using ceramic capacitors, make sure they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at the input. Selecting the Output Capacitor The output capacitor C SYS from the typical application circuit is in parallel with the SYS load. CSYS absorbs the high-frequency switching ripple current and smoothes the output voltage. Its impedance must be much less than the system load to ensure it properly absorbs the ripple current. Use a ceramic capacitor because it has a lower ESR and a smaller size. This allows the ESR of the output capacitor to be ignored. Thus, the output voltage ripple is given with Equation (7): SYS SYS IN SYS SYS S V1V Vr% V8 C f L (7) In order to guarantee ±0.5% system voltage accuracy, the maximum output voltage ripple maximum output voltage ripple occurs at the minimum system voltage and the maximum input voltage. For V IN = 7V, V SYS_MIN = 3.6V, L = 2.2µH, f S = 1.6MHz, and r =0.1%. The output capacitor can be calculated as 11µF using Equation (8): SYS _ MIN IN SYS 2 S V1 VC 8f L r (8) Then, choose a 22µF ceramic capacitor. Resistor Selection for the NTC Sensor Figure 9 shows an internal resistor divider reference circuit that limits both the high and low temperature thresholds at V TH_High and V TH_Low, respectively. For a given NTC thermistor, select an appropriate R T1 and R T2 to set the NTC window using Equation (9) and Equation (10): T2 NTC_Cold TH_Low T1 T2 NTC_Cold NTC R/ / R V RR / / R V (9) TH_HighT2 NTC_Hot T1 T2 NTC_Hot VR/ / R R R //R VCC (10) RNTC_Hot is the value of the NTC resistor at a high temperature (within the required temperature operating range), and R NTC_Cold is the value of the NTC resistor at a low temperature. The two resistors (RT1 and RT2) allow the high and low temperature limits to be programmed independently. With this feature, the MP2624 can fit most types of NTC resistors and different temperature operating range requirements. R T1 and R T2 values depend on the type of the NTC resistor selected. For example, for a 103AT thermistor, the thermistor has the following electrical characteristics: At 0°C, R NTC_Cold = 27.28kΩ; at 60°C, RNTC_Hot = 3.02kΩ. The following equation calculations are derived assuming that the NTC window is between 0°C and 50°C. According to Equation (9) and Equation (10), use TH_Low NTC V V and TH_High NTC V V from the EC table to calculate R T1 = 2.27k Ω and R T2 = 6.86kΩ.
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 43 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PCB Layout Guidelines Efficient PCB layout is critical to meet specified noise rejection requirements and improve efficiency. For best results follow the guidelines below: 1) Route the power stage adjacent to the grounds. Aim to minimize the high-side switching node (SW, inductor) trace lengths in the high- current paths and the current sense resistor trace. 2) Keep the switching node short and away from all small control signals, especially the feedback network. 3) Place the input capacitor as close as possible to PMID and PGND. 4) Place the output inductor close to the IC and connect the output capacitor between the inductor and PGND of the IC. 5) For high-current applications, the pins for the power pads (IN, SW, SYS, BATT, and PGND) should be connected to as much copper on the board as possible. This improves thermal performance because the board conducts heat away from the IC. 6) Connect the PCB ground plane directly to the return of all components via holes. Also, it is recommended to place it, via holes, inside the PGND pads for the IC, if possible. Typically, a star ground design approach is used to keep circuit block currents isolated (high-power/low- power small signals), which reduces noise coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue; segregating the components minimizes coupling between the signals and stability requirements. 4) Pull the connection wire from the MCU (I 2C) far away from the SW mode and cooper regions. SCL and SDA should be closely in parallel.
4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Table 3. The BOM of the Key Components
1206 Any
1 C2 1μF Ceramic Capacitor;10V;
0603 Any
0805 Any
1 C6 470nF Ceramic Capacitor;16V;
2 C7,C8 22uF Ceramic Capacitor;10V;
1 RT1 10k Film Resistor;1% 0603 Any
1 RT2 15k Film Resistor;1%; 0603 Any
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2624 Rev.1.05 www.MonolithicPower.com 45 4/9/2018 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
PACKAGE INFORMATION
QFN-22 (3mm X 4mm) SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH . 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX . 4) JEDEC REFERENCE IS MO -220. 5) DRAWING IS NOT TO SCALE . PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID 0.20X0.10 0.20x0.10 0.10x45?