EVBUM2710D

EVBUM2710 ONSEMI | Alldatasheet

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© Semiconductor Components Industries, LLC, 2020 January, 2020 − Rev. 0

1 Publication Order Number:

Power Delivery 3.0 w/PPS and a 4-Switch Buck Boost Controller Evaluation Board User's Manual FUSB3307MX−PPS−GEVB (SOIC14 Package) FUSB3307MPX−PPS−GEVB* (QFNW20 Package) STR−FUSB3307MX−PPS−EVK* (SOIC14 with Strata Support) STR−FUSB3307MPX−PPS−EVK* (QFNW20 with Strata Support) Introduction The FUSB3307 evaluation board (GEVB), or kit (EVK), is a complete platform to evaluate the T ype−C interface detection and USB Power Delivery 3.0 solution the FUSB3307 provides. The EVB is designed for both stand−alone operation and connection to test equipment for specific testing requirements. Using a single DC power supply, the EVB functions as a source only port.

Description

The various FUSB3307 evaluation boards contain a USB T ype−C source controller supporting USB Power Delivery (PD) 3.0 with PPS (Programmable Power Supply) based on USB PD 3.0 standards, as well as a 4−stage buck boost controller, delivering VBUS levels from 3.3 V to 21 V , and supporting nominal current loads up to 5 A. The evaluation board has a VBAT connector for a DC power supply. It connects to the input switch of the NCV81599 DC to DC 4−Switch Buck Boost Controller. The FUSB3307 is used for CV/CC control by providing feedback compensation to the NCV81599 controller. Charging voltages and currents are measured by detecting VFB and the current sensing resistor. The sensed voltage and current feed to the compensation logic and then controls the CATH pin for constant voltage (CV) or constant current (CC) control. A 5 m /C0087 VBUS load sense resistor is assembled on the EVB. On the EVB, there are multiple test points for device validation. For example, VBUS and GND_SNS test points can be used for VBUS load testing. Key Features

• Wide Input V oltage Range 4.5 V ~ 32 V
• Wide Output V oltage Range 3.3 V ~ 21 V
• Type−C r1.4 / USB PD 3.0 v1.2 Compliant
• USB−IF TID # 1430
• Type−C Source Only
• Detects Cable Marker Identity and offers 3 A or 5 A Power Objects
• VCONN Supply
• CV/CC Control with CATH Pin
• On Board 5 m/C0087 Rsense Resistor
• Over−Current/Short−Circuit Protection (OCP)
• Auto−tuning OCP for Low Output V oltages
• Over−Temperature Protection (OTP)
• Over− and Under−Voltage Protection (OVP/UVP)
• Cable Fault Detection
• External NFET for VBUS Control
• Easily Accessible Test Points for Rapid Evaluation and Performance Measurements www.onsemi.com EVAL BOARD USER’S MANUAL

Figure 1. Evaluation Board Photo

Figure 4. VBAT Input Filter and Type−C Receptacle

www.onsemi.com Descriptions for the Evaluation Board Test Points VBAT VBA T is the input DC voltage to power the evaluation board. It must be between 4.5 V and 32 V . V_IN V_IN is the same as VBAT after the input filter. VCC VCC on the evaluation board is VCC for the NCV81599. It is not the same as VCC for the FUSB3307. This is a constant 5V output from the NCV81599 when VBAT is applied. VBUS VBUS, which is also the same as VCC for the FUSB3307, is the device operating power from primary side. The default initial VCC of the FUSB3307 is 5 V (typical), with a valid range of 4.5 V to 5.5 V . The CATH pin is controlled to keep VCC in the valid range. The FUSB3307 VCC voltage sensing is used for OVP and UVP with an internal 1:9 resistor divider. The FUSB3307 VCC is also used for the FUSB3307 VCC current discharge function through an internal resistance, 22~25 /C0087, when it’s needed. After an explicit contract is established, the valid FUSB3307 VCC can be in the range of 3.3 V−5% (3.135 V) up to 21 V+5% (22.05 V) for the case of USB PD PPS contracts. VDD VDD is the internal 5 V regulator output from the FUSB3307, and an external 1 uF capacitor is required. The VDD is used for internal device power as well as VCONN supply when needed. VBUSOUT VBUSOUT is VBUS between the external NFET load switch and the Type−C receptacle and is also where a recommended external resistor, typically 39 /C0087, is tied to the DISC pin for the VBUS discharge path. An internal path has 22 to 23 /C0087 in series with a switch. GND Evaluation board and device GND which is tied together with IS−. The IS− pin is tied to the FUSB3307 side of the current sense resistor. IS+ connects to ground sense return path, GND_SNS, from the Type−C receptacle. GND_SNS This is the return ground sense path from the T ype−C receptacle. IS+ connects to this ground sense return path for sensing the sink load current. IFB This is a constant current amplifying signal. The voltage level on this point is the amplified current sense signal. This pin connects to the internal CC loop amplifier’s non−inverting input terminal. Externally, the pin connects to the FUSB3307 VCC through a capacitor and resistor network, which contributes to the CATH pin current ramp. VFB This is the output voltage sensing voltage. This pin is for CV regulation, and connects to the internal CV loop amplifier non−inverting input terminal. Externally, it is tied to the output voltage resistor divider (1:10) on the evaluation board, where there is a 120 k/C0087 pull up to VCC and a 13.3 k/C0087 pull down to GND, creating the 1:10 divider. SFB The SFB test point is the CATH pin for the FUSB3307. CA TH is the feedback signal to the primary controller. It connects to the comp pin of the NCV81599. CATH pin is open−drain output and controlled by CV/CC logic in the FUSB3307. CC1, CC2 Configuration Channel 1 and 2, these pins are used to detect USB Type−C devices and to communicate using USB PD communication protocol when applicable. Also used for VCONN supply. For USB PD, the maximum capacitance is limited to 600 pF. Descriptions of Other FUSB3307 Pins that do not have Test Points on the Evaluation Board GATE Gate drive signal to drive the gate of external NFET load switch. Using an internal charge pump, the external NFET gate is controlled using this pin. The source power of the charge pump is from FUSB3307 VCC. IS+, IS− Current sensing amplifier positive/negative terminals. IS+ is connected to the GND_SNS return path of the Type−C receptacle. IS− connects to the device GND pin. Charging current is calculated as: the voltage on IS+ is divided by Rsense (i.e. 5 m/C0087) and then amplified 40 times, which will be actual sense current. The sense resistor needs to be 5 m/C0087. D−, D+ D−, D+ can be used for multiple purposes by the FUSB3307. The default programmed function is for BC1.2 functionality, used for signaling of BC1.2 host operation. Another option for these pins’ function is for maximum power control: PDIV0 and PDIV1. This mode is controlled by programming (fuse trimmed during production). The QFNW package has a PDIV2 pin which can limit the total power by 50%. See the FUSB3307 datasheet for a full description of the PDIV0, PDIV1, and PDIV2 functionality.

www.onsemi.com Descriptions of Jumpers, Connectors on the Evaluation Board P3, P4, and P5 If the FUSB3307 device mounted on the evaluation board is programmed to support PDIV0, PDIV1, or PDIV2, then the P3, P4, and P5 jumpers permit shorting any of the three PDIVn signals to GND. Leaving the jumper open allows the signal to be pulled up to VDD via R52, R53, or R45. Note that R52 and R53 are not populated by default, so if a custom FUSB3307 device is used with PDIV0, PDIV1 functionality, R52 and R53 need to also be populated with 10 k /C0087 resistors. See the FUSB3307 datasheet for a full description of the PDIV0, PDIV1, and PDIV2 functionality. This two pin connector is used for supplying VBAT and GND to the evaluation board. This 16 pin header is used for attaching the optional Strata controller daughter card to the evaluation board. The Type−C receptacle. Descriptions of Key Features VCC OVP (Over−Voltage Protection) VCC voltage is measured by an ADC with 1/10 th VCC voltage. Since the VCC range is wide, between 3.3 V ~ 21 V, VCC OVP voltage threshold is defined in the datasheet as 121% of the PD contract voltage. There is a maximum OVP spec (23.8V Typ) which governs in general. So, in the case of a 5 V PD contract, the OVP trigger point is 6.05 V and so on for other PD contract voltages. For a 20 V PD contract, the OVP will be triggered by either the 121% (24.2 V) trigger point or the maximum OVP spec (23 V min / 23.8 V Typ / 24.8 V max). Once an OVP Fault is triggered, VBUS will be shut off (external NFET off) and so the sink will be disconnected. Also, the CATH signal will drop to GND to recover VCC back to 5 V . There will be no PD Alert message transmitted to the sink device caused by the OVP Fault, which is different from OCP or OTP Faults. If an OTP or OCP Fault happens, there is a PD Alert message sent to the attached sink device. When VBUS voltage is changing because of a PD contract change, the OVP is disabled during the transition time which is called OVP blanking time, typically 221 ms. CC OVP (Over−Voltage Protection) In the Type−C receptacle, there could be a chance to short between VBUS and either CC signal. The FUSB3307 has high voltage protection for this case. The threshold is 6.5 V Typ with 28 /C0109s debounce. VCC UVP (Under−Voltage Protection) Like OVP, another protection is UVP which is the case when the VCC voltage drops blow the spec, which is 65% of contract voltage. For example, at VBUS of 5 V , the UVP trigger point is 3.25 V . There is the same blanking time of 221 ms during any VBUS voltage transition. Once UVP occurs, there is a PD Alert message sent to the sink device. VCC OCP (Over−Current Protection) The FUSB3307 senses the VBUS load current via a small Rsense resistor (5 milliohm) as described in the datasheet. The OCP fault is triggered at 120% of the maximum current for the requested Power Data Object (PDO) for fixed supplies only, typically 3.6A for a 3A maximum fixed supply current. For PPS APDOs (Augmented Power Data Objects), Constant Current Limiting (CL) is used as specified in the USB PD specification where the voltage will drop to a low value based on keeping the current constant and equal to the requested PPS current. More details can be found in the FUSB3307 datasheet. Once an OCP Fault is triggered, VBUS will be shut off (external NFET off) and so the sink will be disconnected. Also, the CATH signal will drop to GND to recover VCC back to 5V . There will be an OCP Fault happens, there is a PD Alert message sent to the attached sink device upon the FUSB3307 establishing an explicit contract with the sink device. OTP (Over−Temperature Protection) OTP is measured internally for the SOIC package. There are two different thresholds, 125C for a warning or 135C for a Fault. If the warning threshold is triggered longer then the OTP debounce time, typically 80 ms, a PD Alert message for the temperature warning will be sent to the sink. Once the Fault threshold is triggered, the FUSB3307 will disable the Type−C connection, shut off VBUS (external NFET off), and monitor the Fault. Once the Fault has been cleared, the FUSB3307 will wait a recovery time, typically 2 s, and then begin monitoring the CC lines for an attach. Upon re−establishing an explicit contract with the sink, a PD Alert message will be sent to let the sink know that the FUSB3307 previously experienced an OTP Fault. The QFNW package also has an NTC pin to monitor the external temperature. In the case of the QFNW package, only the external temperature will trigger a PD Alert for a warning. The NTC pin is connected to an NTC resistor (100 k/C0087 ±1%, B25/50 = 4300k ±1%) in parallel with a 20 k/C0087 resistor to GND. But, either the internal temperature threshold or the external temperature threshold can cause an OTP Fault. CATH feedback The CATH pin is used to provide feedback to the circuit providing VCC/VBUS to the FUSB3307. Typically an

60 W Efficiency

12 V , 15 V , and 20 V with load varying from 0.5 A to 3 A. Figure 9. Efficiency Curves Figure 10. 5 V Regulation Figure 11. 9 V Regulation

5 V , when there is a light load, less than 450 mA, or no load. presence unless VBUS is 5 V when the cable is unplugged. VBUS voltage when the internal discharge FET is turned on.

20 V to 5 V and the waveform in Figure 40 is when the

Figure 39. VBUS Discharge, from 20 V to 5 V, Figure 40. VBUS Discharge, from 20 V to 0 V, when voltage change, but, with a 500 mA load. Figure 41. VBUS Discharge, from 20 V to 15 V, Figure 42. VBUS Discharge, from 20 V to 15 V,

20 V to 5 V without a load, Figure 44 shows a waveform

above 250 mA, there is no VBUS discharge. Figure 43. VBUS Discharge, from 20 V to 5 V, Figure 44. VBUS Discharge, from 20 V to 5 V,

20 V to 5 V with 2 A load and Figure 46 shows a waveform

Figure 45. VBUS Discharge, from 20 V to 5 V, Figure 46. VBUS Discharge, from 20 V to 15 V,

verified which takes about 50 ms. Figure 54. VCONN when Non−cable Marker Cable Figure 55. VCONN when Cable Marker Cable is Figure 57 shows the thermals for 27 W (9 V/3 A). Figure 56. Thermal Image and Data for 15 W (5 V/3 A) Figure 57. Thermal Image and Data for 27 W (9 V/3 A)

15 W − 5 V/3 A

27 W − 9 V/3 A

Figure 59 shows the thermals for 45 W (15 V/3 A). Figure 58. Thermal Image and Data for 36 W (12 V/3 A) Figure 59. Thermal Image and Data for 45 W (15 V/3 A)

36 W − 12 V/3 A

45 W − 15 V/3 A

Figure 60 shows the thermals for 60 W (20 V/3 A). Figure 60. Thermal Image and Data for 60 W (20 V/3 A)

60 W − 20 V/3 A

www.onsemi.com USB−IF PD Compliance Testing Results The FUSB3307D6MX passed testing for USB PD3.0 with PPS at the USB−IF PD Compliance Workshop #114 the week of June 10, 2019, using the STR−FUSB3307MX−PPS−GEVB. TID: 1430. QuadraMAX − v0.8.7074

• PASSED LeCroy − v3.81 build 836
• PASSED
• PASSED MQP − v6.06.08
• PASSED USB2.0 Electricals
• PASSED Type−C and PD IOP
• test against Google phone, Google laptop, and Macbook
• PASSED Ellisys − v3.1.7095
• PASSED

Table 1. BILL OF MATERIALS

9 C1 C2 C3 C4 C5

4 C6 C31 C38 C39 1uF 0402 10V Murata GCM155C71A105KE38 Yes

2 C7 C19 1uF 0603 25V Murata GCM188R71E105KA64 Yes

1 C16 330uF TH_8mm 35V Illinois 337AVG035MGBJ Yes

1 C17 100uF TH_8mm 35V Nichicon RL81V101MDN1KX Yes

2 C20 C21 10nF 0402 50V Murata GCM155R71H103KA55D Yes

1 C22 1uF 0603 16V Murata GCM188R71C105KA64J Yes

3 C23 C25 C35 1nF 402 50V Murata GCM155R71H102KA37D Yes

2 C24 C27 390pF 0402 50V Murata GRM1555C1H391JA01D Yes

1 C28 100pF 0402 50V Murata GRM1555C1H101GA01D Yes

1 C29 1uF 0402 50V Taiyo Yuden UMK105CBJ105MV−F Yes

2 C32 C34 470pF 0402 50V Murata GCM155R71H471KA37D Yes

1 C33 47nF 0402 50V Murata GRM155R71H473KE14D Yes

2 C36 C37 1uF 0402 16V Murata GRM155C81C105KE1 1D Yes

1 C40 100nF 0402 50V Murata GCM155R71H104ME02 Yes

2 D1 D2 NSVR0240V2 SOD−523 40V ON Semiconductor NSVR0240V2T1G No

1 D3 SZMM3Z18VT1G SOD−323 18V ON Semiconductor SZMM3Z18VT1G No

1 D5 SZ1SMB30CAT3G SMB 30V Littelfuse SZ1SMB30CAT3G Yes

3 D6 D7 D9 SZESD7241 X2DFN2 25V ON Semiconductor SZESD7241N2T5G No

1 FB1 50@100M 1206 Murata BLM31SN500SZ1L Yes

1 J1 632 723 300 011 Wurth Elektronik 632723300011 Yes

3 J2 J4 J5 613 002 111 21 1x2pin

1 J3 691216710002 2−Pin

1 J6 SGAP0 SGAP0 Wurth Elektronik 613016243121 Yes

1 L2 160nH 7x7mm Coilcraft XAL5030−161MEC No

4 Q1 Q2 Q3 Q4 NVTFS4C10N u8−FL 30V ON Semiconductor NVTFS4C10NWFTAG No

1 Q5 NVTFS002N04CL u8−FL 40V ON Semiconductor NVTFS002N04CLTAG No

1 Q6 NVMFS5A140PLZ SO8−FL −40V ON Semiconductor NVMFS5A140PLZWFT1G No

2 Q7 Q8 2V7002W SOT−323 60V ON Semiconductor 2V7002WT1G No

3 Q9 Q10 Q11 2V7002L SOT−23 60V ON Semiconductor 2V7002LT1G No

1 R3 20k 0402 Yageo RC0402FR−0720KL Yes

6 R4 R5 R11 R12

1 R6 10k 0603 Yageo SR0603FR−7T10KL Yes

Table 1. BILL OF MATERIALS (continued)

5 R13 R15 R17 R18

1 R16 1k 1206 Vishay CRCW12061K00JNEA Yes

1 R21 301k 0402 KOA Speer RK73H1ETTP3013F Yes

3 R25 R52 R53 DNP 0402 DNP

10 R26 R27 R28 R32

5 R31 R33 R43 R44

1 R35 47k 0402 Yageo RC0402FR−0747KL Yes

1 R36 220k 0402 Yageo RC0402FR−07220KL Yes

1 R39 120k 0402 Yageo RC0402FR−07120KL Yes

1 R40 34K 0402 Yageo RC0402FR−0734KL Yes

1 R41 100K 0402 Yageo RC0402FR−07100KL Yes

1 R56 226K 0402 Yageo RC0402FR−07226KL Yes

1 RT1 100k 0402 Murata NCP15WF104F03RC Yes

5 TP1 TP2 TP9 TP15

1 U1 NCT375 DFN8

1 U2 NCV81599 QFN32

1 U3 NCV213R SC−70−6 ON Semiconductor NCV213RSQT2G No

1 U4 CAT24C512 UDFN−8 ON Semiconductor CAT24C512HU5IGT3 No

1 U5 FUSB3307 SOIC−14 ON Semiconductor FUSB3307D6MX No

1 U6 DNP QFNW20 ON Semiconductor DNP No

1 U7 NIV1161 WDFN6 ON Semiconductor NIV1161MTTAG No

USB Type−C is a registered trademark of USB Implementers Forum, Inc.

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