EVBUM2257 ONSEMI | Alldatasheet
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and cost in the development of a product prototype. a specific operating frequency. self-contained, CCD image acquisition sub-system. are provided to facilitate easy connection to a frame grabber. Figure 1. Block Diagram (Overview)
12 Bit Output
Table 1. POWER SUPPLY REQUIREMENTS selects a CCD binning mode (See section Binning Modes). to position 0 and 2.5 MHz when set in any other position. the operational flow of the evaluation board (Figure 4). the programming of these registers. are used to generate the horizontal and vertical clocks. required peak-to-peak voltage swing of the CCD clocks. The peak-to-peak swing of the clocks is adjustable. the offset voltage are adjustable. outputs of voltage dividers.
register values are downloaded from PLD2 upon power up. junction transistor in the emitter follower configuration. component of the video signal. ByteBlaster programming hardware. a multiple of the unit integration time. Figure 2. Unit Integration Timing Adjustment integration switches appropriately (See Table 9). inputs are needed to acquire images. three frame grabber sync signals in differential TTL format. CCD Daughter Boards plug into these connectors. timing board to the proper pins of the CCD. Board, from a single +5 V source. must be connected to the board via J5.
http://onsemi.com BOARD REQUIREMENTS Power Supply The board requires only a single +5 V , 1.5 Amp or greater power supply to operate. An on board switching power supply generates the necessary +15 V , 120 mA and –10 V , 120 mA power supplies from the 5 V input. Although extensive filtering is done on board, the power supplied to the board must be quiet and stable in order to achieve the best possible performance. (See Power Supply Modes, for an alternative way to power the board.) Inputs In the Free-Run mode, the evaluation board requires no input signals to begin acquiring images. In Still mode, the evaluation board will acquire a single image on the falling edge of the Image_Acquire control line. This can be accomplished via the push button (S4) or, remotely, by utilizing the Image_Acquire control line. See Section Still/Free-Run Modes for more information on Still and Free-Run modes. See Sections Line/Switches Modes and AD_IN/EX Modes for information on additional optional inputs. Outputs D[11..0] ( ±) − 12 bits of Differential TTL Digital information INTEGRA TE − A signal provided to allow the user to synchronize the strobing of LED illuminators or opening of a shutter, during the integration period. FRAME ( ±)* − Differential TTL Frame grabber vertical sync signal. LINE ( ±)* − Differential TTL Frame grabber horizontal sync signal. PIX (±)* − Differential TTL Frame grabber pixel sync *These sync signals can be modified if necessary to accommodate different Frame Grabbers. JTAG Programming Altera 7000S In System Programmable (ISP) PLD’s are used on this board. A ten-pin header (J8) is provided to allow for the programming of these PLD’s. Since these parts are re-programmable, custom digital logic can be implemented for timing and mode adjustments or additions. Any custom implementation can be made quickly and easily to via the JTAG programming interface provided by this connector. CONFIGURATION MODES The following modes of operation are available to the user: Line/Switches Modes The Line/Switches Jumper (SW5) selects whether some of the board settings will be controlled externally through the J6 connector (Line), or via the on-board switches (Switches). If this switch is set to Line, then the integration time and the binning mode must be set remotely via digital I/O. The still/free-run mode switch (SW3, 3-position switch) can also be set externally when the Line mode is selected. Set SW3 to the middle position if it is desired to control this line externally. Still/Free-Run Modes The “Still/Free-Run” switch (SW3) is a three-position switch that selects whether the board will operate in the still mode, or a free-running mode. If SW3 is placed in the middle position (“LINE”), the image capture mode is determined by the voltage on the STILL/FREE-RUN pin on the input connector (J6−27). Setting this line LOW selects the free-run mode, and setting it HIGH selects the still mode. In still mode, the Image_Acquire control line must be strobed in order to acquire a single image. This is accomplished by either pressing the on-board acquire button (S4) or, remotely, bringing the Image_Acquire line low and then back high. The detection of the falling edge of this signal starts the image acquisition process. The still mode acquisition process is as follows: 1. The CCD is flushed of all accumulated charge. 2. The CCD is exposed to light during the integration time. 3. The image is clocked out of the CCD. The system then waits for the next Image_Acquire signal. In the Free-Run mode, the system will continuously capture images and clock them out. No flushing is done, as the clocking out of the previous image serves this same purpose. See Figure 4 for the Clocking State Machine Diagram. AD_IN/EX Modes The board comes with an Analog Devices AD9816 12 bit A/D converter on board. This A/D has several features, such as multiple configurations, programmable gain, and offset registers which require initialization and/or programming on power up. The programming of these registers is done via a three wire serial interface.
http://onsemi.com EXT A three wire serial interface is provided on the J6 connector of the board, and the AD9816 registers can be controlled remotely via these when the A/D_IN/EX Jumper (SW4) is set to EXT. See Figure 5 for AD9816 serial timing diagrams and information. INT If it is not desired to control the programming of the A/D’s registers remotely, set Jumper SW4 to INT. PLD2 contains a state machine that serially loads in the following default values to these registers upon power up. A/D Default Register Settings: No. of channels: 1 Mode: CDS Mode Input Span: 3 V Channel Selected: Green Red PGA Gain*: 1 Green PGA Gain: 1 Blue PGA Gain*: 1 Red Offset*: 0 mv Green Offset: 0 mv Blue Offset*: 0 mv *Although the Red and Blue channels are not used, these registers are still initialized to these default settings. Adjustments Adjustments can be made to the A/D registers during operation of the board by utilizing the DATA dipswitch (SW10), the ADDRESS switch (SW9), and the Image_Acquire control line. After setting SW9 to the desired Address, and SW10 to the desired Data, send an Image_Acquire signal either by pressing the Image_Acquire button or remotely via the J6 connector control line. This will load the new value into PLD2 and a state machine inside the PLD will then serial load the new data into the A/D’s register. This is true whether or not the board is running in Still or Free Run Mode. (See Figure 5 for more information on the AD9816 registers.) CCD Modes The CCD Select switch (SW1) setting determines the line and frame length timing. This switch is pre-set at ONSemiconductor. (See Table 5) Binning Modes The BIN Select switch (SW2) setting determines the Binning mode operation. (Table 6) Integration Modes The INT Select switches (SW6, SW7) settings determine the Integration Time. SW6 is the Coarse Adjust. SW7 is the Fine Adjust. (Table 9) Frame Grabber Diagnostic Modes When set to ENABLE, the Sync_Test_Enable switch (SW12) tri-states the 12-bit output bus out of the A/D converter, and enables the output of either the pixel number or the line number onto the output bus, depending on how the Sync_Test_pix/line Jumper is set (SW11). This provides a diagnostic test to make certain the Frame Grabber is synchronized correctly with the board. The line counter in PLD1 is a binary up-counter, therefore the line count that is output to the output bus will increment sequentially (0, 1, 2, 3, 4, 5...) until the last line in the frame. The pixel counter in PLD1 is a gray code up counter, therefore the pixel count that is output to the output bus will increment in gray code transition counts (0, 1, 3, 2, 6, 7, 5, 4...) until the last pixel in the line. Power Supply Modes Power can be supplied to the board in one of two ways: Switching Power Supply The board comes supplied with a 500 kHz switching power supply (Linear Technologies LT1372). If it is desired to utilize the on-board switching supply, the board should be configured as follows: 1. Connect a 5 V , 1.5 A or greater lab supply to the J5 power connector. 2. Install Jumper 6 and Jumper 4. 3. Remove Jumper 7 and Jumper 5. 4. Set Jumper 1 to the ON position. External Supply Operation To disable the on-board switching supply and operate using external supplies: 1. Remove Jumpers 4 and 6; 2. Install Jumpers 5 and 7; 3. Move Jumper 1 to the “OFF” position to disable the switching power supply; 4. Connect +18 V , −18 V , and +5 V to power input connector J5. Functionality The switching supply generates +15 V and –10 V supply “islands”. The same is true for the +15 V and –10 V regulators on the board. Jumpers 4 and 6 connect the switcher supplies to the +15 V , −10 V power plane. Jumpers 5 and 7 connect the regulated outputs to the +15 V , −10 V power plane. Jumper 1 either enables or disables the LT1372 Switcher.
connectors J1 and J2 to the appropriate pins on the device. and drives the video signal down to the timing board. Table 2. VARIABLE BIAS VOLTAGES
- These voltages are optimized for the particular KAF Series image sensor being used and are fixed at the factory according to the image
sensor specification. Adjustments should not be made to them without consulting ON Semiconductor. one of them is selected depending on the application. incorrect and are reversed in that part of the schematic. the pin labeling on the schematic is incorrect.
Pixel frequency:The pixel frequency is 1/8 the master clock. adjusting R6, the unit integration time can be varied. to be recalculated for any new unit integration time. Figure 3. System Block Diagram
40 Mhz
Figure 4. Clocking State Machine
0 Configuration Register
1 MUX Register
2 Red PGA Register 1X to 6X (Note 2) 0 (1X)
3 Green PGA Register 1X to 6X (Note 2) 0 (1X)
4 Blue PGA Register 1X to 6X (Note 2) 0 (1X)
5 Red Offset Register −100 mV to 100 mV (Note 3) 0 (0 mV)
6 Green Offset Register −100 mV to 100 mV (Note 3) 0 (0 mV)
7 Blue Offset Register −100 mV to 100 mV (Note 3) 0 (0 mV)
Figure 5. AND9816 Register Configuration
3 Wire Serial Interface Timing
Table 4. BOARD SWITCHES, INPUTS, OUTPUTS INTEGRATE Active high signal indicates when in integration state. Can be used to sync LED’s or shutter with this state. Table 5. CCD MODES
1 Test Mode 1 1500 1200
2 Test Mode 2 10 4
3 Test Mode 3 1500 1200
4 Test Mode 4 2300 2150
5 KAF−1603 1700 1100
6 KAF−6303 3300 2150
7 KAF−0402 1000 650
8 KAF−3200 2300 1600
9 KAF−1001 1200 1150
Table 6. BINNING MODES NOTE: Binning Mode is not included in the timing program for the KAF−16801 and KAF−4301 image sensors. Table 7. BINNING MODES WHEN CONFIGURED FOR USE WITH KAF−16801 with a unique PLD program. That PLD program does not support binning modes other than 1x1 (normal full resolution readout). Table 8. KAF−4301 SW2 PIXEL RATE SETTINGS Table 9. INTEGRATION TIME MODES
- If both SW7 and SW6 are set to zero, the integration time is set to 10 ms.
Figure 6. Pixel Rate Timing
Figure 9. Frame Rate Timing for the KAF−0261, 0402, 1001, 1603, 4301, 6303, 16801
1 Frame = N Lines
Figure 10. Frame Timing for the KAF−3200 Sensor
Figure 13. Free Run Mode: Integration Timing Figure 14. Binning Mode Timing (2x2 Binning Shown)
- Dynamic Range Calculated using KAF−1600 Sensor, Full Well = 115000 Electrons Measured
Figure 17. Measured Performance: Dynamic Range
Figure 18. Measured Performance: A/D Programmable Gain
Table 11. IMAGER BOARD CONNECTORS J1, J2 Table 12. INPUT CONNECTOR J6
1 INT0 2 GND
3 INT2 4 GND
5 INT3 6 GND
7 INT5 8 GND
9 IMAGE_ACQUIRE 10 GND
11 BIN0 12 GND
13 BIN1 14 GND
15 SCLOCK 16 GND
17 INT1 18 GND
19 SLOAD 20 GND
21 INT4 22 GND
23 BIN2 24 GND
25 SDATA 26 GND
27 STILL/FREE−RUN 28 GND
Table 13. OUTPUT CONNECTOR J4
Table 14. INTEGRATE SYNC CONNECTOR J7 Table 15. POWER CONNECTOR J5 Table 16. JTAG CONNECTOR J8
http://onsemi.com WARNINGS AND ADVISORIES ON Semiconductor is not responsible for customer damage to the Timing Board or Imager Board electronics. The customer assumes responsibility and care must be taken when probing, modifying, or integrating the ON Semiconductor Evaluation Board Kits. When programming the Timing Board, the Imager Board must be disconnected from the Timing Board before power is applied. If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD, damage to the Imager Board will occur. Purchasers of a ONSemiconductor Evaluation Board Kit may, at their discretion, make changes to the Timing Generator Board firmware. ON Semiconductor can only support firmware developed by, and supplied by, ON Semiconductor. Changes to the firmware are at the risk of the customer.
ORDERING INFORMATION
Please address all inquiries and purchase orders to: Truesense Imaging, Inc.
1964 Lake Avenue
Rochester, New York 14615 Phone: (585) 784−5500 E-mail: info@truesenseimaging.com ON Semiconductor reserves the right to change any information contained herein without notice. All information furnished by ON Semiconductor is believed to be accurate. REFERENCES [1] KAF−0261, KAF−0402, KAF−1001, KAF−1603, KAF−3200, KAF−6303, KAF−16801, and KAF−4301 Device Specifications [2] Full Frame Evaluation Kit Schematics [3] Analog Devices AD9816 Product Data Sheet ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidia ries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 EVBUM2257/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative